A method and system for controlling charging time based on load end capacitance value

Abstract

The application provides a method and system for controlling charging time based on load end capacitance value, and relates to the technical field of new energy sources. The method comprises the following steps: according to a solid-state power control unit circuit, a corresponding simulation model is established in a dynamic system modeling tool, and a fitting curve is determined through the simulation model; the on and off of a current limiting branch in the solid-state power control unit circuit is controlled to generate a current response signal and a voltage signal at the load end, and the current response signal and the voltage signal are processed in sequence by using a sampling circuit, Fourier transform, FPGA and the fitting curve to obtain the capacitance value of the load end; the on time of the current limiting branch is determined according to the maximum value of a plurality of preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value of the load end, and the current limiting branch is turned on according to the on time to complete the charging of the capacitance of the load end. In this way, the on time of the current limiting branch is dynamically adjusted by using the capacitance value of the load end, and the efficiency and reliability of the system can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new energy, in particular to a method and system for controlling charging time based on load end capacitance value. BACKGROUND

[0002] The rapid development of new energy vehicles has significantly promoted the electrification and intelligentization process of electric vehicles. The traditional 12V system has been difficult to meet the higher power requirements of modern electric vehicles. Therefore, the 48V system is becoming a future development trend. In the scenario of the 48V system, the low-voltage circuit breaker and fuse in traditional vehicles are difficult to meet the requirements of increasingly complex circuits. In order to meet the performance indicators of the power distribution system, a solid-state power control unit is used to replace the low-voltage circuit breaker and fuse. However, with the development of new energy vehicle power systems, the types and capacities of the load ends are also increasing. New energy vehicle power systems include motor drive systems, on-board chargers, DC-DC converters, and high-power infotainment systems. Many capacitive loads are included in new energy vehicle power systems. Due to the charge conservation characteristics of capacitive loads, the voltage across them cannot change abruptly, so a large current surge will occur at the moment of turning on, which can easily cause the failure of switching devices. Especially for high-power capacitive loads, using a solid-state power control unit will face a large current surge at startup.

[0003] Currently, in order to handle the large current surge of the solid-state power control unit at startup, a current limiting branch is usually used. For example, a current limiting resistor is used in series with a current limiting branch power tube. When turned on, the current limiting branch is connected, the current limiting branch charges the capacitive load, and after a certain time, the main branch is turned on. Since the equivalent impedance of the main branch is much smaller than that of the current limiting branch, the current limiting branch can be short-circuited, and finally the current limiting during the on process is realized. However, since the load end capacitive impedance value is unknown, the current limiting branch opening time is fixed, which causes large power loss, wastes the heat capacity of the current limiting branch, and may cause device damage, resulting in low reliability. In addition, the current limiting branch opening time is fixed. This fixed time design will cause additional power loss, thereby reducing the efficiency of the system. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a method and system for controlling charging time based on load end capacitance value, to solve the problems of reducing the efficiency of the system and low reliability in the prior art.

[0005] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0006] The first aspect of the present application provides a method for controlling charging time based on load end capacitance value, comprising:

[0007] According to the solid-state power control unit circuit, a corresponding simulation model is established in a dynamic system modeling tool, and a fitting curve is determined through the simulation model, the fitting curve being used to indicate a rule between a ratio of preset real parts of the load end at different angular frequencies and a capacitance value; the solid-state power control unit circuit is connected with a sampling circuit, a field-programmable gate array (FPGA) and the load end;

[0008] The current response signal and the voltage signal are generated at the load end by turning on and turning off the current limiting branch in the solid-state power control unit circuit, and the capacitance value of the load end is obtained by processing the current response signal and the voltage signal in sequence by using the sampling circuit, the Fourier transform, the FPGA and the fitting curve.

[0009] The turning-on time of the current limiting branch is determined according to the maximum of the plurality of preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value of the load end, and the current limiting branch is turned on according to the turning-on time, so that the capacitance of the load end is charged.

[0010] The second aspect of the present application provides a system for controlling charging time based on a capacitance value of a load end, comprising:

[0011] The establishing module is configured to establish a corresponding simulation model in a dynamic system modeling tool according to a solid-state power control unit circuit, and determine a fitting curve through the simulation model, the fitting curve being used to indicate a rule between a ratio of preset real parts of the load end at different angular frequencies and a capacitance value; the solid-state power control unit circuit is connected with a sampling circuit, a field-programmable gate array (FPGA) and the load end.

[0012] The processing module is configured to control turning on and turning off of a current limiting branch in the solid-state power control unit circuit, to generate a current response signal and a voltage signal at the load end, and to obtain the capacitance value of the load end by processing the current response signal and the voltage signal in sequence by using the sampling circuit, the Fourier transform, the FPGA and the fitting curve.

[0013] The control module is configured to determine the turning-on time of the current limiting branch according to the maximum of the plurality of preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value of the load end, and to control turning on of the current limiting branch according to the turning-on time, so that the capacitance of the load end is charged.

[0014] The third aspect of the present application provides an electronic device, comprising: at least one processor; and at least one memory connected with the processor through a bus; wherein the processor, the memory and the bus complete communication with each other; the processor is configured to call program instructions in the memory to execute the method for controlling charging time based on a capacitance value of a load end according to the first aspect or any one of the optional embodiments of the first aspect.

[0015] Compared with the prior art, the method and system for controlling charging time based on load end capacitance value provided by the application establish a corresponding simulation model in a dynamic system modeling tool according to a solid-state power control unit circuit, and determine a fitting curve through the simulation model, the fitting curve being used to indicate the law between the ratio of preset real parts at different angular frequencies and the capacitance value; the on and off of the current limiting branch in the solid-state power control unit circuit is controlled to generate a current response signal and a voltage signal at the load end, and the current response signal and the voltage signal are processed in sequence by using a sampling circuit, Fourier transform, FPGA and the fitting curve to obtain the capacitance value of the load end; the on time of the current limiting branch is determined according to the maximum of a plurality of preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value of the load end, and the current limiting branch is turned on according to the on time to enable the capacitance of the load end to complete charging. In this way, by controlling the on and off of the current limiting branch in the solid-state power control unit circuit, the current response signal and the voltage signal are collected, without adding additional circuits on the basis of the existing solid-state power control unit circuit, the capacitance value of the load end is obtained by using the sampling circuit, Fourier transform, FPGA and the fitting curve, and the on time of the current limiting branch is dynamically adjusted by using the capacitance value of the load end, which can effectively suppress the inrush current in the on process, improve the efficiency of the system, avoid additional power loss, cause less heat capacity, and improve the reliability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the present application are shown by way of example, and wherein like reference numerals refer to like elements throughout. In the drawings:

[0017] Figure 1 A flowchart of a method for controlling charging time based on a load end capacitance value is schematically shown;

[0018] Figure 2 An equivalent circuit model schematic diagram of a load end is schematically shown;

[0019] Figure 3 A fitting curve corresponding to the ratio of preset real parts at different capacitance values is schematically shown;

[0020] Figure 4 An impedance measurement circuit diagram is schematically shown;

[0021] Figure 5 A schematic diagram of a load inrush current size of a 940uF capacitance value with no current limiting branch is schematically shown;

[0022] Figure 6The schematic diagram of the size of the load inrush current of the infinite current branch opening 1670uF capacitance value is shown;

[0023] Figure 7 The schematic diagram of the size of the load inrush current of the infinite current branch opening 2400uF capacitance value is shown;

[0024] Figure 8 The schematic diagram of the size of the load inrush current of the infinite current branch opening 2870uF capacitance value is shown;

[0025] Figure 9 The schematic diagram of the size of the load inrush current of the infinite current branch opening 3560uF capacitance value is shown;

[0026] Figure 10 The schematic diagram of the size of the load inrush current of the infinite current branch opening 4500uF capacitance value is shown;

[0027] Figure 11 The schematic diagram of the size of the load inrush current of the infinite current branch opening 940uF capacitance value is shown;

[0028] Figure 12 The schematic diagram of the size of the load inrush current of the infinite current branch opening 1670uF capacitance value is shown;

[0029] Figure 13 The schematic diagram of the size of the load inrush current of the infinite current branch opening 2400uF capacitance value is shown;

[0030] Figure 14 The schematic diagram of the size of the load inrush current of the infinite current branch opening 2870uF capacitance value is shown;

[0031] Figure 15 The schematic diagram of the size of the load inrush current of the infinite current branch opening 3560uF capacitance value is shown;

[0032] Figure 16 The schematic diagram of the size of the load inrush current of the infinite current branch opening 4500uF capacitance value is shown;

[0033] Figure 17 The schematic diagram of the size of the load inrush current of the infinite current branch opening 940uF capacitance value is shown;

[0034] Figure 18 The schematic diagram of the size of the load inrush current of the infinite current branch opening 1670uF capacitance value is shown;

[0035] Figure 19 The schematic diagram of the size of the load inrush current of the infinite current branch opening 2400uF capacitance value is shown;

[0036] Figure 20A power loss schematic diagram under a 2870uF capacitance value is schematically shown;

[0037] Figure 21 A power loss schematic diagram under a 3560uF capacitance value is schematically shown;

[0038] Figure 22 A power loss schematic diagram under a 4500uF capacitance value is schematically shown;

[0039] Figure 23 A structural diagram of a system for controlling a charging time based on a load end capacitance value is schematically shown;

[0040] Figure 1 A structural diagram of an electronic device is schematically shown. DETAILED DESCRIPTION

[0041] Exemplary embodiments of the present application will be described in detail with reference to the drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0042] It should be noted that: unless otherwise specified, the technical terms or scientific terms used in the present application should be understood as the usual meaning understood by those skilled in the art to which the present application belongs.

[0043] The method in the embodiments of the present application will be described in detail below.

[0044] Figure 1 A flowchart of the method for controlling a charging time based on a load end capacitance value in the embodiments of the present application is schematically shown, referring to Figure 2 As shown, the method for controlling a charging time based on a load end capacitance value can include:

[0045] S101, according to the solid-state power control unit circuit, a corresponding simulation model is established in a dynamic system modeling tool, and a fitting curve is determined through the simulation model.

[0046] The fitting curve is used to indicate the law between the ratio of the preset real part of the load end at different angular frequencies and the capacitance value. The solid-state power control unit circuit is connected with the sampling circuit, FPGA and the load end.

[0047] Specifically, an equivalent model of the load end is established, Figure 2 An equivalent circuit model schematic diagram of the load end is schematically shown, referring to Figure 3 As shown, the equivalent model of the load end includes an equivalent resistance , an equivalent capacitance and an equivalent inductance . one end of an equivalent capacitance is connected to one end of an equivalent resistance , the other end of the equivalent capacitance is connected to one end of an equivalent inductance , the other end of the equivalent resistance is connected to the other end of the equivalent inductance . According to the equivalent model of the load end, the internal impedance of the load end can be determined, and the expression of the internal impedance of the load end is:

[0048] ;

[0049] wherein, is the preset real part of the load end, is the preset imaginary part of the load end, is the imaginary unit, is the angular frequency.

[0050] Simplifying the expression of the internal impedance of the load end , the preset real part of the load end and the preset imaginary part of the load end are obtained as:

[0051] ;

[0052] According to the expression of the preset real part of the load end and the preset imaginary part of the load end, it can be seen that under the condition that the load end does not change, that is, the modulus of the internal impedance of the load end is constant, when the angular frequency changes, the preset real part of the load end and the preset imaginary part of the load end change regularly. According to the expression of the preset real part of the load end and the preset imaginary part of the load end, the relationship between the preset real part of the load end and the equivalent resistance , the equivalent capacitance , the equivalent inductance , and the angular frequency can be determined. Under the condition that the equivalent resistance , the equivalent inductance is unchanged, changing the angular frequency can obtain the value of the preset real part of the load end under different angular frequencies. Therefore, according to the solid-state power control unit circuit, a corresponding simulation model can be established in a dynamic system modeling tool, and a fitting curve can be determined through the simulation model.

[0053] The dynamic system modeling tool can be Simulink and Matlab.

[0054] Exemplarily, the simulation model adopts typical industrial control parameters of an electric vehicle: the total capacitance range of the load end is set to 0-5000uF, the inductance range is 0-500uH, and based on the actual situation that the parallel connection of multiple loads of an electric vehicle leads to the reduction of equivalent resistance, the fixed resistance parameter is 84Ω to simulate typical resistance value industrial control of an electric vehicle. By changing the inductance and capacitance values in the typical resistance value industrial control of an electric vehicle, the ratio of the preset real part under different capacitance values can be obtained. According to the simulation model, the fitting curve between the ratio of the preset real part of the load end under different angular frequencies and the capacitance value can be determined. Figure 3 The fitting curve corresponding to the ratio of the preset real part under different capacitance values is schematically shown, as shown in Figure 3 The vertical coordinate is the capacitance value, and the horizontal coordinate is the ratio of the preset real part of the load end under different angular frequencies. Figure 4 The curves of five different inductance values are respectively a curve with a circle, a curve with a square, a curve with a star, a curve with a downward triangle, and a curve with a cross. The inductance value of the curve with a circle is 100uH, the inductance value of the curve with a square is 200uH, the inductance value of the curve with a star is 300uH, the inductance value of the curve with a downward triangle is 400uH, and the inductance value of the curve with a cross is 500uH. Through the above five curves of different inductance values, it can be seen that changing the size of the capacitance value of the load end, although the inductance values are different, the ratio of the preset real part of the load end is similar, so in the actual solid-state power control unit circuit, by changing the angular frequency, the preset real part and imaginary part of the load end under different angular frequencies are obtained, and based on the ratio of the preset real part of the load end under different angular frequencies, the capacitance value of the load end can be determined.

[0055] S102, control the on and off of the current limiting branch in the solid-state power control unit circuit to generate a current response signal and a voltage signal at the load end, and use a sampling circuit, Fourier transform, FPGA and a fitting curve to sequentially process the current response signal and the voltage signal to obtain the capacitance value of the load end.

[0056] Figure 4 The impedance measurement circuit diagram is schematically shown, as shown in Figure 5As shown, the impedance measurement circuit includes a solid-state power control unit circuit, a sampling circuit, an FPGA, a load end, a power supply and an inductor. The sampling circuit includes a current sampling circuit and a voltage sampling circuit. The positive terminal of the power supply, one end of the inductor and one end of the current sampling circuit are all connected, the negative terminal of the power supply, one end of the load end and one end of the voltage sampling circuit are all connected, the other end of the inductor, the other end of the current sampling circuit and one end of the solid-state power control unit circuit are all connected, one end of the FPGA is connected to the other end of the current sampling circuit and the other end of the solid-state power control unit circuit, and the other end of the voltage sampling circuit, the other end of the FPGA, the other end of the load end and the other end of the solid-state power control unit circuit are all connected. The solid-state power control unit circuit includes a first resistor, a first capacitor, a first freewheeling diode, a first MOS tube, a second capacitor, a second freewheeling diode and a second MOS tube. One end of the first resistor, the other end of the current sampling circuit, the other end of the inductor, one end of the second capacitor, the cathode of the second freewheeling diode and the drain of the second MOS tube are all connected, the other end of the first resistor, one end of the first capacitor, the cathode of the first freewheeling diode and the drain of the first MOS tube are all connected, the other end of the first capacitor, the anode of the first freewheeling diode, the source of the first MOS tube, the other end of the second capacitor, the anode of the second freewheeling diode and the anode of the second MOS tube, the other end of the load end, the other end of the voltage sampling circuit and the other end of the FPGA are all connected, and one end of the FPGA, the gate of the first MOS tube and the gate of the second MOS tube are all connected.

[0057] The solid-state power control unit circuit includes two branches, namely a current limiting branch and a main branch. The first resistor, the first capacitor, the first freewheeling diode and the first MOS tube form the current limiting branch, and the second capacitor, the second freewheeling diode and the second MOS tube form the main branch. The MOSFET device includes the first capacitor, the first freewheeling diode, the first MOS tube, the second capacitor, the second freewheeling diode and the second MOS tube.

[0058] Specifically, step S102 includes:

[0059] Step A1: control the MOSFET device in the current limiting branch to turn on and turn off to generate a current response signal and a voltage signal at the load end.

[0060] Dividing the voltage signal by the current response signal can obtain the impedance corresponding to the load end at the angular frequency

[0061] ;

[0062] wherein, is the impedance corresponding to the load end at the angular frequency is the voltage signal at the angular frequency ,​​ is the angular frequency of the current response signal.

[0063] Specifically, step A1 comprises:

[0064] Step A11: controlling the MOSFET device in the current limiting branch to turn on and turn off to generate a square wave signal.

[0065] Specifically, before turning on the main branch of the solid-state power control unit, the MOSFET device in the current limiting branch is controlled to turn on and turn off to generate a square wave signal with an angular frequency of .

[0066] Step A12: controlling the square wave signal to flow through the load end to generate a corresponding current response signal and voltage signal at the load end.

[0067] Step A2: using a sampling circuit to sample the current response signal and the voltage signal to obtain a discrete current response signal and a discrete voltage signal.

[0068] Step A3: performing Fourier transform on the discrete current response signal and the discrete voltage signal to obtain a transformed current response signal and a transformed voltage signal.

[0069] Since the FPGA can only process discrete signals, the current response signal and the voltage signal need to be discretized to obtain a discrete current response signal and a discrete voltage signal, that is, the expression of the impedance corresponding to the load end at the angular frequency needs to be transformed into a discrete form, and Fourier transform is performed on the discrete current response signal and the discrete voltage signal. For example, the discrete and Fourier transform are performed on the signal , the signal may be a current response signal or a voltage signal, the signal is sampled at a sampling period to obtain a discrete time sequence with a length of , and Fourier transform is performed on the sampled signal:

[0070] ;

[0071] wherein, is the transformed signal, i.e., the transformed current response signal or the transformed voltage signal, is the frequency index of the discrete frequency spectrum corresponding to the discrete time sequence, which is used to determine a specific frequency in the signal to calculate the transformed signal, is the length of the discrete time sequence corresponding to the discrete signal, is the sampling period, a discrete time sequence corresponding to the discrete signal.

[0072] Step A4: determining a discrete impedance expression according to the transformed current response signal and the transformed voltage signal.

[0073] Specifically, the discrete impedance expression is:

[0074] ;

[0075] wherein, is the discrete impedance, is a discrete time sequence corresponding to the discrete voltage signal, is a discrete time sequence corresponding to the voltage signal, is a sampling period, is a length of the discrete time sequence corresponding to the discrete voltage signal, is a discrete time sequence corresponding to the discrete current response signal, is a discrete time sequence corresponding to the discrete current response signal, is a length of the discrete time sequence corresponding to the discrete current response signal, is an imaginary unit. The length of the discrete time sequence corresponding to the discrete voltage signal is the same as the length of the discrete time sequence corresponding to the discrete current response signal .

[0076] Step A5: determining a ratio of target real parts of the load end at different angular frequencies by using the FPGA provided with the discrete impedance expression and the plurality of angular frequencies.

[0077] Wherein, the plurality of angular frequencies are all different.

[0078] Specifically, step A5 includes:

[0079] Step A51: determining a real part of the load end at a target angular frequency by using the FPGA provided with the discrete impedance expression.

[0080] Wherein, the target angular frequency is different from the plurality of angular frequencies.

[0081] The target angular frequency can be , and the plurality of angular frequencies can be , , etc.

[0082] Step A52: determining a target real part of the load end at different angular frequencies according to the real part of the load end at the target angular frequency and the plurality of angular frequencies.

[0083] Exemplary, the is changed to with , respectively, to obtain and the target real part and imaginary part of the load end under the angular frequency.

[0084] Step A53: According to the target real part of the load end under different angular frequencies, the ratio of the target real part of the load end under different angular frequencies is determined.

[0085] Step A6: The ratio of the target real part of the load end under different angular frequencies is substituted into the fitting curve to obtain the capacitance value of the load end.

[0086] S103, according to the maximum value of the plurality of preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value of the load end, the turn-on time of the current limiting branch is determined, and the current limiting branch is turned on according to the turn-on time, so that the capacitance of the load end is charged.

[0087] After turning on the current limiting branch, the power supply will first charge the capacitance of the load end through the current limiting branch, at this time the voltage and current across the load end are:

[0088] ;

[0089] ;

[0090] wherein, is the voltage across the load end, is the voltage across the DC power supply, is the turn-on time, is the time constant, , is the resistance of the current limiting branch, is the capacitance value of the load end, is the current across the load end.

[0091] Taking the derivative of the above expression of the voltage and current across the load end, the voltage transformation rate and the current transformation rate corresponding to the capacitance of the load end can be obtained:

[0092] ;

[0093] ;

[0094] wherein, is the voltage transformation rate corresponding to the capacitance of the load end, is the current transformation rate corresponding to the capacitance of the load end.

[0095] When the time When the voltage transformation rate of the load end and the current transformation rate of the load end corresponding to the capacitor of the load end are determined through the expression, the voltage and current variation law of the load end are both 0, and at this time, the loop of the turn-on impedance measurement circuit will have no inrush current. However, in practice, the turn-on time of the current limiting branch cannot be infinitely long, so the voltage transformation rate of the load end is determined according to the following expression, and when the voltage variation law of the load end is less than the parameter , it is determined that the capacitor of the load end has been fully charged:

[0096] ;

[0097] wherein, is the voltage transformation rate of the load end, is the voltage sampling value of the load end. When , the voltage corresponding to the capacitor of the load end is about 95% of the power supply voltage, and it can be determined that the capacitor of the load end has been fully charged. Therefore, the turn-on time of the current limiting branch can be controlled to turn on, so that the capacitor of the load end is fully charged.

[0098] Specifically, step S103 comprises:

[0099] Step B1: determining a plurality of turn-on times corresponding to a plurality of preset capacitance value ranges according to the maximum value of the plurality of preset capacitance value ranges and the resistance of the current limiting branch.

[0100] The plurality of preset capacitance value ranges can be six preset capacitance value ranges, and the load end capacitor range is 0-5000uF. The load end capacitor range can be divided into six preset capacitance value ranges, and the six preset capacitance value ranges are 0-1400uF, 1400-2000uF, 2000-2600uF, 2600-3200uF, 3200-4000uF and 4000-5000uF.

[0101] Specifically, step B1 comprises:

[0102] Step B11: determining a plurality of time constants corresponding to a plurality of preset capacitance value ranges according to the maximum value of the plurality of preset capacitance value ranges and the resistance of the current limiting branch.

[0103] According to the product of the maximum value of the six preset capacitance value ranges, i.e. 1400uF, 2000uF, 2600uF, 3200uF, 4000uF, 5000uF, and the resistance of the current limiting branch, six time constants corresponding to the maximum value of the six preset capacitance value ranges are determined.

[0104] Step B12: determining a plurality of turn-on times according to the plurality of time constants and a preset value.

[0105] The preset value is set to 3, and the corresponding 6 turn-on times are obtained by multiplying the 6 time constants determined in step B11 by the preset value 3. The 6 turn-on times are 42.24 ms, 60.48 ms, 78.62 ms, 96.77 ms, 120.96 ms and 151.20 ms, respectively. The corresponding 6 turn-on losses are 1.6087 W, 2.298 W, 2.9878 W, 3.677 W, 4.5966 W and 5.7457 W, respectively, which can be determined by the formula for calculating the turn-on loss in the prior art.

[0106] Step B2: Establish a correspondence table of a plurality of preset capacitance value ranges and a plurality of turn-on times.

[0107] According to the 6 preset capacitance value ranges and the determined 6 turn-on times, a correspondence table of the 6 preset capacitance value ranges and the 6 turn-on times is established. Table 1 is the turn-on time and the turn-on loss under different capacitance conditions, and Table 1 has the correspondence of the 6 preset capacitance value ranges, the 6 turn-on times, the 6 preset real part ratios, the 6 capacitance conditions and the 6 turn-on losses. Among them, the 6 preset real part ratios are the ratios of the preset real parts at different angular frequencies at the load end in step S101, the preset real part ratios are 1:2, 2:3, 3:4, 4:5, 5:6 and 6:8, respectively, the capacitance conditions are condition one, condition two, condition three, condition four, condition five and condition six, respectively, condition one is the case where the preset capacitance value range is 0-1400uF, condition two is the case where the preset capacitance value range is 1400-2000uF, condition three is the case where the preset capacitance value range is 2000-2600uF, condition four is the case where the preset capacitance value range is 2600-3200uF, condition five is the case where the preset capacitance value range is 3200-4000uF, and condition six is the case where the preset capacitance value range is 4000-5000uF.

[0108] Table 1 Turn-on time and turn-on loss under different capacitance conditions

[0109]

[0110] Step B3: Determine the target preset capacitance value range corresponding to the capacitance value at the load end.

[0111] Among them, the plurality of preset capacitance value ranges include the target preset capacitance value range.

[0112] For example, when the capacitance value at the load end is 1500uF, it can be determined that the target preset capacitance value range corresponding to 1500uF is 1400-2000uF.

[0113] Step B4: In the correspondence table, find the turn-on time corresponding to the target preset capacitance value range.

[0114] Following the example in step B3, the activation time for 1400-2000uF is 60.48ms.

[0115] Step B5: Control the current-limiting branch to turn on according to the turn-on time so that the capacitor at the load end can be fully charged.

[0116] Following the example in step B4, the current-limiting branch is turned on based on an on-time of 60.48ms to allow the capacitor at the load end to complete charging.

[0117] The effectiveness of the method for controlling charging time by the load-side capacitance proposed in this invention is verified through the following simulation experiments.

[0118] Figure 6 This diagram schematically illustrates the magnitude of the surge current when a 940uF load with unlimited current branch is applied. Figure 7 This diagram schematically illustrates the magnitude of the surge current when a 1670uF load with unlimited current branch is applied. Figure 8 This diagram schematically illustrates the magnitude of the surge current when a 2400uF load with unlimited current branch is applied. Figure 9 This diagram schematically illustrates the magnitude of the surge current when a 2870uF load with unlimited current branch is applied. Figure 10 This diagram schematically illustrates the magnitude of the surge current when a 3560uF load with unlimited current branch is applied. Figures 5 to 10 This diagram schematically illustrates the surge current magnitude of a 4500uF capacitance load when an infinite current branch is connected. See also... Figure 11 As shown, the horizontal axis represents turn-on time, and the vertical axis represents current amplitude. Capacitors of 940uF, 1670uF, 2400uF, 2870uF, 3560uF, and 4500uF were turned on in the unlimited current branch. With the increase in the capacitance at the load end, the amplitude and oscillation degree of the surge current also increase, reaching a maximum turn-on surge current of 76A. Such excessive surge current can cause significant impact on the components in the solid-state power control unit circuit, leading to component breakdown and subsequent current damage, severely affecting the reliability and stability of the system.

[0119] Figure 12 The diagram illustrates the surge current magnitude of a 940uF capacitive load under a current-limiting strategy. Figure 13 The diagram illustrates the surge current of a 1670uF capacitive load under a current-limiting strategy. Figure 14 The diagram illustrates the surge current magnitude of a 2400uF capacitive load under a current-limiting strategy. Figure 15 The diagram illustrates the surge current magnitude of a 2870uF capacitive load under a current-limiting strategy. Figure 16Fig. 6 schematically shows a diagram of the inrush current size under the current limiting strategy when the 3560uF capacitance load is turned on, Figures 11 to 16 Fig. 7 schematically shows a diagram of the inrush current size under the current limiting strategy when the 4500uF capacitance load is turned on. Referring to Figure 17 As shown, the abscissa is the turn-on time, and the ordinate is the current amplitude. When the 940uF capacitance, 1670uF capacitance, 2400uF capacitance, 2870uF capacitance, 3560uF capacitance, and 4500uF capacitance are turned on under the current limiting strategy, the inrush current is significantly suppressed. By precisely controlling the turn-on time of the current limiting branch, the maximum value of the inrush current is successfully limited to within 13A, which reduces the amplitude of the inrush current by 83%. Compared with the case without using the current limiting strategy, the oscillation amplitude of the current is greatly reduced, effectively avoiding damage to the circuit components of the solid-state power control unit caused by excessive inrush current.

[0120] Figure 18 Fig. 8 schematically shows a diagram of the power loss under the 940uF capacitance, Figure 19 Fig. 9 schematically shows a diagram of the power loss under the 1670uF capacitance, Figure 20 Fig. 10 schematically shows a diagram of the power loss under the 2400uF capacitance, Figure 21 Fig. 11 schematically shows a diagram of the power loss under the 2870uF capacitance, Figure 22 Fig. 12 schematically shows a diagram of the power loss under the 3560uF capacitance, Figures 17 to 22 Fig. 13 schematically shows a diagram of the power loss under the 4500uF capacitance. Referring to Figures 17 to 22 As shown, the abscissa is the turn-on time, and the ordinate is the turn-on power. Under the 940uF capacitance, 1670uF capacitance, 2400uF capacitance, 2870uF capacitance, 3560uF capacitance, and 4500uF capacitance, the power loss using the current limiting strategy is the power loss of the current limiting branch before the inrush current occurs. The longer the turn-on time of the current limiting branch, the more power loss it causes. From Figure 1 It can be concluded that, compared with the 4000-5000uF preset capacitance range, the turn-on loss is reduced by 72%, 60%, 48%, 36%, and 20% respectively under different capacitance ranges, as shown in Table 1. The overall efficiency of the circuit is significantly improved, and the performance of the solid-state power control unit is optimized.

[0121] Based on the above Figure 23As can be seen from the implementation manner, the embodiment of the present application establishes a corresponding simulation model in a dynamic system modeling tool according to the solid-state power control unit circuit, and determines a fitting curve through the simulation model, the fitting curve being used to indicate a rule between a ratio of preset real parts of the load end at different angular frequencies and a capacitance value; the current limiting branch in the solid-state power control unit circuit is controlled to be turned on and turned off to generate a current response signal and a voltage signal at the load end, and the current response signal and the voltage signal are processed in sequence by using the sampling circuit, the Fourier transform, the FPGA and the fitting curve to obtain the capacitance value of the load end; the turn-on time of the current limiting branch is determined according to a maximum value of a plurality of preset capacitance value ranges, a resistance of the current limiting branch and the capacitance value of the load end, and the current limiting branch is controlled to be turned on according to the turn-on time to enable the capacitance of the load end to complete charging. In this way, by controlling the current limiting branch in the solid-state power control unit circuit to be turned on and turned off, the current response signal and the voltage signal are collected, without adding an additional circuit on the basis of the existing solid-state power control unit circuit, the capacitance value of the load end is obtained by using the sampling circuit, the Fourier transform, the FPGA and the fitting curve, and the turn-on time of the current limiting branch is dynamically adjusted by using the capacitance value of the load end, which can not only effectively suppress the inrush current in the turn-on process, but also improve the efficiency of the system, avoids causing additional power loss, enables the generated heat capacity to be small, and improves the reliability of the system.

[0122] Based on the same inventive concept, as an implementation of the above-mentioned method for controlling the charging time based on the capacitance value of the load end, the embodiment of the present application further provides a system for controlling the charging time based on the capacitance value of the load end. Figure 23 The structure diagram of the system for controlling the charging time based on the capacitance value of the load end in the embodiment of the present application is shown in Figure 24 The system for controlling the charging time based on the capacitance value of the load end can include:

[0123] The establishing module 2301 is configured to establish a corresponding simulation model in a dynamic system modeling tool according to the solid-state power control unit circuit, and determine a fitting curve through the simulation model, the fitting curve being used to indicate a rule between a ratio of preset real parts of the load end at different angular frequencies and a capacitance value; the solid-state power control unit circuit is connected with the sampling circuit, the FPGA and the load end;

[0124] The processing module 2302 is configured to control the current limiting branch in the solid-state power control unit circuit to be turned on and turned off to generate a current response signal and a voltage signal at the load end, and process the current response signal and the voltage signal in sequence by using the sampling circuit, the Fourier transform, the FPGA and the fitting curve to obtain the capacitance value of the load end;

[0125] The control module 2303 is used to determine the turn-on time of the current-limiting branch based on the maximum value of multiple preset capacitance ranges, the resistance of the current-limiting branch and the capacitance of the load end, and to control the turn-on of the current-limiting branch according to the turn-on time so that the capacitor at the load end can be charged.

[0126] Processing module 2302 is specifically used to control the switching on and off of MOSFET devices in the current-limiting branch to generate current response signals and voltage signals at the load end; it uses a sampling circuit to sample the current response signals and voltage signals to obtain discrete current response signals and discrete voltage signals; it performs Fourier transform on the discrete current response signals and discrete voltage signals to obtain transformed current response signals and transformed voltage signals; it determines discrete impedance expressions based on the transformed current response signals and transformed voltage signals; it uses an FPGA with discrete impedance expressions and multiple angular frequencies to determine the ratio of the target real part at the load end at different angular frequencies, and the multiple angular frequencies are all different; it substitutes the ratio of the target real part at the load end at different angular frequencies into the fitting curve to obtain the capacitance value at the load end.

[0127] The processing module 2302 controls the MOSFET devices in the current-limiting branch to turn on and off, so as to generate current response signals and voltage signals at the load end, including: controlling the MOSFET devices in the current-limiting branch to turn on and off, generating a square wave signal; controlling the square wave signal to flow through the load end, so as to generate corresponding current response signals and voltage signals at the load end.

[0128] Processing module 2302 uses an FPGA with discrete impedance expressions and multiple angular frequencies to determine the ratio of the target real parts of the load at different angular frequencies. This includes: using the FPGA with discrete impedance expressions to determine the real part of the load at the target angular frequency, where the target angular frequency is different from the multiple angular frequencies; determining the target real parts of the load at different angular frequencies based on the real part of the load at the target angular frequency and the multiple angular frequencies; and determining the ratio of the target real parts of the load at different angular frequencies based on the target real parts of the load at different angular frequencies.

[0129] Processing module 2302, the discrete impedance expression is:

[0130] ;

[0131] in, For discrete impedances, For discrete voltage signals, the discrete time series is... The voltage signal corresponding to the first A discrete time series The sampling period is Let be the length of the discrete-time sequence corresponding to the discrete voltage signal. This is the discrete-time sequence corresponding to the discrete current response signal. The first corresponding to the discrete current response signal A discrete time series Let be the length of the discrete time series corresponding to the discrete current response signal. It is the imaginary unit.

[0132] The control module 2303 is specifically used to determine multiple turn-on times corresponding to multiple preset capacitance ranges based on the maximum value of multiple preset capacitance ranges and the resistance of the current-limiting branch; establish a correspondence table between multiple preset capacitance ranges and multiple turn-on times; determine the target preset capacitance range corresponding to the capacitance value of the load, where the multiple preset capacitance ranges include the target preset capacitance range; look up the turn-on time corresponding to the target preset capacitance range in the correspondence table; and control the current-limiting branch to turn on according to the turn-on time so that the capacitor at the load end can complete charging.

[0133] The control module 2303 determines multiple turn-on times corresponding to multiple preset capacitance ranges based on the maximum value of multiple preset capacitance ranges and the resistance of the current limiting branch, including: determining multiple time constants based on the maximum value of multiple preset capacitance ranges and the resistance of the current limiting branch; and determining multiple turn-on times based on multiple time constants and preset values.

[0134] Based on the same inventive concept, embodiments of the present invention also provide an electronic device. Figure 24 This is a structural diagram of the electronic device in an embodiment of the present invention. See also... ​ As shown, the electronic device 240 may include: at least one processor 2401; and at least one memory 2402 and bus 2403 connected to the processor 2401; wherein the processor 2401 and the memory 2402 communicate with each other through the bus 2403; the processor 2401 is used to call program instructions in the memory 2402 to execute the method of controlling charging time based on load end capacity in one or more of the above embodiments.

[0135] It should be noted that the above description of the system embodiment for controlling charging time based on load-side capacitance is similar to the description of the method embodiment for controlling charging time based on load-side capacitance, and has similar beneficial effects. For any technical details not disclosed in the system embodiment of the present invention, please refer to the description of the method embodiment for controlling charging time based on load-side capacitance.

[0136] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of controlling charging time based on load end capacitance value, characterized by, The method comprises the following steps: According to the solid-state power control unit circuit, a corresponding simulation model is established in a dynamic system modeling tool, and a fitting curve is determined through the simulation model, the fitting curve being used to indicate the law between the ratio of the preset real part of the load end at different angular frequencies and the capacitance value; the solid-state power control unit circuit is connected with a sampling circuit, an FPGA and a load end; The solid-state power control unit circuit is controlled to turn on and turn off the current limiting branch to generate a current response signal and a voltage signal at the load end, and the sampling circuit, Fourier transform, the FPGA and the fitting curve are used to process the current response signal and the voltage signal in sequence to obtain the capacitance value of the load end; According to the maximum value of a plurality of preset capacitance value ranges, the resistance of the current limiting branch and the capacitance value of the load end, the turn-on time of the current limiting branch is determined, and the current limiting branch is turned on according to the turn-on time to complete the charging of the capacitance of the load end.

2. The method of controlling the charging time based on the load end capacitance value according to claim 1, wherein, The control of the solid-state power control unit circuit to turn on and turn off the current limiting branch to generate a current response signal and a voltage signal at the load end, and the use of the sampling circuit, Fourier transform, the FPGA and the fitting curve to process the current response signal and the voltage signal in sequence to obtain the capacitance value of the load end, comprises: The MOSFET device in the current limiting branch is controlled to turn on and turn off to generate the current response signal and the voltage signal at the load end; The sampling circuit is used to sample the current response signal and the voltage signal to obtain discrete current response signals and discrete voltage signals; The discrete current response signals and the discrete voltage signals are subjected to Fourier transform to obtain transformed current response signals and transformed voltage signals; According to the transformed current response signals and the transformed voltage signals, a discrete impedance expression is determined; The FPGA provided with the discrete impedance expression and a plurality of angular frequencies are used to determine the ratio of the target real part of the load end at different angular frequencies, and the plurality of angular frequencies are all different; The ratio of the target real part of the load end at different angular frequencies is substituted into the fitting curve to obtain the capacitance value of the load end.

3. The method of controlling charging time based on load end inductance value according to claim 2, characterized in that, The control of the MOSFET device in the current limiting branch to turn on and turn off to generate the current response signal and the voltage signal at the load end comprises: The MOSFET device in the current limiting branch is controlled to turn on and turn off to generate a square wave signal; The square wave signal is controlled to flow through the load end to generate the corresponding current response signal and voltage signal at the load end.

4. The method of controlling charging time based on load end capacitance value according to claim 2, characterized in that, The use of the FPGA provided with the discrete impedance expression and a plurality of angular frequencies to determine the ratio of the target real part of the load end at different angular frequencies comprises: The FPGA provided with the discrete impedance expression is used to determine the real part of the load end at a target angular frequency, and the target angular frequency is different from the plurality of angular frequencies; According to the real part of the load end at the target angular frequency and the plurality of angular frequencies, the target real part of the load end at different angular frequencies is determined. Determine a ratio of target real parts of the load end at different angular frequencies according to the target real parts of the load end at the different angular frequencies.

5. The method of controlling charging time based on load end capacitance value according to claim 2, characterized in that, The discrete impedance expression is: ； wherein, is the discrete impedance, is a discrete time sequence corresponding to the discrete voltage signal, is a first discrete time sequence corresponding to the voltage signal, is a sampling period, is a length of the discrete time sequence corresponding to the discrete voltage signal, is a discrete time sequence corresponding to the discrete current response signal, is a first discrete time sequence corresponding to the discrete current response signal, is a length of the discrete time sequence corresponding to the discrete current response signal, is the imaginary unit, is a length of the discrete time sequence corresponding to the discrete signal.

6. The method for controlling charging time based on load end capacitance value according to claim 1, characterized in that, Determine the turn-on time of the current limiting branch according to the maximum of the plurality of preset capacitance value ranges, the resistance of the current limiting branch, and the capacitance value of the load end, and control the current limiting branch to turn on according to the turn-on time, so that the capacitance of the load end is fully charged, including: Determine a plurality of turn-on times corresponding to the plurality of preset capacitance value ranges according to the maximum of the plurality of preset capacitance value ranges and the resistance of the current limiting branch; Establish a correspondence table of the plurality of preset capacitance value ranges and the plurality of turn-on times; Determine a target preset capacitance value range corresponding to the capacitance value of the load end, and the plurality of preset capacitance value ranges include the target preset capacitance value range; In the correspondence table, find the turn-on time corresponding to the target preset capacitance value range; Control the current limiting branch to turn on according to the turn-on time, so that the capacitance of the load end is fully charged.

7. The method of controlling charging time based on load end inductance value according to claim 6, characterized in that, Determine a plurality of turn-on times corresponding to the plurality of preset capacitance value ranges according to the maximum of the plurality of preset capacitance value ranges and the resistance of the current limiting branch, including: Determine a plurality of time constants corresponding to the maximum of the plurality of preset capacitance value ranges and the resistance of the current limiting branch; Determine the plurality of turn-on times according to the plurality of time constants and a preset value.

8. A system for controlling charging time based on load end capacitance value, characterized in that, Including: The establishing module is configured to establish a corresponding simulation model in a dynamic system modeling tool according to a solid-state power control unit circuit, and determine a fitting curve through the simulation model, the fitting curve being used to indicate a rule between a ratio of preset real parts of a load end at different angular frequencies and a capacitance value; the solid-state power control unit circuit is connected with a sampling circuit, an FPGA, and the load end; The processing module is configured to control a current limiting branch in the solid-state power control unit circuit to turn on and turn off, so as to generate a current response signal and a voltage signal at the load end, and process the current response signal and the voltage signal in sequence by using the sampling circuit, Fourier transform, the FPGA, and the fitting curve, to obtain a capacitance value of the load end; The control module is configured to determine a turn-on time of the current limiting branch according to a maximum of a plurality of preset capacitance value ranges, a resistance of the current limiting branch, and a capacitance value of the load end, and control the current limiting branch to turn on according to the turn-on time, so that the capacitance of the load end is fully charged.

9. The system for controlling charging time based on load end inductance value according to claim 8, characterized in that, The processing module is specifically configured to control the turn-on and turn-off of the MOSFET device in the current limiting branch to generate the current response signal and the voltage signal at the load end; sample the current response signal and the voltage signal by using the sampling circuit to obtain discrete current response signals and discrete voltage signals; perform Fourier transform on the discrete current response signals and the discrete voltage signals to obtain transformed current response signals and transformed voltage signals; determine a discrete impedance expression according to the transformed current response signals and the transformed voltage signals; determine the ratio of the target real part of the load end at different angular frequencies by using the FPGA provided with the discrete impedance expression and a plurality of angular frequencies, the plurality of angular frequencies being all different; and substitute the ratio of the target real part of the load end at the different angular frequencies into the fitting curve to obtain the capacitance value of the load end.

10. An electronic device, comprising: The electronic device comprises: at least one processor; and at least one memory connected with the processor through a bus; wherein the processor, the memory complete mutual communication through the bus; the processor is used to call the program instruction in the memory, to execute the method for controlling the charging time based on the load end capacitance value as claimed in any one of claims 1 to 7.

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