Transverse double-diffused field effect transistor and manufacturing method thereof

Abstract

A well region, an intrinsic epitaxial layer, a first ion implantation region and a second ion implantation region are formed on a substrate, the intrinsic epitaxial layer is located between the well region and the second ion implantation region, a voltage is applied to a second metal layer to enable the device to be normally started, and the first ion implantation region and the second ion implantation region are formed. The intrinsic epitaxial layer is added, so that a conducting channel is wider, the on-resistance is reduced, the first ion injection region comprises a plurality of layers of injection regions, a first selective injection region and a second selective injection region which are sequentially arranged relative to the intrinsic epitaxial layer, and when the device is in a reverse biased cut-off state, the on-resistance is reduced. High voltage of the third metal layer is conducted to the multi-layer injection region through the second selective injection region and the first selective injection region, a reverse bias state is formed in the multi-layer injection region, a space charge region is widened, the multi-layer injection region is totally changed into a depletion region in the longitudinal direction and is depleted towards the intrinsic epitaxial layer on the left side, the intrinsic epitaxial layer continues to form reverse bias with the well region after being depleted, and the depletion region continues to be widened; higher voltage can be borne, and meanwhile, the overall area of the device is not increased.

Description

Technical Field

[0001] This invention belongs to the technical field of semiconductor device fabrication processes, and particularly relates to a lateral double-diffused field-effect transistor and its fabrication method. Background Technology

[0002] In the field of electronic devices, the laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) is a widely used voltage-controlled device. It has three terminals: gate, source, and drain. When the voltage applied to the gate is greater than the threshold voltage, a conductive channel is formed between the drain and source, and the device is in the on-state. When the gate voltage is less than the threshold voltage, the current between the drain and source is cut off, and the device is in the off-state. For example, patent application number 202310376829.0 discloses a gate-controlled resurf high-voltage LDMOS structure. Specifically, by adding a new gate, the LDMOS structure in the off-state is close to a conventional off-state resurf LDMOS structure. Furthermore, by turning on the P-top layer in the on-state, an inversion channel is formed in the drift region to reduce the specific on-resistance, thereby achieving superior "voltage withstand capability-specific conductance" characteristics.

[0003] However, conventional LDMOS structures, such as Figure 1 As shown, in traditional LDMOS designs, to enable the drain-source junction to withstand higher voltages without breakdown (i.e., to achieve a higher drain-source breakdown voltage), the drift region is typically lengthened. However, this approach has significant drawbacks. Lengthening the drift region increases the LDMOS's on-state resistance and also increases the device's area, which is highly detrimental to designs requiring the integration of numerous devices, increasing integration difficulty and cost. Therefore, there is an urgent need for a novel lateral double-diffused field-effect transistor (LDMOSFET) that possesses higher drain-source breakdown voltage characteristics while maintaining relatively low on-resistance, thereby addressing the aforementioned problems in existing LDMOS technology. Summary of the Invention

[0004] In view of this, the present invention provides a lateral double-diffused field-effect transistor and its fabrication method, which has higher drain-source breakdown voltage characteristics and lower on-resistance. The specific technical solution is as follows.

[0005] In a first aspect, the present invention provides a lateral double-diffused field-effect transistor, comprising: Substrate of the first conductivity type; A well region of a first conductivity type is formed on one side of the substrate, a first ion implantation region is located on the other side of the substrate, and an intrinsic epitaxial layer is located between the well region and the first ion implantation region. The first ion implantation region includes a multilayer implantation region connected to the intrinsic epitaxial layer, a first selective implantation region of a second conductivity type, and a second selective implantation region of a second conductivity type located at the edge of the substrate. The multilayer implantation region is located between the intrinsic epitaxial layer and the first selective implantation region, and the first selective implantation region is located between the multilayer implantation region and the second selective implantation region. A second ion implantation region of a second conductivity type is formed within the well region, the second ion implantation region including a third selective implantation region and a fourth selective implantation region of a second conductivity type located within the third selective implantation region; The trap region extends along one side of the second ion implantation region to the silicon oxide layer on the multilayer implantation region and the polycrystalline silicon layer located on the silicon oxide layer; A first barrier layer is formed on a third selective implantation region on one side of the polysilicon layer and located between the fourth selective implantation region and the well region, and a second barrier layer is formed on a first selective implantation region on the other side of the polysilicon layer; A first metal layer is formed on the fourth selective implantation region, a second metal layer is located on the polysilicon layer corresponding to the intrinsic epitaxial layer, and a third metal layer is formed on the second selective implantation region.

[0006] As a preferred embodiment of the above technical solution, the first conductivity type is P-type and the second conductivity type is N-type.

[0007] As a preferred embodiment of the above technical solution, the multilayer implantation region includes a first ion implantation sub-region of a second conductivity type formed on the upper surface of the substrate, a second ion implantation sub-region of a first conductivity type located on the first ion implantation sub-region, a third ion implantation sub-region of a second conductivity type located on the second ion implantation sub-region, a fourth ion implantation sub-region of a first conductivity type located on the third ion implantation sub-region, and a fifth ion implantation sub-region of a second conductivity type located on the fourth ion implantation sub-region. The first ion implantation sub-region, the second ion implantation sub-region, the third ion implantation sub-region, the fourth ion implantation sub-region, and the fifth ion implantation sub-region are aligned in a direction perpendicular to the substrate.

[0008] Secondly, the present invention also provides a method for manufacturing a lateral double-diffused field-effect transistor, comprising the following steps: A substrate of a first conductivity type is provided, and an intrinsic epitaxial layer is formed on the substrate; A well region of a first conductivity type is formed in an intrinsic epitaxial layer on one side of the substrate. The intrinsic epitaxial layer is photolithographically lithographically and ion implanted to form a multilayer implanted region. The multilayer implanted region is located between a first intrinsic subregion and a second intrinsic subregion. The first intrinsic subregion is located between the well region and the multilayer implanted region. The second intrinsic subregion is located at the edge of the substrate. The first intrinsic subregion and the second intrinsic subregion belong to the intrinsic epitaxial layer. A silicon oxide layer is grown on the well region, the intrinsic epitaxial layer and the multilayer implantation region, and polysilicon is deposited on the silicon oxide layer. Photolithography is used to etch away part of the silicon oxide layer and the polysilicon to form a silicon oxide layer and a polysilicon layer located on the well region and the first intrinsic subregion. Ion implantation is performed on the edge of the well region and the second intrinsic sub-region to respectively form a second ion implantation region of the second conductivity type and a second selective implantation sub-region located within the well region; TEOS is deposited on the second ion implantation region and the second selective implantation sub-region, and a portion of the TEOS is etched away to form a first barrier layer on one side of the polysilicon layer and a second barrier layer on the other side of the polysilicon layer. Ion implantation is performed on the second ion implantation region according to the first barrier layer to form a third selective implantation region and a fourth selective implantation region of the second conductivity type located within the third selective implantation region. Ion implantation is also performed on the second selective implantation sub-region according to the second barrier layer to form a second selective implantation region and a first selective implantation region of the second conductivity type located between the multilayer implantation region and the second selective implantation region and corresponding to the second barrier layer. A first metal layer is formed on the fourth selective implantation region, a second metal layer corresponding to the first intrinsic subregion is formed on the polysilicon layer, and a third metal layer is formed on the second selective implantation region.

[0009] As a preferred embodiment of the above technical solution, the first conductivity type is P-type, the second conductivity type is N-type, the resistivity of the substrate is 40~70 ohm*cm, and the growth thickness of the intrinsic epitaxial layer is 8~12μm.

[0010] As a preferred embodiment of the above technical solution, the multilayer implantation region includes a first ion implantation sub-region of a second conductivity type formed on the upper surface of the substrate, a second ion implantation sub-region of the first conductivity type located on the first ion implantation sub-region, a third ion implantation sub-region of the second conductivity type located on the second ion implantation sub-region, a fourth ion implantation sub-region of the first conductivity type located on the third ion implantation sub-region, and a fifth ion implantation sub-region of the second conductivity type located on the fourth ion implantation sub-region. The first ion implantation sub-region, the second ion implantation sub-region, the third ion implantation sub-region, the fourth ion implantation sub-region, and the fifth ion implantation sub-region are aligned in a direction perpendicular to the substrate. The implantation energy of the first ion implantation sub-region, the second ion implantation sub-region, the third ion implantation sub-region, the fourth ion implantation sub-region, and the fifth ion implantation sub-region decreases sequentially. The implantation dose range of the multilayer implantation region is 1E11~1E13cm. -2 The injection energy range of the multilayer injection region is 20~1000keV.

[0011] As a preferred embodiment of the above technical solution, the ion implantation dose of the fourth selective implantation region is less than the ion implantation dose of the third selective implantation region, and the implantation dose of the second selective implantation sub-region is 2E13~5E14 cm⁻¹. -2 .

[0012] As a preferred embodiment of the above technical solution, the injection depth of the fourth selective injection region is less than the injection depth of the third selective injection region, and the injection depth of the second selective injection sub-region is the same as the injection depth of the first ion implantation sub-region.

[0013] As a preferred embodiment of the above technical solution, the injection dose in the well region is 3E12~6E12cm. -2 The injection energy is 100~120keV; the thickness of the polycrystalline silicon layer is 3000~6000Å, and the resistivity of the polycrystalline silicon layer is 0.001~0.01Ω*cm.

[0014] As a preferred embodiment of the above technical solution, the initial deposition thickness of the TEOS is 3000~6000 Å, the first metal layer is the source of the lateral double-diffused field-effect transistor, the second metal layer is the gate of the lateral double-diffused field-effect transistor, and the third metal layer is the drain of the lateral double-diffused field-effect transistor.

[0015] This invention provides a lateral double-diffused field-effect transistor (LDMOS) and its fabrication method. By forming a well region, an intrinsic epitaxial layer, a first ion implantation region, and a second ion implantation region on a substrate, with the intrinsic epitaxial layer located between the well region and the second ion implantation region, a voltage is applied to the second metal layer to enable normal device operation. Increasing the intrinsic epitaxial layer widens the conductive channel and reduces the on-resistance. The first ion implantation region includes a multilayer implantation region, a first selective implantation region, and a second selective implantation region arranged sequentially relative to the intrinsic epitaxial layer. When the LDMOS is in reverse-biased off-state, the high voltage of the third metal layer is conducted through the second selective implantation region and the first selective implantation region to the multilayer implantation region, forming a reverse-biased state. The space charge region widens, and the entire longitudinal direction becomes a depletion region, depleting towards the intrinsic epitaxial layer on the left. After the intrinsic epitaxial layer is depleted, it continues to form a reverse bias with the well region, and the depletion region continues to widen. The LDMOS of this invention can withstand higher voltages without increasing the overall device area. Attached Figure Description

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 This is a schematic diagram of the structure of a conventional lateral double-diffusion field-effect transistor; Figure 2 A flowchart illustrating the fabrication method of the lateral double-diffused field-effect transistor provided by the present invention; Figure 3 This is a schematic diagram of the structure of the transverse double-diffusion field-effect transistor provided by the present invention; Figures 4 to 11 This is a process diagram illustrating the fabrication method of the lateral double-diffused field-effect transistor provided by the present invention.

[0018] The symbols for the main components are explained below: 10-Substrate; 20-Trap region; 30-First ion implantation region; 31-Multilayer implantation region; 310-First ion implantation sub-region; 311-Second ion implantation sub-region; 312-Third ion implantation sub-region; 313-Fourth ion implantation sub-region; 314-Fifth ion implantation sub-region; 32-First selective implantation region; 33-Second selective implantation region; 34-Second selective implantation sub-region; 40-Intrinsic epitaxial layer; 41-First intrinsic sub-region; 42-Second intrinsic sub-region; 50-Second ion implantation region; 51-Third selective implantation region; 52-Fourth selective implantation region; 60-Silicon oxide layer; 70-Polysilicon layer; 80-First barrier layer; 90-Second barrier layer; 100-First metal layer; 110-Second metal layer; 120-Third metal layer; 130-First N+ implantation region; 140-Second N+ implantation region; 150-Drift region. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] It should be noted that when an element is said to be "fixed to" another element, it can be directly on the other element or there may be an intervening element. When an element is said to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is said to be "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] See Figure 2 , Figures 4 to 11 The present invention also provides a method for fabricating a lateral double-diffused field-effect transistor, comprising the following steps: S1: Provide a substrate 10 of a first conductivity type, and form an intrinsic epitaxial layer 40 on the substrate 10; In this embodiment, as Figure 4 As shown, the first conductivity type is P-type, the second conductivity type is N-type, the intrinsic epitaxial layer 40 is an epitaxial layer, the resistivity of the substrate 10 is 40~70 ohm*cm, and the growth thickness of the intrinsic epitaxial layer 40 is 8~12μm. The substrate 10 is made of silicon wafer, and the intrinsic epitaxial layer is grown on the surface of the P-type silicon substrate.

[0022] S2: A well region 20 of a first conductivity type is formed in the intrinsic epitaxial layer 40 on one side of the substrate 10. The intrinsic epitaxial layer 40 is photolithographically lithographically and ion-implanted to form a multilayer implantation region 31. The multilayer implantation region 31 is located between the first intrinsic sub-region 41 and the second intrinsic sub-region 42. The first intrinsic sub-region 41 is located between the well region 20 and the multilayer implantation region 31, and the second intrinsic sub-region 42 is located at the edge of the substrate 10. The first intrinsic sub-region 41 and the second intrinsic sub-region 42 belong to the intrinsic epitaxial layer 40. In this embodiment, as Figure 5 and Figure 6 As shown, the multilayer implantation region 31 includes a first ion implantation sub-region 310 of the second conductivity type formed on the upper surface of the substrate 10, a second ion implantation sub-region 311 of the first conductivity type located on the first ion implantation sub-region 310, a third ion implantation sub-region 312 of the second conductivity type located on the second ion implantation sub-region 311, a fourth ion implantation sub-region 313 of the first conductivity type located on the third ion implantation sub-region 312, and a fifth ion implantation sub-region 314 of the second conductivity type located on the fourth ion implantation sub-region 313. The first ion implantation sub-region 310, the second ion implantation sub-region 311, the third ion implantation sub-region 312, the fourth ion implantation sub-region 313, and the fifth ion implantation sub-region 314 are aligned in a direction perpendicular to the substrate 10. The implantation energy of the first ion implantation sub-region 310, the second ion implantation sub-region 311, the third ion implantation sub-region 312, the fourth ion implantation sub-region 313, and the fifth ion implantation sub-region 314 decreases sequentially. The implantation dose range of the multilayer implantation region 31 is 1E11~1E13 cm⁻¹. -2 The injection energy range of the multilayer injection region 31 is 20~1000keV.

[0023] It should be noted that the intrinsic epitaxial layer in S1 involves coating with photoresist (coating), photolithography, defining the PW region (P-well region 20) window, and then forming the PW region through ion implantation or diffusion and doping. Preferably, boron is implanted into the PW region, and the implantation dose of the well region 20 is 3E12~6E12 cm⁻¹. -2The implantation energy is 100~120 keV. A multilayer implantation region 31 is formed through photolithography and ion implantation, resulting in a multilayer structure of N1, P1, N2, P2, and N3. Preferably, high-energy ion implantation is used first to form the deepest N1 region, followed by sequentially decreasing the implantation energy to form the P1, N2, P2, and N3 regions. These five layers are vertically aligned. Boron is implanted into the P1 and P2 regions, while phosphorus is implanted into the N1, N2, and N3 regions. This ensures that when the device is in reverse bias cutoff, the multilayer implantation region 31 forms a depletion region vertically, allowing the device to withstand higher voltages. In other words, the multilayer implantation region 31 and the substrate 10 can form multiple reverse PN junctions, improving the device's internal breakdown voltage characteristics.

[0024] S3: A silicon oxide layer 60 is grown on the well region 20, the intrinsic epitaxial layer 40 and the multilayer implantation region 31, and polysilicon is deposited on the silicon oxide layer 60. Photolithography is used to etch away part of the silicon oxide layer 60 and the polysilicon to form a silicon oxide layer 60 and a polysilicon layer 70 on the silicon oxide layer 60 located on the well region 20 and the first intrinsic sub-region 41. In this embodiment, as Figure 7 As shown, the silicon wafer is first cleaned, then a gate silicon oxide layer (silicon oxide layer 60) is grown, and a heavily doped N-type polysilicon poly layer (polysilicon layer 70) is deposited. Excess polysilicon and gate silicon oxide layers are then removed using photolithography and etching processes. The thickness of the gate silicon oxide layer is determined according to the required gate breakdown voltage; the thickness of the polysilicon layer 70 is 3000~6000 Å, and the resistivity of the polysilicon layer 70 is 0.001~0.01 Ω*cm. The etching process preferably uses dry etching to first remove the polysilicon poly layer, then remove the gate silicon oxide layer. The boundary of one side of the gate silicon oxide layer is aligned with the N1~N3 regions, and the polysilicon layer 70 is aligned with the silicon oxide layer 60.

[0025] S4: Ion implantation is performed on the edge of the well region 20 and the second intrinsic sub-region 42 to form a second ion implantation region 50 and a second selective implantation sub-region 34 of the second conductivity type located in the well region 20, respectively. In this embodiment, as Figure 8 As shown, both the second ion implantation region 50 and the second selective implantation sub-region 34 are N-regions, i.e., lightly doped implantation regions. The ion implantation depth of the second ion implantation region 50 is less than that of the second selective implantation sub-region 34. In other words, N-region selective implantation is performed through processes such as photolithography, implantation, and resist removal. Preferably, the N-implantation in the source region on the left side of the substrate 10 (second ion implantation region 50) is shallower; the N-implantation in the drain region on the right side (second selective implantation sub-region 34) is deeper, at the same depth as the N1 region. The implanted element is phosphorus, and the implantation dose of the second selective implantation sub-region 34 is 2E13~5E14 cm⁻¹. -2The second ion implantation region 50 is ion implanted along the left side of the polysilicon layer 70 and the silicon oxide layer 60 into the well region 20, and the second selective implantation sub-region 34 facilitates the subsequent fabrication of the drain region.

[0026] S5: Deposit TEOS on the second ion implantation region 50 and the second selective implantation sub-region 34, and etch away part of the TEOS to form a first barrier layer 80 on one side of the polysilicon layer 70 and a second barrier layer 90 on the other side of the polysilicon layer 70. In this embodiment, as Figure 9 As shown, TEOS plays an irreplaceable role as an important deposition source, especially in the low-temperature silicon dioxide formation process. TEOS (tetraethoxysilane) is a common silicon source in chemical vapor deposition processes used to generate silicon dioxide thin films, which can serve as dielectric layers, isolation layers, or protective layers. The silicon wafer is first cleaned, then TEOS (dielectric layer) is deposited, and then the TEOS is removed by dry etching. Barrier layers are formed on both sides of the poly region: a first barrier layer 80 on the second ion implantation region 50 and a second barrier layer 90 on the second selective implantation sub-region 34. The initial deposition thickness of the TEOS is 3000~6000 Å.

[0027] S6: Ion implantation is performed on the second ion implantation region 50 according to the first barrier layer 80 to form a third selective implantation region 51 and a fourth selective implantation region 52 of the second conductivity type located in the third selective implantation region 51; and ion implantation is performed on the second selective implantation sub-region 34 according to the second barrier layer 90 to form a second selective implantation region 33 and a first selective implantation region 32 of the second conductivity type located between the multilayer implantation region 31 and the second selective implantation region 33 and corresponding to the second barrier layer 90. In this embodiment, as Figure 10 As shown, the first barrier layer 80 and the second barrier layer 90 serve as isolation or protective layers. Ion implantation is performed on the second ion implantation region 50 to form a fourth selective implantation region 52 located within the second ion implantation region 50, and the unimplanted second ion implantation region 50 serves as a third selective implantation region 51. Simultaneously, ion implantation is performed on the second selective implantation sub-region 34 to form a first selective implantation region 32 (denoted as the right N- region) and a second selective implantation region 33 (denoted as the right N+ region). The doping concentration of the first selective implantation region 32 is less than that of the second selective implantation region 33, and the doping concentration of the fourth selective implantation region 52 (denoted as the left N+ region) is greater than that of the third selective implantation region 51 (denoted as the left N- region). The fourth selective implantation region 52 is the source region of the device, and the second selective implantation region 33 is the drain region of the device.

[0028] It should be noted that the implantation depth of the fourth selective implantation region 52 is less than that of the third selective implantation region 51, and the implantation depth of the second selective implantation sub-region 34 is the same as that of the first ion implantation sub-region 310. Selective implantation of the N+ region is performed first, followed by photolithography, implantation, and resist removal processes. Preferably, the N+ implantation in the left source region is shallower (fourth selective implantation region 52) and shallower than that in the N- region (third selective implantation region 51); the N+ implantation in the right drain region is deeper (second selective implantation region 33), at the same depth as the N1 region. The implanted element is phosphorus, and the implantation dose is 2E15~1E16 cm⁻¹. -2 .

[0029] S7: A first metal layer 100 is formed on the fourth selective implantation region 52, a second metal layer 110 corresponding to the first intrinsic subregion 41 is formed on the polysilicon layer 70, and a third metal layer 120 is formed on the second selective implantation region 33.

[0030] In this embodiment, as Figure 11 As shown, the first metal layer 100 is the source of the lateral double-diffused field-effect transistor, the second metal layer 110 is the gate of the lateral double-diffused field-effect transistor, and the third metal layer 120 is the drain of the lateral double-diffused field-effect transistor. Metal deposition is first performed on the upper surface of the substrate 10, and then the source metal, gate metal, and drain metal are formed by photolithography and etching.

[0031] It should be noted that the lateral double-diffused field-effect transistor provided by this invention can be turned on normally when the gate voltage is greater than the threshold voltage. Due to the addition of the intrinsic epitaxial layer, the carrier density attracted to its surface is higher and the conductive channel is wider, resulting in lower resistance when conducting. When the lateral double-diffused field-effect transistor is in the reverse-biased cutoff state, the high drain voltage is conducted to the N1, N2, and N3 regions through the deep N+ and deep N- regions, forming a reverse bias with the vertical P1 and P2 regions. The space charge region widens, and eventually the entire vertical region becomes a depletion region. Then, it is depleted to the intrinsic epitaxial layer on the left. After the intrinsic epitaxial layer is depleted, it continues to form a reverse bias with PW, and the depletion region continues to widen. Therefore, the lateral double-diffused field-effect transistor provided by this invention can withstand higher voltages without increasing the overall device area.

[0032] See Figure 3 The present invention provides a lateral double-diffused field-effect transistor, comprising: Substrate 10 of the first conductivity type; A first conductivity type well region 20, a first ion implantation region 30, and an intrinsic epitaxial layer 40 are formed on one side of the substrate 10, the first conductivity type well region 20, the first ion implantation region 30, the first ion implantation region 30, the first ion implantation region 30, the first conductivity type well region 31, the first selective implantation region 32, the second conductivity type well region 33, and the second selective implantation region 33, the second conductivity type well region 32, which are located at the edge of the substrate 10. The multilayer implantation region 31 is located between the intrinsic epitaxial layer 40 and the first selective implantation region 32, and the first selective implantation region 32 is located between the multilayer implantation region 31 and the second selective implantation region 33. A second ion implantation region 50 of a second conductivity type is formed within the well region 20. The second ion implantation region 50 includes a third selective implantation region 51 and a fourth selective implantation region 52 of a second conductivity type located within the third selective implantation region 51. The trap region 20 extends along one side of the second ion implantation region 50 to the silicon oxide layer 60 on the multilayer implantation region 31 and the polysilicon layer 70 located on the silicon oxide layer 60; A first barrier layer 80 is formed on one side of the polysilicon 70 layer and on the third selective implantation region 51 located between the fourth selective implantation region 52 and the well region 20, and a second barrier layer 90 is formed on the first selective implantation region 32 on the other side of the polysilicon layer 70. A first metal layer 100 is formed on the fourth selective implantation region 52, a second metal layer 110 is located on the polysilicon layer 70 corresponding to the intrinsic epitaxial layer 40, and a third metal layer 120 is formed on the second selective implantation region 33.

[0033] In this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the intrinsic epitaxial layer 40 is an epitaxial layer, and the multilayer implantation region 31 includes a first ion implantation sub-region 310 of the second conductivity type formed on the upper surface of the substrate 10, a second ion implantation sub-region 311 of the first conductivity type located on the first ion implantation sub-region 310, a third ion implantation sub-region 312 of the second conductivity type located on the second ion implantation sub-region 311, a fourth ion implantation sub-region 313 of the first conductivity type located on the third ion implantation sub-region 312, and a fifth ion implantation sub-region 314 of the second conductivity type located on the fourth ion implantation sub-region 313. The first ion implantation sub-region 310, the second ion implantation sub-region 311, the third ion implantation sub-region 312, the fourth ion implantation sub-region 313, and the fifth ion implantation sub-region 314 are aligned in a direction perpendicular to the substrate 10. The first metal layer 100 is the source metal of the device (lateral double-diffused field-effect transistor, LDMOS), the second metal layer 110 is the gate metal of the device, the third metal layer 120 is the drain metal of the device, the silicon oxide layer 60 is the gate silicon oxide layer of the device, and the intrinsic epitaxial layer 40 is the epitaxial layer (intrinsic semiconductor refers to an ideal semiconductor without impurities or defects, that is, it is imagined that there are no impurity atoms in the semiconductor, and the arrangement of atoms in space also follows a strict periodicity).

[0034] like Figure 1As shown, a conventional lateral double-diffused field-effect transistor mainly includes a P-type substrate, a P-type well region 20 and an N-type drift region 150 formed on the substrate 10, a first N+ implantation region 130 located in the well region 20 and a second N+ implantation region 140 located in the drift region 150, a silicon oxide layer 60 between the first N+ implantation region 130 and the second N+ implantation region 140, a polysilicon layer 70 on the silicon oxide layer 60, a first metal layer 100 formed on the first N+ implantation region 130, a second metal layer 110 formed on the polysilicon layer 70, and a third metal layer 120 formed on the second N+ implantation region 140. In this design, the first N+ injection region 130 is the source region of a conventional lateral double-diffused field-effect transistor (LDMOS), the second N+ injection region 140 is the drain region of the same transistor, the first metal layer 100 is the source metal, the second metal layer 110 is the gate metal, and the third metal layer 120 is the drain metal. To achieve a higher drain-source breakdown voltage, the drift region 150 is typically lengthened. This increases the on-resistance of the LDMOS and correspondingly increases the device area, which is detrimental to integrated design. To address the technical problem of traditional LDMOS requiring high drain-source breakdown voltage, this invention adds an intrinsic epitaxial layer 40. The intrinsic epitaxial layer 40 is located between the well region 20 and the second ion implantation region 50, and is located below the gate oxide layer, i.e., below the gate metal. When a voltage is applied to the gate metal and the gate voltage is greater than the threshold voltage, the device can be turned on normally. The carrier density attracted to its surface will be higher, the conductive channel will be wider, and therefore the resistance will be lower when it is turned on.

[0035] It should be noted that the first ion implantation region 30 includes a multilayer implantation region 31, a first selective implantation region 32, and a second selective implantation region 33 arranged sequentially relative to the intrinsic epitaxial layer 40. The conductivity type of the first selective implantation region 32 and the second selective implantation region 33 is N. The doping concentration of the first selective implantation region 32 is less than that of the second selective implantation region 33. The multilayer implantation region 31 is composed of multiple implantation sub-regions of different conductivity types forming a PN junction in series. The second ion implantation region 50 includes a third selective implantation region 51 and a fourth selective implantation region 52 of the same conductivity type. The third selective implantation region 51 and the fourth selective implantation region 52 form PN junctions with the well region 20, respectively. When the LDMOS is in the reverse bias cutoff state, the high drain voltage is conducted through the deep N+ region (second selective implantation region 33) and N- region (first selective implantation region 32) to the N1 region (first ion implantation sub-region 310), N2 region (third ion implantation sub-region 312), and N3 region (fifth ion implantation sub-region 314). N1, N2, and N3 form a reverse bias state with the vertical P1 region (second ion implantation sub-region 311) and P2 region (fourth ion implantation sub-region 313), and the space charge region widens. Eventually, the entire vertical region becomes a depletion region, and then the intrinsic epitaxial layer on the left is depleted. After the intrinsic epitaxial layer is depleted, it continues to form a reverse bias with PW (well region 20), and the depletion region continues to widen. Therefore, the LDMOS of this invention can withstand higher voltages, while the overall device area does not increase. The potential change depends on the distribution of impurities in the semiconductor, while the width of the space charge region depends on the impurity concentration of the semiconductor. The higher the doping concentration, the narrower the corresponding space charge region. In addition, the width of the space charge region is also controlled by the applied voltage. When the applied voltage strengthens the electric field of the space charge region, the space charge region widens. Conversely, when the applied voltage weakens the electric field of the space charge region, the space charge region narrows. By utilizing the characteristic that the width of the space charge region changes with the applied voltage, various semiconductor devices can be fabricated.

[0036] It should be understood that by forming a well region 20, an intrinsic epitaxial layer 40, a first ion implantation region 30, and a second ion implantation region 40 on the substrate 10, with the intrinsic epitaxial layer 40 located between the well region 20 and the second ion implantation region 50, and applying voltage to the second metal layer 110 to enable normal device operation, the addition of the intrinsic epitaxial layer 40 makes the conductive channel wider and reduces the on-resistance. The first ion implantation region 30 includes a multilayer implantation region 31, a first selective implantation region 32, and a second selective implantation region 33 arranged sequentially relative to the intrinsic epitaxial layer 40. When the LDMOS is in the reverse bias cutoff state, the high voltage of the third metal layer 120 is conducted to the multilayer implantation region 31 through the second selective implantation region 33 and the first selective implantation region 32, forming a reverse bias state in the multilayer implantation region 31, widening the space charge region, and turning the entire longitudinal direction into a depletion region that depletes towards the intrinsic epitaxial layer 40 on the left. After the intrinsic epitaxial layer 40 is depleted, it continues to form a reverse bias with the well region 20, and the depletion region continues to widen. The LDMOS of the present invention can withstand higher voltages, while the overall device area does not increase.

[0037] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0039] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A lateral double-diffusion field-effect transistor, characterized in that, include: Substrate of the first conductivity type; A well region of a first conductivity type is formed on one side of the substrate, a first ion implantation region is located on the other side of the substrate, and an intrinsic epitaxial layer is located between the well region and the first ion implantation region. The first ion implantation region includes a multilayer implantation region connected to the intrinsic epitaxial layer, a first selective implantation region of a second conductivity type, and a second selective implantation region of a second conductivity type located at the edge of the substrate. The multilayer implantation region is located between the intrinsic epitaxial layer and the first selective implantation region, and the first selective implantation region is located between the multilayer implantation region and the second selective implantation region. A second ion implantation region of a second conductivity type is formed within the well region, the second ion implantation region including a third selective implantation region and a fourth selective implantation region of a second conductivity type located within the third selective implantation region; The trap region extends along one side of the second ion implantation region to the silicon oxide layer on the multilayer implantation region and the polycrystalline silicon layer located on the silicon oxide layer; A first barrier layer is formed on a third selective implantation region on one side of the polysilicon layer and located between the fourth selective implantation region and the well region, and a second barrier layer is formed on a first selective implantation region on the other side of the polysilicon layer; A first metal layer is formed on the fourth selective implantation region, a second metal layer is located on the polysilicon layer corresponding to the intrinsic epitaxial layer, and a third metal layer is formed on the second selective implantation region.

2. The lateral double-diffusion field-effect transistor according to claim 1, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

3. The transverse double-diffusion field-effect transistor according to claim 2, characterized in that, The multilayer implantation region includes a first ion implantation sub-region of a second conductivity type formed on the upper surface of the substrate, a second ion implantation sub-region of a first conductivity type located on the first ion implantation sub-region, a third ion implantation sub-region of a second conductivity type located on the second ion implantation sub-region, a fourth ion implantation sub-region of a first conductivity type located on the third ion implantation sub-region, and a fifth ion implantation sub-region of a second conductivity type located on the fourth ion implantation sub-region. The first ion implantation sub-region, the second ion implantation sub-region, the third ion implantation sub-region, the fourth ion implantation sub-region, and the fifth ion implantation sub-region are aligned in a direction perpendicular to the substrate.

4. A method for fabricating a lateral double-diffused field-effect transistor, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, and an intrinsic epitaxial layer is formed on the substrate; A well region of a first conductivity type is formed in an intrinsic epitaxial layer on one side of the substrate. The intrinsic epitaxial layer is photolithographically lithographically and ion implanted to form a multilayer implanted region. The multilayer implanted region is located between a first intrinsic subregion and a second intrinsic subregion. The first intrinsic subregion is located between the well region and the multilayer implanted region. The second intrinsic subregion is located at the edge of the substrate. The first intrinsic subregion and the second intrinsic subregion belong to the intrinsic epitaxial layer. A silicon oxide layer is grown on the well region, the intrinsic epitaxial layer and the multilayer implantation region, and polysilicon is deposited on the silicon oxide layer. Photolithography is used to etch away part of the silicon oxide layer and the polysilicon to form a silicon oxide layer and a polysilicon layer located on the well region and the first intrinsic subregion. Ion implantation is performed on the edge of the well region and the second intrinsic sub-region to respectively form a second ion implantation region of the second conductivity type and a second selective implantation sub-region located within the well region; TEOS is deposited on the second ion implantation region and the second selective implantation sub-region, and a portion of the TEOS is etched away to form a first barrier layer on one side of the polysilicon layer and a second barrier layer on the other side of the polysilicon layer. Ion implantation is performed on the second ion implantation region according to the first barrier layer to form a third selective implantation region and a fourth selective implantation region of the second conductivity type located within the third selective implantation region. Ion implantation is also performed on the second selective implantation sub-region according to the second barrier layer to form a second selective implantation region and a first selective implantation region of the second conductivity type located between the multilayer implantation region and the second selective implantation region and corresponding to the second barrier layer. A first metal layer is formed on the fourth selective implantation region, a second metal layer corresponding to the first intrinsic subregion is formed on the polysilicon layer, and a third metal layer is formed on the second selective implantation region.

5. The method for fabricating a lateral double-diffused field-effect transistor according to claim 4, characterized in that, The first conductivity type is P-type, the second conductivity type is N-type, the resistivity of the substrate is 40~70 ohm*cm, and the growth thickness of the intrinsic epitaxial layer is 8~12μm.

6. The method for manufacturing a lateral double-diffused field-effect transistor according to claim 4, characterized in that, The multilayer implantation region includes a first ion implantation sub-region of a second conductivity type formed on the upper surface of the substrate, a second ion implantation sub-region of the first conductivity type located on the first ion implantation sub-region, a third ion implantation sub-region of the second conductivity type located on the second ion implantation sub-region, a fourth ion implantation sub-region of the first conductivity type located on the third ion implantation sub-region, and a fifth ion implantation sub-region of the second conductivity type located on the fourth ion implantation sub-region. The first, second, third, fourth, and fifth ion implantation sub-regions are aligned in a direction perpendicular to the substrate. The implantation energy of the first, second, third, fourth, and fifth ion implantation sub-regions decreases sequentially. The implantation dose range of the multilayer implantation region is 1E11~1E13 cm⁻¹. -2 The injection energy range of the multilayer injection region is 20~1000keV.

7. The method for manufacturing a lateral double-diffused field-effect transistor according to claim 6, characterized in that, The ion implantation dose in the fourth selective implantation region is less than the ion implantation dose in the third selective implantation region, and the implantation dose in the second selective implantation sub-region is 2E13~5E14 cm⁻¹. -2 .

8. The method for manufacturing a lateral double-diffused field-effect transistor according to claim 6, characterized in that, The injection depth of the fourth selective injection region is less than that of the third selective injection region, and the injection depth of the second selective injection sub-region is the same as that of the first ion implantation sub-region.

9. The method for manufacturing a lateral double-diffused field-effect transistor according to claim 4, characterized in that, The injection dose into the trap region is 3E12~6E12 cm⁻¹ -2 The injection energy is 100~120keV; the thickness of the polycrystalline silicon layer is 3000~6000Å, and the resistivity of the polycrystalline silicon layer is 0.001~0.01Ω*cm.

10. The method for manufacturing a lateral double-diffused field-effect transistor according to claim 4, characterized in that, The initial deposition thickness of the TEOS is 3000~6000 Å. The first metal layer is the source of the lateral double-diffused field-effect transistor, the second metal layer is the gate of the lateral double-diffused field-effect transistor, and the third metal layer is the drain of the lateral double-diffused field-effect transistor.

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