Vertical thin film transistor and manufacturing method thereof

Abstract

The invention discloses a vertical thin film transistor and a manufacturing method thereof. The vertical thin film transistor comprises a first semiconductor layer, a sacrificial layer, a second semiconductor layer, a third semiconductor layer, a first grid electrode, a source electrode and a drain electrode. The first semiconductor layer is disposed on the substrate and has a first heavily doped portion and an extension portion. The sacrificial layer covers the extension portion of the first semiconductor layer and exposes the first heavily doped portion. The second semiconductor layer is disposed on the sacrificial layer and has a second heavily doped portion. The third semiconductor layer covers and contacts a portion of the first heavily doped portion, a sidewall of the sacrificial layer, and a portion of the second heavily doped portion. In a direction perpendicular to the substrate, the second heavily doped portion overlaps the extension portion, and the first gate overlaps the second heavily doped portion, the extension portion and the third semiconductor layer. The source electrode and the drain electrode are electrically connected with the first heavily doped part and the second heavily doped part respectively.

Description

Technical Field

[0001] This invention relates to a transistor and a method for manufacturing the same, and more particularly to a vertical thin-film transistor and a method for manufacturing the same. Background Technology

[0002] To meet the demands of high-resolution, low-power, and high-frequency display operations, short-channel thin-film transistors (TFTs) with high switching speeds, high electron mobility, and smaller dimensions have become a key development focus. Among these, vertical TFTs, with their high integration capabilities, are particularly favored for their ability to further save layout space and manufacturing costs. However, existing vertical TFTs still face some challenges, such as poor fabrication process stability, which prevents their operational electrical performance from reaching the expected levels. Summary of the Invention

[0003] This invention provides a vertical thin-film transistor with an ultra-short channel and stable operating electrical properties.

[0004] This invention provides a method for manufacturing a vertical thin-film transistor, which has better manufacturing process stability and production yield.

[0005] The vertical thin-film transistor of the present invention includes a first semiconductor layer, a sacrificial layer, a second semiconductor layer, a third semiconductor layer, a first gate, a source, and a drain. The first semiconductor layer is disposed on a substrate and has a first heavily doped portion and an extended portion. The sacrificial layer covers the extended portion of the first semiconductor layer and exposes the first heavily doped portion. The second semiconductor layer is disposed on the sacrificial layer and has a second heavily doped portion. In a direction perpendicular to the substrate, the second heavily doped portion overlaps with the extended portion of the first semiconductor layer. The third semiconductor layer covers and contacts a portion of the first heavily doped portion, the sidewalls of the sacrificial layer, and a portion of the second heavily doped portion. In a direction perpendicular to the substrate, the first gate overlaps the second heavily doped portion, the extended portion, and the third semiconductor layer. The source and drain are electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

[0006] The method for manufacturing a vertical thin-film transistor according to the present invention includes forming a first semiconductor material layer on a substrate; forming a sacrificial layer on the first semiconductor material layer to cover a first portion of the first semiconductor material layer and expose a second portion of the first semiconductor material layer; forming a second semiconductor material layer on the sacrificial layer; performing a heavy doping process on the second portion of the first semiconductor material layer and the second semiconductor material layer; forming a third semiconductor layer on the first semiconductor material layer and the second semiconductor material layer after the heavy doping process; performing a laser annealing process on the first semiconductor layer and the second semiconductor material layer; forming a gate electrode and a source electrode on the substrate; and forming a drain electrode. After the heavy doping process and the laser annealing process, the first portion and the second portion of the first semiconductor material layer respectively form an extension portion and a first heavily doped portion of the first semiconductor material layer, and the second semiconductor material layer forms a second heavily doped portion of the second semiconductor material layer. The source electrode and the drain electrode are electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

[0007] Based on the above, in a vertical thin-film transistor and its manufacturing method according to an embodiment of the present invention, the first semiconductor layer, in addition to the first heavily doped portion, also has an extension portion extending between the sacrificial layer and the substrate. This extension portion prevents the subsequently formed third semiconductor layer from getting trapped in the gap between the sacrificial layer and the first heavily doped portion due to insufficient manufacturing process precision, thus avoiding the formation of an effective short channel. In other words, it can significantly improve the manufacturing process margin of the sacrificial layer, thereby enhancing the manufacturing process and operational stability of the vertical thin-film transistor. Attached Figure Description

[0008] Figure 1 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to the first embodiment of the present invention;

[0009] Figures 2A to 2F yes Figure 1 A cross-sectional schematic diagram of the manufacturing process of a vertical thin-film transistor;

[0010] Figures 3A to 3E yes Figure 1 A cross-sectional schematic diagram of another manufacturing process for vertical thin-film transistors;

[0011] Figure 4 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to a second embodiment of the present invention;

[0012] Figures 5A to 5F yes Figure 4 A cross-sectional schematic diagram of the manufacturing process of a vertical thin-film transistor;

[0013] Figure 6 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to a third embodiment of the present invention;

[0014] Figure 7 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to the fourth embodiment of the present invention;

[0015] Figures 8A to 8G yes Figure 7 A cross-sectional schematic diagram of the manufacturing process of a vertical thin-film transistor;

[0016] Figure 9 This is a cross-sectional schematic diagram of a component substrate according to an embodiment of the present invention;

[0017] Figures 10A to 10H yes Figure 9 A cross-sectional schematic diagram of the manufacturing process of the component substrate.

[0018] Symbol explanation:

[0019] 10, 10A, 10B, 10C, 10D: Component substrate

[0020] 100:Substrate

[0021] 105: Buffer layer

[0022] 110: First semiconductor layer

[0023] 110ex: Extended section

[0024] 110hd: First doped portion

[0025] 110M: First semiconductor material layer

[0026] 110Mp1: Part 1

[0027] 110Mp2: Part Two

[0028] 110s1, 110s2, 120s: Surface

[0029] 110t, 115t, 120t: Thickness

[0030] 115, 115A: Sacrificial Layer

[0031] 115M: Sacrificial Material Layer

[0032] 115Ma: First Sub-Sacrificial Material Layer

[0033] 115Mb: Second Subsacrificial Material Layer

[0034] 115sw: Sidewall

[0035] 120, 120A: Second semiconductor layer

[0036] 120ch: channel

[0037] 120hd: Second doped portion

[0038] 121hd: Third doped portion

[0039] 122hd: Fourth doped portion

[0040] 120M, 120M”: Second semiconductor material layer

[0041] 130, 130A: Third semiconductor layer

[0042] 130M: Third semiconductor material layer

[0043] 135: Dielectric layer

[0044] 145: Insulation layer

[0045] 160M: Etching protective material layer

[0046] 161: First Etched Protective Pattern

[0047] 162, 162A: Second etched protective pattern

[0048] CH: Passage Area

[0049] DE, DE': drain

[0050] GE, GE', GE”: gate

[0051] L: Extension length

[0052] LB: Laser beam

[0053] SE, SE': Source

[0054] SL1: First sub-layer

[0055] SL2: Second Sublayer

[0056] TFT: Thin Film Transistor

[0057] TH1: First contact hole

[0058] TH2: Second contact hole

[0059] VTFT, VTFT-A, VTFT-B, VTFT-C, VTFT-D: Vertical Thin Film Transistors

[0060] Z: Direction

[0061] θ: included angle Detailed Implementation

[0062] As used herein, “about,” “approximately,” “essentially,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or, for example, within ±30%, ±20%, ±15%, ±10%, ±5%. Furthermore, as used herein, “about,” “approximately,” “essentially,” or “substantially” may be used to select a more acceptable range of deviations or standard deviations depending on the nature of the measurement, the cutting nature, or other properties, and may not apply to all properties with a single standard deviation.

[0063] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it may be directly on or connected to the other element, or intermediate elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element, no intermediate elements are present. As used herein, "connection" can refer to a physical and / or electrical connection. Furthermore, an "electrical connection" may involve the presence of other elements between two elements.

[0064] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used herein to describe the relationship between one element and another, as illustrated in the figures. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one figure is flipped, an element described as being "below" to another element will be oriented "above" to that element. Thus, the exemplary term "below" can include both "below" and "above" orientations, depending on the specific orientation of the figure. Similarly, if a device in one figure is flipped, an element described as being "below" or "under" another element will be oriented "above" to that element. Thus, the exemplary terms "above" or "below" can include both "above" and "below" orientations.

[0065] This document describes exemplary embodiments with reference to cross-sectional views as schematic diagrams of idealized embodiments. Therefore, variations in the shape of the illustrations can be expected as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include, for example, shape deviations caused by manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the claims.

[0066] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0067] Figure 1 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to a first embodiment of the present invention. Figures 2A to 2F yes Figure 1 A cross-sectional schematic diagram of the manufacturing process of a vertical thin-film transistor. Figures 3A to 3E yes Figure 1 A cross-sectional schematic diagram of another manufacturing process for vertical thin-film transistors.

[0068] Please refer to Figure 1 The vertical thin-film transistor (VTFT) includes a first semiconductor layer 110, a sacrificial layer 115, a second semiconductor layer 120, and a third semiconductor layer 130. The first semiconductor layer 110 is disposed on the substrate 100 and has a first heavily doped portion 110hd and an extension portion 110ex. In this embodiment, a buffer layer 105 may also be provided between the first semiconductor layer 110 and the substrate 100. The material of the buffer layer 105 is, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials). In some embodiments, the buffer layer 105 may be a single-layer structure or a multi-layer structure, but is not limited thereto.

[0069] A sacrificial layer 115 is disposed on the substrate 100. Notably, the sacrificial layer 115 covers the extension 110ex of the first semiconductor layer 110 and exposes the first heavily doped portion 110hd, wherein the sidewalls of the extension 110ex are in contact with the sidewalls of the first heavily doped portion 110hd. Alternatively, the extension 110ex of the first semiconductor layer 110 extends from the first heavily doped portion 110hd and extends below the sacrificial layer 115. For example, the extension length L of the extension 110ex below the sacrificial layer 115 may be greater than or equal to 0.5 μm, but is not limited thereto.

[0070] The first semiconductor layer 110 can be a single-layer or multi-layer structure. In a preferred embodiment, the material of the first heavily doped portion 110hd of the first semiconductor layer 110 may include polysilicon semiconductor material, while the material of its extended portion 110ex may include amorphous silicon semiconductor material, but is not limited thereto. The material of the sacrificial layer 115 includes, for example, silicon oxide and silicon nitride, but is not limited thereto.

[0071] A second semiconductor layer 120 is disposed on the sacrificial layer 115 and has a second heavily doped portion 120hd. In a direction perpendicular to the substrate 100 (e.g., direction Z), the second heavily doped portion 120hd of the second semiconductor layer 120 overlaps with an extension portion 110ex of the first semiconductor layer 110. For example, in this embodiment, the dopant concentration of the second heavily doped portion 120hd is substantially the same as the dopant concentration of the first heavily doped portion 110hd, but this is not a limitation. The second semiconductor layer 120 can be a single-layer structure or a multi-layer structure. In a preferred embodiment, the material of the second semiconductor layer 120 may include polysilicon semiconductor material, but this is not a limitation.

[0072] The third semiconductor layer 130 covers and contacts a portion of the first heavily doped portion 110hd, the sidewall 115sw of the sacrificial layer 115, and a portion of the second heavily doped portion 120hd. For example, in this embodiment, the third semiconductor layer 130 may contact a portion of the surface 110s2 of the first heavily doped portion 110hd facing away from the substrate 100 and a portion of the surface 120s of the second heavily doped portion 120hd facing away from the substrate 100. The third semiconductor layer 130 may be a single-layer structure or a multi-layer structure.

[0073] In a preferred embodiment, the material of the third semiconductor layer 130 may include, but is not limited to, polysilicon semiconductor material. Specifically, the portion of the third semiconductor layer 130 that contacts the sidewall 115sw of the sacrificial layer 115 may define the channel region CH of the vertical thin-film transistor (VTFT). In this embodiment, the length of the channel region CH may be less than 3 μm. That is, the vertical thin-film transistor (VTFT) of this embodiment may be a thin-film transistor with an ultra-short channel.

[0074] In a preferred embodiment, the thickness 115t of the sacrificial layer 115 may be greater than or equal to twice the thickness 110t of the first heavily doped portion 110hd or the thickness 120t of the second heavily doped portion 120hd, wherein the defining direction of each film layer thickness is, for example, along a direction perpendicular to the substrate 100 (e.g., direction Z), but is not limited thereto. To ensure that the vertical thin-film transistor VTFT has sufficient channel length, the angle θ between the sidewall 115sw of the sacrificial layer 115 and the surface 110s1 of the extension 110ex of the first semiconductor layer 110 connecting the sacrificial layer 115 is less than 90 degrees. In a preferred embodiment, the angle θ may be less than 60 degrees, for example, any angle in the range of 30 degrees to 60 degrees.

[0075] First, it should be noted that since the first semiconductor layer 110, in addition to the first heavily doped portion 110hd, also has an extension portion 110ex extending between the sacrificial layer 115 and the substrate 100, it can effectively prevent gaps from forming between the sacrificial layer 115 and the first heavily doped portion 110hd due to insufficient manufacturing process precision. This would prevent the subsequently formed third semiconductor layer 130 from getting trapped in the gaps and failing to form an effective short channel. In other words, the provision of the extension portion 110ex can significantly improve the manufacturing process margin of the sacrificial layer 115, thereby improving the manufacturing process and operational stability of the vertical thin-film transistor (VTFT).

[0076] Furthermore, the vertical thin-film transistor (VTFT) also includes a gate GE, a source SE, and a drain DE disposed on the substrate 100. For example, in this embodiment, the gate GE may be disposed on the side of the third semiconductor layer 130 facing away from the substrate 100. That is, the vertical thin-film transistor (VTFT) of this embodiment may be a top-gate thin-film transistor, but is not limited thereto. More specifically, in the Z direction, the gate GE may overlap the first heavily doped portion 110hd, the extension portion 110ex, the second heavily doped portion 120hd, and the third semiconductor layer 130.

[0077] In this embodiment, a dielectric layer 135 may be provided between the third semiconductor layer 130 and the gate GE. The dielectric layer 135 may be a single-layer structure or a multi-layer structure, and its material may include, for example, silicon oxide, silicon nitride, or other suitable insulating materials. For example, an insulating layer 145 may be covered on the gate GE, and the source SE and drain DE are disposed on the insulating layer 145. The material of the insulating layer 145 may include, for example, inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stack of at least two of the above materials), organic materials (e.g., polyester (PET), polyolefins, polyacrylonitriles, polycarbonates, polyoxyalkylene compounds, polystyrene, polyethers, polyketides, polyols, polyaldehydes, or other suitable materials, or combinations thereof), or other suitable materials, or combinations thereof.

[0078] In this embodiment, the source (SE) and drain (DE) can penetrate the insulating layer 145 and the dielectric layer 135 to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. The gate (GE), source (SE), and drain (DE) can each be a single-layer or multi-layer structure, and their materials include, for example, transparent conductive materials (e.g., metal oxides), non-transparent conductive materials (e.g., molybdenum, aluminum, copper, titanium, chromium, etc.), combinations thereof, or other suitable conductive materials.

[0079] It should be noted that the vertical thin-film transistor (VTFT) of this embodiment can be applied on the component substrate 10, and the component substrate 10 can serve as a driving circuit board for the display panel. The display panel can be a self-emissive display panel, such as an organic light-emitting diode (OLED) display panel or a micro light-emitting diode (micro-LED) display panel, but is not limited thereto. In other applications, the display panel can also be a non-self-emissive display panel, such as a liquid crystal display (LCD) panel or an electrophoretic display (EPD) panel.

[0080] For example, a vertical thin-film transistor (VTFT) can be used as a driving element within the display area of ​​a display panel, such as a driving element for display subpixels, but is not limited thereto. In other applications, a vertical thin-film transistor (VTFT) can also be used as a driving element within the non-display area of ​​a display panel, such as a driving element for peripheral circuitry.

[0081] The following will exemplarily describe a method for manufacturing a vertical thin-film transistor (VTFT). Please refer to... Figure 2A First, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on the substrate 100. Preferably, the first semiconductor material layer 110M is made of amorphous silicon, for example. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0082] Please refer to Figure 2B and Figure 2C Next, a sacrificial material layer 115M is formed on the first semiconductor material layer 110M, and a second semiconductor material layer 120M is formed on the sacrificial material layer 115M. The sacrificial material layer 115M and the second semiconductor material layer 120M are patterned to form a stacked structure of the sacrificial layer 115M and the second semiconductor material layer 120M. The patterning process is, for example, photolithography, but is not limited to it.

[0083] Of particular note is that the sacrificial layer 115 formed by the patterning process covers the first portion 110Mp1 of the first semiconductor material layer 110M and exposes the second portion 110Mp2 of the first semiconductor material layer 110M, such as... Figure 2CAs shown. Because the first semiconductor material layer 110M reserves a first portion 110Mp1 to be covered by the sacrificial layer 115, gaps between the sacrificial layer 115 and the first semiconductor material layer 110M due to insufficient manufacturing process precision can be avoided, thereby ensuring that the subsequently fabricated third semiconductor layer can form a short channel. In this embodiment, in order to cover the deviation between the manufacturing process and the design, the extension length L of the first portion 110Mp1 of the first semiconductor material layer 110M below the sacrificial layer 115 can be greater than or equal to 0.5 μm, but is not limited thereto. The extension length L can be adjusted according to the actual manufacturing process deviation.

[0084] Please refer to Figure 2D The second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are fabricated using a heavy doping process. Since the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are fabricated simultaneously using a heavy doping process, the dopant concentration of the second portion 110Mp2 of the first semiconductor material layer 110M is essentially equal to the dopant concentration of the second semiconductor material layer 120M.

[0085] Please refer to Figure 2E and Figure 2F After the heavy doping fabrication process is completed, a third semiconductor material layer 130M is formed on the first semiconductor material layer 110M, and a laser annealing process is performed on the first semiconductor material layer 110M, the second semiconductor material layer 120M, and the third semiconductor material layer 130M. After the laser annealing process is completed, the first portion 110Mp1 and the second portion 110Mp2 of the first semiconductor material layer 110M respectively form the extension portion 110ex and the first heavily doped portion 110hd of the first semiconductor layer 110, the second semiconductor material layer 120M forms the second heavily doped portion 120hd of the second semiconductor layer 120, and the third semiconductor material layer 130M forms the third semiconductor layer 130.

[0086] For example, in this embodiment, the second portion 110Mp2 of the first semiconductor material layer 110M and the amorphous silicon semiconductor material of the second semiconductor material layer 120M will transform into polycrystalline silicon semiconductor material after being irradiated by a laser beam. However, since the first portion 110Mp1 of the first semiconductor material layer 110M is covered by the second semiconductor material layer 120M, the exposure of the laser beam LB received by it is insufficient, resulting in the first portion 110Mp1 of the first semiconductor material layer 110M still retaining the composition of amorphous silicon semiconductor material after the laser annealing process.

[0087] Next, a gate GE is formed on the substrate 100. In this embodiment, Figure 1The method for manufacturing a vertical thin-film transistor (VTFT) may further include: forming a dielectric layer 135 to cover a third semiconductor layer 130, wherein a gate GE is formed on the dielectric layer 135. Please refer to... Figure 2F and Figure 1 After the gate GE is fabricated, an insulating layer 145 is formed to cover the gate GE and the dielectric layer 135, and a source SE and a drain DE are formed on the insulating layer 145. The source SE and the drain DE penetrate the insulating layer 145 and the dielectric layer 135 to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively.

[0088] This completes the process. Figure 1 Fabrication of vertical thin-film transistors (VTFTs).

[0089] However, the invention is not limited thereto. Figure 1 In another manufacturing process for vertical thin-film transistors (VTFTs), the laser annealing process can be performed twice. For example, after forming the second semiconductor material layer 120M and the sacrificial layer 115 and before performing the heavy doping process, a first laser annealing process can be performed on the first semiconductor material layer 110M and the second semiconductor material layer 120M. Figure 3A and Figure 3B As shown. Only after completing the first laser annealing process is the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M subjected to a heavy doping process, as shown. Figure 3B and Figure 3C As shown.

[0090] After completing the heavy doping fabrication process, a third semiconductor material layer 130M is formed on the first semiconductor layer 110 and the second semiconductor layer 120, and a second laser annealing process is performed on the third semiconductor material layer 130M to form the third semiconductor layer 130. Figure 3D and Figure 3E As shown. Since the steps of forming the first semiconductor material layer 110M, the second semiconductor material layer 120M and the sacrificial layer 115, as well as the methods of forming the gate GE, source SE and drain DE, are similar to the manufacturing methods of the foregoing embodiments, detailed descriptions can be found in the relevant paragraphs of the foregoing embodiments, and will not be repeated here.

[0091] Another embodiment will be described below to illustrate the present invention in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiment, and they will not be repeated below.

[0092] Figure 4 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to a second embodiment of the present invention. Figures 5A to 5F yes Figure 4 A cross-sectional schematic diagram of the manufacturing process of a vertical thin-film transistor. Please refer to... Figure 4 In this embodiment, the vertical thin-film transistor VTFT-A on the component substrate 10A and Figure 1 The difference between vertical thin-film transistors (VTFTs) lies in the location of the gate.

[0093] Specifically, the gate GE” of the vertical thin-film transistor VTFT-A can be selectively disposed below the third semiconductor layer 130. That is, the vertical thin-film transistor VTFT-A in this embodiment can be a bottom-gate thin-film transistor. Specifically, in this embodiment, the sacrificial layer 115A has a first sublayer SL1 and a second sublayer SL2, and the gate GE” is sandwiched between the first sublayer SL1 and the second sublayer SL2. Therefore, in the Z direction, the gate GE” overlaps the extension portion 110ex, the second heavily doped portion 120hd, and the third semiconductor layer 130, but does not overlap the first heavily doped portion 110hd. On the other hand, since the gate GE” is enclosed within the sacrificial layer 115A, the third semiconductor layer 130 in this embodiment is not covered by [missing information - likely a specific material or structure]. Figure 1 Dielectric layer 135 in the middle.

[0094] The following will exemplarily describe a method for manufacturing a vertical thin-film transistor (VTFT-A). Please refer to... Figure 5A First, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on the substrate 100. Preferably, the first semiconductor material layer 110M is made of amorphous silicon, for example. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0095] Please refer to Figure 5B and Figure 5C Next, a sacrificial material layer 115M and a gate GE are formed on the first semiconductor material layer 110M, and a second semiconductor material layer 120M is formed on the sacrificial material layer 115M. The step of forming the sacrificial material layer 115M may include sequentially forming a first sub-sacrificial material layer 115Ma and a second sub-sacrificial material layer 115Mb on the first semiconductor material layer 110M. It is particularly noteworthy that the gate GE is formed after the formation of the first sub-sacrificial material layer 115Ma and before the formation of the second sub-sacrificial material layer 115Mb.

[0096] A patterning process is performed on the sacrificial material layer 115M and the second semiconductor material layer 120M to form a stacked structure of the sacrificial layer 115A and the second semiconductor material layer 120M. The patterning process is, for example, photolithography, but is not limited to this. It is particularly noteworthy that the sacrificial layer 115A formed by the patterning process covers a first portion 110Mp1 of the first semiconductor material layer 110M and exposes a second portion 110Mp2 of the first semiconductor material layer 110M, such as... Figure 5C As shown. Since the first semiconductor material layer 110M reserves a first portion 110Mp1 for the sacrificial layer 115A to cover, it can avoid the formation of a gap between the sacrificial layer 115A and the first semiconductor material layer 110M due to insufficient manufacturing process precision, thereby ensuring that the subsequently manufactured third semiconductor layer can form a short channel.

[0097] Please refer to Figure 5D The second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are fabricated using a heavy doping process. Since the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M are fabricated simultaneously using a heavy doping process, the dopant concentration of the second portion 110Mp2 of the first semiconductor material layer 110M is essentially equal to the dopant concentration of the second semiconductor material layer 120M.

[0098] Please refer to Figure 5E and Figure 5F After the heavy doping fabrication process is completed, a third semiconductor material layer 130M is formed on the first semiconductor material layer 110M, and a laser annealing process is performed on the first semiconductor material layer 110M, the second semiconductor material layer 120M, and the third semiconductor material layer 130M. After the laser annealing process is completed, the first portion 110Mp1 and the second portion 110Mp2 of the first semiconductor material layer 110M respectively form the extension portion 110ex and the first heavily doped portion 110hd of the first semiconductor layer 110, the second semiconductor material layer 120M forms the second heavily doped portion 120hd of the second semiconductor layer 120, and the third semiconductor material layer 130M forms the third semiconductor layer 130.

[0099] For example, in this embodiment, the second portion 110Mp2 of the first semiconductor material layer 110M and the amorphous silicon semiconductor material of the second semiconductor material layer 120M will transform into polycrystalline silicon semiconductor material after being irradiated by a laser beam. However, since the first portion 110Mp1 of the first semiconductor material layer 110M is covered by the second semiconductor material layer 120M, the exposure of the laser beam LB received by it is insufficient, resulting in the first portion 110Mp1 of the first semiconductor material layer 110M still retaining the composition of amorphous silicon semiconductor material after the laser annealing process.

[0100] Please refer to Figure 5F and Figure 4 After the fabrication of the third semiconductor layer 130 is completed, an insulating layer 145 is formed to cover the third semiconductor layer 130, and a source electrode SE and a drain electrode DE are formed on the insulating layer 145. The source electrode SE and the drain electrode DE penetrate the insulating layer 145 to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. This completes the fabrication process. Figure 4 Fabrication of a vertical thin-film transistor VTFT-A.

[0101] Figure 6 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to a third embodiment of the present invention. Please refer to... Figure 6 In the element substrate 10B of this embodiment, the vertical thin-film transistor VTFT-B can be a dual-gate thin-film transistor. Specifically, the vertical thin-film transistor VTFT-B of this embodiment can simultaneously have a gate GE located above the third semiconductor layer 130 and a gate GE located below the third semiconductor layer 130. Since the method of setting and forming the gate GE in this embodiment is similar to... Figure 1 The gate GE of the vertical thin-film transistor VTFT, and the setting and formation method of the gate GE are similar to those of the vertical thin-film transistor VTFT. Figure 4 The gate GE of the vertical thin-film transistor VTFT-A is described in detail in the relevant paragraphs of the foregoing embodiments, and will not be repeated here.

[0102] Figure 7 This is a cross-sectional schematic diagram of a vertical thin-film transistor according to the fourth embodiment of the present invention. Figures 8A to 8G yes Figure 7 A cross-sectional schematic diagram of the manufacturing process of a vertical thin-film transistor. Please refer to... Figure 7 Compared to Figure 1 The vertical thin-film transistor VTFT of the component substrate 10C in this embodiment further includes a first etch protection pattern 161 and a second etch protection pattern 162.

[0103] In this embodiment, a first etch protection pattern 161 is disposed between the first heavily doped portion 110hd of the first semiconductor layer 110 and the third semiconductor layer 130A, and contacts the first heavily doped portion 110hd and the third semiconductor layer 130A. A second etch protection pattern 162 is disposed between the second heavily doped portion 120hd of the second semiconductor layer 120 and the third semiconductor layer 130A, and contacts the second heavily doped portion 120hd and the third semiconductor layer 130A. The source electrode SE penetrates the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and the first etch protection pattern 161 to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110. The drain electrode DE penetrates the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and the second etch protection pattern 162 to electrically connect the second heavily doped portion 120hd of the second semiconductor layer 120.

[0104] Alternatively, the source electrode SE can be electrically connected to the first heavily doped portion 110hd via the first contact hole TH1 of the first etch protection pattern 161 through the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and the first etch protection pattern 161, while the drain electrode DE can be electrically connected to the second heavily doped portion 120hd via the second contact hole TH2 of the second etch protection pattern 162 through the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and the second etch protection pattern 162. It is particularly noteworthy that the orthographic projections of the first contact hole TH1 and the second contact hole TH2 on the substrate 100 lie within the orthographic projections of the first etch protection pattern 161 and the second etch protection pattern 162 on the substrate 100.

[0105] Because the etching solution used in the etching process of the third semiconductor layer 130A does not have an etching selectivity for the third semiconductor layer 130A and the first heavily doped portion 110hd (or the second heavily doped portion 120hd), when etching the third semiconductor layer 130A in order to expose the first heavily doped portion 110hd and the second heavily doped portion 120hd, it is easy to damage or even break the film of the underlying heavily doped portion, resulting in the failure of the electrical connection between the source SE and the drain DE and the heavily doped portion.

[0106] Therefore, by providing the aforementioned first etch protection pattern 161 and second etch protection pattern 162, damage to the heavily doped portion from the etchant can be prevented during the etching of the third semiconductor layer 130A. Preferably, the materials of the first etch protection pattern 161 and the second etch protection pattern 162 may include silicon oxide (SiO) or silicon nitride (SiN). From another perspective, during the etching process of the etch protection pattern, since the etchant has an etching selectivity ratio between the material of the etch protection pattern (e.g., SiO or SiN) and the material of the heavily doped portion (e.g., Si), damage to the heavily doped portion from the etchant can be prevented during the etching process of the etch protection pattern.

[0107] The following will exemplarily describe a method for manufacturing a vertical thin-film transistor (VTFT-C). Please refer to... Figure 8A First, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on the substrate 100. Preferably, the first semiconductor material layer 110M is made of amorphous silicon, for example. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0108] Please refer to Figure 8B and Figure 8C Next, a sacrificial material layer 115M is formed on the first semiconductor material layer 110M, and a second semiconductor material layer 120M is formed on the sacrificial material layer 115M. The sacrificial material layer 115M and the second semiconductor material layer 120M are patterned to form a stacked structure of the sacrificial layer 115M and the second semiconductor material layer 120M. The patterning process is, for example, photolithography, but is not limited to it.

[0109] First, it should be noted that in the manufacturing process of the vertical thin-film transistor VTFT-C in this embodiment, the laser annealing process can be performed twice. For example, after forming the second semiconductor material layer 120M and the sacrificial layer 115 and before performing the heavy doping process, the first semiconductor material layer 110M and the second semiconductor material layer 120M can be subjected to a first laser annealing process. Figure 8C and Figure 8D As shown. Only after completing the first laser annealing process is the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M subjected to a heavy doping process, as shown. Figure 8D and Figure 8E As shown.

[0110] After completing the heavy doping fabrication process, a first etch protection pattern 161 and a second etch protection pattern 162 are formed on the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. Next, a third semiconductor material layer 130M is formed to cover the first etch protection pattern 161, the second etch protection pattern 162, the first heavily doped portion 110hd, the second heavily doped portion 120hd, and the sidewall 115sw of the sacrificial layer 115. A second laser annealing process is then performed on the third semiconductor material layer 130M to form the third semiconductor layer 130A, as shown below. Figure 8F and Figure 8G As shown.

[0111] Please refer to Figure 8G and Figure 7 After the fabrication of the third semiconductor layer 130A is completed, a gate GE is formed on the substrate 100. In this embodiment, Figure 7 The manufacturing method of the vertical thin-film transistor (VTFT-C) may further include: forming a dielectric layer 135 to cover a third semiconductor layer 130A, wherein a gate electrode GE is formed on the dielectric layer 135. After the gate electrode GE is fabricated, an insulating layer 145 is formed to cover the gate electrode GE and the dielectric layer 135, and a source electrode SE and a drain electrode DE are formed on the insulating layer 145, wherein the source electrode SE and the drain electrode DE penetrate the insulating layer 145, the dielectric layer 135, the third semiconductor layer 130A, and an etched protective pattern to electrically connect the first heavily doped portion 110hd of the first semiconductor layer 110 and the second heavily doped portion 120hd of the second semiconductor layer 120, respectively. This completes the process. Figure 7 Fabrication of vertical thin-film transistor VTFT-C.

[0112] Figure 9 This is a cross-sectional schematic diagram of a component substrate according to an embodiment of the present invention. Figures 10A to 10H yes Figure 9 A cross-sectional view illustrating the manufacturing process of the component substrate. Please refer to... Figure 9 Compared to Figure 6 In addition to the component substrate 10B, the component substrate 10D in this embodiment may also be provided with a thin-film transistor (TFT). Unlike the vertical thin-film transistor VTFT-D, which is a bottom-gate type thin-film transistor, the thin-film transistor TFT is a top-gate type thin-film transistor.

[0113] In this embodiment, the thin-film transistor (TFT) may include a source (SE'), a drain (DE'), a gate (GE'), a third doped portion (121hd), a fourth doped portion (122hd), and a channel (120ch). Specifically, the third doped portion (121hd), the fourth doped portion (122hd), and the channel (120ch) of the TFT may be on the same film layer as the second doped portion (120hd) of the vertical thin-film transistor (VTFT-D), for example, the second semiconductor layer (120A). The second etch protection pattern (162A) covering a portion of the second doped portion (120hd) of the vertical thin-film transistor (VTFT-D) may also cover the third doped portion (121hd), the fourth doped portion (122hd), and the channel (120ch) of the TFT. The gate (GE') of the TFT is disposed on the second etch protection pattern (162A) and is covered by an insulating layer (145). The source (SE') and drain (DE') of the TFT may be on the same film layer as the source (SE) and drain (DE) of the vertical thin-film transistor (VTFT-D).

[0114] It should be noted that in this embodiment, a second etch protection pattern 162A is provided between the gate GE' of the thin-film transistor TFT and the second semiconductor layer 120A, therefore, it is not necessary to set up a second etch protection pattern 162A. Figure 1 The dielectric layer 135 shown represents the electrically isolated gate GE' and channel 120ch.

[0115] The following will provide an illustrative description of the manufacturing methods for vertical thin-film transistor VTFT-D and thin-film transistor TFT. Please refer to... Figure 10A First, a buffer layer 105 and a first semiconductor material layer 110M are sequentially formed on the substrate 100. Preferably, the first semiconductor material layer 110M is made of amorphous silicon, for example. However, the present invention is not limited thereto. In another embodiment, the first semiconductor material layer 110M can be formed directly on the substrate 100, that is, the buffer layer 105 can be omitted.

[0116] Please refer to Figure 10B Next, a sacrificial layer 115A and a gate GE are formed on the first semiconductor material layer 110M. Since the steps for forming the sacrificial layer 115A and the gate GE in this embodiment are similar to... Figure 4 The details of the sacrificial layer 115A and the gate GE can be found in the relevant paragraphs of the foregoing embodiments and will not be repeated here. It is particularly noteworthy that the sacrificial layer 115A, formed by the patterning process, covers a first portion 110Mp1 of the first semiconductor material layer 110M and exposes a second portion 110Mp2 of the first semiconductor material layer 110M. Since the first semiconductor material layer 110M reserves the first portion 110Mp1 to be covered by the sacrificial layer 115A, gaps between the sacrificial layer 115A and the first semiconductor material layer 110M due to insufficient fabrication process precision can be avoided, thereby ensuring that the subsequently fabricated third semiconductor layer can form a short channel.

[0117] Please refer to Figure 10C A second semiconductor material layer 120M is formed on the sacrificial layer 115A, and the first semiconductor material layer 110M and the second semiconductor material layer 120M are fabricated using a laser annealing process. For example... Figure 10D As shown, an etch protection material layer 160M is then formed to cover the first semiconductor material layer 110M and the second semiconductor material layer 120M, and another gate GE' is formed on the etch protection material layer 160M.

[0118] After the gate GE' is fabricated, a heavy doping process is performed on the second portion 110Mp2 of the first semiconductor material layer 110M and the second semiconductor material layer 120M, as follows: Figure 10D and Figure 10EAs shown. The first portion 110Mp1 and the second portion 110Mp2 of the first semiconductor material layer 110M form the extension portion 110ex and the first heavily doped portion 110hd of the first semiconductor layer 110, respectively. The second semiconductor material layer 120M forms the second heavily doped portion 120hd, the third heavily doped portion 121hd and the fourth heavily doped portion 122hd of the second semiconductor layer 120A. The undoped portion of the second semiconductor material layer 120M (i.e. the portion that overlaps with the gate GE' along the Z direction) forms the channel 120ch.

[0119] Please refer to Figure 10E and Figure 10F Next, a patterning process is performed on the etch protection material layer 160M to form a first etch protection pattern 161 and a second etch protection pattern 162A, exposing a portion of the first heavily doped portion 110hd, the sidewall 115sw of the sacrificial layer 115A, and a portion of the second heavily doped portion 120hd. After the patterning process of the etch protection material layer 160M is completed, a third semiconductor material layer 130M is formed to cover the etch protection pattern, a portion of the first heavily doped portion 110hd, the sidewall 115sw of the sacrificial layer 115A, and a portion of the second heavily doped portion 120hd. The third semiconductor material layer 130M then undergoes another laser annealing and patterning process to form the third semiconductor layer 130. Figure 10G and Figure 10H As shown. The patterning process includes, for example, photolithography, but is not limited to this.

[0120] Because the etching solution used in the etching process of the third semiconductor material layer 130M does not have an etching selectivity for the third semiconductor material layer 130M and the first heavily doped portion 110hd (or the second heavily doped portion 120hd), when etching the third semiconductor material layer 130M in order to expose part of the first heavily doped portion 110hd and part of the second heavily doped portion 120hd, it is easy to damage or even break the film of the underlying heavily doped portion, resulting in the failure of the electrical connection between the subsequently formed source SE, drain DE, source SE' and drain DE' and the heavily doped portion.

[0121] Therefore, by providing the aforementioned first etch protection pattern 161 and second etch protection pattern 162A, damage to the heavily doped portion from the etchant can be prevented during the etching of the third semiconductor material layer 130M. Preferably, the materials of the first etch protection pattern 161 and the second etch protection pattern 162A may include silicon oxide (SiO) or silicon nitride (SiN). From another perspective, during the etching process of the etch protection pattern, since the etchant has an etching selectivity ratio between the material of the etch protection pattern (e.g., SiO or SiN) and the material of the heavily doped portion (e.g., Si), damage to the heavily doped portion from the etchant can be prevented during the etching process of the etch protection pattern.

[0122] Since the methods for forming the source SE, drain DE, source SE', and drain DE' are similar to Figure 4 The manufacturing method of the vertical thin-film transistor VTFT-A is detailed in the relevant paragraphs of the foregoing embodiments and will not be repeated here. This completes the process. Figure 9 Fabrication of vertical thin-film transistor VTFT-D and thin-film transistor TFT.

[0123] In summary, in a vertical thin-film transistor and its manufacturing method according to an embodiment of the present invention, the first semiconductor layer, in addition to the first heavily doped portion, also has an extension portion extending between the sacrificial layer and the substrate. This extension portion prevents the subsequently formed third semiconductor layer from getting trapped in the gap between the sacrificial layer and the first heavily doped portion due to insufficient fabrication process precision, thus avoiding the formation of an effective short channel. In other words, it significantly improves the fabrication process margin of the sacrificial layer, thereby enhancing the fabrication process and operational stability of the vertical thin-film transistor.

Claims

1. A vertical thin-film transistor, comprising: A first semiconductor layer is disposed on a substrate and has a first heavily doped portion and an extended portion; A sacrificial layer is disposed on the substrate, the sacrificial layer covering the extended portion and exposing the first heavily doped portion; A second semiconductor layer is disposed on the sacrificial layer and has a second heavily doped portion, wherein the second heavily doped portion overlaps with the extension portion of the first semiconductor layer in a direction perpendicular to the substrate. A third semiconductor layer covers and contacts a portion of the first heavily doped portion, the sidewalls of the sacrificial layer, and a portion of the second heavily doped portion; A first gate is disposed on the substrate, wherein, in a direction perpendicular to the substrate, the first gate overlaps the second heavily doped portion, the extended portion, and the third semiconductor layer; and The source and drain are disposed on the substrate and are electrically connected to the first heavily doped portion and the second heavily doped portion, respectively.

2. The vertical thin-film transistor of claim 1, further comprising: A dielectric layer is disposed on the substrate and covers the third semiconductor layer, wherein the first gate is disposed on the dielectric layer and overlaps the first heavily doped portion in the direction perpendicular to the substrate.

3. The vertical thin-film transistor of claim 2, wherein the extended portion of the first semiconductor layer extends from the first heavily doped portion.

4. The vertical thin-film transistor of claim 2, wherein the thickness of the sacrificial layer is greater than or equal to twice the thickness of the first heavily doped portion or the second heavily doped portion.

5. The vertical thin-film transistor of claim 2, further comprising: A first etch protection pattern is disposed between the first heavily doped portion and the third semiconductor layer, and contacts the first heavily doped portion and the third semiconductor layer; as well as A second etch protection pattern is disposed between the second heavily doped portion and the third semiconductor layer, and contacts both the second heavily doped portion and the third semiconductor layer. The source electrode penetrates the third semiconductor layer and the first etch protection pattern to electrically connect the first heavily doped portion, and the drain electrode penetrates the third semiconductor layer and the second etch protection pattern to electrically connect the second heavily doped portion.

6. The vertical thin-film transistor of claim 5, wherein the source is electrically connected to the first heavily doped portion via a first contact hole, the drain is electrically connected to the second heavily doped portion via a second contact hole, and the orthogonal projections of the first contact hole and the second contact hole on the substrate lie within the orthogonal projections of the first etch protection pattern and the second etch protection pattern on the substrate.

7. The vertical thin-film transistor of claim 1, wherein the sacrificial layer has a first sub-layer and a second sub-layer, and the first gate is sandwiched between the first sub-layer and the second sub-layer.

8. The vertical thin-film transistor of claim 7, wherein the extended portion of the first semiconductor layer extends from the first heavily doped portion.

9. The vertical thin-film transistor of claim 7, wherein the thickness of the sacrificial layer is greater than or equal to twice the thickness of the first heavily doped portion or the second heavily doped portion.

10. The vertical thin-film transistor of claim 7, further comprising: A first etch protection pattern is disposed between the first heavily doped portion and the third semiconductor layer, and contacts the first heavily doped portion and the third semiconductor layer; as well as A second etch protection pattern is disposed between the second heavily doped portion and the third semiconductor layer, and contacts both the second heavily doped portion and the third semiconductor layer. The source electrode penetrates the third semiconductor layer and the first etch protection pattern to electrically connect the first heavily doped portion, and the drain electrode penetrates the third semiconductor layer and the second etch protection pattern to electrically connect the second heavily doped portion.

11. The vertical thin-film transistor of claim 10, wherein the source is electrically connected to the first heavily doped portion via a first contact hole, the drain is electrically connected to the second heavily doped portion via a second contact hole, and the orthogonal projections of the first contact hole and the second contact hole on the substrate lie within the orthogonal projections of the first etch protection pattern and the second etch protection pattern on the substrate.

12. The vertical thin-film transistor of claim 7, further comprising: A dielectric layer is disposed on the substrate and covers the third semiconductor layer; as well as The second gate is disposed on the dielectric layer and overlaps the first heavily doped portion, the second heavily doped portion, the extension portion and the third semiconductor layer in the direction perpendicular to the substrate.

13. The vertical thin-film transistor of claim 1, wherein the extension portion of the first semiconductor layer has a surface connected to the sacrificial layer, and the angle between the sidewall of the sacrificial layer and the surface of the extension portion is less than 60 degrees.

14. A method for manufacturing a vertical thin-film transistor, comprising: A first semiconductor material layer is formed on the substrate; A sacrificial layer is formed on the first semiconductor material layer, which covers a first portion of the first semiconductor material layer and exposes a second portion of the first semiconductor material layer. A second semiconductor material layer is formed on the sacrificial layer; The second portion of the first semiconductor material layer and the second semiconductor material layer are subjected to a heavy doping fabrication process; After the heavy doping fabrication process is completed, a third semiconductor layer is formed on the first semiconductor material layer and the second semiconductor material layer. A laser annealing process is performed on the first semiconductor material layer and the second semiconductor material layer. After the heavy doping process and the laser annealing process are completed, the first part and the second part of the first semiconductor material layer respectively form the extension part and the first heavily doped part of the first semiconductor layer, and the second semiconductor material layer forms the second heavily doped part of the second semiconductor layer. A gate is formed on the substrate; as well as A source and a drain are formed to electrically connect the first heavily doped portion and the second heavily doped portion, respectively.

15. The method for manufacturing a vertical thin-film transistor as claimed in claim 14, wherein the laser annealing process is performed after the heavy doping process, and the step of forming the third semiconductor layer includes: Forming a third semiconductor material layer; as well as The laser annealing process is applied to the third semiconductor material layer.

16. The method for manufacturing a vertical thin-film transistor as claimed in claim 14, wherein the laser annealing process precedes the heavy doping process, and the step of forming the third semiconductor layer includes: Forming a third semiconductor material layer; as well as Another laser annealing process is used to fabricate the third semiconductor material layer.

17. The method for manufacturing a vertical thin-film transistor as described in claim 14, further comprising: A dielectric layer is formed to cover the third semiconductor layer, wherein the gate is formed on the dielectric layer.

18. The method of manufacturing a vertical thin-film transistor as claimed in claim 14, wherein the step of forming the sacrificial layer comprises: A first sub-sacrificial material layer and a second sub-sacrificial material layer are sequentially formed on the first semiconductor material layer, wherein the gate is formed after the formation of the first sub-sacrificial material layer and before the formation of the second sub-sacrificial material layer; as well as The first sub-sacrificial material layer and the second sub-sacrificial material layer are patterned to form the first sub-layer and the second sub-layer of the sacrificial layer.

19. The method for manufacturing a vertical thin-film transistor as described in claim 14, further comprising: Before forming the third semiconductor layer, a first etch protection pattern and a second etch protection pattern are formed on the first semiconductor material layer and the second semiconductor material layer, respectively.

20. The method for manufacturing a vertical thin-film transistor as claimed in claim 19, wherein the first etch protection pattern and the second etch protection pattern are formed after the heavy doping process is completed.

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