Photovoltaic cell and method of manufacturing the same, photovoltaic module

Abstract

The embodiment of the present application relates to the photovoltaic field, and provides a photovoltaic cell and a manufacturing method thereof, and a photovoltaic module, the photovoltaic cell comprising: a substrate; a plurality of first electrodes arranged at intervals along a first direction and a plurality of second electrodes arranged at intervals along a second direction on the surface of the substrate, the first direction and the second direction intersecting; the surface of the substrate comprising an overlapping region provided with the first electrodes and the second electrodes simultaneously, the first electrode in the overlapping region being provided with the second electrode on the side away from the substrate; a dielectric layer at least between the second electrode and the first electrode, and having apertures in the overlapping region, and at least part of the number of apertures containing the first electrode and / or the second electrode, so that the first electrode and the second electrode are in contact, and at least the electrical performance of the photovoltaic cell is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaic, in particular to a photovoltaic cell, a manufacturing method thereof and a photovoltaic module. BACKGROUND

[0002] Photovoltaic cells are increasingly widely used as a sustainable clean energy source. A photovoltaic cell is a device that uses the photovoltaic principle to generate carriers to convert solar light energy into electrical energy. Electrodes are usually used in photovoltaic cells to extract carriers, thereby effectively utilizing electrical energy. The mainstream types of current photovoltaic cells include BC (Back Contact) cells, TOPCON (Tunnel Oxide Passivated Contact) cells, PERC (Passivated emitter and real cell) cells, and heterojunction cells (Heterojunction with Intrinsic Thin-film, referred to as HIT or HJT), etc.

[0003] However, in order to further transport and collect the photo-generated carriers generated in the photovoltaic cell, electrodes will be formed in the photovoltaic cell, and other film layers will also be designed in the photovoltaic cell. Based on this, in order to further comprehensively improve the electrical performance of the photovoltaic cell, the cooperation between the electrodes and other film layers in the photovoltaic cell needs to be further studied. SUMMARY

[0004] The embodiments of the present application provide a photovoltaic cell, a manufacturing method thereof and a photovoltaic module, which at least have the advantages of improving the electrical performance of the photovoltaic cell.

[0005] According to some embodiments of the present application, the embodiments of the present application provide a photovoltaic cell, comprising: a substrate; a plurality of first electrodes arranged at intervals along a first direction and a plurality of second electrodes arranged at intervals along a second direction on a surface of the substrate, the first direction and the second direction intersecting; wherein the surface of the substrate comprises an overlapping region provided with the first electrodes and the second electrodes, the first electrodes in the overlapping region are provided with the second electrodes on a side away from the substrate; a dielectric layer at least between the second electrodes and the first electrodes, and the dielectric layer in the overlapping region has pores, and at least part of the number of the pores accommodate the first electrodes and / or the second electrodes, so that the first electrodes and the second electrodes are in contact.

[0006] In some embodiments, the first electrode has opposite bottom and top ends in a third direction, the bottom end being closer to the substrate, the third direction being a thickness direction of the substrate; the thickness of the dielectric layer at a surface of the bottom end is greater than or equal to the thickness of the dielectric layer at a surface of the top end.

[0007] In some embodiments, the thickness of the dielectric layer at a side surface of the first electrode gradually decreases in a direction from the bottom end to the top end.

[0008] In some embodiments, the surface of the substrate further comprises a first region provided with the first electrode; the dielectric layer is further located on the first region and at a surface of the first electrode away from the substrate.

[0009] In some embodiments, the ratio of the area of the overlapping region to the area of the first region is 0.005% to 1.705%.

[0010] In some embodiments, the surface of the substrate further comprises a second region provided with the second electrode; the dielectric layer is further located on the second region and between the second electrode and the substrate.

[0011] In some embodiments, the surface of the substrate further comprises a third region, the third region being a region not provided with the first electrode and the second electrode; the dielectric layer is further located on the third region.

[0012] In some embodiments, the surface of the substrate further comprises a protection region other than the overlapping region, the protection region being a region not provided with the first electrode, the dielectric layer being further located on at least part of the protection region; wherein the ratio of the thickness of the dielectric layer in the overlapping region to the thickness of the dielectric layer in the protection region is 30% to 50%.

[0013] In some embodiments, the thickness of the dielectric layer in the protection region is 30 nm to 200 nm.

[0014] In some embodiments, the photovoltaic cell further comprises: a transparent conductive layer located between the dielectric layer and the substrate and between the first electrode and the substrate.

[0015] In some embodiments, the thickness of the transparent conductive layer is 20 nm to 200 nm.

[0016] In some embodiments, the material of the first electrode and / or the material of the second electrode comprises a metal or a mixture of a metal and an organic polymer; wherein the metal comprises at least one of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, or Sn.

[0017] In some embodiments, the material of the medium layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or magnesium fluoride.

[0018] In some embodiments, the width of the overlap region in a direction perpendicular to the extension direction of the first electrode is 5 μm to 40 μm.

[0019] In some embodiments, the substrate comprises: a substrate, one surface of the substrate comprising fourth regions and fifth regions arranged alternately along the first direction; a first semiconductor layer on the fourth regions, and a first doped layer on a side of the first semiconductor layer away from the substrate; a second semiconductor layer on the fifth regions, and a second doped layer on a side of the second semiconductor layer away from the substrate, the second doped layer and the first doped layer being doped with different types of doped elements; the first electrode comprises first current collecting electrodes on the fourth regions and second current collecting electrodes on the fifth regions, the first current collecting electrodes being electrically connected to the first doped layer, and the second current collecting electrodes being electrically connected to the second doped layer; wherein the first semiconductor layer and the second semiconductor layer are tunneling layers, and the first doped layer and the second doped layer are doped polysilicon layers; or, the first semiconductor layer and the second semiconductor layer are intrinsic amorphous silicon layers, and the first doped layer and the second doped layer are doped amorphous silicon layers; or, the first semiconductor layer is the tunneling layer, the first doped layer is the doped polysilicon layer, the second semiconductor layer is the intrinsic amorphous silicon layer, and the second doped layer is the doped amorphous silicon layer.

[0020] In some embodiments, the substrate comprises: a substrate, having two surfaces opposite along a third direction; a semiconductor layer on one of the two surfaces; a doped layer on a side of the semiconductor layer away from the substrate; the first electrode comprises first current collecting electrodes on a side of the doped layer away from the substrate, and second current collecting electrodes on the other of the two surfaces; wherein the semiconductor layer is a tunneling layer, and the doped layer is a doped polysilicon layer; or, the semiconductor layer is an intrinsic amorphous silicon layer, and the doped layer is a doped amorphous silicon layer.

[0021] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a manufacturing method of a photovoltaic cell, comprising: providing a substrate; forming a plurality of first electrodes arranged at intervals along a first direction on a surface of the substrate; forming an initial dielectric layer on the surface formed by the substrate and the first electrodes; forming a plurality of second electrodes arranged at intervals along a second direction on a surface of the initial dielectric layer, the first direction and the second direction intersecting; wherein the surface of the substrate comprises an overlapping area provided with the first electrodes and the second electrodes simultaneously, in the process of forming the second electrodes, the initial dielectric layer located in the overlapping area is converted into a dielectric layer with pores, and at least part of the pores contain the first electrodes and / or the second electrodes, so that the first electrodes and the second electrodes are in contact.

[0022] In some embodiments, the initial dielectric layer is formed by a deposition process; wherein the processing temperature of the deposition process is 100-300℃, and the processing time of the deposition process is 10-120min.

[0023] In some embodiments, the step of forming the second electrodes comprises: forming a plurality of initial second electrodes arranged at intervals along the second direction on the surface of the initial dielectric layer; and sequentially performing drying treatment and curing treatment on the initial second electrodes to convert the initial second electrodes into the second electrodes; wherein the processing temperature of the drying treatment is 100-200℃, the processing time of the drying treatment is 1-10min, the processing temperature of the curing treatment is 60-250℃, and the processing time of the curing treatment is 0-60min.

[0024] According to some embodiments of the present application, still another aspect of the embodiments of the present application further provides a photovoltaic module, comprising: a cell string connected by a plurality of photovoltaic cells according to any one of the above embodiments or formed by the manufacturing method of the photovoltaic cells according to any one of the above embodiments; an encapsulating adhesive film for covering a surface of the cell string; and a cover plate for covering a surface of the encapsulating adhesive film away from the cell string.

[0025] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0026] The first electrode is designed to be in ohmic contact with the surface of the substrate directly, and on the basis of reserving the medium layer between the first electrode and the second electrode, the medium layer in the overlapping region is designed to have apertures, and at least part of the apertures contain the first electrode and / or the second electrode, so as to ensure that the first electrode and the second electrode are in ohmic contact. In this way, on the one hand, the first electrode is in ohmic contact with the surface of the substrate directly, which is conducive to controlling the good contact morphology between the first electrode and the substrate, so as to improve the collection efficiency of the first electrode for the photo-generated carriers in the substrate; on the other hand, it is conducive to making the raw material of the first electrode be a low-cost low-burn-through conductive material or a non-burn-through conductive material, so that the first electrode is in direct contact with the surface of the substrate, without causing great damage to the substrate, and the preparation cost of the first electrode can be reduced; on the other hand, before the second electrode is formed, the first electrode can be protected by the medium layer, so as to reduce the risk of damage or pollution of the first electrode, thereby improving the yield of the first electrode; on the other hand, while the medium layer in the overlapping region with apertures ensures that the first electrode and the second electrode are in ohmic contact, the raw material of the second electrode can also be a low-cost low-burn-through conductive material or a non-burn-through conductive material, so as to reduce the preparation cost of the second electrode. Therefore, the comprehensive improvement of the electrical performance of the photovoltaic cell is conducive to the comprehensive improvement of the electrical performance of the photovoltaic cell. BRIEF DESCRIPTION OF DRAWINGS

[0027] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are shown by way of illustration in the drawings. These embodiments are described in enough detail to enable those skilled in the art to practice the embodiments and it is understood that the drawings are not a restrictive limitation on the scope of the embodiments described, as at least some point of the embodiments are applicable beyond the specific examples. At least some point of the description is presented in terms of algorithms, systems, methods, software and symbolic representations of operation on data bits that are used by those skilled in the art to convey the substance of their work effectively to others skilled in the art. These descriptions and representations are the means used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art.

[0028] Figure 1 A partial top view schematic diagram of a photovoltaic cell according to an embodiment of the present application is shown in FIG. 1.

[0029] Figure 2 A partial top view schematic diagram of a photovoltaic cell according to an embodiment of the present application is shown in FIG. 1. Figure 1 A partial cross-sectional view schematic diagram of the photovoltaic cell shown in FIG. 1 along a first cross-sectional direction AA1 is shown in FIG. 2.

[0030] Figure 3 A partial cross-sectional view schematic diagram of the photovoltaic cell shown in FIG. 1 along a second cross-sectional direction BB1 is shown in FIG. 3. Figure 1

[0031] Figure 4 A partial cross-sectional view schematic diagram of the photovoltaic cell shown in FIG. 1 along a third cross-sectional direction CC1 is shown in FIG. 4. Figure 1 ​​

[0032] Figure 5 This is another partial top view schematic diagram of a photovoltaic cell provided in an embodiment of this application;

[0033] Figure 6 This is a partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application;

[0034] Figure 7 This is another partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application;

[0035] Figure 8 This is another partial cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of this application;

[0036] Figure 9 A process flow diagram of a method for manufacturing a photovoltaic cell according to another embodiment of this application;

[0037] Figure 10 A partial cross-sectional view of a semi-finished cell after the formation of the initial dielectric layer in a photovoltaic cell manufacturing method provided in another embodiment of this application, along the first cross-sectional direction AA1.

[0038] Figure 11 Provided for yet another embodiment of this application Figure 1 A partial 3D schematic diagram of the battery string in the corresponding photovoltaic module;

[0039] Figure 12 Provided for yet another embodiment of this application Figure 11 A partial cross-sectional schematic diagram of the corresponding photovoltaic module;

[0040] Figure 13 Provided for yet another embodiment of this application Figure 5 A partial 3D schematic diagram of the battery string in the corresponding photovoltaic module;

[0041] Figure 14 Provided for yet another embodiment of this application Figure 13 A partial cross-sectional schematic diagram of the corresponding photovoltaic module.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100, substrate; 110, first region; 120, second region; 130, overlapping region; 140, third region; 101, first electrode; 111, bottom end; 121, top end; 131, first current collecting electrode; 141, second current collecting electrode; 102, second electrode; 103, dielectric layer; 113, aperture; 123, initial dielectric layer; 104, transparent conductive layer; 105, substrate; 115, fourth region; 125, fifth region; 135, surface; 1351, first surface; 1352, second surface; 106, semiconductor layer; 116, first semiconductor layer; 126, second semiconductor layer; 136, second intrinsic amorphous silicon layer; 107, doped layer; 117, first doped layer; 127, second doped layer; 137, second doped amorphous silicon layer; 40, photovoltaic cell; 41, encapsulation adhesive film; 42, cover plate; 43, solder strip. DETAILED DESCRIPTION

[0044] As can be known from the background, the electrical performance of the photovoltaic cell needs to be improved.

[0045] The embodiment of the present application provides a photovoltaic cell and a manufacturing method thereof and a photovoltaic module. In the photovoltaic cell, the first electrode is designed to be in ohmic contact with the surface of the substrate directly, and on the basis of reserving the dielectric layer between the first electrode and the second electrode, the dielectric layer in the overlapping region is designed to have apertures, and at least part of the apertures contain the first electrode and / or the second electrode, so as to ensure the ohmic contact between the first electrode and the second electrode. In this way, on the one hand, the first electrode is in ohmic contact with the surface of the substrate directly, which is conducive to controlling the good contact morphology between the first electrode and the substrate, so as to improve the collection efficiency of the photogenerated carriers in the substrate by the first electrode; on the other hand, it is conducive to making the raw material of the first electrode adopt a low-cost low-burn-through conductive material or a non-burn-through conductive material, so that the first electrode is in direct contact with the surface of the substrate, and the substrate is not damaged greatly, and the preparation cost of the first electrode can be reduced; on the other hand, before the second electrode is formed, the first electrode can be protected by means of the dielectric layer, so as to reduce the risk of damage or pollution of the first electrode, thereby improving the yield of the first electrode; on the other hand, while ensuring the ohmic contact between the first electrode and the second electrode by means of the dielectric layer in the overlapping region having apertures, the raw material of the second electrode can also adopt a low-cost low-burn-through conductive material or a non-burn-through conductive material, so as to reduce the preparation cost of the second electrode. Therefore, the comprehensive improvement of the electrical performance of the photovoltaic cell is conducive to the comprehensive improvement of the electrical performance of the photovoltaic cell.

[0046] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise explicitly specified and limited.

[0047] Reference herein to "embodiments" means that the particular features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily a separate or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can mean: A exists, A and B exist, and B exists. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after it.

[0049] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two), and similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0050] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the embodiments of the present application.

[0051] In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the technical terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0052] In the drawings corresponding to the embodiments of the present application, the thickness and area of a layer are exaggerated for clarity. When a component (such as a layer, film, region, or substrate) is described as being "on" or "at" another component, it can be "directly on" the other component (i.e., in the absence of intervening medium) or intervening components can also be present. In contrast, when a component is described as being "directly on" or "directly at" another component, then there are no intervening components present. Also, when a component is described as being "formed on" or "formed at" another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0053] In the description of the embodiments of the present application, when a component "comprises" another component, unless otherwise specified, other components are not excluded, and other components can also be further included. In addition, when a layer, film, region, or plate, and the like, is referred to as "on / over" another component, it can be "directly on" the other component (i.e., between the other component and another component, no other component is present), or another component can be present therebetween. In addition, when a layer, film, region, plate, and the like, is "directly on" another component, or when a layer, film, region, plate, and the like, is on the surface of another component, it is indicated that no other component is present therebetween.

[0054] The terms used in the description of various described embodiments herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used in the description of various embodiments of the described embodiments and the appended claims, the phrase "the component" is intended to encompass both singular and plural forms unless the context clearly indicates otherwise. Among other things, components include layers, films, regions, or plates.

[0055] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are presented in order to better enable the reader to understand the embodiments of the present application. However, the technical solutions claimed by the embodiments of the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0056] An embodiment of the present application provides a photovoltaic cell, which will be described in detail below with reference to the accompanying drawings.

[0057] In combination with reference Figure 1 and Figure 2The photovoltaic cell comprises: a substrate 100; a plurality of first electrodes 101 arranged on the surface of the substrate 100 and spaced apart along a first direction X, and a plurality of second electrodes 102 arranged on the surface of the substrate 100 and spaced apart along a second direction Y, the first direction X and the second direction Y intersecting; wherein the surface of the substrate 100 comprises an overlapping region 130 provided with the first electrodes 101 and the second electrodes 102, and the first electrodes 101 in the overlapping region 130 are provided with the second electrodes 102 on the side away from the substrate 100; a dielectric layer 103 at least between the second electrodes 102 and the first electrodes 101, and the dielectric layer 103 in the overlapping region 130 has apertures 113, and at least part of the apertures 113 contain the first electrodes 101 and / or the second electrodes 102, so that the first electrodes 101 and the second electrodes 102 are in contact. In this way, the dielectric layer 103 in the overlapping region 130 can be regarded as a film layer discontinuously distributed between the first electrodes 101 and the second electrodes 102.

[0058] wherein, Figure 1 a partial top view schematic diagram of a photovoltaic cell provided by an embodiment of the present application, Figure 2 as Figure 1 a partial cross-sectional view schematic diagram of the photovoltaic cell shown in the first cross-sectional direction AA1. In addition, Figure 1 the positions of the first electrodes 101 and the second electrodes 102 on the surface of the substrate 100 are schematically shown for clarity, and the dielectric layer is not shown.

[0059] It is worth noting that in the current mainstream electrode design, in order to achieve ohmic contact between the first electrode and the surface of the substrate, the first electrode needs to penetrate other film layers on the surface of the substrate 100, for example, the dielectric layer. Therefore, the raw material of the first electrode usually adopts high-cost high-sintering-through conductive material, which needs high-temperature sintering annealing, is easy to excessively erode part of the film layers in the substrate, affects the performance of the film layer, and also makes the contact morphology of the first electrode and the surface of the substrate not easy to control. Moreover, no additional film layer is designed at the contact position of the first electrode and the second electrode.

[0060] In contrast, in the photovoltaic cell provided by the embodiment of the present application, the first electrode 101 can be designed to be in ohmic contact with the surface of the substrate 100 directly, and on the basis of retaining the dielectric layer 103 between the first electrode 101 and the second electrode 102, the dielectric layer 103 in the overlapping area 130 is designed to have the apertures 113, and at least part of the apertures 113 contain the first electrode 101 and / or the second electrode 102, so as to ensure the ohmic contact between the first electrode 101 and the second electrode 102. In this way, on the one hand, the first electrode 101 is in ohmic contact with the surface of the substrate 100 directly, which is conducive to controlling the good contact morphology between the first electrode 101 and the substrate 100, so as to improve the collection efficiency of the photogenerated carriers in the substrate 100 by the first electrode 101; on the other hand, it is conducive to making the raw material of the first electrode 101 be the low burn-through conductive material or the non-burn-through conductive material with low cost, so that the first electrode 101 is in direct contact with the surface of the substrate 100, and the substrate 100 will not be damaged greatly, and the preparation cost of the first electrode 101 can be reduced; on the other hand, before the second electrode 102 is formed, the first electrode 101 can be protected by the dielectric layer 103, so as to reduce the risk of damage or pollution of the first electrode 101, thereby improving the yield of the first electrode 101; on the other hand, while ensuring the ohmic contact between the first electrode 101 and the second electrode 102 by the dielectric layer 103 in the overlapping area 130, the raw material of the second electrode 102 can also be the low burn-through conductive material or the non-burn-through conductive material with low cost, so as to reduce the preparation cost of the second electrode 102. Therefore, the comprehensive improvement of the electrical performance of the photovoltaic cell is facilitated by the multi-aspect cooperation.

[0061] It should be noted that in the photovoltaic cell provided by the embodiment of the present application, the dielectric layer 103 can be located on other regions of the surface of the substrate 100 in addition to being located between the first electrode 101 and the second electrode 102, so that the dielectric layer 103 can play a role in reducing reflection or protection, which will be described later. Based on this, the dielectric layer 103 between the first electrode 101 and the second electrode 102, i.e., the dielectric layer 103 in the overlapping area 130 has the apertures 113, which is conducive to ensuring the ohmic contact between the first electrode 101 and the second electrode 102 without removing the dielectric layer 103 in the overlapping area 130, and avoiding the etching damage to the first electrode when the dielectric layer in the overlapping area is removed, and the preparation process of the photovoltaic cell can be simplified.

[0062] The photovoltaic cell provided by the embodiment of the present application will be described in more detail below with reference to the accompanying drawings.

[0063] In some embodiments, continuing to refer to Figure 2The first electrode 101 has opposite bottom end 111 and top end 121 along the third direction Z, the bottom end 111 is closer to the substrate 100, and the third direction Z is the thickness direction of the substrate 100; in the dielectric layer 103 in the overlapping area 130, the thickness of the dielectric layer 103 on the surface of the bottom end 111 is greater than or equal to the thickness of the dielectric layer 103 on the surface of the top end 121.

[0064] It should be noted that, Figure 2 In the first electrode 101, the bottom end 111 and the top end 121 are divided by a dashed line, and Figure 2 The divided bottom end 111 and top end 121 are only a relative example, and the proportion of the bottom end 111 and top end 121 in the first electrode 101 is not limited.

[0065] It is worth noting that, based on the manufacturing process of the first electrode 101, the cross-sectional shape of the first electrode 101 along the direction perpendicular to the extension direction of the first electrode 101 can be approximately semicircular. In other words, along the direction gradually away from the substrate 100, the cross-sectional width of at least part of the first electrode 101 gradually decreases. In practical applications, the cross-sectional shape of the first electrode along the direction perpendicular to the extension direction of the first electrode can also be approximately rectangular.

[0066] In addition, when the cross-sectional shape of the first electrode is semicircular, the top end of the first electrode can include a top surface with a larger width in the first direction and a side surface inclined to the center of the top end.

[0067] In some cases, based on the surface topography of the first electrode 101, when the dielectric layer 103 is designed on the surface of the first electrode 101, the dielectric layer 103 with a relatively thick thickness is designed on the bottom end 111, which is beneficial to improve the protection effect of the dielectric layer 103 on the surface contact between the first electrode 101 and the substrate 100; at least the dielectric layer 103 with a relatively thin thickness is designed on the side surface of the top end 121, which is beneficial to reduce the difficulty of forming the pore 113 in the dielectric layer 103, so as to further ensure the ohmic contact between the second electrode 102 and the first electrode 101.

[0068] In addition, in the case that the first electrode 101 protrudes from the surface of the substrate 100, based on the manufacturing process of the dielectric layer 103, the coverage of the dielectric layer 103 at the step changes, which is easy to form the dielectric layer 103 with a relatively thick thickness on the bottom end 111, and at least the dielectric layer 103 with a relatively thin thickness on the side surface of the top end 121. It is worth noting that in the case that the width of the top surface of the top end 121 is small, the top surface of the top end 121 will also form a dielectric layer 103 with a relatively thin thickness. In practical applications, in the case that the width of the top surface of the top end is large, the top surface of the top end will also form a dielectric layer with a relatively thick thickness, for example, the thickness of the dielectric layer on the bottom end is basically the same.

[0069] In some examples, continue to refer to Figure 2 In the dielectric layer 103 located in the overlapping region 130, the thickness of the dielectric layer 103 located on the side of the first electrode 101 gradually decreases along the direction from the bottom end 111 to the top end 121. It is worth noting that when the first electrode 101 protrudes from the surface of the substrate 100, and the cross-sectional width of at least a portion of the first electrode 101 gradually decreases along the direction gradually away from the substrate 100, the dielectric layer 103 has the characteristic of becoming thinner towards the top. The thinner thickness is more advantageous when designing the second electrode 102, so that the dielectric layer 103 located between the second electrode 102 and the first electrode 101 has pores 113.

[0070] It should be noted that the side surface of the first electrode 101 includes the surface of the bottom end 111 and the side surface of the top end 121. In actual application, based on the difference in the width of the top surface of the top end, the thickness of the dielectric layer on the top surface of the top end may be less than the thickness of the dielectric layer on the side surface of the top end, and the thickness of the dielectric layer on the top surface of the top end may also be basically the same as the thickness of the dielectric layer on the bottom end.

[0071] The following provides a detailed description of the layout and location of the dielectric layer 103 on the substrate 100.

[0072] In some embodiments, in conjunction with reference Figure 1 and Figure 3 , Figure 3 for Figure 1 The photovoltaic cell shown is a partial cross-sectional schematic diagram along the second cross-sectional direction BB1. The surface of the substrate 100 may also include a first region 110 on which the first electrode 101 is disposed; the dielectric layer 103 is also located on the first region 110 and on the surface of the first electrode 101 away from the substrate 100.

[0073] It should be noted that the first region 110 can be considered as the area where the first electrode 101 is disposed but the second electrode 102 is not disposed. In other words, the first region 110 can be considered as the area where the first electrode 101 is located except for the portion located in the overlapping region 130, that is, the area where the portion of the first electrode 101 is not covered by the second electrode 102. Thus, if the dielectric layer 103 is designed to be located in the overlapping region 130 and the first region 110, the dielectric layer 103 will cover the entire surface of the first electrode 101, and the surface of the first electrode 101 not covered by the second electrode 102 will also be covered by the dielectric layer 103.

[0074] Generally, the first electrode 101 contains more metal materials, and has stronger reflection ability to incident light. The medium layer 103 is designed to be located in the overlapping region 130 and the first region 110, and the reflectivity of the incident light irradiated to the region where the first electrode 101 is located can be reduced by means of the medium layer 103, that is, the anti-reflection effect of the medium layer 103 can avoid the incident light from being directly irradiated on the surface of the first electrode 101, so as to avoid the phenomenon that a large amount of incident light reflected by the first electrode 101 propagates in a direction away from the substrate 100 and cannot be utilized by the substrate 100, thereby facilitating more incident light to be absorbed and utilized by the substrate 100; on the other hand, the medium layer 103 can play a protective role for the entire first electrode 101.

[0075] It is worth emphasizing that, compared with the medium layer 103 in the overlapping region 130 having the aperture 113, the medium layer 103 in the first region 110 has higher density and good insulation performance, in other words, the medium layer 103 in the first region 110 almost has no aperture that can realize electrical conduction. Alternatively, the medium layer 103 in the overlapping region 130 can be regarded as a film layer discontinuously distributed between the first electrode 101 and the second electrode 102, and the medium layer 103 in the first region 110 can be regarded as a film layer continuously distributed on the surface of the substrate 100. In addition, the thickness of the medium layer 103 in the first region 110 is basically consistent with the thickness of the medium layer 103 in the overlapping region 130.

[0076] Based on this, only the medium layer 103 located between the second electrode 102 and the first electrode 101, that is, the medium layer 103 in the overlapping region 130 has the aperture 113 that can realize electrical conduction, is beneficial to realizing ohmic contact of the first electrode 101 and the second electrode 102 without removing the medium layer 103 in the overlapping region 130 when the medium layer 103 is prepared, and can avoid etching damage to the first electrode when the medium layer in the overlapping region is removed, and can simplify the preparation process of the photovoltaic cell.

[0077] In some cases, continuing to combine reference Figure 1 and Figure 3 The ratio of the area of the overlapping region 130 to the area of the first region 110 can be 0.005% to 1.705%, for example, can be 0.05%, 0.1%, 0.15%, 0.2%, 0.25%, 0.3%, 0.35%, 0.4%, 0.45%, 0.5%, 0.55%, 0.6%, 0.65%, 0.7%, 0.75%, 0.8%, 0.85%, 0.9%, 0.95%, 1%, 1.05%, 1.1%, 1.15%, 1.2%, 1.25%, 1.3%, 1.35%, 1.4%, 1.45%, 1.5%, 1.55%, 1.6%, 1.65% or 1.7%, etc.

[0078] It is worth noting that the area of ​​the overlapping region 130 can be considered as the layout area occupied by the overlapping portions of a single first electrode 101 and a single second electrode 102 on the surface of the substrate 100, and the area of ​​the first region 110 can be considered as the layout area occupied by a single first electrode 101 on the surface of the substrate 100. Designing the ratio of the area of ​​the overlapping region 130 to the area of ​​the first region 110 to be 0.005% to 1.705% is beneficial in ensuring that the single first electrode 101 and the single second electrode 102 have suitable contact areas, and that different regions in the single first electrode 101 can respectively achieve ohmic contact with multiple second electrodes 102, thereby ensuring that the second electrodes 102 have a good current-collecting effect on the charge carriers in the first electrode 101.

[0079] In some embodiments, in conjunction with reference Figures 1 to 4 , Figure 4 for Figure 1 The photovoltaic cell shown is a partial cross-sectional schematic diagram along the third cross-sectional direction CC1. The surface of the substrate 100 may also include a second region 120 on which a second electrode 102 is disposed; the dielectric layer 103 is also located on the second region 120 and between the second electrode 102 and the substrate 100.

[0080] It should be noted that the second region 120 can be considered as the region where the second electrode 102 is disposed but the first electrode 101 is not disposed. In other words, the second region 120 can be considered as the region where the second electrode 102 is located except for the portion located in the overlapping region 130, that is, the region where the portion of the second electrode 102 that does not overlap with the first electrode 101 is located. Thus, if the dielectric layer 103 is designed to be located in the overlapping region 130 and the second region 120, then the second electrode 102 can be considered as being located on the side of the dielectric layer 103 away from the substrate 100, that is, not only is there a dielectric layer 103 including pores 113 disposed between the second electrode 102 and the first electrode 101, but there is also a dielectric layer 103 disposed between the portion of the second electrode 102 that does not overlap with the first electrode 101 and the substrate 100.

[0081] It is worth emphasizing that, compared to the dielectric layer 103 located in the overlap region 130, which has pores 113, the dielectric layer 103 located in the second region 120 has a higher density and better insulation properties. In other words, the dielectric layer 103 located in the second region 120 has almost no pores that can achieve electrical conduction. Alternatively, the dielectric layer 103 located in the overlap region 130 can be regarded as a film layer that is discontinuously distributed between the first electrode 101 and the second electrode 102, while the dielectric layer 103 located in the second region 120 can be regarded as a film layer that is continuously distributed on the surface of the substrate 100.

[0082] In addition, the second electrode 102 is designed to be located above the medium layer 103, so that the second electrode 102 is not covered by the medium layer 103, and the medium layer 103 does not cause failure in the subsequent electrical connection of the second electrode 102 in the two adjacent photovoltaic cells by the solder strip. In other words, the second electrode 102 is designed to be exposed above the medium layer 103, so as to facilitate the subsequent effective electrical connection of the solder strip to the second electrode 102. Moreover, compared with the scheme of forming the medium layer with the anti-reflection function on the surface of the first electrode and the second electrode and removing the medium layer on the surface of the second electrode, the photovoltaic cell provided by the embodiment of the present application does not need to perform the operation of removing the medium layer on the surface of the second electrode 102, so that the etching damage to the second electrode 102 can be avoided, and the preparation process of the photovoltaic cell can be simplified.

[0083] In some cases, in combination with reference to Figures 1 to 4 The medium layer 103 is located on the first area 110, the second area 120, and the overlapping area 130. Unlike the surface of the entire first electrode 101 away from the substrate 100 being covered by the medium layer 103, the entire second electrode 102 can be considered to be located on the side of the medium layer 103 away from the substrate 100, and the medium layer 103 located between the second electrode 102 and the first electrode 101 has an aperture 113, so that the second electrode 102 and the first electrode 101 are in ohmic contact.

[0084] In some embodiments, in combination with reference to Figures 1 to 4 The surface of the substrate 100 can further include a third area 140, which is an area without the first electrode 101 and the second electrode 102; and the medium layer 103 is also located on the third area 140. In this way, the substrate 100 can be protected by the medium layer 103 located on the third area 140, and the risk of reflection of the light incident on the third area 140 can be reduced, thereby improving the absorption and utilization of light by the substrate 100 located on the third area 140.

[0085] It is worth emphasizing that, compared with the medium layer 103 located in the overlapping area 130 having the aperture 113, the medium layer 103 located in the third area 140 has a higher density and good insulation performance, that is, the medium layer 103 located in the third area 140 has almost no aperture that can realize electrical conduction. In other words, the medium layer 103 located in the overlapping area 130 can be considered as a non-continuous film layer between the first electrode 101 and the second electrode 102, and the medium layer 103 located in the third area 140 can be considered as a continuous film layer on the surface of the substrate 100.

[0086] In some cases, in combination with reference to Figures 1 to 4The medium layer 103 can be located on the first area 110, the second area 120, the overlapping area 130 and the third area 140. In other words, the medium layer 103 can be located on the entire surface of the substrate 100, and the first electrode 101 is arranged between the medium layer 103 and the substrate 100, and the second electrode 102 is arranged on the side of the medium layer 103 away from the substrate 100.

[0087] In some embodiments, in combination with reference to Figures 1 to 4 The surface of the substrate 100 can further include a protection area in addition to the overlapping area 130, the protection area being an area where the first electrode 101 is not arranged, and the medium layer 103 is also located on at least part of the area of the protection area; wherein the ratio of the thickness of the medium layer 103 located in the overlapping area 130 to the thickness of the medium layer 103 located in the protection area can be 30% to 50%, for example, can be 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48% or 49%, etc.

[0088] It should be noted that the protection area includes at least one of the second area 120 and the third area 140. In addition, compared with the medium layer 103 located in the overlapping area 130 having the pores 113, the medium layer 103 located in the protection area, for example, the medium layer 103 located in any one of the second area 120 and the third area 140, has higher density. In other words, the medium layer 103 located in any one of the second area 120 and the third area 140 has almost no pores that can realize electrical conduction, that is, the medium layer 103 located in any one of the second area 120 and the third area 140 has good insulation performance, avoiding unnecessary electrical connection between the first electrode 101 and other conductive components in the subsequent process, and the medium layer 103 located in any one of the second area 120 and the third area 140 can be used as an anti-reflection layer to reduce the reflectivity of the incident light, greatly increasing the area of the region in the substrate 100 that can be used to efficiently absorb the incident light, to reduce optical reflection loss and improve the current density of the photovoltaic cell. In addition, the medium layer 103 can cover the entire surface formed by the substrate 100 and the first electrode 101.

[0089] It is worth noting that, since the surface of the substrate 100 has been designed with the first electrode 101 before the design of the medium layer 103, the surface formed by the substrate 100 and the first electrode 101 is in a convex state at the area where the first electrode 101 is located. Based on the manufacturing process of the medium layer 103, the coverage of the medium layer 103 at the convex part changes, so that the thickness of the medium layer 103 located in the protection area is greater than the thickness of at least part of the medium layer 103 located in the overlapping area 130, and the thickness of the medium layer 103 located in the protection area is greater than the thickness of at least part of the medium layer 103 located in the first area 110. Based on the control of the manufacturing process of the medium layer 103, the ratio of the thickness of the medium layer 103 located in the overlapping area 130 to the thickness of the medium layer 103 located in the protection area can be designed to be 30% to 50%. In this way, it is beneficial to ensure that a relatively thick medium layer 103 is arranged on the protection area to improve the protection effect and the anti-reflection effect of the substrate 100, while a relatively thin medium layer 103 is arranged on the overlapping area 130 to reduce the difficulty of forming the aperture 113 in the medium layer 103 located in the overlapping area 130, so as to further ensure the ohmic contact between the second electrode 102 and the first electrode 101.

[0090] In some cases, the thickness of the medium layer 103 located in the protection area can be 30nm to 200nm, for example, it can be 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm or 190nm, etc.

[0091] In some embodiments, referring to Figures 2 to 4 The photovoltaic cell can further include a transparent conductive layer 104 located between the medium layer 103 and the substrate 100 and between the first electrode 101 and the substrate 100.

[0092] It is worth noting that the transparent conductive layer 104 is used to assist the electrical connection between the first electrode 101 and the substrate 100. The transparent conductive layer 104 can be arranged on at least the area used to prepare the first electrode 101, i.e., the first area 110, before the design of the first electrode 101. Generally, the transparent conductive layer 104 can be arranged on the periphery of the first area 110 in addition to the first area 110 in the surface of the substrate 100. In other words, the orthographic projection of the first electrode 101 on the substrate 100 is located in the orthographic projection of the transparent conductive layer 104 on the substrate 100, and the area of the orthographic projection of the transparent conductive layer 104 on the substrate 100 can be greater than or equal to the area of the orthographic projection of the first electrode 101 on the substrate 100.

[0093] In addition, the medium layer 103 between the first electrode 101 and the second electrode 102, i.e., the medium layer 103 in the overlapping region 130 has the aperture 113, which is beneficial to ensure the ohmic contact of the first electrode 101 and the second electrode 102 without removing the medium layer 103 in the overlapping region 130. This not only avoids the etching damage to the first electrode caused by removing the medium layer in the overlapping region, but also avoids the etching damage to the transparent conductive layer in contact with the first electrode, reduces the risk of additional defects in multiple film layers, and thus further ensures the excellent electrical performance of the photovoltaic cell.

[0094] In some cases, referring to Figure 1 , the photovoltaic cell can be a cell with electrodes on both sides, such as a TOPCON cell, a PERC cell, or a heterojunction cell. Based on this, the polarity of the first electrode 101 on the same surface of the substrate 100 is the same, and the transparent conductive layer 104 (referring to Figure 2 ) can be located on the entire surface of the substrate 100.

[0095] In other cases, referring to Figure 5 , Figure 5 is another partial top view schematic diagram of a photovoltaic cell provided by an embodiment of the present application. The photovoltaic cell can be a cell with electrodes on one side, such as a BC cell. Based on this, the polarity of the two adjacent first electrodes 101 in the first direction X is different, for example, the first electrode 101 includes the first current collecting electrode 131 and the second current collecting electrode 141, and the transparent conductive layer 104 in contact with the two first electrodes 101 with different polarities has a spacing, in other words, the transparent conductive layer 104 (referring to Figure 2 ) can correspond to the first electrode 101 one by one.

[0096] It should be noted that Figure 2 can also be regarded as a partial cross-sectional view schematic diagram of the photovoltaic cell along the first cross-sectional direction AA1 shown in Figure 5 ; Figure 3 can also be regarded as a partial cross-sectional view schematic diagram of the photovoltaic cell along the second cross-sectional direction BB1 shown in Figure 5 ; Figure 4 can also be regarded as a partial cross-sectional view schematic diagram of the photovoltaic cell along the third cross-sectional direction CC1 shown in Figure 5 ;

[0097] In some cases, continuing to refer to Figures 2 to 4The thickness of the transparent conductive layer 104 can be 20 nm to 200 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, or 190 nm, etc.

[0098] In some embodiments, reference is made to Figures 1 to 5 The material of the first electrode 101 can include a metal or a mixture of a metal and an organic polymer.

[0099] In some embodiments, reference is made to Figures 1 to 5 The material of the second electrode 102 can include a metal or a mixture of a metal and an organic polymer.

[0100] In the above two embodiments, the metal can include at least one of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, or Sn.

[0101] In some embodiments, reference is made to Figures 1 to 5 The material of the dielectric layer 103 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or magnesium fluoride.

[0102] In some embodiments, reference is made to Figures 1 to 5 The dielectric layer 103 can be a single-layer structure or a stacked structure.

[0103] In some embodiments, reference is made to Figures 1 to 5 The refractive index of the dielectric layer 103 can be 1.46 to 2.5, for example, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, 2, 2.05, 2.1, 2.15, 2.2, 2.25, 2.3, 2.35, 2.4, or 2.45, etc.

[0104] In some embodiments, reference is made to Figures 1 to 3 The width of the overlapping region 130 in the direction perpendicular to the extension direction of the first electrode 101 can be 5 μm to 40 μm, for example, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, or 35 μm, etc. It should be noted that the width of the overlapping region 130 can be regarded as the width of the first electrode 101, and thus the width of the first electrode 101 can also be 5 μm to 40 μm.

[0105] In some embodiments, reference is made to Figures 1 to 3The height of the first electrode 101 in the third direction Z can be 5 μm to 30 μm, for example, 10 μm, 15 μm, 20 μm, or 25 μm, etc. The third direction Z is the thickness direction of the substrate 100.

[0106] It should be noted that the cross-sectional shape of the first electrode 101 in the cross section perpendicular to the extension direction of the first electrode 101 can be approximately semicircular or rectangular, and the height of the first electrode 101 can be considered as the average height of different parts of the first electrode 101.

[0107] Based on different designs inside the substrate 100, the photovoltaic cell can include at least the following two types.

[0108] In some embodiments, referring to Figure 6 , Figure 6 A partial cross-sectional schematic view of a photovoltaic cell provided by an embodiment of the present application can include: a substrate 105, one surface 135 of the substrate 105 including fourth regions 115 and fifth regions 125 arranged alternately in the first direction X; a first semiconductor layer 116 on the fourth region 115, and a first doped layer 117 on the side of the first semiconductor layer 116 away from the substrate 105; a second semiconductor layer 126 on the fifth region 125, and a second doped layer 127 on the side of the second semiconductor layer 126 away from the substrate 105, the second doped layer 127 and the first doped layer 117 being doped with different types of doping elements; and a first electrode 101 including a first current collecting electrode 131 on the fourth region 115 and a second current collecting electrode 141 on the fifth region 125, the first current collecting electrode 131 being electrically connected to the first doped layer 117, and the second current collecting electrode 141 being electrically connected to the second doped layer 127. In this way, the photovoltaic cell can be considered as a BC cell, and the first electrode 101 and the second electrode 102 are provided on only one surface of the substrate 100 (see Figure 5 ), and the first electrode 101 includes the first current collecting electrode 131 and the second current collecting electrode 141 with different polarities.

[0109] The types of BC cells are described in detail below.

[0110] In some cases, the first semiconductor layer 116 and the second semiconductor layer 126 can be tunneling layers, and the first doped layer 117 and the second doped layer 127 can be doped polysilicon layers. In this way, the photovoltaic cell is a TBC cell (TOPCon BackContact, referring to a cross-passivation back contact cell).

[0111] In some examples, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC (heterojunction back contact) cell.

[0112] In some examples, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC (heterojunction back contact) cell.

[0113] In some examples, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC (heterojunction back contact) cell.

[0114] In some examples, the N-type doping element can be at least one of a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element, etc. A P-type semiconductor substrate is doped with a P-type element, and the P-type doping element can be at least one of a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or an indium (In) element, etc.

[0115] In some examples, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC (heterojunction back contact) cell. Figure 7 or Figure 8 In some examples, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC (heterojunction back contact) cell.

[0116] In some examples, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC (heterojunction back contact) cell. Figure 7 In some examples, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC (heterojunction back contact) cell. Figure 8Another partial cross-sectional schematic view of a photovoltaic cell is provided for an embodiment of the present application.

[0117] It should be noted that the two surfaces 135 of the substrate 105 opposite along the third direction Z can be a first surface 1351 and a second surface 1352 respectively. In some examples, continuing to refer to Figure 7 or Figure 8 , the semiconductor layer 106 and the doped layer 107 are located on the first surface 1351, and the first current collecting electrode 131 is located on the second surface 1352.

[0118] The type of the cell with electrodes on both sides is described in detail below.

[0119] In some cases, referring to Figure 7 , the semiconductor layer 106 can be a tunneling layer, and the doped layer 107 can be a doped polysilicon layer. In this way, the photovoltaic cell is a TOPCON cell.

[0120] In other cases, referring to Figure 8 , the semiconductor layer 106 is an intrinsic amorphous silicon layer, and the doped layer 107 is a doped amorphous silicon layer.

[0121] In some examples, continuing to refer to Figures 1 to 10 , the semiconductor layer 106 is a first intrinsic amorphous silicon layer, and the doped layer 107 is a first doped amorphous silicon layer, and the first intrinsic amorphous silicon layer and the first doped amorphous silicon layer are stacked on the first surface 1351; the substrate 100 can further include: a second intrinsic amorphous silicon layer 136 located on the second surface 1352; a second doped amorphous silicon layer 137 located on a side of the second intrinsic amorphous silicon layer 136 away from the second surface 1352; and a second current collecting electrode 141 located on a side of the second doped amorphous silicon layer 137 away from the second intrinsic amorphous silicon layer 136. In this way, the photovoltaic cell is a heterojunction cell.

[0122] In the various embodiments described above, the material of the tunneling layer can include one or more of silicon oxide, silicon carbide, silicon nitride, and silicon oxynitride.

[0123] In summary, the first electrode 101 is designed to be in ohmic contact with the surface of the substrate 100 directly, and on the basis of reserving the dielectric layer 103 between the first electrode 101 and the second electrode 102, the dielectric layer 103 in the overlapping area 130 is designed to have the apertures 113, and at least part of the apertures 113 contain the first electrode 101 and / or the second electrode 102, so as to ensure the ohmic contact between the first electrode 101 and the second electrode 102. In this way, on the one hand, the first electrode 101 is in ohmic contact with the surface of the substrate 100 directly, which is conducive to controlling the first electrode 101 and the substrate 100 to have a good contact morphology, so as to improve the collection efficiency of the first electrode 101 to the photo-generated carriers in the substrate 100; on the other hand, it is conducive to making the raw material of the first electrode 101 be able to use low-cost low-burn-through conductive materials or non-burn-through conductive materials, so that the first electrode 101 is in direct contact with the surface of the substrate 100, and the substrate 100 will not be damaged, and the preparation cost of the first electrode 101 can be reduced; on the other hand, before the second electrode 102 is formed, the first electrode 101 can be protected by the dielectric layer 103, so as to reduce the risk of damage or pollution of the first electrode 101, thereby improving the yield of the first electrode 101; on the other hand, while the dielectric layer 103 in the overlapping area 130 with the apertures 113 ensures the ohmic contact between the first electrode 101 and the second electrode 102, it also makes the raw material of the second electrode 102 be able to use low-cost low-burn-through conductive materials or non-burn-through conductive materials, so as to reduce the preparation cost of the second electrode 102. Therefore, the comprehensive improvement of the electrical performance of the photovoltaic cell is conducive to the comprehensive improvement of the electrical performance of the photovoltaic cell.

[0124] Another embodiment of the present application also provides a manufacturing method of a photovoltaic cell for forming the photovoltaic cell provided by the foregoing embodiments. The manufacturing method of the photovoltaic cell provided by another embodiment of the present application will be described in detail below in combination with the drawings. It should be noted that the same or corresponding parts of the foregoing embodiments will not be described herein.

[0125] In combination with Figure 9 , Figure 1 A process flow chart of the manufacturing method of the photovoltaic cell provided by another embodiment of the present application is shown in FIG. 6. The manufacturing method of the photovoltaic cell at least includes the following steps:

[0126] S1: referring to any one of Figures 5 to 8 , Figure 1 , a substrate 100 is provided.

[0127] S2: referring to Figure 5 or Figure 10 , a plurality of first electrodes 101 are formed on the surface of the substrate 100 and arranged at intervals along the first direction X.

[0128] S3: referring to Figure 10, Figure 10 A partial sectional view of a semi-finished product along the first cross-sectional direction AA1 after forming the initial medium layer in the method for manufacturing the photovoltaic cell according to another embodiment of the present application is shown in FIG. 4. The initial medium layer 123 is formed on the surface constituted by the substrate 100 and the first electrode 101.

[0129] S4: Combination reference Figure 2 and Figure 5 The second electrode 102 is formed on the surface of the initial medium layer 123 in the second direction Y. The first direction X and the second direction Y intersect. The surface of the substrate 100 includes the overlapping region 130 where the first electrode 101 and the second electrode 102 are arranged simultaneously. During the formation of the second electrode 102, the initial medium layer 123 in the overlapping region 130 is converted into the medium layer 103 with the pores 113. At least part of the pores 113 contain the first electrode 101 and / or the second electrode 102, so that the first electrode 101 and the second electrode 102 are in contact.

[0130] It is worth noting that the step of forming the initial medium layer 123 is interposed between the steps of forming the first electrode 101 and the second electrode 102. First, after the formation of the first electrode 101, the surface constituted by the substrate 100 and the first electrode 101 is uneven because the first electrode 101 protrudes from the surface of the substrate 100. Based on this, the thickness of the initial medium layer 123 formed on the overlapping region 130 is thin and it is difficult to form a dense initial medium layer 123 on the overlapping region 130 because of the decrease in the coverage of the film layer at the mutation or step during the preparation of the initial medium layer 123. In other words, the initial medium layer 123 formed on the overlapping region 130 is loose itself. Further, after the formation of the initial medium layer 123, the second electrode 102 is formed. The initial medium layer 123 in the overlapping region 130 is easily penetrated by the second electrode 102 because of the thin thickness and the looseness of the initial medium layer 123 in the overlapping region 130. The pores 113 containing the first electrode 101 and / or the second electrode 102 are formed in the initial medium layer 123 in the overlapping region 130 due to the influence of the thermal stress during the formation of the second electrode 102. In this way, the ohmic contact between the first electrode 101 and the second electrode 102 can be achieved without using an additional process to remove the medium layer 103 between the first electrode 101 and the second electrode 102. This avoids etching damage to the first electrode 101 and is conducive to simplifying the manufacturing process of the photovoltaic cell and reducing the manufacturing cost of the photovoltaic cell.

[0131] In addition, the initial medium layer 123 in the area outside the overlapping area 130 can be regarded as the medium layer 103 without the pores capable of realizing the electrical conduction, and can play the effect of insulation and anti-reflection, so as to reduce the reflectivity of the incident light and improve the absorption and utilization of the light by the substrate 100. On this basis, in the manufacturing method of the photovoltaic cell provided by another embodiment of the present application, the preparation process of the medium layer 103 playing the effect of insulation and anti-reflection can be integrated into the steps of forming the first electrode 101 and the second electrode 102, so as to simplify the manufacturing process of the photovoltaic cell as much as possible.

[0132] For example, compared with the technical solution of forming the first electrode after forming the medium layer playing the effect of insulation and anti-reflection, the first electrode needs to have high burn-through to realize the ohmic contact with the surface of the medium layer and the substrate, and in the manufacturing method of the photovoltaic cell provided by another embodiment of the present application, the first electrode 101 directly ohmic contacts with the surface of the substrate 100 before the initial medium layer 123 is formed. This not only helps to control the good contact morphology between the first electrode 101 and the substrate 100, so as to improve the collection efficiency of the photogenerated carriers in the substrate 100 by the first electrode 101, but also helps to use the low-cost low-burn-through conductive material or non-burn-through conductive material as the raw material of the first electrode 101, so that the first electrode 101 directly contacts with the surface of the substrate 100 and does not cause great damage to the substrate 100, and the preparation cost of the first electrode 101 can be reduced. In addition, before the second electrode 102 is formed, the first electrode 101 can be protected by the medium layer 103, so as to reduce the risk of damage or pollution of the first electrode 101, thereby improving the yield of the first electrode 101.

[0133] Compared with the technical solution of forming the medium layer playing the effect of insulation and anti-reflection after forming the first electrode and the second electrode, the medium layer on the surface of the second electrode needs to be removed in order to facilitate the subsequent electrical connection between the second electrode and the solder strip in the adjacent photovoltaic cell. In the manufacturing method of the photovoltaic cell provided by another embodiment of the present application, the second electrode 102 is formed outside the medium layer 103, so that the second electrode 102 is not blocked by the medium layer 103, and there is no need to remove the medium layer 103 by using an additional process, which can avoid etching damage to the second electrode 102, help to simplify the manufacturing process of the photovoltaic cell and reduce the manufacturing cost of the photovoltaic cell, and ensure that the subsequent solder strip and the second electrode 102 have good electrical connection performance.

[0134] In some cases, the raw material of the second electrode 102 can also be a low-cost low-burn-through conductive material or a non-burn-through conductive material, so as to reduce the preparation cost of the second electrode 102.

[0135] The manufacturing method of the photovoltaic cell provided by an embodiment of the present application will be described in more detail below with reference to the accompanying drawings.

[0136] In some embodiments, in combination with reference to Figure 6 and Figure 6 , the step of providing the substrate 100 can comprise: providing a substrate 105, one surface 135 of the substrate 105 comprising fourth regions 115 and fifth regions 125 arranged alternately along the first direction X; forming a first semiconductor layer 116 on the fourth regions 115, and a first doped layer 117 on a side of the first semiconductor layer 116 away from the substrate 105; forming a second semiconductor layer 126 on the fifth regions 125, and a second doped layer 127 on a side of the second semiconductor layer 126 away from the substrate 105, the second doped layer 127 and the first doped layer 117 being doped with different types of doping elements.

[0137] On this basis, the step of forming the first electrode 101 can comprise: forming a first current collector 131 on a side of the first doped layer 117 away from the fourth regions 115, and the first current collector 131 being electrically connected to the first doped layer 117; forming a second current collector 141 on a side of the second doped layer 127 away from the fifth regions 125, and the second current collector 141 being electrically connected to the second doped layer 127; the first electrode 101 comprising the first current collector 131 and the second current collector 141 with different polarities. In this way, the photovoltaic cell can be regarded as a BC cell, and the first electrode 101 and the second electrode 102 are provided on only one surface of the substrate 100. It should be noted that the fourth regions 115 and the fifth regions 125 are both a type of the first regions 110.

[0138] The materials of the first semiconductor layer 116, the first doped layer 117, the second semiconductor layer 126 and the second doped layer 127 and the type of the photovoltaic cell are described in detail below.

[0139] In some cases, the first semiconductor layer 116 and the second semiconductor layer 126 can be tunneling layers, and the first doped layer 117 and the second doped layer 127 can be doped polysilicon layers. In this way, the photovoltaic cell is a TBC cell.

[0140] In other cases, the first semiconductor layer 116 and the second semiconductor layer 126 can be intrinsic amorphous silicon layers, and the first doped layer 117 and the second doped layer 127 can be doped amorphous silicon layers. In this way, the photovoltaic cell is a HBC cell.

[0141] In yet other cases, the first semiconductor layer 116 can be a tunneling layer, the first doped layer 117 can be a doped polysilicon layer, the second semiconductor layer 126 can be an intrinsic amorphous silicon layer, and the second doped layer 127 can be a doped amorphous silicon layer. In practical applications, the first semiconductor layer can also be an intrinsic amorphous silicon layer, the first doped layer can be a doped amorphous silicon layer, the second semiconductor layer can be a tunneling layer, and the second doped layer can be a doped polysilicon layer. In this way, the photovoltaic cell is a HTBC cell.

[0142] It should be noted that the method for manufacturing a photovoltaic cell provided by another embodiment of the present application does not limit the forming process steps of the first semiconductor layer 116, the first doped layer 117, the second semiconductor layer 126 and the second doped layer 127, which can be adjusted according to actual process.

[0143] In some cases, continuing to refer to Figure 7 After the substrate 100 is provided, before the first electrode 101 is formed, the method for manufacturing a photovoltaic cell can further include: forming a transparent conductive layer 104 on the surface of the substrate 100, and subsequently forming the first electrode 101 on the side of the transparent conductive layer 104 away from the substrate.

[0144] In another embodiment, referring to Figure 8 or Figure 7 The step of providing the substrate 100 can include: providing a substrate 105 having two surfaces 135 opposite along a third direction Z; forming a semiconductor layer 106 on one of the two surfaces 135, for example, a first surface 1351; and forming a doped layer 107 on the side of the semiconductor layer 106 away from the substrate 105.

[0145] On this basis, the step of forming the first electrode 101 includes: forming a first current collecting electrode 131 on the side of the doped layer 107 away from the substrate 105, and the first current collecting electrode 131 and the first doped layer 117 are electrically connected; forming a second current collecting electrode 141 on the other of the two surfaces 135, for example, a second surface 1352; and the first electrode 101 includes the first current collecting electrode 131 and the second current collecting electrode 141. In this way, the photovoltaic cell can be regarded as a cell with electrodes on both sides. It should be noted that the method for manufacturing a photovoltaic cell provided by another embodiment of the present application does not limit the forming order of the first current collecting electrode 131 and the second current collecting electrode 141.

[0146] In some cases, the step of forming the second current collector 141 after forming the first current collector 131 can include: first forming an initial first current collector on the side of the doped layer 107 away from the substrate 105, and then baking the initial first current collector; then forming an initial second current collector on the other one of the two surfaces 135, for example, the second surface 1352, and then baking the initial second current collector; and finally solidifying both the initial first current collector and the initial second current collector to convert the initial first current collector into the first current collector 131 and convert the initial second current collector into the second current collector 141. It is worth noting that, before forming the initial second current collector, the initial first current collector is baked to reduce its fluidity and stickiness, which is conducive to avoiding damage to the initial first current collector when the semi-finished battery is flipped, for example, avoiding the initial first current collector from being left on the conveyor belt when the initial first current collector contacts the conveyor belt. After forming the initial second current collector, the initial first current collector and the initial second current collector are solidified, which is also conducive to simplifying the manufacturing process of the first electrode 101.

[0147] The materials of the semiconductor layer 106 and the doped layer 107 and the type of the photovoltaic cell will be described in detail below.

[0148] In some cases, referring to Figure 8 The semiconductor layer 106 can be a tunneling layer, and the doped layer 107 can be a doped polysilicon layer. In this way, the photovoltaic cell is a TOPCON cell.

[0149] In other cases, referring to Figure 8 The semiconductor layer 106 is an intrinsic amorphous silicon layer, and the doped layer 107 is a doped amorphous silicon layer.

[0150] In some examples, continuing to refer to Figure 10 The semiconductor layer 106 is a first intrinsic amorphous silicon layer, and the doped layer 107 is a first doped amorphous silicon layer. The first intrinsic amorphous silicon layer and the first doped amorphous silicon layer are stacked on the first surface 1351. The photovoltaic cell further includes: a second intrinsic amorphous silicon layer 136 on the second surface 1352; a second doped amorphous silicon layer 137 on the side of the second intrinsic amorphous silicon layer 136 away from the second surface 1352; and a second current collector 141 on the side of the second doped amorphous silicon layer 137 away from the second intrinsic amorphous silicon layer 136. In this way, the photovoltaic cell is an HJT cell. The manufacturing method of the photovoltaic cell provided by another embodiment of the present application will be described in detail below with the final photovoltaic cell being an HJT cell as an example.

[0151] In some embodiments, referring to Figure 10The initial medium layer 123 is formed by a deposition process. The deposition process can be performed at a temperature of 100-300°C, for example, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, or 290°C. The deposition process can be performed for a time period of 10-120 minutes, for example, 20, 30, 40, 50, 60, 70, 80, 90, 100, or 110 minutes.

[0152] In some cases, the deposition process for forming the initial medium layer 123 can be a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, a HWCVD (Hot Wire Assisted Chemical Vapor Deposition) process, or an ALD (Atomic Layer Deposition) process.

[0153] In some cases, the initial medium layer 123 can have a thickness of 60-200 nm, for example, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160, 170, 180, or 190 nm.

[0154] In some embodiments, in combination with reference to Figure 2 and Figure 8 The step of forming the second electrode 102 can include: forming a plurality of initial second electrodes on the surface of the initial medium layer 123, the initial second electrodes being arranged at intervals along the second direction Y; and sequentially performing a drying treatment and a curing treatment on the initial second electrodes to convert the initial second electrodes into the second electrode 102. The drying treatment can be performed at a temperature of 100-200°C for a time period of 1-10 minutes. The curing treatment can be performed at a temperature of 60-250°C for a time period of 0-60 minutes.

[0155] It is worth noting that in the drying treatment and the curing treatment, the treatment temperature is higher than the normal temperature, so that the initial dielectric layer 123 with a thin thickness in the overlapping area 130 is easily affected by thermal stress, and then the pores 113 appear in the film layer. Moreover, the second electrode 102 further penetrates into the loose initial dielectric layer 123, and the first electrode 101 can also penetrate into the pores 113 under the influence of thermal stress, so that the first electrode 101 and the second electrode 102 can be in ohmic contact even if there is a dielectric layer 103 between them.

[0156] In some cases, the treatment temperature of the drying treatment can be 110°C, 120°C, 130°C, 140°C, 150°C, 160°C, 170°C, 180°C, or 190°C, etc.

[0157] In some cases, the treatment time of the drying treatment can be 2 min, 3 min, 4 min, 5 min, 6 min, 7 min, 8 min, or 9 min, etc.

[0158] In some cases, the treatment temperature of the curing treatment can be 70°C, 80°C, 90°C, 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, or 240°C, etc.

[0159] In some cases, the treatment time of the curing treatment can be 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, or 55 min, etc.

[0160] The following is a method for manufacturing a HJT cell provided by another embodiment of the present application, that is Figures 1 to 8 The specific embodiments of the photovoltaic cell shown correspond to the comparative examples related thereto:

[0161] Embodiment 1

[0162] The back contact cell 1 is prepared by the following steps:

[0163] (1) An N-type silicon wafer is selected, the resistivity of the N-type silicon wafer is about 0.5Ω·m~8Ω·m, the thickness of the N-type single crystal silicon wafer in the third direction Z is about 100μm~200μm, the short side length of the N-type silicon wafer can be 182mm, and the long side length of the N-type silicon wafer can be 210mm.

[0164] (2) The N-type silicon wafer is cleaned and textured. For example, the cleaning process can use a dilute hydrofluoric acid solution with a concentration of 5% to remove the surface oxide layer; the texturing process can use potassium hydroxide, sodium hydroxide or tetramethylammonium hydroxide plus alcohol method, using the anisotropic etching of single crystal silicon to form a relatively shallow pyramid structure on the surface of the N-type silicon wafer, so as to obtain the substrate 105.

[0165] (3) The substrate 105 is placed in a vacuum chamber, then silane gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer, i.e. the semiconductor layer 106, is formed on the entire area of the first surface 1351 of the substrate 105 by a plasma chemical vapor deposition process. Then silane gas, hydrogen gas and phosphine gas are introduced into the vacuum chamber, and a doped amorphous silicon layer doped with N-type dopant elements, i.e. the doped layer 107, is formed on the intrinsic amorphous silicon layer by a plasma chemical vapor deposition process.

[0166] (4) The semi-finished battery formed after step (3) is turned over, the tray carrying the semi-finished battery is replaced, then silane gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer, i.e. the second intrinsic amorphous silicon layer 136, is formed on the entire area of the second surface 1352 of the substrate 105 by a plasma chemical vapor deposition process; then silane gas, hydrogen and diborane gas are introduced into the vacuum chamber, and a doped amorphous silicon layer doped with P-type dopant elements, i.e. the second doped amorphous silicon layer 137, is formed on the intrinsic amorphous silicon layer by a plasma chemical vapor deposition process, so as to obtain the substrate 100.

[0167] (5) A RPD (reactive plasma deposition) process or a magnetron sputtering process is used for film plating to form a transparent conductive layer 104 on the intrinsic amorphous silicon layer located on the first surface 1351 and the second surface 1352, and the thickness of the transparent conductive layer 104 can be 20 nm to 200 nm.

[0168] (6) Forming an initial first current collecting electrode on the first area and the overlapping area of the second surface 1352 by one or more steps of printing, the printing process including but not limited to screen printing, steel mesh printing, laser transfer printing or copper electroplating, etc., the width of the initial first current collecting electrode can be 5 μm to 40 μm, and the height of the initial first current collecting electrode can be 5 μm to 30 μm; performing 1 time of drying treatment on the initial first current collecting electrode, the processing temperature of the drying treatment is 100 ℃ to 200 ℃, and the processing time of the drying treatment is 1 min to 10 min; then, forming an initial second current collecting electrode on the first area and the overlapping area of the first surface 1351 by one or more steps of printing, the width of the initial second current collecting electrode can be 5 μm to 40 μm, and the height of the initial second current collecting electrode can be 5 μm to 30 μm; performing 1 time of drying treatment on the initial second current collecting electrode, the processing temperature of the drying treatment is 100 ℃ to 200 ℃, and the processing time of the drying treatment is 1 min to 10 min; performing 1 time of curing treatment on the initial first current collecting electrode and the initial second current collecting electrode, the processing temperature of the curing treatment is 60 ℃ to 250 ℃, and the processing time of the curing treatment is 0 min to 60 min, the initial first current collecting electrode is converted into the first current collecting electrode 131, and the initial second current collecting electrode is converted into the second current collecting electrode 141, so as to complete the manufacturing of the first electrode 101.

[0169] (7) Depositing an initial dielectric layer 123 on the first surface 1351 and the second surface 1352 after forming the first electrode 101 by PECVD process, HWCVD process or ALD process, the initial dielectric layer can be a single-layer structure or a laminated structure including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or magnesium fluoride.

[0170] (8) Form a second electrode 102 on the semi-finished product battery formed after step (7). Specifically, by one or more steps of printing, the printing process includes but is not limited to screen printing, steel mesh printing, laser transfer printing or copper electroplating, etc. Form an initial second electrode on the second area and the overlapping area of the second surface 1352, which can be called an initial first bus electrode, and the area ratio of the overlapping area to the first area can be 0.005%~1.705%; the initial second electrode formed on the second surface 1352, i.e. the initial first bus electrode, is subjected to 1 drying treatment, and the process parameters of the drying treatment can be the same as those of the drying treatment in step (6); then, by one or more steps of printing, an initial second electrode is also formed on the second area and the overlapping area of the first surface 1351, which can be called an initial second bus electrode; the initial second electrode formed on the first surface 1351, i.e. the initial second bus electrode, is subjected to 1 drying treatment, and the process parameters of the drying treatment can be the same as those of the drying treatment in step (6); the initial second electrode located on the two surfaces 135, i.e. the initial first bus electrode and the initial second bus electrode, is subjected to 1 curing treatment, and the curing treatment temperature is 60℃~250℃, and the curing treatment time is 0min~60min. The initial first bus electrode is converted into a first bus electrode, and the initial second bus electrode is converted into a second bus electrode, and the second electrode 102 includes the first bus electrode and the second bus electrode, to complete the manufacturing of the second electrode 102.

[0171] Comparative Example 1

[0172] The back contact battery 2 is prepared by the following steps:

[0173] Steps (1) to (6) are the same as those of Example 1, and will not be repeated here.

[0174] (7) Form a second electrode on the surface formed by the first electrode and the substrate before forming the medium layer with anti-reflection effect.

[0175] (8) Form a medium layer with anti-reflection effect on the semi-finished product battery formed after step (7). In this way, when the adjacent photovoltaic cells are electrically connected by the solder strip, the solder strip cannot be effectively electrically connected with the second electrode due to the barrier of the medium layer.

[0176] Comparative Example 2

[0177] The back contact battery 3 is prepared by the following steps:

[0178] Steps (1) to (6) are the same as those of Example 1, and will not be repeated here.

[0179] (7) Before forming a dielectric layer that has an anti-reflection effect, a second electrode is formed directly on the surface formed by the first electrode and the substrate.

[0180] (8) A dielectric layer that has an anti-reflection effect is formed on the semi-finished battery formed after step (7).

[0181] (9) Remove the dielectric layer on the surface of the second electrode so that the subsequent solder ribbon can achieve effective electrical connection with the exposed second electrode. In this step, the removal process is prone to causing etching damage to the second electrode, and may also cause etching damage to the doped amorphous silicon layer on the transparent conductive layer, which can easily reduce the electrical connection performance of the subsequent solder ribbon and the second electrode, as well as reduce the electrical performance of the photovoltaic cell.

[0182] Table 1 shows the electrical performance indices for back contact battery 1, back contact battery 2, and back contact battery 3.

[0183]

[0184] Note: VOC represents open-circuit voltage, FF represents fill factor, Rs represents series resistance, Jsc represents short-circuit current, eta represents photoelectric conversion efficiency, and welding pull force represents the connection strength between the welding strip and the second electrode.

[0185] The experimental results show that, in Example 1, using the back-contact battery manufacturing method provided in an embodiment of this application, the design of interleaving the step of forming the initial dielectric layer 123 between the steps of forming the first electrode 101 and forming the second electrode 102 improves various electrical performance indices of the final photovoltaic cell. For example, the open-circuit voltage, fill factor, short-circuit current, and photoelectric conversion efficiency are all increased, and the series resistance is reduced. Moreover, the subsequent solder ribbon can be directly soldered to the second electrode, which helps to improve the welding pull force between the solder ribbon and the second electrode.

[0186] Another embodiment of this application provides a photovoltaic module for converting received light energy into electrical energy. The photovoltaic module provided in another embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0187] Reference Figures 11 to 14 ,as well as Figure 11 The photovoltaic module includes: a battery string, which is formed by connecting multiple photovoltaic cells 40 provided in the foregoing embodiments, or by connecting photovoltaic cells 40 formed by the manufacturing method of multiple photovoltaic cells provided in the foregoing embodiments; an encapsulating film 41 for covering the surface of the battery string; and a cover plate 42 for covering the surface of the encapsulating film 41 facing away from the battery string.

[0188] in, Figure 1A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6. Figure 12 A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6. Figure 11 A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6. Figure 13 A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6. Figure 5 A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6. Figure 14 A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6. Figure 13 A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6. Figures 1 to 4 A partial sectional view of a corresponding photovoltaic module is shown in FIG. 6.

[0189] In some embodiments, in combination with reference to Figure 7 , Figure 8 , Figure 11 and Figure 12 and Figure 11 , the photovoltaic cell 40 is a double-sided electrode cell, including but not limited to a TOPcon cell, a PERC cell or a HJT cell.

[0190] It should be noted that the plurality of photovoltaic cells 40 can be electrically connected by the solder strip 43. Figure 12 and Figures 2 to 6 Only the positional relationship between the photovoltaic cells 40 is shown, that is, the second electrodes of the photovoltaic cells 40 have the same polarity, for example, the arrangement direction of the first bus electrodes is the same or in other words the first surfaces 1351 of the first bus electrodes of each photovoltaic cell 40 are arranged on the same side, so that the solder strip 43 connects different sides of two adjacent photovoltaic cells 40 respectively. In other embodiments, the photovoltaic cells can also be arranged according to the same side of the second electrodes of different polarities, that is, the first electrodes of the adjacent plurality of photovoltaic cells on the same side are arranged in the order of first bus electrode, second bus electrode, first bus electrode, second bus electrode in turn, and the solder strip connects two adjacent photovoltaic cells on the same side.

[0191] In other embodiments, in combination with reference to Figure 13 , and Figure 14 and Figure 13 , the photovoltaic cell 40 is a BC cell, including but not limited to a HBC cell, a TBC cell or an HTBC cell.

[0192] It should be noted that the plurality of photovoltaic cells 40 can be electrically connected by the solder strip 43. Figure 14 and ​Only the positional relationship between the photovoltaic cells 40 is shown, i.e. each photovoltaic cell 40 has one side of the second electrode 102 facing the same side, so that the solder strip 43 connects two adjacent photovoltaic cells 40 on the same side. In other embodiments, the photovoltaic cells can also be arranged such that the second electrodes of two adjacent photovoltaic cells are on different sides, and the solder strip connects two adjacent photovoltaic cells on different sides.

[0193] In some embodiments, the photovoltaic cells 40 are electrically connected in a whole piece or multiple pieces to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or parallel. The photovoltaic cells 40 can be whole piece cells or sliced cells, where a sliced cell refers to a cell formed by cutting a whole piece cell.

[0194] In some embodiments, the encapsulation film 41 includes a first encapsulation layer and a second encapsulation layer, the first encapsulation layer covers one of the front surface or the back surface of the photovoltaic cell 40, and the second encapsulation layer covers the other of the front surface or the back surface of the photovoltaic cell 40. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as a polyvinyl butyral (PVB) film, an ethylene-vinyl acetate (EVA) film, a polyolefin elastomer (POE) film, or a polyethylene terephthalate (PET) film, or at least one of the first encapsulation layer or the second encapsulation layer can also be an EP film, an EPE film, or a PVP film. The EP film refers to a co-extrusion film formed by stacking an EVA film and a POE film, the EPE film refers to a co-extrusion film formed by stacking an EVA film, a POE film, and an EVA film in sequence, and the PVP film refers to a co-extrusion film formed by stacking a POE film, an EVA film, and a POE film in sequence. The co-extrusion film can be prepared by extruding one or more raw materials onto another film that has been prepared, or by bonding different types of films to each other during film processing.

[0195] In some cases, the first encapsulation layer and the second encapsulation layer have a boundary before lamination, and after the lamination process, the photovoltaic module is formed without the concept of the first encapsulation layer and the second encapsulation layer, i.e. the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0196] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plates with light transmission function. Specifically, the surface of the cover plate 42 facing the encapsulation film 41 can be a concave-convex surface or a suede surface containing a plurality of convex structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate opposite the first encapsulation layer and a second cover plate opposite the second encapsulation layer.

[0197] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, and therefore the protection scope of the embodiments of the present application should be subject to the scope defined by the claims.

Claims

1. A photovoltaic cell, characterized in that, include: Base; A plurality of first electrodes are located on the surface of the substrate and are spaced apart along a first direction, and a plurality of second electrodes are spaced apart along a second direction, wherein the first direction and the second direction intersect. The surface of the substrate includes an overlapping area where the first electrode and the second electrode are simultaneously disposed, and the second electrode is disposed on the side of the first electrode located away from the substrate in the overlapping area. A dielectric layer, at least between the second electrode and the first electrode, and having pores in the overlapping region, the pores being formed during the formation of the second electrode, with at least a portion of the pores accommodating the first electrode and / or the second electrode, such that the first electrode and the second electrode are in contact; The surface of the substrate also includes a protection zone other than the overlapping region. The protection zone is a region where the first electrode is not disposed. The dielectric layer is also located on at least a portion of the protection zone. The thickness of the dielectric layer located in the protection zone is greater than the thickness of at least a portion of the dielectric layer located in the overlapping region. The thickness of the dielectric layer located in the protection zone is 30 nm to 200 nm.

2. The photovoltaic cell according to claim 1, characterized in that, The first electrode has a bottom end and a top end along a third direction, the bottom end being closer to the substrate, and the third direction being the thickness direction of the substrate; in the dielectric layer located in the overlapping region, the thickness of the dielectric layer on the surface located at the bottom end is greater than or equal to the thickness of the dielectric layer on the surface located at the top end.

3. The photovoltaic cell according to claim 2, characterized in that, In the dielectric layer located in the overlapping region, the thickness of the dielectric layer located on the side of the first electrode gradually decreases along the direction from the bottom end to the top end.

4. The photovoltaic cell according to claim 1, characterized in that, The surface of the substrate further includes a first region on which the first electrode is disposed; the dielectric layer is also located on the first region and on the surface of the first electrode away from the substrate.

5. The photovoltaic cell according to claim 4, characterized in that, The ratio of the area of ​​the overlapping region to the area of ​​the first region is 0.005% to 1.705%.

6. The photovoltaic cell according to claim 1, characterized in that, The surface of the substrate further includes a second region on which the second electrode is disposed; the dielectric layer is also located on the second region and between the second electrode and the substrate.

7. The photovoltaic cell according to claim 1, characterized in that, The surface of the substrate further includes a third region, which is a region where the first electrode and the second electrode are not disposed; the dielectric layer is also located on the third region.

8. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The ratio of the thickness of the medium layer located in the overlapping area to the thickness of the medium layer located in the protected area is 30% to 50%.

9. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, Also includes: A transparent conductive layer is located between the dielectric layer and the substrate, and between the first electrode and the substrate.

10. The photovoltaic cell according to claim 9, characterized in that, The thickness of the transparent conductive layer is 20nm~200nm.

11. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The material of the first electrode and / or the material of the second electrode comprises a metal or a mixture of a metal and an organic polymer; wherein the metal comprises at least one of Ag, Al, Cu, Mg, Mo, W, Cr, Ni or Sn.

12. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or magnesium fluoride.

13. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The width of the overlapping region in the extension direction perpendicular to the first electrode is 5 μm to 40 μm.

14. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The substrate includes: A substrate, one surface of which includes a fourth region and a fifth region arranged alternately along the first direction; A first semiconductor layer and a first doped layer, wherein the first semiconductor layer is located on the fourth region and the first doped layer is located on the side of the first semiconductor layer away from the substrate; A second semiconductor layer and a second doped layer, the second semiconductor layer being located on the fifth region, the second doped layer being located on the side of the second semiconductor layer away from the substrate, the second doped layer and the first doped layer being doped with different types of doping elements; The first electrode includes a first current collector electrode located in the fourth region and a second current collector electrode located in the fifth region. The first current collector electrode is electrically connected to the first doped layer, and the second current collector electrode is electrically connected to the second doped layer. Wherein, the first semiconductor layer and the second semiconductor layer are tunneling layers, and the first doped layer and the second doped layer are doped polycrystalline silicon layers; or, the first semiconductor layer and the second semiconductor layer are intrinsic amorphous silicon layers, and the first doped layer and the second doped layer are doped amorphous silicon layers; or, the first semiconductor layer is the tunneling layer, the first doped layer is the doped polycrystalline silicon layer, the second semiconductor layer is the intrinsic amorphous silicon layer, and the second doped layer is the doped amorphous silicon layer.

15. The photovoltaic cell according to any one of claims 1 to 7, characterized in that, The substrate includes: The substrate has two surfaces opposite each other along a third direction; A semiconductor layer is located on one of the two surfaces; A doped layer is located on the side of the semiconductor layer away from the substrate; The first electrode includes a first current collector located on the side of the doped layer away from the substrate, and a second current collector located on the other of the two surfaces; Wherein, the semiconductor layer is a tunneling layer and the doped layer is a doped polycrystalline silicon layer; or, the semiconductor layer is an intrinsic amorphous silicon layer and the doped layer is a doped amorphous silicon layer.

16. A method for manufacturing a photovoltaic cell, characterized in that, include: Provide a base; A plurality of first electrodes are formed on the surface of the substrate at intervals along a first direction; An initial dielectric layer is formed on the surface formed by the substrate and the first electrode. A plurality of second electrodes are formed on the surface of the initial dielectric layer at intervals along a second direction, wherein the first direction and the second direction intersect. The substrate surface includes an overlapping region where the first electrode and the second electrode are simultaneously disposed. During the formation of the second electrode, the initial dielectric layer located in the overlapping region is simultaneously transformed into a porous dielectric layer, and at least a portion of the pores accommodate the first electrode and / or the second electrode, thereby making contact between the first electrode and the second electrode. The substrate surface also includes a protection zone other than the overlapping region, which is a region where the first electrode is not disposed. The dielectric layer is located in at least a portion of the protection zone, and the thickness of the dielectric layer in the protection zone is greater than the thickness of at least a portion of the dielectric layer in the overlapping region. The thickness of the dielectric layer in the protection zone is 30 nm to 200 nm.

17. The method for manufacturing a photovoltaic cell according to claim 16, characterized in that, The initial medium layer is formed by a deposition process; wherein the deposition process is carried out at a temperature of 100℃ to 300℃ and for a duration of 10 min to 120 min.

18. The method for manufacturing a photovoltaic cell according to claim 16, characterized in that, The steps for forming the second electrode include: A plurality of initial second electrodes are formed on the surface of the initial dielectric layer at intervals along the second direction; The initial second electrode is subjected to drying and curing processes in sequence to transform it into the second electrode. The drying process is carried out at a temperature of 100℃ to 200℃ and for a duration of 1 min to 10 min. The curing process is carried out at a temperature of 60℃ to 250℃ and for a duration of 0 min to 60 min.

19. A photovoltaic module, characterized in that, include: A battery string is formed by connecting multiple photovoltaic cells as described in any one of claims 1 to 15, or by connecting multiple photovoltaic cells formed by the manufacturing method of the photovoltaic cells as described in any one of claims 16 to 18; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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