Apparatus and method for communication between electronic components

Abstract

A system may include communication circuitry that is part of a microcontroller. The one or more registers may be configured to enable communication between the communication circuitry and the one or more external peripherals without a CPU or other processor controlling communication. The one or more registers may be configured to allow a particular trigger event to initiate communication between the communication circuitry and the external peripheral. The DMA controller may transfer data from the communication circuitry to the memory, and may transfer data from the memory to an external peripheral.

Description

[0001] priority

[0002] This application claims priority to jointly owned U.S. Patent Application No. 63 / 464,481, filed May 5, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to systems and methods for communication between electronic components. Background Technology

[0004] A microcontroller typically includes a central processing unit (CPU), program and data storage memory, input-output (I / O) ports, and multiple peripherals fabricated on an integrated circuit (IC) die (“chip”). Some of these peripherals may be core-independent peripherals (CIPs), defined as peripherals that can operate without continuous CPU input. A CIP can initially be configured by the microcontroller and then operate independently after configuration. The IC die may be encapsulated or packaged in an IC package with terminals that allow external circuitry to connect to it. Electrical connections on the IC die may be “pads” and can be wire-bonded to IC package pins. Most external wiring pins are associated with the microcontroller’s I / O ports, with each I / O port pin permanently associated with one bit of the I / O port. Corresponding IC die pads are used for these I / O ports and are wire-bonded to the corresponding external pins. Other external pins provide DC power and ground to the IC die. I / O port pins are typically so-called multi-function pins and can be shared with peripherals under program control. Therefore, there may be certain predefined associations for each pin, or so-called Peripheral Port Selection (PPS) logic may allow the selection of a variety of assignable peripheral functions.

[0005] Core Independent Peripherals (CIPs) can handle their tasks to maintain the operation of external peripheral devices without code execution by or supervision from a central processing unit (CPU). Such peripheral devices are referred to as Core Independent Peripherals (CIPs). Therefore, CIPs simplify the implementation of complex control systems and provide designers with innovative flexibility. CIPs are internally integrated and receive inputs from both internal and external sources, and can provide outputs to both internal and external targets, such as other integrated peripherals or external components.

[0006] However, not all input and / or output connections of all Core Independent Peripheral Devices (CIPs) are available to all other CIPs; instead, they may have one or more connections available only for the corresponding external pins. To connect different CIPs that are not within the normal internal selection options, this connection must be made using external port pins. This can be problematic on low-pin-count devices, as it can lead to reduced functionality. Therefore, larger devices with a correspondingly larger number of additional port pins must be used. The main disadvantage is the cost and size of the larger devices. Another option is to significantly increase the connection selection registers and associated multiplexer circuitry for all CIPs to allow selection for any other CIP connected with them, but this is not a feasible option in most cases.

[0007] The specific CIP included in a particular chip is a hardware decision that must be made based on market demand and performance capabilities. Chips targeting different markets with varying performance capabilities may have entirely different sets of included CIPs, requiring the development of an entire separate chip. Alternatively, additional peripherals can be attached externally to the CPU, and the CPU can communicate with these external peripherals using existing protocols such as SPI or I2C. However, this introduces significant latency when communicating on an external bus and may also compromise the independence of the CIP, as the CPU needs to be active to communicate with these external peripherals.

[0008] A system and method are needed to communicate with external peripheral devices that allow the external peripheral devices to operate as CIPs without CPU code execution or supervision. Summary of the Invention

[0009] The example in this article enables the system to communicate between electronic components without requiring the CPU or other processor to be active.

[0010] According to one aspect, a device includes a microcontroller. The microcontroller includes communication circuitry, a central processing unit (CPU), a direct memory access (DMA) controller, and memory. The communication circuitry can be coupled to the CPU, the DMA controller, and an external peripheral device. The communication circuitry may include: a trigger configuration register for storing trigger configuration settings; an address configuration register for storing an address of the external peripheral device; a count configuration register for storing a value; and at least one trigger input. The communication circuitry can enter a peripheral communication mode based on the trigger configuration settings and a trigger event on the at least one trigger input. The communication circuitry can transfer multiple bytes between the communication circuitry and an external peripheral device addressed by an address stored in the address configuration register. The transferred multiple bytes may be based on a value stored in the count register. The communication circuitry can exit the peripheral communication mode based on the completion of the transfer of multiple bytes and based on the trigger configuration settings. The DMA controller can transfer data between the communication circuitry and the memory.

[0011] According to one aspect, a system includes an external peripheral device and a microcontroller coupled to the external peripheral device. The microcontroller may include communication circuitry, a CPU, a DMA controller, and memory. The communication circuitry may be coupled to the CPU and the DMA controller. The communication circuitry may include: a trigger configuration register for storing trigger configuration settings; an address configuration register for storing an address of the external peripheral device; a counter register for storing a value; and at least one trigger input. In operation, the communication circuitry may enter a peripheral communication mode based on the trigger configuration settings in the trigger configuration register and a trigger event on the at least one trigger input. The communication circuitry may transfer multiple bytes between the communication circuitry and the external peripheral device addressed by the address stored in the address configuration register, the transferred bytes being based on the value stored in the counter register. The communication circuitry may exit the peripheral communication mode based on the configuration settings in the trigger configuration register. The DMA controller may transfer data between the communication circuitry and the memory.

[0012] According to one aspect, a method includes the steps of: writing to one or more configuration registers in a communication circuit; configuring a DMA controller to transfer data between the communication circuit and a memory; receiving a trigger signal at the communication circuit, the trigger signal being specified by a value stored in at least one configuration register in the configuration register; transferring data between an external peripheral device and the communication circuit, the address of the external peripheral device being based on a value stored in at least one configuration register in the configuration register, and multiple bytes of data to be transferred being based on a value stored in at least one configuration register in the configuration register; terminating communication based on completion of data transfer and based on a value stored in at least one configuration register in the configuration register; and transferring data between the communication circuit and the memory based on the configuration of the DMA controller. Attached Figure Description

[0013] Figure 1 One example of various examples of devices used for communication is shown, which includes a microcontroller and external peripherals connected via a communication bus.

[0014] Figure 2 This is one example of a series of timing diagrams illustrating data transmission over a communication bus.

[0015] Figure 3 Another example of a timing diagram illustrating data transmission via a communication bus is shown.

[0016] Figure 4 This illustrates a method for communication between electronic components. Detailed Implementation

[0017] Figure 1 One example of various examples of system 100 is shown, which includes a microcontroller 120 and an external peripheral device 150. Figure 1 The example uses one external peripheral device 150 for illustration, but this is not intended to be limiting. System 100 may include more than one external peripheral device 150. Multiple peripheral devices may be multiple instances of the same peripheral device, or they may be instances of different peripheral devices. Microcontroller 120 may include CPU 110.

[0018] CPU 110 may be coupled to internal peripheral device 130. Internal peripheral device 130 may be one example of a variety of peripheral devices, including but not limited to timers, logic elements, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), pulse width modulators, universal asynchronous receivers / transmitters (UARTs), interrupt controllers, or counters.

[0019] Internal peripheral device 130 can generate peripheral output signal 135. Peripheral output signal 135 can be a trigger input to communication circuit 140. Communication circuit 140 can be an I2C controller circuit, a Serial Peripheral Interface (SPI) controller circuit, or another type of communication circuit. Communication circuit 140 can generate transactions on communication bus 112. Communication bus 112 can be a shared I2C bus, a shared SPI bus, or another type of communication bus.

[0020] DMA controller 160 may be coupled to communication circuitry 140. DMA controller 160 may transfer data from communication circuitry 140 to memory 170, or may transfer data from memory 170 to communication circuitry 140.

[0021] The DMA controller 160 can directly control data transfers between different memory regions without CPU intervention. The DMA controller 160 can be programmed to transfer data between different memory locations, move different data sizes, and use different hardware triggers to initiate data transfers. The DMA controller 160 can access the general-purpose registers, special-function registers, or flash memory of the microcontroller 120.

[0022] The DMA controller 160 may include one or more addressing modes, including but not limited to fixed address mode, increment mode, decrement mode, post-increment mode, or post-decrement mode. The DMA controller 160 may include programmable source and destination sizes. The DMA controller 160 may be configured to transfer data from a source address to a destination address.

[0023] In one example of various examples, CPU 110, internal peripherals 130, communication circuitry 140, DMA controller 160, and memory 170 may be fabricated on a single semiconductor substrate as part of microcontroller 120. Figure 1 Other circuits not shown may also be included in the microcontroller 120.

[0024] In one example of various examples, internal peripheral device 130 may be a timer. Internal peripheral device 130 may be configured by CPU 110 to set the timer duration, timer clock source, and other configurable parameters of internal peripheral device 130. In operation, CPU 110 may configure internal peripheral device 130 via internal bus 111. In operation, internal peripheral device 130 may count for a predetermined duration based on its configuration, and upon reaching the predetermined duration, internal peripheral device 130 may assert a peripheral output signal 135. Peripheral output signal 135 may be a trigger input to communication circuitry 140. Internal peripheral device 130 may assert peripheral output signal 135 for a predetermined duration, after which peripheral output signal 135 may be deasserted. Internal peripheral device 130 may repeat the timer sequence or perform a single timer operation.

[0025] The external output signal 135 can be coupled to the communication circuit 140. Figure 1 The illustrated example includes an internal peripheral device 130 and a peripheral output signal 135, but this is not intended to be limiting. System 100 may include multiple internal peripheral devices, and multiple peripheral outputs may be coupled to communication circuitry 140. Communication circuitry 140 may respond to peripheral output signal 135 based on multiple configuration register settings. In one example of the various examples, communication circuitry 140 may include a trigger configuration register 141. Trigger configuration register 141 may include one or more configuration settings, including but not limited to trigger enable settings, trigger source settings, read / write selection settings, stop / restart condition settings, and end event output settings.

[0026] Trigger configuration register 141 may include trigger enable setting 171 to enable communication circuitry 140 to respond to trigger events. Trigger enable setting 171 may allow communication circuitry 140 to be programmed to respond to specific trigger events, including but not limited to signal transitions or levels. Trigger configuration register 141 may be programmed to respond to transitions or levels on peripheral output signal 135. In one example of various examples, multiple peripheral outputs may be input to communication circuitry 140, and trigger configuration register 141 may include trigger source setting 172 to configure communication circuitry 140 to respond to one or more of the multiple peripheral outputs. Trigger configuration register 141 may allow communication circuitry 140 to be programmed to respond to timer outputs, logic signals, sensor outputs, GPIO signals, interrupt signals, or other signals not specifically mentioned. When a trigger event is received by communication circuitry 140, and communication circuitry 140 is programmed to respond to the trigger event, communication circuitry 140 may enter peripheral communication mode. Trigger configuration register 141 may include a read / write selection setting 173 to allow communication circuitry 140 to respond to trigger events using read or write operations transmitted by communication circuitry 140 via communication bus 112. Trigger configuration register 141 may include a stop / restart condition setting 174 to allow communication circuitry 140 to be programmed to issue a stop condition via communication bus 112 at the end of a peripheral communication mode. Trigger configuration register 141 may include an end event output setting 175 to specify one or more interrupt outputs to be generated by communication circuitry 140 at the end of a peripheral communication mode.

[0027] In one example of various examples, communication circuitry 140 may include address configuration register 142. Address configuration register 142 may store the address value of external peripheral device 150. The address value may be the I2C address of external peripheral device 150. The address value may be the register address of a register in external peripheral device 150. In this way, communication circuitry 140 can access specific register locations within external peripheral device 150. Communication circuitry 140 can write to or read from the address stored in address configuration register 142 via communication bus 112. Communication circuitry 140 can write to and read from the address stored in address configuration register 142 in I2C communication mode. Communication circuitry 140 can write to and read from the address stored in address configuration register 142 in SPI communication mode.

[0028] In one example of various examples, communication circuitry 140 may include a count configuration register 143. The count configuration register 143 may be programmed to store a value specifying a number of bytes of data to be transferred to external peripheral device 150 in a write operation, or a number of bytes of data to be read from external peripheral device 150 in a read operation. The communication direction (write operation or read operation) may be set by triggering a read / write selection setting 173 on configuration register 141.

[0029] DMA controller 160 can transfer data between communication circuitry 140 and memory 170. DMA controller 160 can be configured by CPU 110 to transfer data from communication circuitry 140 to a specific location in memory 170 during a read operation. DMA controller 160 can be configured by CPU 110 to transfer data from a specific location in memory 170 to communication circuitry 140 during a write operation. Communication circuitry 140 can then transfer the data stored in memory 170 to external peripheral device 150. Communication circuitry 140 can issue commands to DMA controller 160, including full flag, empty flag, and message completion flag. DMA controller 160 can transfer data between communication circuitry 140 and memory 170 based at least on commands received from communication circuitry 140.

[0030] In one example of various examples, communication bus 112 may be an SPI bus. Communication circuitry 140 may include a chip select configuration register 144, which specifies the GPIO or peripheral pin to be used as the chip select signal. The chip select signal enables communication circuitry 140 to address external peripheral devices via the SPI bus.

[0031] Communication circuitry 140 may include multiple trigger configuration registers 141, multiple address configuration registers 142, multiple count configuration registers 143, and multiple chip select configuration registers 144. In one example of various examples, communication circuitry 140 may include four trigger configuration registers 141, four address configuration registers 142, four count configuration registers 143, and four chip select configuration registers 144. In one example of various examples, a corresponding trigger configuration register 141 may include an associated address configuration register 142, count configuration register 143, and chip select configuration register 144. Each trigger configuration register 141 may include a configuration setting specifying which address configuration register in the address configuration register 142 is applied to the corresponding trigger configuration register 141. As one example of various examples, multiple trigger configuration registers 141 may be programmed to access the same address location. One trigger can be used to read data from the address, and another trigger can be used to write data to the same address.

[0032] End event output setting 175 can specify a transfer register empty interrupt to indicate that no additional data is available for transfer to external peripheral device 150. End event output setting 175 can specify a receive register full interrupt to indicate that no additional storage space is available for data to be read from external peripheral device 150. End event output setting 175 can specify a message completion interrupt to indicate the completion of message transmission.

[0033] exist Figure 1 In the illustrated example, external peripheral device 150 may be an analog-to-digital converter (ADC). External peripheral device 150 may be programmed by communication circuitry 140 via communication bus 112, wherein communication circuitry 140 may receive commands from CPU 110. Trigger configuration register 141 may be programmed with a value that configures communication circuitry 140 to respond to the rising edge of peripheral output signal 135. Trigger configuration register 141 may be programmed with a value that configures communication circuitry 140 to read data when triggered. Trigger configuration register 141 may be programmed with a value that configures external peripheral device 150 to issue a stop condition via communication bus 112 after data has been read.

[0034] Address configuration register 142 can be programmed with a value corresponding to the address of a register within external peripheral device 150. Counter configuration register 143 can be programmed with the value 1, corresponding to the byte of data to be read from the address stored in address configuration register 142.

[0035] The DMA controller 160 can be configured by the CPU 110 to transfer data from the communication circuitry 140 to the memory 170. The DMA controller 160 can be configured to transfer data between the communication circuitry 140 and the memory 170, configured to provide at least the addresses of the source and destination data, as well as a count of the data blocks to be transferred. The data blocks can be bits, bytes, words, or other sizes of data.

[0036] During operation, after configuration is complete, CPU 110 can be placed into a low-power sleep mode. Communication circuitry 140 can enter peripheral communication mode upon triggering by a signal or event identified by communication circuitry 140 based on the value in trigger configuration register 141. During peripheral communication mode, communication circuitry 140 can issue a transaction on communication bus 112 to read one byte of data from external peripheral device 150 based on the values ​​programmed in trigger configuration register 141, address configuration register 142, and count configuration register 143. This one byte of data can then be transferred from communication circuitry 140 to memory 170 by DMA controller 160 based on DMA controller 160's configuration.

[0037] After a byte of data is read from external peripheral device 150, the peripheral communication mode can be terminated based on the settings in the trigger configuration register 141. The peripheral communication mode can also be terminated using the transmission of a stop condition via communication bus 112.

[0038] In this way, data can be read from external peripheral device 150 without any ongoing activity from CPU 110. Data read from external peripheral device 150 can be stored in memory 170 by DMA controller 160 based on its configuration, and is accessible by other peripheral devices in microcontroller 120. Data stored in memory 170 is accessible by microcontroller 120. Data is stored in memory 170 by DMA controller 160 and is accessible by CPU 110.

[0039] In this way, system 100 can copy the contents of one or more registers of external peripheral device 150 to memory 170 within microcontroller 120, enabling the registers of external peripheral device 150 to be used as internal special function registers for memory mapping of external peripheral device 150. Without system 100, the registers of external peripheral device 150 would need to be accessed via I2C or SPI interface, and data would need to be moved via the activity of CPU 110.

[0040] Figure 2 This is one example of various examples of transactions on the communication bus 112. Figure 2 The example transactions can be found by referring to... Figure 1 The communication circuit 140 described and illustrated is emitted. Figure 2 The illustrated transaction may represent a transaction on communication bus 112, which may be a shared I2C bus. Trace 210 may be a clock signal. Trace 210 may be the SCL signal on the I2C bus. Trace 220 may be a data signal, an address signal, or a combination of address and data signals. Trace 220 may be the SDA signal on the I2C bus.

[0041] Prior to time 201, trigger configuration register 141, address configuration register 142, and count configuration register 143 can be programmed to initiate a write operation to external peripheral device 150 when trigger signal 230 is asserted.

[0042] At time 201, trigger signal 230 can be asserted and can trigger a write operation to external peripheral device 150.

[0043] At time 202, communication circuit 140 may issue an I2C START condition on communication bus 112. In the example utilizing the SPI bus, a chip select signal may be asserted (not shown).

[0044] At time 203, communication circuitry 140 can transmit data to external peripheral device 150 on communication bus 112. Trace 210 may include clock pulse 211, and trace 220 may include data transition 221, wherein clock pulse 211 and data transition 221 can convey values ​​stored in address configuration register 142. Figure 2 The illustrated example includes eight clock pulses on trace 210, but this is not intended to be limiting. Other examples may include more than... Figure 2 The number of clock pulses shown may be greater than, or may include more than Figure 2 A smaller number of clock pulses are shown. At time 204, the address transfer can be completed, and data transfer can begin. Trace 210 may include clock pulse 212, and trace 220 may include data transition 222, wherein clock pulse 212 and data transition 222 can write data between communication circuit 140 and external peripheral device 150 via communication bus 112. Clock pulse 212 and data transition 222 can transfer a single byte of data, or can transfer multiple bytes of data, the multiple bytes of data being transferred being based on a value stored in counter configuration register 143. Figure 2 In the example shown, a single byte of data can be transmitted.

[0045] At time 205, the stop condition can be transmitted on traces 210 and 220 on the communication bus 112. In the example utilizing the SPI bus, the chip select signal can be deasserted.

[0046] In this way, the communication circuit can write data to external peripheral devices via the I2C bus without the need for interaction or control from the CPU or processor.

[0047] Figure 3 Another example of a transaction on communication bus 112 is shown. Figure 3 The example transactions can be found by referring to... Figure 1 The communication circuit 140 described and illustrated is emitted. Figure 3 The illustrated transaction may represent a transaction on communication bus 112, which may be a shared I2C bus. Trace 310 may be a clock signal. Trace 310 may be the SCL signal on the I2C bus. Trace 320 may be a data signal, an address signal, or a combination of address and data signals. Trace 320 may be the SDA signal on the I2C bus.

[0048] Prior to time 301, trigger configuration register 141, address configuration register 142, and count configuration register 143 can be programmed to initiate a read operation from a specific address in external peripheral device 150 when trigger signal 330 is asserted.

[0049] At time 301, trigger signal 330 can be asserted as triggering a read operation from external peripheral device 150.

[0050] At time 302, communication circuit 140 can issue an I2C START on communication bus 112. In the example using the SPI bus, the chip select signal can be asserted.

[0051] At time 303, communication circuit 140 can transmit data on communication bus 112. Trace 310 may include clock pulse 311, and trace 320 may include data transition 321, wherein clock pulse 311 and data transition 321 can convey the value stored in address configuration register 142 to external peripheral device 150. Clock pulse 311 can be transmitted from communication circuit 140 to external peripheral device 150 via communication bus 112. Data transition 321 can be transmitted from external peripheral device 150 to communication circuit 140 via communication bus 112, enabling communication circuit 140 to read data from external peripheral device 150.

[0052] At time 304, communication circuit 140 can read data from external peripheral device 150. Figure 3 In the illustrated example, clock pulse 312 may be generated by communication circuitry 140, and data transition 322 may be generated by external peripheral device 150, and may represent reading a single byte of data. In other examples, communication circuitry 140 may read multiple bytes of data, the multiple bytes of data being read based on a value stored in counter configuration register 143.

[0053] At time 305, communication circuit 140 can terminate the peripheral communication mode by sending a stop condition on communication bus 112. In the example using the SPI bus, the chip select signal can be deasserted.

[0054] Figure 3 The example illustrates a single read operation, but this is not intended to be limiting. The specific bit patterns transmitted and received on trace 320 are not intended to be limiting. In other examples, different bit patterns may be transmitted and received on trace 320.

[0055] In this way, the communication circuit can read data from external peripheral devices via the I2C bus without the need for interaction or control from the CPU or processor.

[0056] Figure 4 This illustrates a method for communication between electronic components.

[0057] At operation 410, the configuration registers in the communication circuitry can be programmed. Configuration registers may include a trigger configuration register, an address configuration register, a count configuration register, and a chip select configuration register. Other configuration registers not specifically mentioned may also be included.

[0058] At operation 415, the DMA controller can be configured to transfer data between the communication circuitry and the memory, configured to provide at least the addresses of the source and destination data, as well as a count of the data blocks to be transferred. Data blocks can be bits, bytes, words, or other sizes of data.

[0059] At operation 420, the communication circuitry can receive a trigger signal. The trigger signal can be a specific signal as specified by the value stored in the trigger configuration register.

[0060] At operation 430, the communication circuitry can enter a peripheral communication mode to communicate with external peripheral devices via a communication bus. In one example of various examples, the communication circuitry can write multiple bytes to the register address of an external peripheral device via the communication bus, the multiple bytes being specified by a value stored in a count configuration register, and the register address being specified by a value stored in an address configuration register. In one example of various examples, the communication circuitry can read multiple bytes from the register address of an external peripheral device via the communication bus, the multiple bytes being specified by a value stored in a count configuration register, and the register address being specified by a value stored in an address configuration register. In one example of various examples, the communication circuitry can assert a chip select signal to enable communication to a specific external peripheral device.

[0061] At operation 440, the peripheral communication mode can be terminated by a stop condition based on a value stored in the trigger configuration register.

[0062] At operation 450, the DMA controller can transfer data between the communication circuitry and the memory based on the DMA controller configuration.

Claims

1. An apparatus, the apparatus comprising: A microcontroller, comprising a communication circuit, a central processing unit (CPU), a direct memory access (DMA) controller, and memory, wherein the communication circuit is coupled to the CPU, the DMA controller, and external peripheral devices, and the communication circuit includes: A trigger configuration register, which is used to store trigger configuration settings; An address configuration register is used to store the address of the external peripheral device; A counter configuration register, which is used to store numerical values; At least one trigger input; The communication circuit described herein is used for: Entering peripheral communication mode based on the trigger configuration settings and trigger events on at least one trigger input; Multiple bytes are transmitted between the communication circuit and the external peripheral device addressed by the address stored in the address configuration register, the transmitted multiple bytes being based on the value stored in the counter register; and Based on the completion of the transmission of the multiple bytes and based on the trigger configuration settings, exit the peripheral communication mode, and The DMA controller is used to transfer data between the communication circuit and the memory.

2. The device according to claim 1, wherein the trigger configuration settings include trigger enable settings, trigger source settings, read / write selection settings, stop / restart condition settings, and end event output settings.

3. The device according to claim 2, wherein the end event output setting specifies one or more interrupt outputs, the one or more interrupt outputs including at least one of a transmit register empty interrupt, a receive register full interrupt, and a message completion interrupt.

4. The device according to any one of claims 1 to 3, wherein the communication circuitry includes a chip selection configuration register.

5. The device according to any one of claims 1 to 4, wherein the DMA controller is used to transfer data between the communication circuit and one or more general-purpose registers within the microcontroller.

6. The device according to any one of claims 1 to 5, wherein transmitting multiple bytes includes reading multiple bytes from the external peripheral device.

7. The device according to any one of claims 1 to 6, wherein transmitting multiple bytes includes writing multiple bytes to the external peripheral device.

8. A communication system, the communication system comprising: External peripheral equipment; A microcontroller coupled to the external peripheral device, the microcontroller including a communication circuit, a CPU, a DMA controller, and a memory, the communication circuit being coupled to the CPU and the DMA controller, and the communication circuit including: A trigger configuration register, which is used to store trigger configuration settings; An address configuration register is used to store the address of the external peripheral device; A counter register, which is used to store numerical values; At least one trigger input; The communication circuit mentioned above: Entering peripheral communication mode based on the trigger configuration settings in the trigger configuration register and the trigger events on the at least one trigger input; Multiple bytes are transmitted between the communication circuit and the external peripheral device addressed by the address stored in the address configuration register, the transmitted multiple bytes being based on the value stored in the counter register; Exit the peripheral communication mode based on the configuration settings in the trigger configuration register, and The DMA controller is used to transfer data between the communication circuit and the memory.

9. The system according to claim 8, wherein the trigger configuration settings include trigger enable settings, trigger source settings, read / write selection settings, stop / restart condition settings, and end event output settings.

10. The system of claim 9, wherein the end event output setting specifies one or more interrupt outputs, the one or more interrupt outputs including at least one of a transfer register empty interrupt, a receive register full interrupt, and a message completion interrupt for triggering DMA transfer.

11. The system according to any one of claims 8 to 10, wherein the communication circuitry includes a chip selection configuration register.

12. The system according to any one of claims 8 to 11, wherein the DMA controller is used to transfer data between the communication circuit and one or more general-purpose registers within the microcontroller.

13. The system according to any one of claims 8 to 12, wherein the DMA controller is configured to transfer data from a source address to a destination address.

14. A method for communicating with an external peripheral device, the method comprising: Write to one or more configuration registers in the communication circuit; Configure the DMA controller to transfer data between the communication circuitry and the memory; A trigger signal is received at the communication circuit, the trigger signal being specified by a value in at least one configuration register stored in the configuration register; Data is transmitted between an external peripheral device and the communication circuit, wherein the address of the external peripheral device is based on a value stored in at least one configuration register in the configuration register, and the plurality of bytes of data to be transmitted are based on a value stored in at least one configuration register in the configuration register; The communication is terminated based on the completion of the data transmission and based on the value in at least one configuration register stored in the configuration register. as well as Data is transferred between the communication circuit and the memory based on the configuration of the DMA controller.

15. The method of claim 14, wherein the configuration register comprises one or more trigger configuration registers, one or more address configuration registers, and one or more counter registers.

16. The method according to any one of claims 14 to 15, wherein the configuration register includes one or more chip select configuration registers.

17. The method according to any one of claims 14 to 16, wherein the trigger configuration register includes trigger enable settings, trigger source settings, read / write selection settings, stop / restart condition settings, and end event output settings.

18. The method of claim 17, wherein the end event output setting specifies one or more interrupt outputs, the one or more interrupt outputs including at least one of a transfer register empty interrupt, a receive register full interrupt, and a message completion interrupt for triggering a DMA transfer.

19. The method of any one of claims 14 to 18, the method comprising causing the DMA controller to transfer data between the communication circuit and one or more general-purpose registers within the microcontroller.

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