Mixing mode RFFE bus error handling

Abstract

The receiving circuit has a clock generator circuit, a synchronization circuit, and a controller. The clock generator circuit is configured to generate a fundamental clock signal having a fundamental frequency. The synchronization circuit is configured to synchronize an edge in the base clock signal with an edge in the Manchester encoded data signal received through the serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a sequence start condition of a first type indicating a transaction of the first type during which the first pulse has a pulse duration defined for the sequence start condition of the first type. The Manchester encoding data signal is received through a serial bus; configuring the first timer to expire after the first timeout period; and ignoring the first pulse when signaling consistent with the sequence start condition of the first type has not been received before expiration of the first timer.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 183,833, filed March 14, 2023, which has been assigned to the assignee of this patent application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] This disclosure relates generally to serial communication, and more specifically to clock generation at a receiver coupled to a communication bus that supports single-wire and two-wire peripherals. Background Technology

[0004] Mobile communication devices may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-a-chip (SoC) devices. These components may include processing circuitry, user interface components, storage devices, and other peripheral components that communicate via a serial bus. The serial bus may operate according to a standardized or proprietary protocol. In one example, the serial bus operates according to the Internal Integrated Circuit (I2C bus or I2C) protocol. The I2C bus was developed to connect low-speed peripheral devices to a processor, where the I2C bus is configured as a multi-point bus. A two-wire I2C bus includes a serial data line (SDA) carrying data signals and a serial clock line (SCL) carrying clock signals. In another example, the Improved Internal Integrated Circuit (I3C) protocol, defined by the Mobile Industry Processor Interface (MIPI) Consortium, derives certain specific implementation aspects from the I2C protocol, which includes separate clock and data lines.

[0005] In another example, the RF Front-End (RFFE) interface defined by the MIPI Alliance provides a communication interface for controlling various RF front-end devices, including power amplifiers (PAs), low-noise amplifiers (LNAs), antenna tuners, filters, sensors, power management devices, switches, etc. These devices can be co-located in a single IC device or provided in multiple IC devices. In yet another example, the System Power Management Interface (SPMI) defined by the MIPI Alliance provides a hardware interface that can be implemented between the baseband or application processor and peripheral components. In some implementations, the SPMI is deployed to support power management operations within the device.

[0006] Replacing parallel buses with serial buses defined by MIPI reduces the number of physical general-purpose input / output (GPIO) pins required to support communication between multiple devices. However, as device complexity increases, the demand for GPIO pins also increases, and there is a need for a simpler bus architecture, including one that supports communication via a single GPIO pin as well as via a single wire. There is also a need for error handling in single-wire communication. Summary of the Invention

[0007] Certain aspects of this disclosure provide systems, apparatus, methods, and techniques related to error handling when transmitting data via a single-wire serial bus. A clock signal generated at the receiver is synchronized with each transition in the Manchester-coded signal of the encoded data bits. The single-wire serial bus can format datagrams according to a protocol defined by RFFE, SPMI, or another standard.

[0008] In various aspects of this disclosure, a receiving circuit includes: a clock generator circuit configured to generate a fundamental clock signal having a fundamental frequency; a synchronization circuit configured to synchronize an edge in the fundamental clock signal with an edge in a Manchester-coded data signal received via a serial bus; and a controller. The controller may be configured to: detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of Sequence Start Condition (SSC), the first type of SSC indicating a first type of transaction during which the Manchester-coded data signal is received via the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0009] In various aspects of this disclosure, a method of data communication includes: configuring an oscillator to generate a basic clock signal having a basic frequency; configuring a synchronization circuit to synchronize an edge in the basic clock signal with an edge in a Manchester-encoded data signal received via a serial bus; detecting that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of SSC, the first type of SSC indicating a first type of transaction during which the Manchester-encoded data signal is received via the serial bus; configuring a first timer to expire after a first timeout period; and ignoring the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0010] In various aspects of this disclosure, a data communication apparatus includes: components for generating a basic clock signal having a basic frequency; components for synchronizing an edge in the basic clock signal with an edge in a Manchester-encoded data signal received via a serial bus; and components for determining whether a first pulse received from the serial bus indicates a first type of transaction, during which the Manchester-encoded data signal is received via the serial bus. The components for determining whether the first pulse indicates a first type of transaction may be configured to determine whether the first pulse has a duration corresponding to a pulse duration defined for a first type of SSC and whether it is followed in transmission by signaling consistent with a first type of SSC received before a first timeout period expires.

[0011] In various aspects of this disclosure, a processor-readable storage medium stores code thereon, and when executed by a processor in processing circuitry, the processing circuitry causes the processing circuitry to: configure an oscillator to generate a fundamental clock signal having a fundamental frequency; configure a synchronization circuit to synchronize an edge in the fundamental clock signal with an edge in a Manchester-encoded data signal received via a serial bus; detect a first pulse received from the serial bus having a duration corresponding to a pulse duration defined for a first type of SSC, the first type of SSC indicating a first type of transaction during which the Manchester-encoded data signal is received via the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0012] In one aspect, the pulse duration defined for the first type of SSC is longer than the pulse duration defined for the second type of transaction, in which data is received via a serial bus using a bus clock signal that defines the timing of the data signal. The frequency of the basic clock signal can be a multiple of the frequency of the bus clock signal.

[0013] In one respect, the signaling consistent with the first type of SSC includes a synchronization mode.

[0014] In one aspect, the controller is configured to ignore the first pulse by configuring the second timer to expire after the second timeout period and by putting one or more circuits in the clock generator circuitry into an idle state when the second timer expires. The controller can also be configured to restart the second timer when a change in the signaling state of the serial bus is detected before the second timer expires.

[0015] In some respects, the controller is also configured to: receive Manchester-coded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC; determine that an error has occurred during the transmission or decoding of the Manchester-coded data or command bits; configure a third timer to expire after a third timeout period; and, when the third timer expires, put one or more circuits in the clock generator circuitry into an idle state. The controller may also be configured to: restart the third timer when a change in the signaling state of the serial bus is detected before the third timer expires. The Manchester-coded data or command bits are received in datagrams configured according to the Radio Frequency Front-End (RFFE) protocol. Attached Figure Description

[0016] Figure 1 An example is illustrated of a device employing a data link between IC devices, which operates selectively according to one of a plurality of available standards.

[0017] Figure 2 A first example of an apparatus employing a data link that can be used to communicatively couple two or more devices is illustrated.

[0018] Figure 3 A second example of an apparatus is illustrated, which employs a data link that can be used to communicatively couple two or more devices, including various radio frequency front-end devices.

[0019] Figure 4 This includes timing diagrams illustrating the signaling sent to depict the boundaries of RFFE and SPMI datagrams.

[0020] Figure 5 An example is illustrated of a system in which a host device communicates with one or more single-line slave devices according to certain aspects disclosed herein.

[0021] Figure 6 Examples of single-wire serial interfaces that can be configured according to certain aspects of this disclosure are illustrated.

[0022] Figure 7 An example is illustrated of a system in which single-line slave devices and two-line slave devices coexist, according to certain aspects disclosed herein.

[0023] Figure 8 The initiation of a two-line transaction and the initiation of a single-line transaction transmitted via a serial bus according to certain aspects of this disclosure are illustrated.

[0024] Figure 9 Examples of Manchester-coded and control signaling, according to certain aspects of this disclosure, that can be used to exchange data between a host device and a single-line slave device are illustrated.

[0025] Figure 10 Examples of write and read transactions performed on a single-wire serial bus that can be adapted according to certain aspects disclosed herein are illustrated.

[0026] Figure 11 Examples of bus status errors that may affect a mixed-mode serial bus are shown.

[0027] Figure 12 An example of a single-wire receiver circuit configured according to certain aspects disclosed herein is illustrated.

[0028] Figure 13 This is an example illustrating certain aspects disclosed herein. Figure 12 The state diagram of the operation of the single-wire receiving circuit.

[0029] Figure 14 A two-wire receiver circuit configured according to certain aspects disclosed herein is illustrated.

[0030] Figure 15 This is an example illustrating certain aspects disclosed herein. Figure 14 The state diagram of the operation of the two-wire receiving circuit.

[0031] Figure 16 An example of an apparatus employing processing circuitry adaptable to certain aspects disclosed herein is illustrated.

[0032] Figure 17 This is a flowchart illustrating a method for data communication at a host device according to certain aspects disclosed herein.

[0033] Figure 18 Examples of specific hardware implementations of devices adapted to certain aspects disclosed herein are illustrated. Detailed Implementation

[0034] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and not as representing only the configurations in which the concepts described herein can be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0035] Several aspects of the invention will now be described with reference to various apparatuses and methods. These apparatuses and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0036] Certain aspects of this disclosure relate to communication of digital signals comprising transitions between two or more signaling states. For the purposes of this description, the transition between two signaling states in a digital signal may be referred to as an edge. A transition from a low-voltage signaling state to a higher-voltage signaling state may be referred to as a positive edge, positive transition, rising edge, rising transition, or positive transition edge. A transition from a higher-voltage signaling state to a low-voltage signaling state may be referred to as a negative edge, negative transition, falling edge, falling transition, or negative transition edge.

[0037] Certain aspects of this disclosure relate to serial bus configurations in which multiple devices can communicate at various times. The described serial bus typically operates in a hierarchical manner, as one device controls communication during a transaction. The controlling device may be referred to as a master device, bus master, management device, or another term supported by a standard defining a protocol implemented by the controlling device. In some serial bus configurations, a single controlling device manages or controls communication during all transactions conducted via the serial bus. In other serial bus configurations, for each transaction conducted via the serial bus, multiple devices may operate as controlling devices, and one device may act as the controlling device. The controlling device may provide a common clock signal transmitted over a conventional two-wire serial bus. The controlling device may provide control signaling that identifies the type of transaction to be conducted over the conventional two-wire serial bus. During certain transactions, the controlling device may send commands to one or more receiving devices using address information provided in or with a command. The receiving device may be referred to as a client device, slave device, dependent device, peripheral device, or another term supported by a standard defining a protocol implemented by the controlling device. For the purposes of this disclosure, the controlling device will be referred to as a master device, and the associated receiving device will be referred to as a dependent device.

[0038] Devices comprising multiple SoCs and / or other IC devices typically employ a shared communication interface, which may include a serial bus or other data communication link to connect the processor to modems and other peripherals. The serial bus or other data communication link may operate according to multiple standards or protocols. For example, the serial bus may operate according to I2C, I3C, SPMI, and / or RFFE protocols, or another protocol that can be configured for half-duplex operation. The increased functionality and complexity of operating devices coupled to a serial bus, and the imposition of tighter timing constraints to support applications, peripherals, and sensors, can lead to greater demands on general-purpose input / output (GPIO) pin availability and communication link throughput.

[0039] Certain aspects of this disclosure relate to techniques for communicating over a single-wire bus using Manchester encoding and synchronization signaling that can be distinguished by devices coupled to the single-wire bus. The synchronization signaling can be configured to enable the receiving device to synchronize with a clock signal generated in the device currently transmitting over the single-wire bus. In one aspect, the host device may be adapted to format datagrams according to an RFFE or SPMI protocol. The receive clock used to sample the Manchester encoded signal can be resynchronized at each bit transmission interval, thereby eliminating the possibility of cumulative effects of transmission errors on the phase and frequency of the Manchester encoded signal or on the receive clock. Certain aspects of this disclosure address error handling techniques suitable for mixed-mode serial buses, including two-wire serial buses supporting communication with both single-wire and two-wire peripherals.

[0040] According to certain aspects of this disclosure, an oscillator in a peripheral device can be configured to generate a fundamental clock signal with a fundamental frequency. The edges of the fundamental clock signal are synchronized with the edges of Manchester-encoded data signals received via a serial bus. Receiver circuitry in the peripheral device can determine when a pulse received from the serial bus has a duration that matches or corresponds to a pulse duration defined for a first type of Sequence Start Condition (SSC). The first type of SSC can indicate a first type of transaction, during which the Manchester-encoded data signal is received via a single wire through the serial bus. Another type of SSC can indicate a second type of transaction, in which data and clock signals are transmitted using two wires of the serial bus. A first timer can be configured to expire after a first timeout period, and the first pulse can be ignored if no signaling consistent with the first type of SSC is received before the first timer expires.

[0041] Some aspects disclosed herein provide alternatives to or complements to serial bus protocols, such as I2C, I3C, SPMI, and / or RFFE protocols. Some aspects are applicable to serial buses operating in half-duplex or full-duplex mode.

[0042] Example of a device using a serial data link

[0043] According to certain aspects of this disclosure, serial data links can be used to interconnect electronic devices that are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebooks, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), appliances, sensors, security devices, vending machines, smart meters, drones, multi-rotor helicopters, or any other similar functional devices.

[0044] Figure 1 An example of a device 100 that may employ a data communication bus is illustrated. Device 100 may include processing circuitry 102 having multiple circuits or devices 104, 106, and / or 108, which may be implemented in a SoC or one or more ASICs. In one example, device 100 may be a communication device, and processing circuitry 102 may include processing devices provided in ASIC 104, one or more peripheral devices 106, and a transceiver 108 enabling the device to communicate with a radio access network, a core access network, the Internet, and / or another network via antenna 124.

[0045] ASIC 104 may have one or more processors 112, one or more modems 110, onboard memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer, enabling one or more processors 112 to execute software modules residing in onboard memory 114 or other processor-readable storage device 122 provided on processing circuitry 102. Software modules may include instructions and data stored in onboard memory 114 or processor-readable storage device 122. ASIC 104 may access its onboard memory 114, processor-readable storage device 122, and / or storage devices external to processing circuitry 102. Onboard memory 114 and processor-readable storage device 122 may include read-only memory (ROM) or random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash cards, or any memory device that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, floppy disk, or hard disk, etc. Processing circuitry 102 may also be operatively coupled to external devices such as antenna 124, display 126, operator controls such as switches or buttons 128, 130 and / or an integrated or external keyboard 132, and other components. The user interface module may be configured to operate with display 126, external keyboard 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0046] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable communication between certain devices 104, 106, and / or 108. In one example, ASIC 104 may include bus interface circuitry 116, which includes a combination of circuits, counters, timers, control logic units, and other configurable circuitry or modules. In one example, bus interface circuitry 116 may be configured to operate according to a communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100.

[0047] Figure 2 A first example of an apparatus 200 employing a data link that can be used to communicatively couple two or more devices is illustrated. Here, apparatus 200 includes a plurality of devices 202 and 2220 to 2220 coupled to a two-wire serial bus 220. N Equipment 202 and 2220 to 222 NIt can be implemented in one or more semiconductor IC devices such as application processors, SoCs, or ASICs. In various specific implementations, devices 202 and 2220 to 222... N Some of the devices may include, support, or operate as modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, and / or other such components or devices. In some examples, one or more devices 2220 to 222 N It can be used to control, manage, or monitor sensor devices. Devices 202 and 2220 to 222 are connected via serial bus 220. N Communication between them is controlled by the host device 202. Some types of buses can support multiple host devices 202.

[0048] In one example, host device 202 may include interface controller 204 that manages access to the serial bus, configures dynamic addresses for slave devices, and / or generates clock signals 228 to be transmitted on clock line 218 of the serial bus 220. Host device 202 may include configuration register 206 or other storage device 224 and other control logic components 212 configured to handle protocols and / or higher-level functions. Control logic component 212 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. Host device 202 includes transceiver 210 and line drivers / receivers 214a and 214b. Transceiver 210 may include a receiver, transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage device circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 228 provided by clock generation circuitry 208. Additional timing clocks 226 may be used by control logic component 212 and other functions, circuitry, or modules.

[0049] One or more devices 2220 to 222 NIt can be configured to operate as a slave device. In some examples, a slave device may include circuitry and modules supporting a display, an image sensor, and / or circuitry and modules controlling and communicating with one or more sensors measuring environmental conditions. In one example, device 2220 configured to operate as a slave device may provide control functions, modules, or circuitry 232, including circuitry and modules for supporting a display, an image sensor, and / or controlling and communicating with one or more sensors measuring environmental conditions. In this example, device 2220 may include a configuration register 234 or other storage device 236, control logic unit 242, transceiver 240, and line drivers / receivers 244a and 244b. Control logic unit 242 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 240 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing, logic, and storage device circuitry and / or devices. In one example, the transmitter encodes and transmits data based on timing in clock signal 248 provided by clock generation and / or recovery circuitry 246. In some cases, clock signal 248 may be derived from a signal received from clock line 218. Other timing clocks 238 may be used by control logic unit 242 and other functions, circuits, or modules.

[0050] Serial bus 220 can operate according to RFFE, I2C, I3C, SPMI, or other protocols. Devices 202 and 2220 to 222 N At least one of them can be configured to operate as both a master device and a slave device on serial bus 220. Devices 202 and 2220 to 222 N Two or more of these devices can be configured to operate as master devices on serial bus 220. The protocol selected to control the operation of serial bus 220 can define DC characteristics affecting certain signal levels associated with serial bus 220, and / or AC characteristics affecting certain timing aspects of signals transmitted on serial bus 220. In various examples, the two-wire serial bus 220 transmits data on data line 216 and a clock signal on clock line 218. In some cases, the data can be encoded in the signaling state or in the signaling state transitions between data line 216 and clock line 218.

[0051] Figure 3A second example of an apparatus 300 employing a data link that can be used to communicatively couple two or more devices is illustrated. In this example, a chipset or device 302 employs multiple RFFE buses 330, 332, 334 to couple various RF front-end devices 318, 320, 322, 324, 326, 328. A modem 304 includes an RFFE interface 308 that couples the modem 304 to a first RFFE bus 330. The modem 304 can communicate with a baseband processor 306 and an RF IC (RFIC 312) via one or more communication links 310, 336. The illustrated device 302 may be embodied in one or more of the following: mobile communication devices, mobile phones, mobile computing systems, laptops, tablet computing devices, media players, gaming devices, wearable computing devices and / or communication devices, electrical appliances, etc.

[0052] In various examples, device 302 may be implemented using one or more baseband processors 306, modems 304, RFICs 312, multiple communication links 310, 336, multiple RFFE buses 330, 332, 334, and / or other types of buses. Device 302 may include other processors, circuitry, modules, and may be configured for various operations and / or different functionalities. Figure 3 In the illustrated example, the modem is coupled to the RF tuner 318 via its RFFE interface 308 and first RFFE bus 330. The RFIC 312 may include one or more RFFE interfaces 314, 316, a controller, a state machine, and / or a processor that configures and controls certain aspects of the RF front end. The RFIC 312 can communicate with the PA 320 and the power tracking module 322 via the first RFFE interface and the second RFFE bus 332 in its RFFE interface 314. The RFIC 312 can communicate with the switch 324 and one or more LNAs 326, 328 via the second RFFE interface and the third RFFE bus 334 in its RFFE interface 316.

[0053] Bus latency can affect the serial bus's ability to process high-priority, real-time, and / or other time-constrained messages. Low-latency messages, or messages requiring low bus latency, may involve sensor states, device-generated real-time events, and virtualized GPIO states. In one example, bus latency can be measured as the time elapsed between when a message becomes available for transmission and the delivery of that message, or in some cases, the start of its transmission. Other measurements of bus latency may be employed. Bus latency typically includes delays incurred when transmitting higher-priority messages, interrupt handling, the time required to terminate datagrams in progress on the serial bus, the time for sending commands that cause the bus to switch between transmit and receive modes, bus arbitration, and / or command transmission specified by the protocol.

[0054] In some examples, delay-sensitive messages may include coexistence messages. Sending coexistence messages in a multi-system platform prevents or reduces conflicts between certain device types, including, for example, switches 324, LNAs 326, 328, PAs 320, and other types of devices operating concurrently in a manner that may generate inter-device interference or potentially damage one or more devices. Devices that may interfere with each other can exchange coexistence management (CxM) messages to allow each device to signal impending actions that may cause interference or conflict. CxM messages can be used to manage the operation of shared components, including switches 324, LNAs 326, 328, PAs 320, and / or antennas.

[0055] Multipoint interfaces (such as RFFE, SPMI, I3C, etc.) can reduce the number of physical input / output (I / O) pins used for communication between multiple devices. Protocols supporting communication over multipoint serial buses define datagram structures for sending command, control, and data payloads. Certain common features are defined for the datagram structures of different protocols, including addressing for selecting devices to receive or send data, clock generation and management, interrupt handling, and device priority. In this disclosure, examples of the RFFE protocol may be used to illustrate certain aspects disclosed herein. However, the concepts disclosed herein are applicable to other serial bus protocols and standards.

[0056] Figure 4 Timing diagrams 400 and 420 illustrate signaling transmitted to delineate the boundaries of datagrams sent according to the RFFE protocol. Timing diagrams 400 and 420 show the relative timing of signals transmitted on a two-wire serial bus, which provides a clock signal on SCLK 402 and facilitates data exchange via SDATA 404. The first timing diagram 400 illustrates the timing of a sequence start condition (SSC 408), which is transmitted to signal the start of a transaction, such as the transmission of datagram 410. SSC 408 is transmitted when the serial bus is in idle state 406. In idle state 406, SCLK 402 is driven at full strength by the master device, while slave devices coupled to the serial bus present high impedance to SCLK 402. SCLK 402 is held in a low signaling state (here, zero volts) by the master device. In idle state 406, SDATA 404 is weakly driven by the host device or held in a weakly driven low signaling state 412 using a hold circuit or a weak pull-down circuit. For example, the hold circuit or weak pull-down circuit can maintain the signaling state of SDATA 404 when the host device has put its line driver into a high-impedance state, and when no other device is driving SDATA 404. The weakly driven low signaling state 412 can be easily overcome by another line driver capable of driving SDATA 404 at full strength.

[0057] In the master-driven SSC 408, the master device begins transmitting SSC 408 at a first time point 414, at which time the master device begins driving SDATA 404, which is initially in a low signaling state, at full strength. The master device then provides pulse 416 on SDATA 404 while continuing to drive SCLK 402 to a low signaling state. Pulse 416 has a duration of at least one cycle of the clock signal provided on SCLK 402 during the transmission of datagram 410. At a second time point 418, the master device begins transmitting clock pulses on SCLK 402, thereby providing a clock signal for controlling or indicating the timing of datagram 410 transmitted on SDATA 404.

[0058] For example, second timing diagram 420 illustrates the timing of a bus stop cycle (BPC 424) that can be sent to signal the termination of datagram 422. BPC 424 is sent by providing a falling edge 428 on SDATA 404 when SCLK 402 is in a high signaling state 430. By protocol, transitions on SDATA 404 are permitted only during the transmission of datagram 422 when the clock signal is in a low signaling state, and the falling edge 428 occurring when SCLK 402 is in a high signaling state 430 is interpreted as control signaling (i.e., BPC 424). The falling edge 428 is provided by the master device driving SDATA 404 low at full strength. The master device then drives SCLK 402 low and continues to drive SCLK 402 at full strength through subsequent bus idle intervals 426, 436. After driving SCLK 402 low, the host device initiates a bus idle interval 436 at time 432 when it puts its line driver into a high-impedance state. When no other device is driving SDATA 404, SDATA 404 remains in a weakly driven low signaling state 434. BPC 424 is terminated, and the serial bus enters a bus idle interval 426 until the next datagram is ready to be transmitted.

[0059] The various examples provided herein depict examples of a single-wire serial bus in which data and commands are configured according to the RFFE protocol. However, these concepts are not limited to the RFFE protocol, and various aspects of this disclosure are equally applicable to I2C, I3C, SPI, SPMI, and other standard-defined or proprietary protocols. The single wire of the single-wire serial bus serves as a data line for bidirectional transmission of control and data signaling. According to certain aspects of this disclosure, timing for communication between single-wire slave devices coupled to the serial bus can be embedded in data transmission, and control signaling can be provided to synchronize clock signals at the transmitter and receiver.

[0060] Figure 5 Examples are illustrated of a host device 502 and one or more single-line slave devices 5041 to 504 according to certain aspects disclosed herein. N The communication system 500. The host device 502 may be located in an RFIC, modem, application processor, or other type of device. The host device 502 may be adapted to communicate with single-line slave devices 5041 to 504. N Data is exchanged on this single line, referred to as SDATA line 506 in the illustrated system 500. The data is encoded in a signal transmitted via SDATA line 506, wherein the signal includes embedded clock information that can be used by a receiving device to decode the data from the signal.

[0061] Master device 502 and single-line slave devices 5041 to 504 N This typically includes the corresponding protocol controllers 508, 5101 to 510. N Protocol controllers 508, 5101 to 510 N This may include a processor, controller, state machine, or other logic circuit configured to support one or more protocols. The protocol controller 508 in the host device 502 may also be configured to manage communication via the SDATA line 506. In some cases, the protocol controller 508 performs some of the functions of the host device. In some specific implementations, the protocol controller 508 in the host device 502 may be used to configure single-wire slave devices 5041 to 504. N One or more of them. The host device 502 can identify single-line slave devices 5041 to 504 as the designated recipients of data to be sent via the SDATA line 506. N The configuration allows the protocol controller 508 to be configured for use with receiver single-wire slave devices 5041 to 504. N The data encoding is to be sent via SDATA line 506 and addressed to single-wire slave devices 5041 to 504. N The signal.

[0062] The host device 502 may include a transmit clock generator 512, which can be used to define the timing of transmissions made via the SDATA line 506. Single-wire slave devices 5041 to 504 N Each of them includes local clock generation circuits 5141 to 514. N It provides corresponding protocol controllers 5101 to 510. N Timing. Local clock generation circuits 5141 to 514. N The synchronization pulse sent by the host device 502 after the SSC can be used, or by the host device 502 or single-line slave devices 5041 to 504 after online turnaround.N Synchronization is achieved by sending a synchronization pulse from one of the circuits. According to certain aspects of this disclosure, local clock generation circuits 5141 to 514... N Synchronization can be achieved using transitions in the Manchester-encoded command and data payloads transmitted via SDATA line 506. Local clock generation circuits 5141 to 514. N This may include a ring oscillator or a delay-locked loop. In some specific implementations, the local clock generation circuits 5141 to 514... N Includes an injection-locked oscillator that responds to synchronization pulses and / or transitions during Manchester-coded commands and data payload transmission.

[0063] Holder circuit 516 may be coupled to SDATA line 506 to facilitate line turnaround, in-band interruption requests, or arbitration processes according to certain aspects disclosed herein. In one example, holder circuit 516 may be configured as a positive feedback circuit that drives SDATA line 506 through a high-impedance output and receives feedback from SDATA line 506 through a low-impedance input. Holder circuit 516 may be configured to maintain the signaling state or voltage of the last assertion on SDATA line 506. Holder circuit 516 may be in host device 502 or single-wire slave devices 5041 to 504. N The active line driver in one of them is easily overcome.

[0064] Figure 6 An example of a single-wire serial interface 600 that can be configured according to certain aspects of this disclosure is illustrated. In this example, a host device 502 and a single-wire slave device 504 are illustrated. N (See Figure 5 The host device 502 includes a protocol controller 602. The protocol controller 602 can be implemented using a processor, microcontroller, or finite state machine, and can be used to control the transmit and receive functions of the host device 502. The protocol controller 602 may include or be coupled to a signal generation circuit 604, which generates signals that couple the host device 502 to one or more slave devices 504. N The synchronization signal and SSC signal are transmitted on the SDATA line 620. The signal generation circuit 604 can be configured to generate different types of SSCs to initiate arbitration, initiate data transmission, or abandon arbitration. The signal generation circuit 604 can be configured to generate a synchronization pulse, which is used to enable the slave device 504. N The clock signal generated at the location is synchronized with the transmission clock signal generated in the host device 502.

[0065] Protocol controller 602 can be configured to selectively activate Manchester encoder 606 and Manchester decoder 608 based on the operating mode of single-wire serial interface 600. Manchester decoder 608 can extract data and clock information from signals received from SDATA line 620. Protocol controller 602 can also be configured to format datagrams for transmission via SDATA line 620. Protocol controller 602 can also be configured to generate commands to be transmitted via SDATA line 620.

[0066] In the illustrated example, single-line slave device 504 N This includes a protocol controller 622. The protocol controller 622 can be implemented using a processor, microcontroller, or finite state machine, and can be used to control a single-wire slave device 504. N The protocol controller 622 may include or be coupled to a signal generation circuit 624, which is in the single-wire slave device 504. N A synchronization pulse to be transmitted is generated during transmission via SDATA line 620. Protocol controller 622 can also be configured to cause signal generation circuit 624 to drive SDATA line 620 to initiate SSC during an in-band interrupt, and can also be configured to cause signal generation circuit 624 to drive SDATA line during arbitration. The synchronization pulse generated by signal generation circuit 604 can be configured to synchronize the clock signal generated at master device 502 with that at slave device 504. N The transmitted clock signal generated in the process is synchronized.

[0067] Protocol controller 622 can be configured to selectively activate Manchester encoder 626 and Manchester decoder 628 based on the operating mode of single-wire serial interface 600. Manchester decoder 628 can extract data and clock information from signals received from SDATA line 620. Protocol controller 622 can also be configured to format datagrams for transmission via SDATA line 620. Protocol controller 622 can also be configured to decompose datagrams and / or respond to commands received from SDATA line 620.

[0068] Protocol controller 602 can be configured to manage and control the operation of line driver 612 and line receiver 610. Protocol controller 622 can be configured to manage and control the operation of line driver 632 and line receiver 630. When inactive or deactivated, line drivers 612, 632 may present a high impedance to SDATA line 620. For example, when single-line slave device 504... NWhen configured or intended to send data or control signals via SDATA line 620, the output of line driver 612 in host device 502 can present high impedance to SDATA line 620. While host device 502 is driving SDATA line 620, single-line slave device 504... N The output of the line driver 632 is typically in a high impedance state.

[0069] A hold circuit 640 coupled to SDATA line 620 facilitates line turnaround, in-band interrupt requests, and arbitration processes in a bidirectional single-wire serial bus. Maintaining the state of SDATA line 620 is typically desired when all devices are in high-impedance mode, during line turnaround, or during arbitration. Line turnaround occurs when master device 502 transitions from transmitting to receiving or from receiving to transmitting. During arbitration, when single-wire slave device 504... N When the host device 502 has a transmit option and the line driver in the host device 502 can present a high impedance to the SDATA line 620 to avoid contention, the host device 502 can enter a high impedance mode. A hold circuit 640 can be used to maintain the state of the SDATA line 620. In one example, the hold circuit 640 can be configured as a positive feedback circuit that drives the SDATA line 620 through a high impedance output and receives feedback from the SDATA line 620 through a low impedance input. The hold circuit 640 can be configured to maintain the last asserted voltage on the SDATA line 620. The hold circuit 640 can be controlled by both the host device 502 and the single-line slave device 504. N The line drivers 612 and 632 in the middle can be easily overcome.

[0070] According to certain aspects disclosed herein, the protocol is used to control the operation of a mixed-mode serial bus coupled to concurrently active two-wire slave devices and single-wire slave devices. The protocol disclosed herein for configuring and controlling single-wire transmissions over the serial bus can coexist with, be based on, and / or be compatible with protocols for configuring and controlling two-wire transmissions over the serial bus. Certain aspects of this disclosure relate to error detection at single-wire slave devices that cannot access clock signals used by two-wire slave devices.

[0071] Figure 7A system 700 according to certain aspects disclosed herein is illustrated, in which a single-wire slave device 704 and a two-wire slave device 706 can coexist, and wherein a master device 702 can communicate with both the single-wire slave device 704 and the two-wire slave device 706. The master device 702 may be located in an RFIC, modem, application processor, or another type of device. The master device 702 is coupled to one or more slave devices 704, 706 via at least an SDATA line 710 of a two-wire serial bus 708 that also has an SCLK line 712. Data may be encoded in a data signal transmitted via the SDATA line 710, and in two-wire communication mode, a receiver can extract data using a clock signal transmitted via the SCLK line 712. In the illustrated example, the serial bus 708 operates according to the RFFE protocol. In other examples, the serial bus 708 may operate according to another protocol such as the I3C protocol, the SPMI protocol, etc. In the illustrated example, each single-wire slave device 704 and each two-wire slave device 706 are coupled to the SDATA line 710. The single-wire slave device 704 is adapted for single-wire communication mode, while the two-wire slave device 706 is also coupled to the SCLK line 712 to receive the clock signal used in two-wire communication mode.

[0072] The host device 702 may include a protocol controller 714, which may be implemented using processing circuitry having a processor, controller, state machine, or other logic components. The protocol controller 714 may be configured to support one or more protocols that can be used to manage the operation of the serial bus 708. In some implementations, the protocol controller 714 may be operable to configure one or more slave devices 704, 706. The protocol controller 714 may determine the configuration of the slave devices 704, 706 as designated recipients of data to be transmitted via the serial bus 708, and may accordingly encode the data in a signal to be transmitted via the SDATA line 710. In some cases, a broadcast message for a combination of single-wire slave device 704 and two-wire slave device 706 may be transmitted twice, once in single-wire communication mode and once in two-wire communication mode. The protocol controller 714 may additionally determine whether and / or when a clock signal should be transmitted via the SCLK line 712. In some implementations, the clock signal is suppressed when data is transmitted to one or more single-wire slave devices 704 in single-wire communication mode.

[0073] According to certain aspects disclosed herein, the host device 702 may select between a single-wire slave device 704 and a dual-wire slave device 706 at the start of a transaction. The host device 702 may use different Sequence Start Conditions (SSCs) to precede single-wire and dual-wire transactions. In some implementations, certain interface characteristics of the single-wire slave device 704 and / or the dual-wire slave device 706 may be configurable. For example, the single-wire slave device 704 and / or the dual-wire slave device 706 coupled to the serial bus 708 may match a specified bus capacitor when driving the SDATA line 710 based on a configurable register setting defined as a capacitor specified by the SDATA line 710. In other cases, the specified bus capacitor may be hardwired in the single-wire slave device 704 and / or the dual-wire slave device 706.

[0074] In some implementations, a programmable sequence of synchronization pulses transmitted after the SSC or other frame start signaling can be used as an edge-sensitive phase synchronization trigger at the receiver. In one example, the synchronization pulses are transmitted before the transmission of data bits (including after a line turnaround event when the receiving device becomes the transmitting device). In other implementations, the first synchronization pulse transmitted can be used as frame start signaling. In some implementations, each synchronization pulse is transmitted in a single clock cycle.

[0075] Interface state transitions can be detected and used to disable or enable the oscillator in the receive clock generation circuitry. For example, the oscillator can be enabled upon detection of an SSC or other frame start signaling, and disabled upon detection of a BPC or other frame end signaling, thereby saving energy by avoiding the need for a constantly on, free-running oscillator. When the single-wire serial bus is controlled by a protocol derived from the RFFE protocol, an SSC indicates the start of a frame.

[0076] Figure 8 Examples of certain aspects of this disclosure can be illustrated by means of... Figure 7 The serial bus 708 illustrated here transmits the start of a two-wire transaction 800 and the start of a single-wire transaction 820. The two-wire transaction 800 and the single-wire transaction 820 can be formatted according to the RFFE protocol.

[0077] Two-wire transaction 800 begins with an SSC 808 of duration consistent with the RFFE protocol. The serial bus 708 is initially idle, with both the SDATA line 802 and the SCLK line 804 in a low signaling state. The host device 702 can initiate two-wire transaction 800 by sending two bits of SSC 808. The bit duration, or the transmission time per data bit, can be determined by the frequency of the internal clock signal used by the host device 702. The internal clock can be selected to control the bit rate of the serial bus 708 during data transmission. SSC 808 comprises a pulse transmitted on the SDATA line 802 while the SCLK line 804 remains low. This pulse consists of a high bit followed by a low bit. Following SSC 808 may be a slave address, which can be part of the command and data information 810. In normal RFFE operation, the command and data information 810 includes the slave address [SA3:SA0]. Information can be captured from the SDATA line 802 based on the timing of the clock pulses in the transmit clock signal 812 provided on the SCLK line 804. No clock pulses are provided during the transmission of the SSC 808, and the receiving device recognizes the transition of signaling state indication control signaling on the SDATA line 802 when the SCLK line 804 is held low.

[0078] Various aspects of the SSC 808 are defined by the RFFE protocol, including the duration of the high and low portions of the SSC 808. The rise time of the preamble transition (T...) R ) and the fall time of the pulse termination transition (T) F The frequency of the clock signal transmitted on the SCLK line 804 is also defined by the protocol. Limitations on the frequency of the clock signal transmitted on the SCLK line 804 can be defined by the design, application, and / or by the RFFE specification and protocol. The protocol controller 714 can be configured to transmit a modified SSC indicating when to transact with the single-wire slave device 704. In some examples, the protocol controller 714 can transmit an extended-length SSC to target the single-wire slave device 704 for communication and / or indicate that the transaction will be conducted in single-wire communication mode. The extended-length SSC can have a duration greater than the duration of the SSC pulse for two-wire operation as defined by the RFFE specification. In some implementations, the protocol controller 714 can transmit a shortened SSC to target the single-wire slave device 704 for communication, wherein the shortened SSC comprises a pulse with a duration less than the duration of the SSC pulse provided according to the RFFE specification. In some cases, the protocol controller 714 can transmit an SSC with modified rise and / or fall times to target the single-wire slave device 704 for communication.

[0079] The illustrated single-wire transaction 820 provides an example of using an extended-duration SSC 822 configured to target a single-wire slave device 704. The serial bus 708 is initially idle, with both the SDATA line 802 and the SCLK line 804 in a low signaling state. The single-wire nature of transaction 820 is indicated by a pulse timing signature in the SSC 822. In the illustrated example, the pulse timing signature corresponds to a pulse duration in the SSC 822 that is three times the pulse duration of the SSC 808 sent to initiate the two-wire transaction 800. In other examples, the pulse duration of the SSC 822 may be some other multiple of the pulse duration of the SSC 808 sent to initiate the two-wire transaction 800.

[0080] The duration of the pulses in SSCs 808 and 828 can be measured or determined using an internal clock signal 806 provided in the single-wire slave device 704 and the two-wire slave device 706. The illustrated internal clock signal 806 is an oversampled signal whose frequency is four times the frequency of the transmit clock signal 812 sent on the SCLK line 804 during a two-wire transaction 800. In one example, the frequency of the transmit clock signal 812 is 52 MHz. The internal clock signal 806 is needed to measure the duration of the pulses in SSCs 808 and 828 because no clock pulses are provided on the SCLK line 804 during the transmission of SSCs 808 or 828.

[0081] The host device 702 initiates a single-wire transaction 820 by sending an extended-duration SSC 822. The pulse in the extended-duration SSC 822 consists of three high bits followed by one low bit. Following the extended-duration SSC 822 is a synchronization mode 824, which includes bits that can be used to synchronize the phase of the internal clock signal 806 with the edges of the data signal transmitted via the SDATA line 802. After the synchronization mode 824 has been sent, command and data information 826 is transmitted by the host device 702 in a Manchester-encoded data signal. The command and payload data in the single-wire transaction 820 can be sampled or captured based on the timing of the synchronized internal clock signal 806.

[0082] According to certain aspects of this disclosure, clock phase and frequency synchronization at the receiver coupled to a single-wire serial bus is acquired and maintained by using Manchester encoding. Manchester encoding embeds clock information into each bit transmitted via the single-wire serial bus by requiring each bit to include a transition in the middle of the bit transmission interval. According to one aspect of this disclosure, the received clock signal can be resynchronized for each Manchester-encoded bit received in the data stream. Synchronization implemented at the bit transmission rate can eliminate the cumulative effects of phase and frequency variations and can ensure error-free data recovery with infinite data frame lengths. In one aspect, higher power efficiency can be achieved by using Manchester encoding.

[0083] Figure 9 Examples of certain aspects of this disclosure are illustrated for use via SDATA line 506 (see Figure 5 In the host device 502 and single-line slave devices 5041 to 504 N This involves Manchester encoding and certain aspects of control signaling for data exchange. As shown in the first timing diagram 900, Manchester encoding encodes each bit of data in the direction of transitions occurring in the middle of bit transmission intervals 902. For example, a signal line may initially be low, and a transition 904 to high indicates a "0" value bit. A transition 906 may initially be high, and a transition 906 to low indicates a "1" value bit. Clock information is embedded in the data signal during transitions occurring within each bit transmission interval 902.

[0084] The second timing diagram 910 illustrates five bit transmission intervals 914a to 914e in the signal carried on SDATA 912. The bit sequence {0,0,1,1,0} transmitted in the five bit transmission intervals 914a to 914e illustrates the transitions within each of the five bit transmission intervals 914a to 914e. It will be observed that transitions may occur at some boundaries between bit transmission intervals 914a to 914e, and no transitions occur at other boundaries between bit transmission intervals 914a to 914e.

[0085] Third timing diagram 920 illustrates certain aspects of the timing associated with transmitting an 8-bit data frame 922 via a single-wire serial bus. The data frame 922 can be serialized and provided to the Manchester encoder in a data signal 924. In some implementations, the Manchester encoder receives parallel data for encoding or accesses the data frame stored in a transmit buffer. The Manchester encoder can encode the data according to the timing provided by the transmit clock signal 926. In one example, the frequency of the transmit clock signal 926 can be 52 MHz. The Manchester encoder generates a Manchester encoded signal 928 for transmission via the single-wire serial bus.

[0086] At the receiving device, the Manchester encoded signal 928 is provided to the Manchester decoder. The Manchester decoder may include or be coupled to a clock generation circuit configured to generate a receive clock signal 930 to be used for decoding data from the Manchester encoded signal 928. The clock generation circuit may include one or more oscillators, one or more frequency dividers, and a phase synchronization circuit. The phase synchronization circuit may be configured to synchronize the receive clock signal 930 based on timing information derived from the Manchester encoded signal 928. The timing information includes a transition 934 of the Manchester encoded signal 928 at the center of each bit transmission interval 932.

[0087] In the illustrated example, each falling edge 938 in the receive clock signal 930 is delayed relative to the corresponding falling edge 936 in the transmit clock signal 926. The delay 940 between the associated falling edges 936, 938 can be configured to provide sufficient setup and hold time for the sampling circuitry in the receiver device. The delay 940 between the associated falling edges 936, 938 can be configured to provide tolerance for phase offset between the transmit clock signal 926 and the receive clock signal 930, including transient phase offset caused by noise affecting the single-wire serial bus and phase offset caused by synchronization loss or incomplete synchronization.

[0088] According to certain aspects of this disclosure, a single-wire serial bus can be configured, managed, controlled, and / or monitored according to standard-defined or proprietary protocols. For the purposes of this description, examples of the RFFE protocol will be illustrated. However, these concepts are not limited to the RFFE protocol, and various aspects of this disclosure are equally applicable to I2C, I3C, SPI, SPMI, and other standard-defined or proprietary protocols. For example, other protocols employ or may be adapted to use similar arbitration schemes, Start-of-Frame (SoF) and End-of-Frame (EoF) signaling, command structures, and datagram or data frame configurations. In some cases, protocols defined for use with a two-wire serial bus may be adapted to implement features such as wire turnaround for controlling the single-wire serial bus.

[0089] Figure 10A write transaction 1000 performed on a single-wire serial bus configured according to certain aspects disclosed herein is illustrated. Write transaction 1000 may begin with the transmission of SSC 1002. In the illustrated example, SSC 1002 has a duration of three transmit clock cycles. In some specific implementations, arbitration may optionally follow SSC 1002. Write transaction 1000 continues by transmitting a synchronization pulse 1004, which the receiving device can use to synchronize its local clock generation circuitry. A write command 1006 is then transmitted. Write command 1006 may have a structure and content compatible with or conforming to one or more commands defined by the RFFE protocol. Manchester encoding may be used to encode write command 1006. The host device then transmits a payload 1008 pointing to the device identified in write command 1006. Payload 1008 may be encoded using Manchester encoding. Write transaction 1000 terminates via EoF 1010. In some cases, EoF 1010 may be indicated by a number of idle SDATA cycles. In one example, EoF 1010 is indicated when SDATA is idle for 7 cycles of the transmit clock.

[0090] A read transaction 1020, executed on a single-wire serial bus and configured according to certain aspects disclosed herein, may begin with the transmission of SSC 1022. In the illustrated example, SSC 1022 has a duration of three transmit clock cycles. Read transaction 1020 continues by transmitting a synchronization pulse 1024, which the receiving device can use to synchronize its local clock generation circuitry. A read command 1026 is then transmitted. The read command 1026 may have a structure and content compatible with or conforming to one or more commands defined by the RFFE protocol. The read command 1026 may be encoded using Manchester encoding.

[0091] The master device provides a turnaround period during which it puts its line drivers into a high-impedance state, and the slave device addressed by read command 1026 activates its line drivers. The slave device sends a synchronization pulse 1028, which the master device can use to synchronize its receive clock generation circuitry. In one example, the slave device uses two cycles of its transmit clock signal to send the synchronization pulse 1028. The slave device then sends the payload 1030. The payload 1030 can be encoded using Manchester encoding. Read transaction 1020 is terminated by EoF 1032. In some cases, EoF 1032 can be indicated by SDATA being idle for several cycles. In one example, EoF 1032 is indicated when SDATA has been idle for 7 cycles of the transmit clock.

[0092] When a serial bus supports different mutually exclusive communication modes, certain bus state errors may occur. For example, a mixed-mode serial bus supporting both single-wire and two-wire RFFE transactions may be susceptible to errors that could lead to deadlock between slave and master devices, including when a slave device fails to respond to a command and / or when a slave device detects an error while decoding data. In some cases, a master or slave device may unilaterally or incorrectly enter a state where it is waiting for signaling that will not be sent.

[0093] Figure 11 An example of a bus state error that may occur when a two-wire RFFE transaction 1100 is performed via a mixed-mode serial bus is illustrated. In the illustrated example, before the host device sends a two-wire SSC 1106 via SDATA 1102 to initiate a two-wire RFFE transaction 1100, SDATA 1102 and SCLK 1104 are in a nominal idle signaling state for a certain period of time. The two-wire SSC 1106 includes a pulse 1110 with a duration (t) corresponding to a clock period of the transmit clock sent via SCLK 1104. 脉冲 1130). A single-wire receiver coupled to the SDATA 1102 measures the duration of the pulse and identifies when a two-wire transaction is beginning. The single-wire receiver can enter idle mode and wait for the next bus idle period, which may be followed by a single-wire SSC.

[0094] The single-wire receiver is not coupled to SCLK 1104 and determines that the serial bus is idle only from the line state of SDATA 1102. In the illustrated example, the two-wire command and data 1108 transmitted via the serial bus produces a sequence of line states 1122, 1124, and 1126 that can be perceived by the single-wire receiver as a single-wire SSC 1128. During the transmission of the two-wire command and data 1108, the all-zero bit sequence makes SDATA 1102 appear to be in idle state 1122. The minimum idle period before the transmission of the SSC can be defined by the protocol as a duration less than 8 periods of the transmit clock transmitted via SCLK 1104, and a sequence of consecutive "0" bits can appear to be a valid idle period for the single-wire receiver. After the all-zero bit transmission, there can be a sequence of three "1" bits and at least one "0" bit. The appearance of idle state 1122 and the subsequent 3-bit high state can be perceived by the single-wire receiver as a valid single-wire SSC 1128. A single-line receiver may exit idle mode and enter an error state, in which the single-line receiver waits for synchronization mode.

[0095] Another example of a bus status error may occur when a two-wire RFFE transaction 1100 is being performed via a mixed-mode serial bus. Bus status errors can be caused by a single-wire receiver discarding a command or by error detection in the single-wire receiver. In some cases, the single-wire receiver may not return data as expected. The single-wire receiver may fail to respond to an acknowledgment of a write command or may fail to send data in response to a read command. Parity errors detected in the received single-wire payload may cause the single-wire receiver to fail to acknowledge the receipt of a command or data. In some cases, parity errors may be caused by bit errors, and in others, they may be caused by clock synchronization errors that prevent the single-wire receiver from capturing one or more bits. In the latter case, the single-wire receiver may avoid transmitting negative acknowledgments because it cannot reliably know when the host device expects an acknowledgment.

[0096] Some aspects of this disclosure relate to circuits and methods by which devices coupled to a mixed-mode serial bus can correctly and reliably handle error conditions that occur during single-wire or two-wire transactions through the serial bus. Certain error handling techniques are disclosed that enable devices coupled to a mixed-mode serial bus to recover from error conditions that may occur during single-wire and / or two-wire transactions on the bus, as well as state errors that may otherwise prevent further bus operation.

[0097] In some respects, timing circuitry can be configured to force the termination of a read or write operation when an expected response delay is anticipated. In one example, one or more timing circuits in the timing circuitry can be configured to reset the receiver or transmitter state machine after a programmable number of clock cycles following a data reception delay. In another example, one or more timing circuits in the timing circuitry can be configured to enforce a minimum timeout period before the local clock oscillator on the single-wire peripheral is disabled or idled. The forced timeout period can be configured with a duration that allows the local clock oscillator to remain active until the received erroneous packet has been completed and completely rejected, and ensures that the single-wire peripheral can reliably detect the next SSC and can be correctly synchronized when the next SSC is a single-wire SSC.

[0098] In some respects, the timing circuitry can be configured with a programmable duration that allows bus snooping by the single-wire peripheral device before it enters an idle or low-power operating mode. The bus snooping and associated logic in the single-wire peripheral device can be configured to deny activity associated with valid two-wire communication on the bus data line (SDATA).

[0099] In some respects, the timing circuitry in a two-wire peripheral device can be configured to reject single-wire communication activity on the bus data line (SDATA) for a programmable time length based on inactivity detection of the clock signal (SCLK).

[0100] The timing circuit may include a timer or counter that is internally sent or received clock signals or timed by a programmable clock frequency that can be configured to provide a real-time clock reference.

[0101] Figure 12 A receiver circuit 1200, which can be configured for single-wire operation according to certain aspects disclosed herein, is illustrated. The receiver circuit 1200 is configured or adapted to be coupled to a data line (SDATA 1220) of a mixed-mode serial bus. In the illustrated example, the receiver circuit 1200 is disposed in a single-wire slave device and is configured to operate as a Manchester decoder that produces an output 1230 representing data encoded in the signal transmitted via SDATA 1220.

[0102] Receiver circuitry 1200 includes a clock generator 1206 configured to provide multiple clock signals 1216. Clock generator 1206 may include or be coupled to a programmable oscillator. The programmable oscillator may be configured to generate a base clock signal at a frequency that is a multiple of the frequency of the clock signal used by the transmitter to encode data for transmission via SDATA 1220. In one example, the programmable oscillator may be configured to generate a base clock signal at a frequency four times (4x) that is the frequency of the clock signal used by the transmitter to encode data for transmission via SDATA 1220. In some implementations, the programmable oscillator may be implemented using programmable ring oscillator circuitry. Clock generator 1206 may include frequency dividers, delay circuitry, phase shifters, inverters, and other circuitry that can modify the frequency or phase of the clock signal. In the illustrated example, clock generator 1206 outputs a sampled signal 1218 that is half the frequency of the base clock signal and twice the frequency of the clock signal used by the transmitter during encoding. The sampling signal 1218 times the trigger 1208 coupled to the SDATA 1220, so that the trigger 1208 can capture data from the SDATA 1220 when enabled.

[0103] Synchronization circuit 1204 can be used to control the frequency and phase of clock signal 1216. Synchronization circuit 1204 can be configured to align the edges of clock signal 1216 with transitions in the data signal transmitted via SDATA 1220. Synchronization circuit 1204 can configure control signal 1214 to enable and disable trigger 1208 based on the current state of receiver circuit 1200. Synchronization circuit 1204 can be configured to enable and disable the oscillator in clock generator 1206 based on the current state of SDATA 1220. In one example, status monitoring circuit 1202 determines when SSC has been received, when SDATA 1220 is active and carrying a data signal, and when the end of transmission has been detected. In some specific implementations, synchronization circuit 1204 uses control and status signals 1212 to manage the operation of clock generator 1206. For example, the synchronization circuit 1204 may be configured to enable the oscillator in response to a control signal 1222 indicating the detection of the SSC received from the status monitoring circuit 1202, to align the frequency and phase of the clock signal 1216 during the transmission of the synchronization pulse, and to continuously adjust the frequency and phase to synchronize the clock signal 1216 using the edges detected in the data signal received from the SDATA 1220 during active transmission.

[0104] The illustrated receiver circuit 1200 includes multiple timers 1224a to 1224e. One or more of the timers 1224a to 1224e can be used by the state monitoring circuit 1202 to determine when an SSC has been detected, and whether the SSC is a single-wire SSC or a dual-wire SSC. One or more of the timers 1224a to 1224e can be monitored by a controller configured to manage the operating state of the receiver circuit 1200. In the illustrated example, the controller circuitry includes a finite state machine 1210. The finite state machine 1210 can be configured to handle error conditions that occur when single-wire or dual-wire transactions are performed via a mixed-mode serial bus.

[0105] Figure 13 Including an example of state diagram 1300, which illustrates when Figure 12 When the receiver circuit 1200 is coupled to the data line (SDATA 1220) of the mixed-mode serial bus, certain operations and functions can be performed by the receiver circuit 1200. The receiver circuit 1200 can be in an idle state 1302 when there is no active participation in a transaction or when no activity is detected on the SDATA 1220. In some implementations, the finite state machine 1210 can disable or idle the oscillator circuit in the clock generator 1206 to save power.

[0106] When finite state machine 1210 determines that SDATA 1220 has transitioned to an active or high logic state 1320, receiver circuit 1200 transitions to SSC detection state 1304. In SSC detection state 1304, finite state machine 1210 can activate the oscillator circuit in clock generator 1206 and other circuits that were de-energized or disabled in idle state 1302. Finite state machine 1210 can determine that SDATA 1220 has transitioned to a high logic state based on signaling received from state monitoring circuit 1202. Receiver circuit 1200 remains in SSC detection state 1304, while SDATA 1220 remains in high logic state 1324. Finite state machine 1210 can initialize and monitor SSC timer 1224a to determine the next state of receiver circuit 1200. In one example, SSC timer 1224a stops when SDATA 1220 transitions to an inactive low logic state upon the termination of a pulse on SDATA 1220. The time value held by SSC timer 1224a indicates the duration of the pulse. Finite state machine 1210 can determine whether the duration of the pulse corresponds to a valid SSC. In some specific implementations, finite state machine 1210 can be configured to identify standard-defined two-wire SSCs and one or more single-wire SSCs. For example, a two-wire SSC may have a duration corresponding to a period of the transmitter clock signal transmitted on SCLK (i.e., one clock cycle), while a single-wire SSC may have a duration corresponding to three clock cycles of the transmitter clock signal. In some cases, other types of single-wire SSCs are defined as having a duration that is some other multiple of the period of the transmitter clock signal.

[0107] When finite state machine 1210 determines that a pulse detected on SDATA 1220 has a duration corresponding to an invalid SSC 1322, the pulse can be ignored, and finite state machine 1210 can return receiver circuit 1200 to idle state 1302. When finite state machine 1210 determines that a pulse detected on SDATA 1220 has a duration corresponding to an active two-line SSC 1340, finite state machine 1210 can transition receiver circuit 1200 to two-line transaction monitoring state 1312, in which two-line transactions are ignored. In some implementations, when the receiver circuit enters two-line transaction monitoring state 1312, finite state machine 1210 can initialize idle timer 1224c. In some examples, idle timer 1224c is reset when SDATA 1220 transitions to high logic state 1342 and is configured to expire when SDATA 1220 remains in low logic state for a programmable number of clock pulses of sampling signal 1218. In other examples, the idle timer 1224c is configured to expire after a duration calculated to ensure that the two-line transaction has fully started before the idle timer 1224c expires. When the idle timer 1224c expires 1344, the finite state machine 1210 can cause the receiver circuitry 1200 to return to the idle state 1302.

[0108] When finite state machine 1210 determines that the pulse detected on SDATA 1220 while the receiver circuit is in SSC detection state 1304 has a duration corresponding to a valid single-wire SSC 1326, finite state machine 1210 can transition the receiver circuit 1200 to synchronization detection state 1306. When the receiver circuit enters synchronization detection state 1306, finite state machine 1210 can initialize synchronization timer 1224b. Synchronization timer 1224b can be configured to expire after a period of time after which a synchronization mode is expected to be received via SDATA 1220. This period of time can be programmed or configured based on the transmitter clock rate and / or programmed or configured to adapt to an expected delay or transmitter startup delay. If synchronization timer 1224b expires or an invalid synchronization mode 1330 is detected, finite state machine 1210 can return the receiver circuit 1200 to idle state 1302. When a valid synchronization mode 1328 is detected before the synchronization timer 1224b expires, the finite state machine 1210 can transition the receiver circuit 1200 to a single-wire transaction processing state 1308. The receiver circuit 1200 can be configured to receive and decode Manchester-encoded commands and data in the single-wire transaction processing state 1308. The finite state machine 1210 can return the receiver circuit 1200 to an idle state 1302 after detecting that the single-wire transaction has been directed to a different device or after the single-wire transaction has successfully completed 1332.

[0109] Finite state machine 1210 can determine that an error 1334 occurred while processing a single-line transaction in single-line transaction processing state 1308, and can cause the receiving circuit to abandon the single-line transaction and enter transaction termination detection state 1310. When the receiving circuit enters transaction termination detection state 1310, finite state machine 1210 can initialize transaction timer 1224d. Transaction timer 1224d can be configured to expire after a duration calculated to be long enough to ensure that the single-line transaction has been completed. In some specific implementations, transaction timer 1224d can be configured to expire after a period of time defined by the protocol or application after SDATA 1220 has been idle. Transaction timer 1224d can be configured to enable the receiving circuit to discard data packets when a parity or cyclic redundancy check (CRC) error is detected, and remain ready to send SSC immediately after the discarded data packets. Finite state machine 1210 can cause the receiver circuit 1200 to return to idle state 1302 after transaction timer 1224d has expired 1336.

[0110] According to certain aspects of this disclosure, when the receiving circuitry enters idle state 1302, the finite state machine 1210 can initialize oscillator timer 1224e. One or more circuits in the receiving circuitry 1200 (including the oscillator circuitry and associated circuitry in the clock generator 1206) can be disabled or idled after oscillator timer 1224e expires. Oscillator timer 1224e can be configured to expire after a duration calculated to achieve an optimal trade-off between the power consumption and responsiveness of clock generator 1206. In some specific implementations, clock generator 1206 requires a period of time to achieve frequency and / or phase locking. Idle clock generator 1206 can be activated upon detection of a possible leading edge of SSC. In one example, oscillator timer 1224e keeps clock generator 1206 active when a second transaction immediately follows a first transaction. In a later example, oscillator timer 1224e can be programmed to expire after a minimum or expected SDATA idle period between the end of a transaction and the next SSC.

[0111] A host device configured according to certain aspects of this disclosure may be configured with one or more timers that enable the host device to avoid bus blocking when a single-wire receiving device detects an error in transmission. For example, the receiving circuit 1200 may exit the single-wire transaction state 1308 after detecting a parity or CRC error in data or a command transmitted by the host device. The host device may start a response timer after completing the transmission of data or command bits to minimize or limit the waiting time for acknowledgments from the receiving circuit 1200 or for data transmitted by the receiving circuit 1200 in response to a read command. For example, the receiving circuit 1200 may detect an error in a read command sent by the host device and may abandon the transaction without responding to the read command. The host device is generally unaware that the receiving circuit 1200 has exited the transaction and may be configured to wait for a response until the response timer expires.

[0112] Figure 14 A receiver circuit 1400, configurable for two-wire operation according to certain aspects disclosed herein, is illustrated. The receiver circuit 1400 is configured to couple to the data line (SDATA 1420) and clock line (SCLK 1422) of a mixed-mode serial bus. In the illustrated example, the receiver circuit 1400 is disposed in a two-wire slave device and is configured to provide an output 1430 representing data encoded in the signal transmitted via SDATA 1420 using a sampled clock signal 1418 derived from a bus clock signal 1416 received via SCLK 1422.

[0113] In the illustrated example, the sampling clock signal 1418 can be generated using a clock and data recovery circuit (CDR circuit 1404). The CDR circuit 1404 may include or be coupled to a clock generator 1406 that provides an internal clock signal 1412. In some implementations, the frequency of the internal clock signal 1412 is a multiple of the frequency of the bus clock signal 1416 received by the SCLK 1422. In one example, the frequency of the internal clock signal 1412 is four times (4x) the frequency of the bus clock signal 1416. In some implementations, the CDR circuit 1404 may be implemented using a programmable ring oscillator circuit, and the CDR circuit 1404 may be configured to phase-align the sampling clock signal 1418 with the bus clock signal 1416. The CDR circuit 1404 may include a frequency divider, delay circuitry, a phase shifter, an inverter, and other circuitry that can modify the frequency or phase of the clock signal. In the illustrated example, CDR circuit 1404 outputs a sampling signal 1418, which is half the frequency of the basic clock signal and twice the frequency of the bus clock signal 1416. Sampling signal 1418 timestamps a flip-flop 1408 coupled to SDATA 1420, enabling flip-flop 1408 to capture data from SDATA 1420 when enabled. Flip-flop 1408 can be enabled by finite state machine 1410, which is configured to manage the state of receiver circuit 1400 and / or handle error conditions occurring when single-wire or dual-wire transactions are performed via a mixed-mode serial bus.

[0114] According to certain aspects of this disclosure, receiver circuit 1400 may include state monitoring circuit 1402 configured to determine when an SSC has been received, when SDATA 1420 is active and carrying a data signal, and when the end of transmission has been detected. The illustrated receiver circuit 1400 includes a plurality of timers 1424a to 1224c. One or more of timers 1424a to 1224c may be used by finite state machine 1410 to determine whether the detected SSC is a single-wire SSC or a single-line SSC and / or to manage the operation of receiver circuit 1400. Detection of the type of SSC can enable receiver circuit 1400 to enter an idle state earlier, thereby saving power. Additionally, one or more of timers 1424a to 1424c may be used to manage the operating state of receiver circuit 1400 before bus clock signal 1416 is available. Timers 1424a to 1424c can be timed by a real-time clock signal provided by clock generator 1406, or by an internal clock signal 1412, a frequency-divided version of the internal clock signal 1412, or another clock signal generated by clock generator 1406 with a frequency that is a multiple of or greater than the frequency of the internal clock signal 1412.

[0115] Figure 15 Including an example of state diagram 1500, which illustrates when Figure 14 When the receiver circuit 1400 is coupled to the mixed-mode serial bus SDATA 1420 and SCLK 1422, certain operations and functions are performed by the receiver circuit 1400. The receiver circuit 1400 can be in an idle state 1502 when there is no active participation in a transaction or when no activity is detected on SDATA 1420. In some implementations, the finite state machine 1410 can disable or idle the oscillator circuit in the clock generator 1406 to save power when the receiver circuit 1400 enters the idle state 1502.

[0116] When finite state machine 1410 determines that SDATA 1420 has transitioned to the active, high logic state 1520, receiver circuit 1400 transitions to the SSC detection state 1504. In the SSC detection state 1504, finite state machine 1410 can activate the oscillator circuit in clock generator 1406 and other circuits that were de-energized or disabled in idle state 1502. Finite state machine 1410 can determine that SDATA 1420 has transitioned to the high logic state based on signaling received from state monitoring circuit 1402. Receiver circuit 1400 remains in SSC detection state 1504, while SDATA 1420 remains in the high logic state 1524. Finite state machine 1410 can initialize and monitor SSC timer 1424a to determine the next state of receiver circuit 1400. In one example, when SDATA 1420 transitions to the inactive, low logic state, SSC timer 1424a stops, thereby terminating the pulses on SDATA 1420. The time value held by SSC timer 1424a indicates the duration of the pulse. Finite state machine 1410 can determine whether the duration of the pulse corresponds to a valid two-wire SSC.

[0117] In some implementations, the finite state machine 1410 can be configured to recognize standard-defined two-wire SSCs and can treat one or more types of single-wire SSCs as dummy SSCs. In one example, a valid two-wire SSC can be indicated by a pulse transmitted when SCLK 1422 is idle, the pulse having a duration corresponding to a period of the transmitter clock. The receiver circuit 1400 can be configured to ignore certain signaling on SDATA 1420, including when signaling following a single-wire SSC is transmitted without any clock signal being transmitted concurrently through SCLK 1422. According to one aspect of this disclosure, a single-wire SSC has a longer duration than a two-wire SSC, and in at least some implementations, the receiver circuit 1400 can enter an idle state when a single-wire SSC is detected.

[0118] When finite state machine 1410 determines that a pulse detected on SDATA 1420 has a duration corresponding to an invalid SSC 1522, the pulse can be ignored, and finite state machine 1410 can return receiver circuit 1400 to idle state 1502. When finite state machine 1410 determines that a pulse detected on SDATA 1420 has a duration corresponding to a valid two-line SSC 1532, finite state machine 1410 can transition receiver circuit 1400 to two-line transaction processing state 1512. Receiver circuit 1400 can be configured to receive and decode commands and data in two-line transaction processing state 1534. Finite state machine 1410 can return receiver circuit 1400 to idle state 1502 after detecting that a two-line transaction has been directed to a different device or after a single-line transaction has completed 1536.

[0119] When finite state machine 1410 determines that the pulse detected on SDATA 1420 when the receiver circuit is in SSC detection state 1504 has a duration corresponding to a valid single-wire SSC 1526, finite state machine 1410 can transition the receiver circuit 1400 to a single-wire transaction state 1506, in which the receiving device 1400 ignores activity on SDATA 1420. In some cases, the receiving device 1400 remains in single-wire transaction state 1506 while SCLK 1422 is idle and SDATA 1420 is active, as indicated by the absence of clock pulse 1528 on SCLK 1422 and the transition of signaling state on SDATA 1420.

[0120] In some implementations, when receiver circuitry 1400 enters single-wire transaction state 1506, finite state machine 1410 can initialize idle timer 1424c. In some examples, idle timer 1424c is reset when SCLK 1422 transitions to high logic state 1524 and is configured to expire while SCLK 1422 and / or SDATA 1420 remain in a low logic state corresponding to a programmable number of cycles of bus clock signal 1416. In other examples, idle timer 1424c is configured to expire after a duration calculated or selected by the application or during system configuration, and when idle timer 1424c expires 1530, finite state machine 1410 can return receiver circuitry 1400 to idle state 1502.

[0121] Examples of processing circuits and methods

[0122] Figure 16This is a diagram illustrating an example of a hardware implementation of device 1600. In some examples, device 1600 may perform one or more functions disclosed herein. According to various aspects of this disclosure, processing circuitry 1602 may be used to implement elements, any portion of elements, or any combination of elements as disclosed herein. Processing circuitry 1602 may include one or more processors 1604 controlled by some combination of hardware modules and software modules. Examples of processors 1604 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic components, discrete hardware circuitry, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors 1604 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 1616. One or more processors 1604 may be configured by a combination of software modules 1616 loaded during initialization, and may also be configured by loading or unloading one or more software modules 1616 during operation.

[0123] In the illustrated example, processing circuitry 1602 may be implemented using a bus architecture typically represented by bus 1610. Depending on the specific application of processing circuitry 1602 and overall design constraints, bus 1610 may include any number of interconnect buses and bridges. Bus 1610 links together various circuits including one or more processors 1604 and storage devices 1606. Storage devices 1606 may include memory devices and mass storage devices, and may be referred to herein as computer-readable storage media and / or processor-readable storage media. Bus 1610 may also link various other circuits, such as timing sources, timers, peripheral devices, voltage regulators, and power management circuitry. Bus interface 1608 provides an interface between bus 1610 and one or more transceivers 1612a, 1612b. Transceivers 1612a, 1612b may be provided for each networking technology supported by the processing circuitry. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules found in transceivers 1612a, 1612b. Each transceiver 1612a, 1612b provides components for communicating with various other devices via a transmission medium. In one example, transceiver 1612a may be used to couple device 1600 to a multi-wire bus. In another example, transceiver 1612b may be used to connect device 1600 to a radio access network. Depending on the nature of device 1600, a user interface 1618 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and this user interface may be communicatively coupled to bus 1610, either directly or via bus interface 1608.

[0124] Processor 1604 may be responsible for managing bus 1610 and for general processing, which may include executing software stored in processor-readable storage medium (including the illustrated storage device 1606). In this regard, processing circuitry 1602 (including processor 1604) may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 1606 may be used to store data manipulated by processor 1604 during software execution, and the software may be configured to implement any of the methods disclosed herein.

[0125] One or more processors 1604 in processing circuitry 1602 can execute software. Software should be broadly interpreted as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other names. The software may reside in a computer-readable form in storage device 1606 or on an external processor-readable storage medium. External processor-readable storage media and / or storage device 1606 may include non-transitory processor-readable storage media. Non-transitory processor-readable storage media include, for example, magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical disks (e.g., compact discs (CDs) or digital versatile discs (DVDs)), smart cards, flash memory devices (e.g., "flash drives," cards, sticks, or flash disks), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM, including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. The processor-readable storage medium and / or storage device 1606 may also include, for example, a carrier wave, a transmit line, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. The processor-readable storage medium and / or storage device 1606 may reside in processing circuitry 1602, in processor 1604, outside of processing circuitry 1602, or distributed across multiple entities including processing circuitry 1602. The processor-readable storage medium and / or storage device 1606 may be embodied in a computer program product. As an example, a computer program product may include a processor-readable storage medium in packaging material. Those skilled in the art will recognize how best to achieve the functionality described throughout this disclosure depends on the specific application and the overall design constraints imposed on the system as a whole.

[0126] Storage device 1606 can maintain and / or organize software in loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 1616. Each software module in software module 1616 may include instructions and data that, when installed or loaded into processing circuitry 1602 and executed by one or more processors 1604, contribute to a runtime image 1614 controlling the operation of one or more processors 1604. Certain instructions, when executed, cause processing circuitry 1602 to perform functions according to certain methods, algorithms, and processes described herein.

[0127] Some software modules in software module 1616 may be loaded during the initialization of processing circuitry 1602, and these software modules 1616 may configure processing circuitry 1602 to perform the various functions disclosed herein. For example, some software modules 1616 may configure the internal devices and / or logic circuitry 1622 of processor 1604, and may manage access to external devices such as transceivers 1612a, 1612b, bus interface 1608, user interface 1618, timers, math coprocessors, etc. Software module 1616 may include control programs and / or operating systems that interact with interrupt handlers and device drivers and control access to various resources provided by processing circuitry 1602. Resources may include memory, processing time, access to transceivers 1612a, 1612b, user interface 1618, etc.

[0128] One or more processors 1604 of the processing circuitry 1602 can be multifunctional, whereby some software modules in software module 1616 are loaded and configured to perform different functions or different instances of the same function. One or more processors 1604 may be additionally adapted to manage background tasks initiated in response to inputs, such as from user interface 1618, transceivers 1612a, 1612b, and device drivers. To support the execution of multiple functions, one or more processors 1604 can be configured to provide a multitasking environment, whereby each of the multiple functions is implemented as a set of tasks to be served by one or more processors 1604 as needed or desired. In one example, the multitasking environment can be implemented using a time-sharing program 1620 that transfers control of the processors 1604 between different tasks, whereby each task returns control of the one or more processors 1604 to the time-sharing program 1620 upon completion of any incomplete operation and / or in response to inputs such as interrupts. When a task has control over one or more processors 1604, the processing circuitry is effectively dedicated to the purpose addressed by the function associated with the control task. The time-sharing program 1620 may include an operating system, a main loop for loop-based transfer control, a function to allocate control of one or more processors 1604 according to function priority, and / or an interrupt-driven main loop to provide control of one or more processors 1604 to a disposal function in response to external events.

[0129] Processing circuitry 1602 may be configured to perform one or more of the functions disclosed herein. For example, processing circuitry 1602 may be configured to operate as a master device coupled to a serial bus. Processing circuitry 1602 may be configured to initiate a pulse on a line coupling processing circuitry 1602 to a slave device, present a high impedance to the line after initiating the pulse, and determine whether the slave device has prematurely terminated the pulse, thereby indicating a first encoded value. If the slave device has not terminated the pulse, processing circuitry 1602 may be configured to terminate the pulse after a duration sufficient to indicate a second encoded value. In one example, the first encoded value is assigned binary 1 and the second encoded value is assigned binary 0. In another example, the first encoded value is assigned binary 0 and the second encoded value is assigned binary 1. Processing circuitry 1602 may be configured to determine the encoded value or may employ a separate PWM decoder.

[0130] Figure 17Flowchart 1700 illustrates a method for data communication that can be performed by the receiving circuitry in a slave device coupled to a single line (SDATA) of a multimode serial bus. One or more single-wire slave devices and one or more two-wire slave devices can be coupled to the multimode serial bus. The master device can exchange Manchester-encoded data with the single-wire slave device. The master device can send Manchester-encoded data and commands to the single-wire slave device via the data line (SDATA) of the multimode serial bus.

[0131] At block 1702, the receiving circuit can configure the oscillator to generate a basic clock signal with a basic frequency. At block 1704, the receiving circuit can configure the synchronization circuit to synchronize the edges of the basic clock signal with the edges of the Manchester-encoded data signal received via the serial bus. At block 1706, the receiving circuit can detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of SSC, which indicates a first type of transaction during which the Manchester-encoded data signal is received via the serial bus. At block 1708, the receiving circuit can configure a first timer to expire after a first timeout period. At block 1710, the receiving circuit can ignore the first pulse if no signaling consistent with the first type of SSC has been received before the first timer expires.

[0132] In some specific implementations, the pulse duration defined for the first type of SSC is longer than the pulse duration defined for the second type of transaction, in which data is received via a serial bus using a bus clock signal that defines the timing of the data signal. The frequency of the basic clock signal can be a multiple of the frequency of the bus clock signal.

[0133] In some examples, the signaling consistent with the first type of SSC includes a synchronization mode.

[0134] In some implementations, ignoring the first pulse includes configuring a second timer to expire after a second timeout period, and idling one or more circuits in the clock generator circuit when the second timer expires. The second timer can be restarted when a change in the signaling state of the serial bus is detected before the second timer expires.

[0135] In some examples, Manchester-coded data or command bits can be received via the serial bus after determining that the second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC. An error can be determined to have occurred during the transmission or decoding of the Manchester-coded data or command bits, and a third timer can then be configured to expire after a third timeout period. When the third timer expires, the receiving circuitry can put one or more circuits in the clock generator circuitry into an idle state. The third timer can be restarted if a transition in the signaling state of the serial bus is detected before the third timer expires. Manchester-coded data or command bits can be received in datagrams configured according to the Radio Front-End (RFFE) protocol.

[0136] Figure 18 This is an illustration of an example of a hardware implementation of a device 1800 employing processing circuitry 1802. The processing circuitry typically has a controller or processor 1816 that may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 1802 may be implemented using a bus architecture typically represented by bus 1820. Depending on the specific application of processing circuitry 1802 and overall design constraints, bus 1820 may include any number of interconnect buses and bridges. Bus 1820 links together various circuits including controller or processor 1816, modules or circuits 1804, 1806, 1808, and 1810, and processor-readable storage medium 1818. One or more physical layer circuits and / or modules 1814 may be provided to support communication links implemented using multi-wire bus 1812, communication via antennas or antenna arrays 1822 (e.g., to a radio access network), etc. Bus 1820 can also link various other circuits, such as timing sources, peripheral devices, voltage regulators and power management circuits, which are well known in the art and will therefore not be described further.

[0137] Processor 1816 is responsible for general processing, including executing software, code, and / or instructions stored on processor-readable storage medium 1818. Processor-readable storage medium 1818 may include non-transitory storage. When executed by processor 1816, the software causes processing circuitry 1802 to perform various functions described herein and for any particular device. Processor-readable storage medium 1818 may be used to store data manipulated by processor 1816 during software execution. Processing circuitry 1802 also includes at least one of modules 1804, 1806, 1808, and 1810. Modules 1804, 1806, 1808, and 1810 may be software modules that run in processor 1816, reside / store in processor-readable storage medium 1818, one or more hardware modules coupled to processor 1816, or some combination thereof. Modules 1804, 1806, 1808, and 1810 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0138] In one configuration, device 1800 includes a module and / or circuitry 1804 adapted to monitor the activity, inactivity, and control signaling of a single-wire bus. Device 1800 also includes a module and / or circuitry 1806 adapted to generate one or more internal clock signals for decoding signals received via the single-wire bus. Device 1800 further includes a module and / or circuitry 1808 configured to synchronize the internal clock signals with edges in signals received via the single-wire bus. Device 1800 also includes a module and / or circuitry 1810 adapted to capture and decode data from signals received via the single-wire bus.

[0139] In one example, device 1800 includes: a clock generator circuit configured to generate a fundamental clock signal having a fundamental frequency; a synchronization circuit configured to synchronize edges in the fundamental clock signal with edges in a Manchester-encoded data signal received via a serial bus; and a controller. The controller may be configured to: detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of SSC, the first type of SSC indicating a first type of transaction during which the Manchester-encoded data signal is received via the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0140] In some specific implementations, the pulse duration defined for the first type of SSC is longer than the pulse duration defined for the second type of transaction, in which data is received via a serial bus using a bus clock signal that defines the timing of the data signal. The frequency of the basic clock signal can be a multiple of the frequency of the bus clock signal.

[0141] In one example, the signaling consistent with the first type of SSC includes a synchronization mode.

[0142] In some implementations, the controller is configured to ignore the first pulse by configuring the second timer to expire after the second timeout period and by putting one or more circuits in the clock generator circuitry into an idle state when the second timer expires. The controller can also be configured to restart the second timer when a change in the signaling state of the serial bus is detected before the second timer expires.

[0143] In some specific implementations, the controller is also configured to: receive Manchester-encoded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC; determine that an error has occurred during the transmission or decoding of the Manchester-encoded data or command bits; configure a third timer to expire after a third timeout period; and, when the third timer expires, put one or more circuits in the clock generator circuitry into an idle state. The controller may also be configured to: restart the third timer when a change in the signaling state of the serial bus is detected before the third timer expires. The Manchester-encoded data or command bits are received in datagrams configured according to the RFFE protocol.

[0144] The processor-readable storage medium 1818 stores code and data. The code can be executed by the processor 1816, a state machine, or a sequencer. When executed by the processor 1816, the code causes the processing circuit 1802 to: configure an oscillator to generate a basic clock signal with a basic frequency; configure a synchronization circuit to synchronize the edges of the basic clock signal with the edges of Manchester-encoded data signals received via a serial bus; detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of SSC, the first type of SSC indicating a first type of transaction during which the Manchester-encoded data signal is received via the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0145] In some examples, the pulse duration defined for the first type of SSC is longer than the pulse duration defined for the second type of transaction, in which data is received via a serial bus using a bus clock signal that defines the timing of the data signal. The frequency of the basic clock signal is a multiple of the frequency of the bus clock signal. In some cases, signaling consistent with the first type of SSC includes a synchronization mode.

[0146] In some examples, the code also causes the processing circuitry to ignore the first pulse by configuring the second timer to expire after the second timeout period and by putting one or more circuits in the clock generator circuitry into an idle state when the second timer expires. The code can also cause the processing circuitry to restart the second timer when a change in the signaling state of the serial bus is detected before the second timer expires.

[0147] In some examples, the code also instructs the processing circuitry to: receive Manchester-encoded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC; determine that an error has occurred during the transmission or decoding of the Manchester-encoded data or command bits; configure a third timer to expire after a third timeout period; and, when the third timer expires, cause one or more circuits in the clock generator circuitry to enter an idle state. The code may also instruct the processing circuitry to restart the third timer if a transition in the signaling state of the serial bus is detected before the third timer expires. The Manchester-encoded data or command bits can be received in datagrams configured according to the RFFE protocol.

[0148] Some specific implementation examples are described in the following numbered clauses:

[0149] 1. A receiving circuit comprising: a clock generator circuit configured to generate a fundamental clock signal having a fundamental frequency; a synchronization circuit configured to synchronize an edge in the fundamental clock signal with an edge in a Manchester-coded data signal received via a serial bus; and a controller configured to: detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of Sequence Start Condition (SSC), the first type of Sequence Start Condition (SSC) indicating a first type of transaction, during which the Manchester-coded data signal is received via the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0150] 2. The receiving circuit as described in Clause 1, wherein the pulse duration defined for the first type of SSC is greater than the pulse duration defined for the second type of transaction, in which data is received via the serial bus using a bus clock signal that defines the timing of the data signal.

[0151] 3. The receiving circuit as described in Clause 2, wherein the frequency of the basic clock signal is a multiple of the frequency of the bus clock signal.

[0152] 4. The receiving circuit described in any one of clauses 1 to 3, wherein the signaling consistent with the SSC of the first type includes a synchronization mode.

[0153] 5. The receiving circuitry described in any one of Clauses 1 to 4, wherein the controller is configured to ignore the first pulse by: configuring a second timer to expire after a second timeout period; and when the second timer expires, causing one or more circuits in the clock generator circuitry to enter an idle state.

[0154] 6. The receiving circuit as described in Clause 5, wherein the controller is further configured to: restart the second timer when a change in the signaling state of the serial bus is detected before the second timer expires.

[0155] 7. The receiving circuitry described in any one of Clauses 1 to 6, wherein the controller is further configured to: receive Manchester-encoded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC; determine that an error has occurred during the transmission or decoding of the Manchester-encoded data or command bits; configure a third timer to expire after a third timeout period; and, when the third timer expires, cause one or more circuits in the clock generator circuitry to enter an idle state.

[0156] 8. The receiving circuit as described in Clause 7, wherein the controller is further configured to: restart the third timer when a change in the signaling state of the serial bus is detected before the third timer expires.

[0157] 9. The receiving circuitry described in Clause 7 or Clause 8, wherein the Manchester-coded data or command bits are received in a datagram configured according to the Radio Frequency Front End (RFFE) protocol.

[0158] 10. A method of data communication, the method comprising: configuring an oscillator to generate a fundamental clock signal having a fundamental frequency; configuring a synchronization circuit to synchronize an edge in the fundamental clock signal with an edge in a Manchester-coded data signal received via a serial bus; detecting that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition (SSC), the first type of sequence start condition (SSC) indicating a first type of transaction, during which the Manchester-coded data signal is received via the serial bus; configuring a first timer to expire after a first timeout period; and ignoring the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0159] 11. The method described in Clause 10, wherein the pulse duration defined for the first type of SSC is greater than the pulse duration defined for the second type of transaction, in which data is received via the serial bus using a bus clock signal that defines the timing of the data signal.

[0160] 12. The method described in Clause 11, wherein the frequency of the basic clock signal is a multiple of the frequency of the bus clock signal.

[0161] 13. The method described in any one of clauses 10 to 12, wherein the signaling consistent with the SSC of the first type includes a synchronization mode.

[0162] 14. The method described in any one of clauses 10 to 13, wherein ignoring the first pulse comprises: configuring a second timer to expire after a second timeout period; and when the second timer expires, causing one or more circuits in the clock generator circuit to enter an idle state.

[0163] 15. The method described in Clause 14, further comprising: restarting the second timer when a change in the signaling state of the serial bus is detected before the second timer expires.

[0164] 16. The method according to any one of clauses 10 to 15, the method further comprising: receiving Manchester-encoded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC; determining that an error has occurred during the transmission or decoding of the Manchester-encoded data or command bits; configuring a third timer to expire after a third timeout period; and when the third timer expires, causing one or more circuits in the clock generator circuitry to enter an idle state.

[0165] 17. The method described in Clause 16, further comprising: restarting the third timer when a change in the signaling state of the serial bus is detected before the third timer expires.

[0166] 18. The method described in Clause 16 or Clause 17, wherein the Manchester-encoded data

[0167] The command bit is received in a datagram configured according to the Radio Front-End (RFFE) protocol.

[0168] 19. A processor-readable storage medium having code stored thereon, the code, when executed by a processor in processing circuitry, causing the processing circuitry to: configure an oscillator to generate a fundamental clock signal having a fundamental frequency; configure a synchronization circuit to synchronize an edge in the fundamental clock signal with an edge in a Manchester-coded data signal received via a serial bus; detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of Sequence Start Condition (SSC), the first type of Sequence Start Condition (SSC) indicating a first type of transaction, during which the Manchester-coded data signal is received via the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse if no signaling consistent with the first type of SSC is received before the first timer expires.

[0169] 20. A processor-readable storage medium as described in Clause 19, wherein the pulse duration defined for the first type of SSC is greater than the pulse duration defined for the second type of transaction, in which data is received via the serial bus using a bus clock signal that defines the timing of the data signal.

[0170] 21. The processor-readable storage medium as described in Clause 20, wherein the frequency of the basic clock signal is a multiple of the frequency of the bus clock signal.

[0171] 22. A processor-readable storage medium as described in any one of Clauses 19 to 21, wherein the signaling consistent with the SSC of the first type includes a synchronization mode.

[0172] 23. A processor-readable storage medium as described in any one of clauses 19 to 22, wherein the code further causes the processing circuitry to ignore the first pulse by: configuring a second timer to expire after a second timeout period; and when the second timer...

[0173] When the clock expires, it puts one or more circuits in the clock generator circuit into an idle state.

[0174] 24. The processor-readable storage medium as described in Clause 23, wherein the code further causes the processing circuitry to: restart the second timer when a change in the signaling state of the serial bus is detected before the second timer expires.

[0175] 25. A processor-readable storage medium as described in any one of Clauses 19 to 24, wherein the code further causes the processing circuitry to: receive Manchester-encoded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC; determine that an error has occurred during the transmission or decoding of the Manchester-encoded data or command bits; configure a third timer to expire after a third timeout period; and, when the third timer expires, cause one or more circuits in the clock generator circuitry to enter an idle state.

[0176] 26. The processor-readable storage medium as described in Clause 25, wherein the code further enables the processing circuitry to: restart the third timer when a change in the signaling state of the serial bus is detected before the third timer expires.

[0177] 27. A processor-readable storage medium as described in Clause 25 or Clause 26, wherein the Manchester-encoded data or command bits are received in a datagram configured according to the Radio Frequency Front End (RFFE) protocol.

[0178] 28. A data communication apparatus comprising: components for generating a basic clock signal having a basic frequency; components for synchronizing an edge in the basic clock signal with an edge in a Manchester-coded data signal received via a serial bus; and components for determining whether a first pulse received from the serial bus indicates a first type of transaction, during which the Manchester-coded data signal is received via the serial bus, wherein the components for determining whether the first pulse indicates the first type of transaction are configured to determine whether the first pulse has a duration corresponding to a pulse duration defined for a sequence start condition (SSC) of the first type and whether it is followed in transmission by signaling consistent with the SSC of the first type received before a first timeout period expires.

[0179] 29. The data communication apparatus as described in Clause 28, further comprising:

[0180] A component for receiving Manchester-encoded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC, wherein one or more circuits in the clock generator circuitry enter an idle state after a second timeout period when it is determined that an error has occurred during the transmission or decoding of the Manchester-encoded data or command bits.

[0181] 30. The data communication apparatus described in Clause 29, wherein the Manchester-coded data or command bits are received in a datagram configured according to the Radio Frequency Front End (RFFE) protocol.

[0182] It should be understood that the specific order or hierarchy of the steps in the disclosed process is an example of the exemplary method. It should be understood that the specific order or hierarchy of the steps in these processes can be rearranged according to design preferences. Furthermore, some steps can be combined or omitted. The appended method claims present elements of multiple steps in a sample order, but are not intended to limit one to the specific order or hierarchy presented.

[0183] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to limit themselves to the aspects shown herein, but should be given the full scope consistent with the claims, wherein references to elements in the singular form, unless specifically stated otherwise, are not intended to mean “one and only one,” but rather “one or more.” Unless otherwise specifically stated, the term “some” refers to one or more. All structural and functional equivalents of elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is expressly recited in the claims. No claim element should be construed as a component plus a function unless the element is expressly stated using the phrase “component for…”.

Claims

1. A receiving circuit, the receiving circuit comprising: A clock generator circuit configured to generate a fundamental clock signal having a fundamental frequency; A synchronization circuit configured to synchronize the edges of the basic clock signal with the edges of the Manchester-encoded data signal received via a serial bus. and The controller is configured to: The detection of a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition (SSC), the first type of sequence start condition (SSC) indicating a first type of transaction, during which the Manchester-coded data signal is received via the serial bus; Configure the first timer to expire after the first timeout period; as well as If no signaling consistent with the first type of SSC is received before the first timer expires, the first pulse is ignored.

2. The receiving circuit according to claim 1, wherein the pulse duration defined for the first type of SSC is greater than the pulse duration defined for the second type of transaction, in which data is received via the serial bus in the data signal using a bus clock signal that defines the timing of the data signal.

3. The receiving circuit according to claim 2, wherein the frequency of the basic clock signal is a multiple of the frequency of the bus clock signal.

4. The receiving circuit of claim 1, wherein the signaling consistent with the first type of SSC includes a synchronization mode.

5. The receiving circuit of claim 1, wherein the controller is configured to ignore the first pulse in the following manner: Configure the second timer to expire after the second timeout period; and When the second timer expires, one or more circuits in the clock generator circuit are put into an idle state.

6. The receiving circuit according to claim 5, wherein the controller is further configured to: When a change in the signaling state of the serial bus is detected before the second timer expires, the second timer is restarted.

7. The receiving circuit according to claim 1, wherein the controller is further configured to: After determining that the second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC, Manchester-coded data or command bits are received via the serial bus. It was determined that an error had occurred during the transmission or decoding of the Manchester-encoded data or command bits; Configure the third timer to expire after the third timeout period; as well as When the third timer expires, one or more circuits in the clock generator circuit are put into an idle state.

8. The receiving circuit according to claim 7, wherein the controller is further configured to: When a change in the signaling state of the serial bus is detected before the third timer expires, the third timer is restarted.

9. The receiving circuit of claim 7, wherein the Manchester-coded data or command bits are received in a datagram configured according to the Radio Frequency Front End (RFFE) protocol.

10. A method for data communication, the method comprising: Configure the oscillator to generate a basic clock signal with a basic frequency; The synchronization circuit is configured to synchronize the edges of the basic clock signal with the edges of the Manchester-encoded data signal received via the serial bus. The detection of a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition (SSC), the first type of sequence start condition (SSC) indicating a first type of transaction, during which the Manchester-coded data signal is received via the serial bus; Configure the first timer to expire after the first timeout period; as well as If no signaling consistent with the first type of SSC is received before the first timer expires, the first pulse is ignored.

11. The method of claim 10, wherein the pulse duration defined for the first type of SSC is greater than the pulse duration defined for the second type of transaction, in which data is received via the serial bus in the data signal using a bus clock signal that defines the timing of the data signal.

12. The method of claim 11, wherein the frequency of the basic clock signal is a multiple of the frequency of the bus clock signal.

13. The method of claim 10, wherein the signaling consistent with the first type of SSC includes a synchronization mode.

14. The method of claim 10, wherein ignoring the first pulse comprises: Configure the second timer to expire after the second timeout period; as well as When the second timer expires, one or more circuits in the clock generator circuit are put into an idle state.

15. The method according to claim 14, further comprising: When a change in the signaling state of the serial bus is detected before the second timer expires, the second timer is restarted.

16. The method according to claim 10, further comprising: After determining that the second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC, Manchester-coded data or command bits are received via the serial bus. It was determined that an error had occurred during the transmission or decoding of the Manchester-encoded data or command bits; Configure the third timer to expire after the third timeout period; and When the third timer expires, one or more circuits in the clock generator circuit are put into an idle state.

17. The method according to claim 16, further comprising: When a change in the signaling state of the serial bus is detected before the third timer expires, the third timer is restarted.

18. The method of claim 16, wherein the Manchester-coded data or command bits are received in a datagram configured according to the Radio Frequency Front-End (RFFE) protocol.

19. A processor-readable storage medium having code stored thereon, the code causing the processing circuitry, when executed by a processor in processing circuitry, to: Configure the oscillator to generate a basic clock signal with a basic frequency; The synchronization circuit is configured to synchronize the edges of the basic clock signal with the edges of the Manchester-encoded data signal received via the serial bus. The detection of a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition (SSC), the first type of sequence start condition (SSC) indicating a first type of transaction, during which the Manchester-coded data signal is received via the serial bus; Configure the first timer to expire after the first timeout period; as well as If no signaling consistent with the first type of SSC is received before the first timer expires, the first pulse is ignored.

20. The processor-readable storage medium of claim 19, wherein the pulse duration defined for the first type of SSC is greater than the pulse duration defined for the second type of transaction, in which data is received via the serial bus in the data signal using a bus clock signal that defines the timing of the data signal.

21. The processor-readable storage medium of claim 20, wherein the frequency of the basic clock signal is a multiple of the frequency of the bus clock signal.

22. The processor-readable storage medium of claim 19, wherein the signaling consistent with the first type of SSC includes a synchronization mode.

23. The processor-readable storage medium of claim 19, wherein the code further causes the processing circuitry to ignore the first pulse in such a way that: Configure the second timer to expire after the second timeout period; and When the second timer expires, one or more circuits in the clock generator circuit are put into an idle state.

24. The processor-readable storage medium of claim 23, wherein the code further enables the processing circuitry to: When a change in the signaling state of the serial bus is detected before the second timer expires, the second timer is restarted.

25. The processor-readable storage medium of claim 19, wherein the code further enables the processing circuitry to: After determining that the second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC, Manchester-coded data or command bits are received via the serial bus. It was determined that an error had occurred during the transmission or decoding of the Manchester-encoded data or command bits; Configure the third timer to expire after the third timeout period; and When the third timer expires, one or more circuits in the clock generator circuit are put into an idle state.

26. The processor-readable storage medium of claim 25, wherein the code further enables the processing circuitry to: When a change in the signaling state of the serial bus is detected before the third timer expires, the third timer is restarted.

27. The processor-readable storage medium of claim 25, wherein the Manchester-coded data or command bits are received in a datagram configured according to a radio frequency front-end (RFFE) protocol.

28. A data communication device, the data communication device comprising: A component used to generate a basic clock signal with a basic frequency; A component for synchronizing the edges of the basic clock signal with the edges of the Manchester-encoded data signal received via a serial bus. and A component for determining whether a first pulse received from the serial bus indicates a first type of transaction, during which the Manchester-encoded data signal is received via the serial bus, wherein the component for determining whether the first pulse indicates the first type of transaction is configured to determine whether the first pulse has a duration corresponding to a pulse duration defined for a sequence start condition (SSC) of the first type and whether it is followed in transmission by signaling consistent with the SSC of the first type received before the expiration of a first timeout period.

29. The data communication apparatus according to claim 28, further comprising: A component for receiving Manchester-coded data or command bits via the serial bus after determining that a second pulse received from the serial bus has a duration corresponding to the pulse duration defined for the first type of SSC. When it is determined that an error has occurred during the transmission or decoding of the Manchester-encoded data or command bits, one or more circuits in the clock generator circuit enter an idle state after the second timeout period.

30. The data communication apparatus of claim 29, wherein the Manchester-coded data or command bits are received in a datagram configured according to the Radio Frequency Front End (RFFE) protocol.

Images