Asynchronous multi-granularity memory access control method in microprocessor, asynchronous circuit and memory access module

Abstract

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

Description

Technical Field

[0001] This invention belongs to the field of asynchronous processor technology, specifically relating to an asynchronous multi-granularity memory access control method, asynchronous circuit, and memory access module in a microprocessor. Background Technology

[0002] In the field of microprocessor design, asynchronous architectures can alleviate a series of problems caused by global clocks and effectively reduce dynamic power consumption. Each module in an asynchronous processor can operate independently, activating relevant logic only when data arrives or interaction requests occur, thus achieving more flexible timing control and better energy management. At the same time, asynchronous circuits are more stable to changes in process technology, voltage, and temperature, eliminating the need for frequent clock frequency calibration or voltage margin adjustments, making them more suitable for operation in uncertain environments.

[0003] In the design of microprocessors with asynchronous architectures, the design of memory access control is of great significance for improving system performance and stability. On the one hand, since asynchronous processors do not rely on a global clock, the control logic needs to be redefined in multiple dimensions such as path selection, address confirmation, and data synchronization when designing the memory access module. On the other hand, memory access instruction types are becoming more diverse, including access requirements with different data widths (such as Byte / Half / Word / Double) and high-bandwidth data block transmissions, requiring the memory access subsystem to have stronger multi-granularity adaptability.

[0004] However, existing memory access control methods have the following shortcomings: 1. In synchronous processors, memory access scheduling based on period alignment typically relies on a unified clock for stage division and signal latching, resulting in clear design logic and controlled timing. However, in asynchronous systems, the memory access process requires dynamic path selection and data transmission driven by request-response events, making traditional memory access mechanisms unsuitable for asynchronous environments. 2. Limited support for data access granularity. When faced with multi-granularity memory access instructions in asynchronous processors, redundant processing logic or alignment buffers are often required, resulting in low access efficiency and increased resource overhead. 3. They often rely on external auxiliary modules such as caches, bus bridges, or MMUs for coordinated control, resulting in high design complexity and poor adaptability. In asynchronous architectures, the control interfaces of these auxiliary modules usually require redesigning the handshake protocol, further increasing system complexity. Summary of the Invention

[0005] To address the problems existing in the above-mentioned background technology, the purpose of this invention is to provide an asynchronous multi-granularity memory access control method, asynchronous circuit, and memory access module in a microprocessor.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: The asynchronous multi-granularity memory access control method in microprocessors includes the following steps: S1. Use the memory access module to unpack the received data and determine whether memory access is required; organize the data that does not need memory access and send it to the write-back module, then the memory access ends; for the data that needs memory access, determine whether it is a multi-word memory access. If yes, proceed to step S2; otherwise, proceed to step S5. S2. Update the memory access list and check if the memory access list is empty. If it is empty, the memory access ends. If it is not empty, integrate the data before the memory access and check if the access address is aligned. If it is aligned, set the memory access count register to 1; if it is not aligned, set the memory access count register to 2. S3. After the memory access count register is reset, the memory access module interacts with DataRout, increments the memory access counter by 1, and determines whether the memory access counter is less than the memory access count register. If so, it continues to interact with DataRout; otherwise, it executes step S4. S4. Integrate the data after memory access and determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and execute step S2; otherwise, execute step S2 directly. S5. Integrate the data before memory access and determine whether the access address is Icache. If it is, read Icache and update the memory access status. If not, the memory access module interacts with DataRout and updates the memory access status. S6. After the memory access status is updated, determine whether the current memory access status is idle. If yes, proceed to step S7; otherwise, proceed to step S5. S7. After integrating the data from the memory access, determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and the memory access ends. If not, organize the data and send it to the dispatch module, and the memory access ends.

[0007] This invention further provides an asynchronous circuit for implementing an asynchronous multi-granularity memory access control method in a microprocessor. It employs a delay-limited asynchronous circuit, whose control path requires only an asynchronous controller, while the data path is constructed using standard logic gate units. The delay-limited asynchronous circuit includes an asynchronous controller and an asynchronous micropipeline structure based on a "transmit-relay-receive" structure. The asynchronous event structures in the asynchronous micropipeline structure include: Source, Trap, Splitter, Selector, WaitMerge, Wait, ArbMerge, and MutexMerge.

[0008] Furthermore, the asynchronous controller is a Click asynchronous controller.

[0009] Furthermore, the "send-relay-receive" structure includes Sender, Relay, and Receiver, wherein: Sender: Includes a flip-flop, an inverter, and a delay module. When it receives the drive pulse signal i_drive, Sender flips the output level signal. The input pulse signal i_free is delayed by the delay module and outputs as o_free. Relay: Composed of XOR gates, XNOR gates, AND gates, D flip-flops, inverters, and delay modules, it is implemented based on the Click asynchronous controller; Receiver: Includes a trigger that is activated when the next-level pulse signal i_freeNext is received.

[0010] Furthermore, in the asynchronous event structure: The source includes an inverter and a delay unit, which use the phase difference to generate a pulse event signal; The Trap includes a delay unit that outputs the input pulse after a delay. Splitter includes: Contap, AND gate, OR gate, and NOR gate; Selectors include: Sender, Relay, Receiver, AND gate, and NOT gate; WaitMerge includes: Contap, AND gate, OR gate; Wait includes: Contap, AND gate, OR gate; ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter, and flip-flop; cFifo includes Sender, Relay, and Receiver, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage; cPmtFifo includes Sender, Relay with enable mechanism, Receiver, and delay unit, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage when the enable signal is high. MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; The Contap uses a sender that does not generate a free signal. The Contap includes a trigger and an inverter to convert pulse signals into level signals.

[0011] The present invention further provides a memory access module employing the aforementioned asynchronous circuit, including a memory access state management module, a data access update module, an instruction / data cache and peripheral interaction interface, and a data interaction interface with a write-back module; the memory access state management module includes a Load-type memory access control state machine and a Store-type memory access control state machine, which are respectively used to describe the state transition process of Load instructions and Store instructions; the data access update module updates the old data accordingly using combinational logic based on the control state bits output by the memory access state management module; the old data refers to the original data that needs to be processed in the data access update module.

[0012] Furthermore, the instruction / data cache and peripheral device interaction interface includes a Selector and a MutexMerge. The Selector is located at the memory access request issuing end and is used to determine whether the data flows to the instruction / data cache or the peripheral device based on the memory access address. The MutexMerge is located at the return end and is used to receive data and events returned from the instruction / data cache or the peripheral device.

[0013] Furthermore, the data interaction interface with the write-back module includes MutexMerge, which is used to receive data and events sent to the write-back module by non-memory access instructions or memory access instructions.

[0014] Furthermore, the control status bits include memory access type bits, memory access flag bits, and unaligned memory access flag bits.

[0015] Compared with the shortcomings and deficiencies of existing technologies, the present invention has the following beneficial effects: 1. The memory access control method of the present invention adopts asynchronous clockless control, which greatly reduces the invalid power consumption caused by clock flipping in synchronous systems. Especially when the module is idle, it avoids fixed-period clock flipping, thereby achieving lower dynamic power consumption and higher energy efficiency. Furthermore, it completely avoids the complexity and skew problem of global clock distribution, improves the scalability of the system, especially its applicability in large-scale integrated systems such as multi-core processors and system-on-a-chip (SoC), and supports more flexible heterogeneous integration and modular design. 2. This invention adopts a dynamic timing scheduling and on-demand activation mechanism, which can dynamically adjust the start and stop status of the module according to different loads and actual operating conditions, thereby optimizing the power consumption management of the system. Especially in low-activity scenarios, it can significantly reduce unnecessary energy consumption. 3. This invention introduces a multi-granularity memory access control mechanism, supporting memory access operations of different granularities. It can flexibly adjust access paths and caching strategies according to different memory access granularities, reducing redundant operations during access and significantly improving memory access efficiency. Fine-grained control of the memory access process using a finite state machine (FSM) further enhances the stability and efficiency of data access. 4. The asynchronous circuit of this invention reduces the complexity of clock trees and timing control circuits, thus lowering the design complexity. Furthermore, due to the locality and loose coupling characteristics of the asynchronous control mechanism, the overall chip debugging process is more intuitive and easier to handle. Especially in multi-core processor and heterogeneous integration applications, the overall chip design is more flexible and easier to expand and modify. 5. The asynchronous multi-granularity memory access control of the present invention can effectively adapt to complex and diverse data access needs, especially for high-bandwidth multi-word access and efficient data transmission, ensuring the system's high efficiency and low latency under large data volume operations, and significantly improving processor performance. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the delay-limited asynchronous circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the asynchronous event structure in the asynchronous micropipeline structure provided in the embodiments of the present invention; Figure 3 This is a schematic diagram of the memory access module provided in an embodiment of the present invention; Figure 4 This is a flowchart of the asynchronous multi-granularity memory access control method in a microprocessor provided in an embodiment of the present invention; Figure 5 This is the non-multi-word memory access granularity type provided in the embodiments of the present invention; Figure 6 This is a Load-type memory access control state machine provided in the embodiments of the present invention; Figure 7 This is a Store-type memory access control state machine provided in the embodiments of the present invention; Figure 8 This is a flowchart of the multi-word Load type memory access control provided in an embodiment of the present invention; Figure 9 This is a flowchart of the multi-word Store type memory access control provided in the embodiments of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] This invention employs customized asynchronous micropipelining technology to achieve multi-granularity control of the memory access module. After analyzing the design requirements of the microprocessor, this invention ultimately adopts a delay-limited asynchronous circuit as the core design scheme. The delay-limited asynchronous circuit is as follows: Figure 1As shown, a modular design approach is adopted, requiring only asynchronous controllers for the control path, while the data path is constructed using standard logic gate units. When the first-level asynchronous controller receives a request event from the previous level, it immediately generates a control signal (fire) to latch the data from the previous level into a register and pass it to subsequent combinational logic for processing. After ensuring the data is latched, it sends a reply event to the previous level and simultaneously sends a request event to the next-level asynchronous controller to receive the data processed by the combinational logic. The actions taken by the next-level asynchronous controller are consistent with those of the previous level. The delay of request events between asynchronous controllers must strictly match the combinational logic timing of the data path to meet setup time requirements. Structurally, this design is similar to synchronous circuits, but it avoids the power consumption and timing problems caused by global clock distribution, making it more energy-efficient than synchronous circuits of the same size.

[0019] Delay-limited asynchronous circuits consist of two important parts: an asynchronous controller and an asynchronous micropipeline structure based on a "transmit-relay-receive" structure.

[0020] The asynchronous controller uses the Click asynchronous controller, which includes four key signal interfaces: inR (previous stage request), inA (previous stage response), outR (subsequent stage request), and outA (subsequent stage response). Its working principle is as follows: when a change in the level of the inR signal is detected, the Click asynchronous controller generates a pulse (fire). This pulse simultaneously triggers two operations: resetting the previous stage module via the inA signal and starting the subsequent stage module via the outR signal. To ensure reliable data transmission, the controller implements strict interlocking conditions: the next pulse (fire) must simultaneously satisfy a valid outA reset and a change in inR. If a valid outA reset signal is not received, the system will remain in a blocked state, thus avoiding data conflicts.

[0021] The asynchronous micropipeline structure is the core of asynchronous circuits. This invention designs an asynchronous micropipeline structure based on a "transmitter-relay-receiver" structure. By precisely controlling the timing characteristics of the pulse signal, it effectively solves the phase problem that may occur in traditional level-triggered mechanisms. The "transmitter-relay-receiver" structure includes a Sender, a Relay, and a Receiver, wherein: Sender: Includes a flip-flop, an inverter, and a delay module. When it receives the drive pulse signal i_drive, Sender flips the output level signal. The input pulse signal i_free is delayed by the delay module and outputs as o_free. Relay: Composed of XOR gates, XNOR gates, AND gates, D flip-flops, inverters, and delay modules, it is implemented based on the Click asynchronous controller; Receiver: Includes a trigger that is activated when the next-level pulse signal i_freeNext is received.

[0022] By analyzing the data path, the asynchronous event structure in the asynchronous micropipeline structure (refer to...) Figure 2 They are divided into the following categories: The source includes an inverter and a delay unit, which generate pulse event signals using phase differences. It is the starting node of the entire asynchronous process and is responsible for generating the initial trigger event. A trap includes a delay unit that outputs the input pulse after a delay. It serves as the termination point for asynchronous processes, ensuring the complete completion of the event. Splitter includes: Contap, AND gate, OR gate, and NOR gate; Selectors include: Sender, Relay, Receiver, AND gate, and NOT gate; WaitMerge includes: Contap, AND gate, and OR gate; Wait (synchronization) includes: CONTAP, AND gate, OR gate; ArbMerge (arbitration) includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter, and flip-flop; cFifo includes a sender, relay, and receiver, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage; cPmtFifo includes a sender, a relay with an enable mechanism, a receiver, and a delay unit, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage when the enable signal is high. MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; The Contap uses a Sender that does not generate a free signal. The Contap includes a flip-flop and an inverter to convert pulse signals into level signals.

[0023] The memory access module primarily performs data read and write operations through Load and Store instructions. Overall, the memory access module includes a memory access status management module, a data access update module, an instruction / data cache and peripheral interaction interface, and a data interaction interface with the write-back module, such as... Figure 3As shown, the memory access state management module includes a Load-type memory access control state machine and a Store-type memory access control state machine, which are used to describe the state transition process of Load and Store instructions, respectively. The data access update module updates the old data using combinational logic based on the control state bits output by the memory access state management module (such as Load / Store memory access flags i_isLoad_1 / i_isStore_1, memory access type bit i_lsuType_2, and misaligned memory access flag o_misaligned_1). The old data refers to the original data that the data access update module needs to process. The data obtained during the unpacking stage is the unprocessed initial data, but if misaligned memory access occurs, two accesses may be required. Therefore, the data access update module always operates on the currently pending old data (not necessarily the initial data). The instruction / data cache and peripheral device interaction interface includes a Selector and a MutexMerge. The Selector, located at the memory access request initiating end, determines whether data flows to the instruction / data cache or a peripheral device based on the memory access address. The MutexMerge, located at the return end, receives data and events returned from the instruction / data cache or peripheral device. The Selector, instruction / data cache, peripheral device, and MutexMerge constitute the data relay center. The data interaction interface with the write-back module includes the MutexMerge, which receives data and events from non-memory access instructions or memory access instructions destined for the write-back module.

[0024] The asynchronous multi-granularity memory access control method employed in this invention considers almost all types of memory access granularity control, and categorizes memory access granularity into two main categories: multi-word memory access and non-multi-word memory access. The overall memory access control process is as follows: Figure 4 As shown, the specific process is as follows: S1. Use the memory access module to unpack the received data and determine whether memory access is required; organize the data that does not need memory access and send it to the write-back module, then the memory access ends; for the data that needs memory access, determine whether it is a multi-word memory access. If yes, proceed to step S2; otherwise, proceed to step S5. S2. Update the memory access list and check if the memory access list is empty. If it is empty, the memory access ends. If it is not empty, integrate the data before the memory access and check if the access address is aligned. If it is aligned, set the memory access count register to 1; if it is not aligned, set the memory access count register to 2. S3. After the memory access count register is reset, the memory access module interacts with DataRout, increments the memory access counter by 1, and determines whether the memory access counter is less than the memory access count register. If so, it continues to interact with DataRout; otherwise, it executes step S4. S4. Integrate the data after memory access and determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and execute step S2; otherwise, execute step S2 directly. S5. Integrate the data before memory access and determine whether the access address is Icache. If it is, read Icache and update the memory access status. If not, the memory access module interacts with DataRout and updates the memory access status. S6. After the memory access status is updated, determine whether the current memory access status is IDLE. If yes, proceed to step S7; otherwise, proceed to step S5. S7. After integrating the data from the memory access, determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and the memory access ends. If not, organize the data and send it to the dispatch module, and the memory access ends.

[0025] The specific implementation method for non-multi-word memory access control is as follows: Traditional memory access instruction widths include: byte, half-word, single-word, and double-word. After the execution module completes its operation, its execution result, along with memory access-related information, is packaged and passed to the memory access module. This information includes the memory access address, memory access type, and instruction category (Load / Store). The memory access module first determines whether the current instruction is a memory access instruction based on the Load / Store instruction flag. If not, it skips the subsequent memory access processing and directly enters the write-back stage. If it is determined to be a memory access instruction, it further verifies whether the memory access address generated by the execution module is valid. If the address exceeds the predefined memory access address space range, it is considered an illegal access, and the memory access module will generate a memory access address exception and a corresponding exception code. This exception event will be packaged and passed to the interrupt exception handling module for unified management. If the address is valid, the Load or Store instruction operation continues to be executed, specifically handling two parts: status update and data update, depending on the instruction type. The memory access status update mainly deals with address alignment issues and memory access rhythm control under different data access granularities. Because the processor designed in this invention has a maximum memory access width of 64 bits per access, while the instruction cache / data cache is accessed in bytes, address misalignment may occur for instructions other than byte-level accesses, such as half-word, word, and double-word accesses. Figure 5 As shown, taking a 32-bit single-word access (lw / sw) as an example, if the starting address is not aligned, two consecutive memory accesses are required to fully retrieve the target data. The different gray areas represent the lowest byte of the instruction's starting access address, with each square representing one byte. For double-word access instructions (such as ld / sd), word alignment is mandatory, so the cases of misalignment are relatively limited, existing only in a single mode.

[0026] To efficiently handle multi-granularity memory access control and alignment, this invention designs two independent finite state machines for the memory access module: a Load-type memory access control state machine and a Store-type memory access control state machine, which are used to describe the state transition processes of Load and Store instructions, respectively. The Load-type memory access control state machine is as follows: Figure 6 As shown, the Load / Store memory access flags (i_isLoad_1 / i_isStore_1) are used to identify whether the current instruction is a Load or Store instruction. The memory access type flag (i_lsuType_2) is used to identify the memory access type of the current instruction, specifying that i_lsuType_2 as 2'b00, 2'b01, 2'b10, and 2'b11 respectively for byte access, half-word access, double-word access, and single-word access. The misaligned memory access flag (o_misaligned_1) is used to indicate whether the current access address is aligned. The circles represent the various states of the control state machine, namely the idle state (sta...). The state machine transitions through the following states: `store_IDLE`, `reset`, `state_LoadByteEnd`, `state_LoadHwordmisa`, `state_LoadHwordEnd`, `state_LoadDwordmisa`, `state_LoadDwordEnd`, `state_LoadWordmisa`, and `state_LoadWordEnd`. For non-byte access Load instructions, if the address is unaligned, the state machine will transition from the initial state to the corresponding "unaligned processing state" (e.g., `state_LoadWordMisa`). In this state, the memory access module completes the first incomplete data access, then transitions to the "access end state" (e.g., `state_LoadWordEnd`) to continue the second access until the target data is fully acquired. If the address is aligned, the intermediate states are skipped, and the access is completed in one step. The state transition logic of the Store instruction is basically the same as that of the Load instruction, except that the Store instruction does not require a write-back operation, so its state machine structure is slightly different. Figure 7 As shown, the Store-type memory access control state machine adopts a similar strategy for address alignment and data segmentation processing logic. It completes data splitting and reassembly for cross-boundary write operations through state transitions, thereby ensuring the correctness and consistency of memory access operations. This stateful memory access control method not only enhances the memory access module's ability to handle complex memory access behaviors but also effectively supports multi-granularity data access and efficient processing across address boundaries, improving the processor's system performance and reliability.

[0027] The specific implementation method for multi-word memory access control is as follows: Multi-word memory access control is more complex than other memory access controls due to the uncertainty of the data size it accesses. Therefore, this invention handles it separately. Theoretically, this granular memory access can access up to 16 registers simultaneously, meaning a maximum data size of 16*32 bits. Because its state update and data transfer mechanisms differ significantly from the aforementioned memory access instructions, it requires separate logic design in asynchronous microprocessor design.

[0028] Multi-word Load type memory access control process as follows Figure 8 As shown, the execution logic is primarily based on a 16-bit register flag, indicating the set of general-purpose registers that need to be written back. First, a bitwise OR operation is performed on this flag to determine if any registers still exist to be accessed; initially, it is always 1. Next, scanning starts from the least significant bit, identifying the two lowest-valued register numbers as the data targets to be written back in the current cycle. After obtaining the register number, the correct data is retrieved through a data transfer center and updated. This process is consistent with the single-word Load instruction. In special cases such as address misalignment, it may be possible that only one register is written back in a given cycle. After a write-back is completed, the 16-bit register flag is updated synchronously, setting the flag of the completed registers to 0, and the current memory access address is also updated. Since the system reads 64 bits of data each time, the address increments by 8. Then, the next loop begins, continuing to judge and process subsequent register read / write operations until all bits in the 16-bit register flag are 0, indicating that the execution of the current multi-word Load instruction is complete.

[0029] Multi-word Store type memory access control process as follows Figure 9 As shown, the overall execution mechanism is consistent with multi-word load-type memory access control. The difference lies in the data source, which is the General Register File (GRF). Data to be written must be read sequentially based on the state of the flag bits in the 16-bit register flags, and accessed in batches of 64 bits. After data reading, the same data update operation as single-word store is performed, including address alignment checks and access size calculations. Once the specific content and size to be written are determined, the corresponding bits in the 16-bit register flags are modified accordingly, indicating that the register data has been successfully delivered. The remaining operations are consistent with the multi-word load-type memory access control process, including updating the memory address, judging and executing the next loop until the instruction is completely finished.

[0030] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An asynchronous multi-granularity memory access control method in a microprocessor, characterized in that, Includes the following steps: S1. Use the memory access module to unpack the received data and determine whether memory access is required; organize the data that does not need memory access and send it to the write-back module, then the memory access ends; for the data that needs memory access, determine whether it is a multi-word memory access. If yes, proceed to step S2; otherwise, proceed to step S5. S2. Update the memory access list and check if the memory access list is empty. If it is empty, the memory access ends. If it is not empty, integrate the data before the memory access and check if the access address is aligned. If it is aligned, set the memory access count register to 1; if it is not aligned, set the memory access count register to 2. S3. After the memory access count register is reset, the memory access module interacts with DataRout, increments the memory access counter by 1, and determines whether the memory access counter is less than the memory access count register. If so, it continues to interact with DataRout; otherwise, it executes step S4. S4. Integrate the data after memory access and determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and execute step S2; otherwise, execute step S2 directly. S5. Integrate the data before memory access and determine whether the access address is Icache. If it is, read Icache and update the memory access status. If not, the memory access module interacts with DataRout and updates the memory access status. S6. After the memory access status is updated, determine whether the current memory access status is idle. If yes, proceed to step S7; otherwise, proceed to step S5. S7. After integrating the data from the memory access, determine whether it is a load instruction. If so, organize the data and send it to the write-back module, and the memory access ends. If not, organize the data and send it to the dispatch module, and the memory access ends.

2. An asynchronous circuit for implementing the asynchronous multi-granularity memory access control method in a microprocessor as described in claim 1, characterized in that, The asynchronous circuit adopts a delay-limited asynchronous circuit, which includes an asynchronous controller and an asynchronous micropipeline structure based on the "transmit-relay-receive" structure. The asynchronous event structure in the asynchronous micropipeline structure includes: Source, Trap, Splitter, Selector, WaitMerge, Wait, ArbMerge, and MutexMerge.

3. The asynchronous circuit as described in claim 2, characterized in that, The asynchronous controller used is the Click asynchronous controller.

4. The asynchronous circuit as described in claim 2, characterized in that, The "send-relay-receive" structure includes Sender, Relay, and Receiver, where: Sender: Includes a flip-flop, an inverter, and a delay module. When it receives the drive pulse signal i_drive, Sender flips the output level signal. The input pulse signal i_free is delayed by the delay module and outputs as o_free. Relay: Composed of XOR gates, XNOR gates, AND gates, D flip-flops, inverters, and delay modules, it is implemented based on the Click asynchronous controller; Receiver: Includes a trigger that is activated when the next-level pulse signal i_freeNext is received.

5. The asynchronous circuit as described in claim 2, characterized in that, In the asynchronous event structure: The source includes an inverter and a delay unit, which use the phase difference to generate a pulse event signal; The Trap includes a delay unit that outputs the input pulse after a delay. Splitter includes: Contap, AND gate, OR gate, and NOR gate; Selectors include: Sender, Relay, Receiver, AND gate, and NOT gate; WaitMerge includes: Contap, AND gate, OR gate; Wait includes: Contap, AND gate, OR gate; ArbMerge includes: cFifo, cPmtFifo, ConTap, AND gate, OR gate, inverter, and flip-flop; cFifo includes Sender, Relay, and Receiver, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage; cPmtFifo includes Sender, Relay with enable mechanism, Receiver, and delay unit, which receives the input event pulse signal, generates timing control signals, and outputs the event pulse signal of the next stage when the enable signal is high. MutexMerge includes: Contap, AND gate, OR gate, and multiplexer; The Contap uses a sender that does not generate a free signal. The Contap includes a trigger and an inverter to convert pulse signals into level signals.

6. A memory access module, characterized in that, The memory access module employs the asynchronous circuit described in any one of claims 2-5. The memory access module includes a memory access state management module, a data access update module, an instruction / data cache and peripheral interaction interface, and a data interaction interface with the write-back module. The memory access state management module includes a Load-type memory access control state machine and a Store-type memory access control state machine, respectively used to describe the state transition process of Load instructions and Store instructions. The data access update module updates the old data accordingly using combinational logic based on the control state bits output by the memory access state management module. The old data refers to the original data that needs to be processed in the data access update module.

7. The memory access module as described in claim 6, characterized in that, The instruction / data cache and peripheral device interaction interface includes a Selector and a MutexMerge. The Selector is located at the memory access request issuing end and is used to determine whether the data flows to the instruction / data cache or the peripheral device based on the memory access address. The MutexMerge is located at the return end and is used to receive data and events returned from the instruction / data cache or the peripheral device.

8. The memory access module as described in claim 6, characterized in that, The data interaction interface with the write-back module includes MutexMerge, which is used to receive data and events sent to the write-back module by non-memory access instructions or memory access instructions.

9. The memory access module as described in claim 6, characterized in that, The control status bits include memory access type bits, memory access flag bits, and unaligned memory access flag bits.

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