Voltage logic simulation design method and system for passive internet-of-things tag chip

Abstract

The invention relates to the technical field of chip simulation, in particular to a voltage logic simulation design method and system for a passive internet-of-things tag chip. The method comprises the following steps: performing energy characteristic measurement on the tag chip, and calculating voltage fluctuation and logic gate triggering probability to obtain energy logic state mapping data; state transition probability distribution mapping is carried out according to the energy logic state mapping data, and a transition probability distribution tensor is constructed; collecting measurement environment parameters in the energy characteristic measurement process, and performing dynamic environment interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; carrying out simulation precision demand distribution based on the interference compensation distribution tensor, and constructing a layered simulation configuration file; and performing multi-precision parallel simulation execution based on the layered simulation configuration file, and generating a probabilistic verification report. Through precise and efficient logic simulation, the reliability of chip design is improved, and the fault probability is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip simulation technology, and in particular to a voltage logic simulation design method and system for a passive IoT tag chip. Background Technology

[0002] Passive IoT tag chips rely entirely on the energy carried by radio frequency signals during operation, resulting in significant fluctuations and uncertainties in the voltage and current supplied to their internal circuits. This intermittent and unstable energy supply directly impacts the stability and reliability of the chip's internal logic circuits, especially under complex environmental changes or non-ideal energy transmission scenarios, making them more prone to logic errors, functional abnormalities, and even system failures. Therefore, how to deeply model and accurately simulate the logic behavior caused by voltage instability during the chip design phase has become a core challenge in ensuring the functional reliability of passive chips.

[0003] Traditional chip circuit simulation methods are mostly based on the assumption of a fixed power supply voltage, employing gate-level logic models or transistor-level simulation techniques to functionally verify logic behavior. However, these methods fall short when faced with the dynamic energy changes unique to passive chips, failing to effectively reflect key indicators such as changes in logic gate states, timing propagation delays, and failure probabilities caused by voltage fluctuations. Furthermore, most existing simulation tools lack the ability to model the complex nonlinear mapping relationship between energy, voltage, and logic, and cannot predict logic behavior based on the combined influence of multiple environmental factors (such as temperature and electromagnetic interference). Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a voltage logic simulation design method and system for passive IoT tag chips, thereby resolving at least one of the aforementioned technical issues.

[0005] To achieve the above objectives, this invention provides a voltage logic simulation design method for a passive IoT tag chip, comprising the following steps: Step S1: Measure the energy characteristics of the tag chip, calculate the voltage fluctuation and logic gate trigger probability, and obtain energy logic state mapping data; Step S2: Map the state transition probability distribution based on the energy logic state mapping data and construct the transition probability distribution tensor; Step S3: Collect measurement environment parameters during the energy characteristic measurement process, and perform dynamic environmental interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; Step S4: Allocate simulation accuracy requirements based on the interference compensation distribution tensor and construct a hierarchical simulation configuration file; Step S5: Perform multi-precision parallel simulation based on the hierarchical simulation configuration file and generate a probabilistic verification report.

[0006] This specification provides a voltage logic simulation design system for a passive IoT tag chip, used to execute the voltage logic simulation design method for a passive IoT tag chip as described above, including: The characteristic measurement module is used to measure the energy characteristics of the tag chip, calculate voltage fluctuations and logic gate trigger probabilities, and obtain energy logic state mapping data. The probability distribution module is used to perform state transition probability distribution mapping based on energy logic state mapping data and construct a transition probability distribution tensor. The interference compensation module is used to collect measurement environment parameters during the energy characteristic measurement process and perform dynamic environmental interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor. The requirement allocation module is used to allocate simulation accuracy requirements based on the interference compensation distribution tensor and to build a hierarchical simulation configuration file. The parallel simulation module is used to perform multi-precision parallel simulations based on hierarchical simulation configuration files and generate probabilistic verification reports.

[0007] The specific benefits of this invention are as follows: By dynamically measuring the energy acquisition process of passive IoT tag chips under actual radio frequency power supply conditions, not only can the voltage fluctuation trend at different times be captured, but the triggering probability of logic gates at different voltage levels can also be statistically analyzed through experimental data to establish a nonlinear mapping relationship between voltage and logic behavior. This mapping data is unavailable in traditional simulation methods based on fixed voltage sources, thus significantly improving the fit of subsequent simulations to real power supply scenarios. This step provides energy-driven logic foundation data for the entire logic simulation design and is the core data source supporting dynamic simulation. By constructing a three-dimensional or four-dimensional tensor (node ​​× time × state × energy), this step can dynamically express the evolution path and transition probability of the logic state of the logic unit during energy fluctuations. This transition tensor greatly improves the ability to express the uncertainty of logic states, supports global modeling of multi-cycle logic propagation paths, helps identify fluctuation-sensitive nodes on critical paths, and provides decision support for subsequent precision scheduling and anomaly prediction.

[0008] By collecting environmental parameters during the measurement process and correcting the state transition tensor, an environment-aware logic behavior tensor is constructed. This dynamic compensation mechanism enables the simulation model to be environmentally adaptable, maintaining predictive accuracy under different deployment scenarios, thus significantly enhancing the simulation's versatility and robustness. The environmental disturbance compensation introduced in this step effectively improves the accuracy of logic reliability assessment in harsh environments. Considering the probability of logic state changes and environmental sensitivity, the simulation accuracy requirements for different nodes and time windows are quantitatively evaluated, and appropriate simulation levels (such as functional level, gate level, transistor level, etc.) are allocated. This constructs an adaptive hierarchical simulation configuration file, enabling on-demand resource allocation. This not only significantly improves the computational efficiency of the simulation, avoiding excessive waste of computational resources at non-critical nodes, but also ensures the simulation accuracy of critical paths or highly volatile sensitive areas, providing technical support for achieving efficient and high-fidelity voltage logic simulation.

[0009] Multi-precision parallel simulation of passive tag chips ensures both logical accuracy and computational efficiency. By scheduling and executing tasks of varying simulation precision using a parallel computing platform, the logical response of each node under complex energy fluctuations is quickly obtained, and a probabilistic verification report is output, including key indicators such as the probability of logical correctness, failure probability, and response delay distribution. Compared to traditional simulation methods that only output deterministic results, this step significantly enhances the depth of evaluation of system reliability, robustness, and extreme condition response capabilities, effectively supporting design optimization and the establishment of safety and fault-tolerant mechanisms. Attached Figure Description

[0010] Figure 1 This is a flowchart illustrating the steps of a voltage logic simulation design method for a passive IoT tag chip according to the present invention. Figure 2 This is a detailed flowchart illustrating the implementation steps of step S1. Figure 3 This is a detailed flowchart illustrating the implementation steps of step S2; Figure 4 This is a flowchart illustrating the detailed implementation steps of step S3. Detailed Implementation

[0011] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0012] This application provides a voltage logic simulation design method and system for a passive IoT tag chip. The execution entities of the voltage logic simulation design method and system for the passive IoT tag chip include, but are not limited to, mechanical equipment, data processing platforms, cloud server nodes, network upload devices, etc., which can be considered as general computing nodes in this application. The data processing platform includes, but is not limited to, at least one of an audio / image management system, an information management system, and a cloud data management system.

[0013] Please see Figures 1 to 4 This invention provides a voltage logic simulation design method for passive IoT tag chips, including the following steps: Step S1: Measure the energy characteristics of the tag chip, calculate the voltage fluctuation and logic gate trigger probability, and obtain energy logic state mapping data; Step S2: Map the state transition probability distribution based on the energy logic state mapping data and construct the transition probability distribution tensor; Step S3: Collect measurement environment parameters during the energy characteristic measurement process, and perform dynamic environmental interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; Step S4: Allocate simulation accuracy requirements based on the interference compensation distribution tensor and construct a hierarchical simulation configuration file; Step S5: Perform multi-precision parallel simulation based on the hierarchical simulation configuration file and generate a probabilistic verification report.

[0014] In the embodiments of the present invention, see Figure 1 This is a flowchart illustrating the steps of a voltage logic simulation design method for a passive IoT tag chip according to the present invention. In this example, the steps of the voltage logic simulation design method for the passive IoT tag chip include: Step S1: Measure the energy characteristics of the tag chip, calculate the voltage fluctuation and logic gate trigger probability, and obtain energy logic state mapping data; In this embodiment, a comprehensive energy characteristic measurement and analysis of the passive IoT tag chip is performed. A radio frequency energy harvesting test platform is built in a laboratory environment, with a vector network analyzer and a spectrum analyzer configured as the main measurement equipment. A systematic variation test is conducted on the radio frequency power density, starting from a minimum of 0.1 mW / cm², increasing in increments of 0.5 mW / cm² up to a maximum of 10 mW / cm², for a total of 20 measurement points at different power levels. Voltage and current waveform data are continuously collected for 30 seconds at each power point. Detailed measurement and calculation of the energy harvesting characteristics under different spatial conditions are performed. The distance between the reader and the tag chip is set from 0.5 meters, increasing by 0.25 meters, with a maximum measurement distance of 5 meters, for a total of 19 measurement positions at different distances. Instantaneous voltage and current values ​​at the chip's output are collected at each position. The collected voltage waveform data undergoes fluctuation amplitude analysis. The mean, standard deviation, and coefficient of variation of the voltage are calculated using statistical analysis methods. It is found that the voltage fluctuation range is within 0... The voltage ranges from 0.8 volts to 1.8 volts, with a standard deviation between 0.12 volts and 0.31 volts and a coefficient of variation fluctuating between 0.15 and 0.35. Trigger characteristics tests were performed on four basic logic gates: AND, OR, NOT, and XOR. Different voltage levels were supplied to each logic gate using a precision power supply and signal generator, and the success probability of their output response was measured. The success rate of the AND gate at 1.2 volts was 95%, the OR gate at 1.0 volts was 92%, the NOT gate at 0.9 volts was 98%, and the XOR gate at 1.3 volts was 89%. A mapping database between energy levels and logic gate responses was established. This database uses a two-dimensional table structure, with rows representing different energy level levels and columns representing different types of logic gates. Each data unit records the trigger probability and response delay time of the corresponding logic gate at that energy level. The response delay time varies between 2 nanoseconds and 25 nanoseconds, ultimately forming a complete energy logic state mapping data structure.

[0015] Step S2: Map the state transition probability distribution based on the energy logic state mapping data and construct the transition probability distribution tensor; In this embodiment, the dynamic state transition process is modeled and analyzed based on the energy logic state mapping data, transforming the static energy logic relationship into a dynamic transition process that considers time variations. Markov state transition modeling is performed on the logic gate trigger probabilities in the mapping data, defining three basic logic states: high-level state, low-level state, and uncertain state. The mutual transition rules between these three states are analyzed. The transition probability from high level to low level is determined based on energy decay characteristics, with a value ranging from 0.05 to 0.25. The transition probability from low level to high level is calculated based on the energy replenishment rate, with typical values ​​between 0.08 and 0.32. The state transition process is then subjected to time discretization analysis, dividing the continuous time process into discrete time points with 1-microsecond intervals. The probability of various state transitions is calculated within each time interval. Considering the response characteristics of the passive tag chip, the total simulation time window is set to 1 millisecond, corresponding to 1000... Discrete time step; a three-dimensional tensor structure is modeled for the discretized state transition data. The first dimension of the tensor represents the time step, with a total of 1000 time points. The second dimension represents the logic node number inside the chip, with a total of 64 logic processing units. The third dimension represents the logic state type, including high level, low level, and uncertain states. Probability normalization is performed on each element in the tensor to ensure that the sum of the three state probabilities of each logic node at each time point equals 1. At the same time, a state duration parameter is introduced to describe the length of time that a certain state remains unchanged. The typical value of this parameter varies between 2 microseconds and 15 microseconds. Noise filtering is performed on the tensor through a data smoothing algorithm. A combination of moving average and Gaussian filtering is used to eliminate the influence of random noise during the measurement process on the calculation of state transition probabilities. Finally, a complete transition probability distribution tensor data structure is constructed, which accurately describes the state transition rules of each logic unit inside the chip at different times.

[0016] Step S3: Collect measurement environment parameters during the energy characteristic measurement process, and perform dynamic environmental interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; In this embodiment, detailed environmental parameter data were collected during the energy characteristic measurement process. Systematic changes in environmental parameters were tested in a constant temperature and humidity laboratory. The ambient temperature was set starting from -20 degrees Celsius, with a measurement point set every 5 degrees Celsius, reaching a maximum of +70 degrees Celsius, for a total of 19 different temperature measurement points. Data acquisition began after each temperature point had stabilized for 30 minutes. A systematic measurement and analysis of relative humidity parameters was also performed. The humidity setting range started from 20%, with a measurement point set every 10%, reaching a maximum of 90%, for a total of 8 different humidity levels. A precision humidity sensor monitors humidity changes in real time, ensuring measurement accuracy within ±1%. Electromagnetic interference (EMI) is analyzed using a broadband spectrum analyzer, scanning background EMI in the 900 MHz to 2.4 GHz band, measuring the power spectral density distribution, and recording the interference intensity at each frequency point, ranging from -80 dB / mW to -40 dB / mW. Regression analysis is performed to analyze the correlation between environmental parameters and voltage fluctuations, deriving environmental impact coefficients through fitting extensive experimental data. The coefficient for temperature's influence on voltage is -0.012 volts per second. The influence coefficients for temperature and humidity were found to be -0.008 volts per percentage of relative humidity, and the influence coefficient for electromagnetic interference was -0.15 volts per milliwatt per square meter. A cross-influence effect between temperature and humidity was also observed, with a cross-influence coefficient of +0.0003 volts per degree Celsius per percentage of relative humidity. Dynamic compensation calculations were performed on the transition probability distribution tensor based on the environmental influence coefficients. The voltage changes caused by environmental factors were applied as correction coefficients to each data element of the tensor. A standard operating voltage of 1.2 volts was used as a reference during the compensation process. Numerical boundary checks were performed on the compensation calculation results to ensure... The compensated probability values ​​are kept within the effective range of 0 to 1. When the compensation result exceeds the normal boundary, a truncation function is used to limit it to prevent invalid probability values. An environmentally adaptive weighting factor is introduced to adjust the compensation intensity. This factor is dynamically adjusted according to the degree to which the current environmental conditions deviate from the standard experimental conditions. The weighting factor value varies between 0.3 and 1.0. The closer the environmental conditions are to the standard conditions, the closer the weighting factor is to 1. Finally, a distribution tensor data structure dynamically compensated for environmental interference is generated. This tensor can accurately reflect the true transition probability distribution of the chip logic state under different environmental conditions.

[0017] Step S4: Allocate simulation accuracy requirements based on the interference compensation distribution tensor and construct a hierarchical simulation configuration file; In this embodiment, a quantitative assessment and analysis of simulation accuracy requirements is performed based on the interference compensation distribution tensor. The simulation accuracy requirement level is determined by calculating the state uncertainty of each logic node. The uncertainty index reflects the difficulty of predicting the node's state, with a value ranging from 0 to 1.58, where 0 indicates a completely predictable state and 1.58 indicates a completely random and unpredictable state. The uncertainty assessment results are then categorized by accuracy level, establishing a three-level accuracy allocation system. Logic nodes with uncertainties greater than 1.2 are classified as high-precision simulation requirement nodes, requiring SPICE-level transistor-level simulation methods with a simulation time step of 0.1 nanoseconds and voltage accuracy at the millivolt level. Logic nodes with uncertainties between 0.6 and 1.2 are classified as medium-precision simulation requirement nodes, using gate-level HDL hardware description language simulation methods with a simulation time step of 1 nanosecond and voltage accuracy at the 10 millivolt level. Logic nodes with uncertainties less than or equal to 0.6 are classified as low-precision simulation requirement nodes, using function-level behavioral modeling simulation methods. The simulation time step is set to 10 nanoseconds, and the voltage accuracy is at the 100 millivolt level. A detailed evaluation and analysis of the computational resource requirements for different accuracy levels is conducted. High-precision SPICE simulation requires 50 milliseconds of CPU time and 128 megabytes of memory per node; medium-precision HDL simulation requires 5 milliseconds of CPU time and 16 megabytes of memory per node; and low-precision behavioral simulation requires 0.5 milliseconds of CPU time and 2 megabytes of memory per node. A load balancing optimization algorithm is used to rationally allocate simulation tasks. Considering the overall system computing power limitations, the overall simulation time is ensured to be controlled within 60 seconds, and the total memory usage does not exceed 80% of the system's available 8 gigabytes of memory, i.e., 6.4 gigabytes. A detailed data structure for the hierarchical simulation configuration file is established. This configuration file records the accuracy level identifier, corresponding simulation engine type, specific time step parameter settings, voltage accuracy threshold requirements, allocated computational resource quota, and task execution priority for each logical node, forming a complete multi-level accuracy simulation execution configuration scheme.

[0018] Step S5: Perform multi-precision parallel simulation based on the hierarchical simulation configuration file and generate a probabilistic verification report.

[0019] In this embodiment, multi-precision parallel simulation is coordinated and executed based on the hierarchical simulation configuration file. The 64 logic nodes within the chip are grouped and managed according to precision requirements. The high-precision simulation group contains 15 critical logic nodes, the medium-precision simulation group contains 28 generally important nodes, and the low-precision simulation group contains 21 minor logic nodes. These three simulation groups execute in parallel within independent computation processes. Time synchronization is performed on each simulation process, employing a master-slave synchronization mechanism to ensure consistent timing across different precision levels. Data exchange and state synchronization are achieved through an inter-process communication interface, with the data exchange interval set to once every 100 simulation steps to avoid frequent communication affecting simulation efficiency. The entire simulation execution process is monitored and performance data is collected, recording key performance parameters such as the number of state transitions, the frequency of logic errors, and the signal response delay time distribution for each logic node in real time. The observed state transition frequency varies between 0.2 MHz and 2.5 MHz, the soft error rate is between 10⁻⁶ and 10⁻⁴ times per hour, and the hard error rate is [missing data]. The simulation results are analyzed and processed using a comprehensive statistical method to calculate key reliability indicators at the system level, including mean time between failures (MTBF), which varies between 2000 and 50000 hours, and overall system availability, which ranges from 99.5% to 99.99% considering a mean time to repair (MTBF) of 2 hours. The Monte Carlo method is used to assess the confidence level of the simulation results, setting a 95% confidence level. Each performance indicator is randomly sampled 1000 times to calculate the upper and lower bounds of the confidence interval, ensuring the statistical reliability of the results. A detailed probabilistic verification report data structure is constructed, containing quantitative assessment results of overall system reliability, detailed performance analysis data for each functional module, statistical distribution of different types of failure modes, confidence intervals for all key performance indicators, evaluation results of simulation execution efficiency, and targeted design improvement suggestions. This forms a complete chip voltage logic simulation verification report document, providing scientific data support and decision-making basis for chip design optimization and reliability improvement.

[0020] In this embodiment, see Figure 2 The diagram below illustrates the detailed implementation steps of step S1. In this embodiment, the detailed implementation steps of step S1 include: Energy characteristics of passive IoT tag chips were measured under different radio frequency power densities and distances, and real-time voltage data of the chips were collected. Calculate the transient voltage values ​​of the chip's real-time voltage data at different power densities; The transient voltage value is fitted with a time-series voltage variation to obtain a voltage time-domain waveform curve; Multi-scale power spectral density calculations are performed on the voltage time-domain waveform curves to generate multi-scale power spectral density features; The trigger probability of logic gates and the trigger response delay parameters under different energy densities are calculated based on the multi-scale power spectral density characteristics to obtain energy logic state mapping data.

[0021] In this embodiment, the received energy state is characterized by measuring the real-time voltage waveform at the chip's input terminal (typically the rectifier circuit output). First, a measurement system is built, comprising an RF source, an adjustable antenna, and a tag chip. The RF source's operating frequency is set to match the tag's operating frequency band (e.g., 915 MHz), and the power output range is set to -20 dBm to +10 dBm in 2 dBm increments to simulate fluctuations in antenna transmit power in a real-world environment. The distance between the antenna and the chip is gradually increased from 10 cm to 1.5 m, with 20 cm intervals, to simulate spatial energy attenuation in different deployment environments. The chip's voltage is sampled using an external high-bandwidth (e.g., 1 GHz) oscilloscope, with a sampling rate recommended to be above 10 MS / s to capture voltage response dynamics within microseconds. A voltage probe is connected between the chip's rectified output and the load, and data acquisition is performed with the chip unconnected to an external power supply, relying solely on the RF power input. To reduce antenna directivity or reflection interference, electromagnetic shielding is required in the laboratory environment, and the RF source and antenna are mounted on non-conductive supports to ensure measurement accuracy. Measurements under each power density and distance condition should last 5 ms and be recorded for multiple cycles (e.g., 20 cycles) for subsequent time-domain and frequency-domain feature analysis. After acquisition, the voltage data is archived and stored according to condition labels, ready for subsequent calculations. The time-series voltage data under different power densities are analyzed to extract the "transient voltage" characteristics representing the chip's stimulated response process. Transient voltage refers to the voltage rise behavior exhibited by the chip during the transition from a powerless state to a steady-state voltage after receiving RF energy excitation. To accurately capture this process, the raw voltage data is first denoised, often using an FIR filter or Savitzky-Golay smoothing algorithm to preserve the main waveform structure while removing high-frequency interference. Subsequently, the start-up interval within each cycle is extracted using a threshold judgment method (e.g., the rising edge is defined as a voltage jump from 0.1 V to 0.9 V), and the peak voltage, voltage settling time (10% to 90% of the rise time), and maximum voltage swing are statistically analyzed for each start-up process. Furthermore, the standard deviation and mean of this process are calculated from multiple sampling data sets to assess the stability and reproducibility of the energy response. This process is repeated for test data at all power densities, ultimately constructing a database of transient voltage characteristics corresponding to various power conditions. This database will serve as a crucial input for subsequent voltage fitting and logic gate driver modeling, and is also a core metric for evaluating the performance boundaries of passive chips in low power density environments.

[0022] Because the voltage rise curves of a chip may exhibit different characteristics under different power density conditions (such as smooth rise, delayed start-up, or oscillation), an appropriate mathematical model must be selected to cover various response behaviors during fitting. For cases with long start-up delays or slow build-up processes, third- or fifth-order polynomial functions, piecewise linear functions, or even wavelet basis functions can be used for fitting. The fitting algorithm is based on the least squares method, combined with a goodness-of-fit index for model selection and optimization, requiring the fitting error between the final time-domain model and the actual sampled data to be within 5%. During the fitting process, the influence of noise on the curve must also be considered; therefore, moving average or baseline correction methods are often used in the data processing stage to improve the stability of the fitting. The fitting results are saved in a standard data structure format, including function expression parameters, effective time intervals, and fitting error statistics, for direct use by the subsequent logic gate simulation module. By converting discrete voltage samples into continuous waveform functions, this step not only achieves modeling of the chip's energy dynamics but also provides a controllable and adjustable voltage input template for digital logic triggering modeling.

[0023] A multi-scale power spectral density (PSD) calculation method is employed to decompose the voltage waveform into different frequency components, constructing a frequency domain feature model reflecting the chip's power supply stability and energy aggregation efficiency. First, a Fast Fourier Transform (FFT) is applied to convert the time-domain voltage signal into a spectral signal, obtaining a preliminary frequency domain energy distribution map. This spectrum shows the voltage energy density at different frequencies, revealing the dominant frequency components in the system response. To further characterize the energy changes of the voltage waveform at different time scales, wavelet transforms (such as Continuous Wavelet Transform (CWT) or Discrete Wavelet Transform (DWT)) are used to decompose the voltage signal into multiple scale levels (typically 6–8), each scale corresponding to a frequency range. Morlet or Daubechies wavelets are used as the mother wavelet function to ensure good resolution in both the time and frequency domains. The energy spectrum extracted at each scale constitutes a multi-scale PSD feature vector, used to describe the chip's time-frequency energy behavior under power supply conditions. These features not only reveal the abrupt changes and stability trends during energy input but also provide time-frequency correlation indicators for subsequent logic gate trigger probability evaluation, particularly suitable for analyzing the chip's behavioral stability and reliability under edge power supply conditions.

[0024] By establishing a correlation between the frequency domain characteristics of voltage and the functional behavior of logic gates, the trigger probability and response delay of logic gates under different energy supply conditions are quantified, thus forming a complete "energy-logic state mapping relationship". First, based on the input voltage requirements of CMOS logic gates (e.g., an inverter threshold of 0.5 V), the minimum voltage amplitude and setup time requirements for stable switching of the logic gate are set (e.g., a stable output delay of less than 1 µs). Next, based on multi-scale PSD characteristics, a perturbation simulation system is constructed. Multiple voltage input curves with typical noise characteristics are synthesized by inversely combining frequency domain parameters (i.e., superimposing perturbation signals conforming to the PSD distribution onto the time-domain waveform). These voltage curves are used to perform multiple simulations of the CMOS logic gate (e.g., running 100 times for each set of parameters), and the number of times the logic gate successfully flips and outputs a stable level is counted, thereby estimating the logic gate trigger probability under the corresponding power density. Simultaneously, the time required for each successful trigger is recorded as a response delay indicator. By modeling this process for all power density and distance combinations, a complete "input energy condition-logic response characteristic" mapping database can be established. This data can not only provide quantitative evaluation basis for chip design, but also provide reliable parameter support for system-level energy scheduling strategy design, especially suitable for application scenarios such as energy harvesting systems, event-driven logic control, and low-power intelligent edge computing.

[0025] In this embodiment, see Figure 3 The diagram below illustrates the detailed implementation steps of step S2. In this embodiment, the detailed implementation steps of step S2 include: Identify the internal logic module of a passive IoT tag chip; Based on the energy logic state mapping data, perform logic gate cascade path analysis to extract voltage connection logic; Based on the voltage connection logic, the internal logic modules are analyzed to perform inter-module connection logic parsing, and the inter-module connection relationships and signal propagation paths are extracted. Based on the connection relationships between modules and the signal propagation path, a directed graph model of the propagation path is constructed to build a node-edge adjacency graph; Based on the logic gate triggering probability, a state transition probability distribution is mapped to the node-edge adjacency graph to construct a transition probability distribution tensor.

[0026] In this embodiment, the internal digital logic components of the passive IoT tag chip are identified and functionally divided at the structural level, providing basic module information for subsequent path modeling and logic state derivation. Since passive chips are often implemented based on ultra-low-power CMOS architecture, their logic section typically includes functional modules such as state machine control units, modulation controllers, demodulation decoders, clock recovery circuits, memory units (e.g., EEPROM interface controllers), and power management logic. The identification process relies on layout analysis and reverse engineering techniques, combined with design documents (if available) for structural reconstruction. First, high-resolution chip surface images combined with focused ion beam (FIB) or scanning electron microscopy (SEM) techniques are used to analyze the chip layer by layer, identifying standard cell layouts and metal wiring connections. Then, circuit identification tools (such as GDS resolvers or Layout2Net) are used to convert the identified physical units into a logic module netlist, thereby recovering the chip's digital circuit structure. At the logic level, by determining the function and connection relationships of logic gates, the gate-level circuits are divided into several functional modules, and the master-slave control or synchronous / asynchronous relationships between modules are further identified according to their timing attributes. The key outcome of this step is the creation of a list of logic modules with clearly defined boundaries and functions, labeling their input / output ports, voltage requirements, and triggering behaviors. This lays the structural foundation for subsequent energy logic modeling and simulation to construct the module map. Based on the previously established energy logic state mapping data, the trigger probability and response delay of each logic gate under different voltage conditions are obtained. Combined with the connection relationships of the gate circuits, the signal driving capability between adjacent gates under different energy conditions is determined. This process requires traversing the chip's gate-level netlist structure, starting from each logic gate, searching along its output port to find the input terminal of the driven gate, identifying gate cascade paths (e.g., inverter → AND gate → latch). To ensure the accuracy of the analysis, each path needs to be labeled to indicate whether the current input voltage is sufficient to drive the next level logic gate to a valid state transition. The judgment is based on the trigger probability threshold (e.g., >90% is considered validly driveable). Here, a gate-level energy sensing matrix can be introduced to map the energy requirements (e.g., minimum voltage threshold), input waveform characteristics, and output response of each level of gate, forming a "voltage-connected logic" from energy input to logic gate cascade. In experiments, various typical energy input conditions are typically selected, and multiple rounds of gate-level path traversal are performed on the circuit to record which paths can achieve complete signal transmission under specific power densities. The analysis results will be used to derive the chip's functional coverage and critical path identification under low-power excitation, which is a core component in constructing an efficient energy logic simulation model.

[0027] By analyzing the module identifiers of different logic gates and their positions in the gate-level paths, the module-level connection logic can be gradually reconstructed. First, all gate-level paths are categorized by logic module labels, and the gate connections between different modules are aggregated to extract the communication boundaries between modules. For example, the output of a state machine module drives the input of an EEPROM control module. This process requires constructing a signal transmission graph between modules. Each edge represents a signal path from the output of one module through a certain gate-level combinational logic to the next module, along with the required energy conditions (e.g., a path requires a power supply of >0.8 V and a delay of less than 1 µs to transmit). Simultaneously, state modeling is performed on the input and output terminals of each module, recording the number of gate-level paths for its external signal transmission and the voltage type it depends on (e.g., pulse-type, steady-state type) to evaluate the timing characteristics and power sensitivity of the module response. In experiments, dozens of typical signal paths can be constructed, and their availability under different power densities can be recorded, further forming an "energy-driven signal transmission mapping table." This analytical result can reveal which modules are in a communicable state and which modules are energy disconnected under power boundary conditions, thereby predicting system-level functional degradation modes. This has practical engineering significance for the steady-state function simulation and energy-saving path optimization of passive chips. Using modules as graph nodes and voltage-driven logic paths between modules as graph edges, a "node-edge adjacency graph" describing the energy-driven signal propagation mechanism within the chip is constructed. Each node represents a logical function module, such as a modulation controller, state machine, or encoding module; each directed edge represents the energy state path upon which the signal propagates from one module to another. The attributes of the edges in the graph include not only the signal propagation direction but also specific energy-driven conditions (such as edge weight representing the minimum trigger voltage) and delay information (such as propagation time and gate level). During the graph construction process, to improve the accuracy and scalability of the graph model, a layered graph construction method is adopted. The first layer describes the voltage threshold conditions, and the second layer describes the signal timing dependencies. This graph structure can be stored in the form of a graph database or adjacency matrix, and supports multi-state queries and path tracing. In the experimental stage, the graph model can be pruned for different energy input conditions, i.e., edges that cannot be effectively triggered under the current energy state are removed, thereby generating an effective propagation subgraph under the current power state. The resulting propagation graph not only provides a data input template for the simulation system, but also serves as the basis for formal verification tools (such as model checking), and is a key step in constructing a graphical representation of the chip's energy logic behavior.

[0028] By combining the previously established logic propagation graph structure with the gate-level triggering probability model, a probability transition graph that evolves with changes in energy state is constructed to simulate the evolution path of the logic behavior of passive chips under different energy conditions. Specifically, each directed edge between graph nodes is assigned a probability weight, derived from the previously calculated logic gate triggering probabilities (e.g., an 85% weight for the edge from module A to module B indicates that, under the current energy density, there is an 85% probability that the signal can stably propagate from A to B). Furthermore, the transition probabilities under each energy input condition are mapped to a three-dimensional tensor structure: dimension one represents the graph nodes, dimension two represents the graph edges, and dimension three represents the power density or voltage state variables. This probability tensor can be used for Markov chain simulations or Monte Carlo path prediction to analyze the degradation modes and critical path survival rates of chip logic functions under energy fluctuations or interruptions. For example, under a certain voltage condition, if the probability of the state machine module successfully driving the output decreases to 40%, the triggering probability of the EEPROM module will decrease synchronously. This model allows for the construction of a complete "energy-propagation probability" dynamic graph structure, which can be used to predict the functional fidelity, response delay distribution, and system robustness of a chip under various power supply fluctuation conditions in simulations.

[0029] In this embodiment, reference Figure 4 The diagram below illustrates the detailed implementation steps of step S3. In this embodiment, the detailed implementation steps of step S3 include: During the energy characteristic measurement process, environmental parameters are collected simultaneously, including temperature, relative humidity, and electromagnetic interference signals. Calculate the measurement interference intensity of the measured environmental parameters; Based on the measured interference intensity, a cross-analysis of environmental interference factors is performed to generate a nonlinear mapping relationship between interference factors and voltage fluctuations. A neural network was trained on the nonlinear mapping relationship between interference factors and voltage fluctuations to obtain multidimensional environmental correction coefficients; Dynamic environmental disturbance compensation is performed on the transition probability distribution tensor based on the multidimensional environmental correction coefficient, generating the disturbance compensation distribution tensor.

[0030] In this embodiment, an integrated environmental monitoring system is constructed, deploying a high-precision temperature sensor (e.g., ±0.1°C resolution), a relative humidity sensor (typical range 0–100%RH, accuracy ±2%RH), and an electromagnetic interference (EMI) detection probe on a chip measurement platform. EMI signals are acquired using a broadband EMI sensor or spectrum analyzer, with the sampling frequency band set between 300 kHz and 3 GHz to cover common radio frequency interference sources. While sampling voltage, environmental parameters are synchronously recorded using a unified time base, with a sampling period of 1 ms recommended to ensure alignment between instantaneous environmental changes and voltage fluctuations. During the experiment, multiple rounds of data acquisition are performed by manually controlling environmental parameters (e.g., using a temperature and humidity chamber to change temperature and humidity conditions, or injecting noise in a specific frequency band using an interference source) to ensure the data has a certain degree of perturbation. Finally, the acquisition results are stored in the form of a multi-channel synchronous time series, providing complete input information for subsequent analysis of external causes of voltage fluctuations. Temperature and humidity data are normalized and standardized to quantify the magnitude of variation caused by deviations from standard test conditions (e.g., 25 degrees Celsius, 50% relative humidity). By comparing with a defined reference operating range, a relative index representing the degree of disturbance can be assigned to the temperature and humidity at each moment. The processing of electromagnetic interference signals is more complex, requiring the calculation of background energy density within the chip's operating frequency band using data collected by a spectrum analyzer. By analyzing the energy distribution of interference signals on the chip's main receiving frequency band, it can be determined whether there are significant interference sources in the current environment, as well as the duration and intensity trends of these interference signals. During the calculation process, special attention is paid to interference sources that are persistent and cover the chip's communication frequency band, as they are most likely to affect the chip's rectification efficiency and internal voltage stability. Finally, by integrating the interference characteristics of temperature, humidity, and electromagnetic signals into a unified interference intensity vector, the foundation is laid for subsequent nonlinear analysis and neural network modeling. This processing flow ensures that external environmental information can be embedded into the logic simulation process in a quantified form, improving the model's adaptability to complex real-world scenarios.

[0031] By statistically analyzing the frequency of joint occurrence and common fluctuation trends of different interference types, we can identify which factors often occur simultaneously and cause significant voltage fluctuations. For example, under high temperature and humidity conditions, the rectification efficiency of a chip may decrease, leading to response delays or longer rise times in the voltage waveform. On the other hand, electromagnetic interference may not cause a voltage drop on its own, but when superimposed on temperature changes, it amplifies the instability in the chip's power supply process. This cross-influence mechanism requires identification of its patterns through multivariate combination analysis. In experiments, multiple test scenarios are typically used, with single or combined interference factors controlled for sample collection, forming a comparison group. By comparing the changing characteristics of the voltage waveform, including peak drift, prolonged settling time, and high-frequency disturbances, a nonlinear relationship model between each interference combination and the voltage response can be established. This model does not pursue analytical expressions but establishes mapping rules between interference input and voltage output through data fitting and pattern recognition, providing high-quality data samples for subsequent adaptive learning and correction coefficient extraction using neural networks. By training a neural network model with regression capabilities, it can automatically learn the complex influence of environmental factors on the chip voltage response and output a set of environmental compensation coefficients for behavior correction. The training data comes from experimental samples collected and processed in previous steps. The input is a feature vector composed of temperature, humidity, and electromagnetic interference, and the output is the change or adjustment value of the chip voltage response, including key parameters such as waveform jitter, average voltage decline, and settling time extension. The neural network structure can adopt a general multilayer perceptron model, with appropriate additions of hidden layers and nonlinear activation functions to capture the complex coupling relationships between different input dimensions. During training, the network needs to be tuned and verified to ensure its generalization ability covers all test environment scenarios. Finally, the network model will generate a set of corresponding correction coefficients for any set of environmental interference inputs. These coefficients can be regarded as dynamic compensation weights for the chip voltage behavior. In simulation applications, this set of correction coefficients will be used to dynamically adjust behavioral parameters such as the trigger probability and timing delay of logic gates, enabling the logic simulation model to have environmental adaptability and thus more realistically reflect the chip's performance in non-ideal scenarios.

[0032] These coefficients are applied to the previously constructed logic state transition model to achieve dynamic compensation and adjustment of the transition probability distribution tensor. The original transition probability tensor represents the probability of signal transmission between logic modules within the chip under different power densities or voltage conditions. When the external environment changes, the original logic triggering probability will inevitably be affected. If not corrected, the simulation model will lose accuracy. Therefore, this step combines the environmental correction coefficient with the energy state on which each signal propagation path depends to dynamically update the state transition probability between each node. Specifically, an adjustment weight is assigned to each pair of logic module connection paths in the transition tensor. This weight is determined by the correction coefficient under the current environmental conditions. In scenarios such as high temperature, high humidity, and strong interference, these weights may decrease significantly, reflecting that some paths no longer have effective communication capabilities under the current conditions. The resulting compensation tensor not only retains the basic topology of the original logic structure but also incorporates dynamic factors from the environmental dimension, providing a dynamic state simulation framework for real-world deployment scenarios. This tensor can be directly used for subsequent behavior prediction, path reconstruction, and fault tolerance mechanism analysis, and is an indispensable core component for achieving high-reliability energy logic modeling.

[0033] In this embodiment, step S4 includes the following steps: Voltage-sensitive path identification and analysis is performed based on interference compensation distribution tensor to extract critical and non-critical logic paths. Accuracy requirements are allocated to critical and non-critical logic paths to obtain three levels of simulation accuracy, including transistor level, gate level, and functional level. Calculate the memory requirements and simulation time for the three simulation accuracy levels to obtain the simulation resource requirements; Dynamic resource scheduling optimization is performed based on simulation resource requirements, and simulation configuration coding is carried out to build a hierarchical simulation configuration file.

[0034] In this embodiment, the stability and transmission probability of different logic paths are ranked using the environmental dynamic features contained in the compensation tensor, and critical and non-critical logic paths are extracted. First, all propagation paths between logic gates and modules are traversed, and the magnitude of state transition probability changes under various disturbance conditions is evaluated. If a path exhibits high probability fluctuations (such as significant decreases or unstable fluctuations) under multiple environmental disturbance scenarios, it can be considered a voltage-sensitive path. In this way, a path stability ranking table can be constructed to distinguish which logic paths are vulnerable to chip functionality and which have good fault tolerance. Furthermore, parameters such as node delay, logic gate type, and energy trigger sensitivity on the path need to be evaluated to ensure that the analysis results reflect actual logic behavior. In experimental verification, by simulating different environmental parameter disturbances, it was found that some paths exhibit significant delay drift or interruption under high humidity + EMI, which can be identified as critical paths. The final path classification results will be used for subsequent simulation accuracy allocation to ensure that critical paths are modeled at higher resolution, improving the accuracy and resource utilization efficiency of the entire simulation system. Based on the criticality and behavioral uncertainty of each path, different levels of simulation accuracy are assigned to construct a refined, multi-layered simulation model. To balance simulation accuracy and resource consumption, the accuracy levels are divided into three layers: transistor level, gate level, and functional level. Critical logic paths, due to their high sensitivity to system function and energy state, require transistor-level modeling to simulate the switching behavior of each transistor, charge accumulation process, and noise interference, ensuring a realistic reflection of voltage response even under extreme conditions. Moderately sensitive paths use gate-level models, analyzing logic propagation delay and gating failures on a per-logic-gate basis. Non-critical paths, which remain stable under most environmental conditions, only require functional-level modeling, focusing on the logical relationships between inputs and outputs without considering electrical details. This layered strategy requires comprehensive evaluation based on multiple indicators, including voltage variation range, path propagation probability variation, and gate delay sensitivity. In practice, typically no more than 20% of the paths in the system are classified as transistor-level, approximately 40% as gate-level, and the remainder as functional-level. Such a distribution can significantly reduce computation and storage costs while ensuring simulation accuracy, providing feasibility for dynamic simulation in large-scale scenarios.

[0035] After establishing a three-layer simulation accuracy model, it is essential to quantitatively assess the resources required for each level, clarifying its memory consumption, computation time, and concurrency requirements during specific operation. This will guide subsequent resource scheduling and platform deployment. The core task of this step is to accurately estimate the average and peak resource requirements of the transistor-level, gate-level, and functional-level models within the same test cycle. First, these three models are deployed on the simulation platform, and a full-cycle simulation of the same chip logic task is performed, recording memory consumption, simulation frames, and processing time per frame. Typically, the memory consumption of the transistor-level model is approximately 5–10 times that of the gate-level model, while the simulation time can be more than 15 times that of the gate-level model. The functional-level model consumes the fewest resources, but its accuracy is insufficient for critical path behavior modeling. In experiments, a passive chip containing approximately 4000 logic gates, under a complete three-layer accuracy configuration, has a total memory requirement fluctuating between 32GB and 64GB, with a simulation frame duration of approximately 120ms. Even with a constant accuracy level, different environmental parameter configurations will also affect resource consumption, requiring dynamic adjustment of the simulation granularity for some paths due to the compensation mechanism. Therefore, peak resource consumption under worst-case environmental conditions must also be considered when assessing resource requirements to avoid runtime resource overflow or simulation interruption. The resulting resource requirement table will provide data support for the scheduling optimization and parallelization strategies of the simulation system, ensuring stable system operation during multi-scenario switching.

[0036] A dynamic resource scheduling algorithm maps simulation modules of different precision levels to heterogeneous processing resources, including CPU threads, GPU core clusters, and high-bandwidth storage blocks. Priorities are assigned to each module based on path criticality and resource consumption levels. A simulation scheduling queue is then established based on system resource distribution, prioritizing the allocation of high-precision resource bits for critical paths. Simultaneously, simulation tasks are divided into multiple subtasks, and a timing diagram is created based on their dependencies and data channels to determine the concurrency window and scheduling granularity in the scheduling strategy. Subsequently, a structured simulation configuration file is generated based on this strategy. This file is encoded in a hierarchical structure, defining configuration parameters, resource mapping location information, and compensation coefficient indices for transistor-level, gate-level, and functional-level modules. This configuration file supports dynamic loading and condition switching; when the system detects changes in external environmental parameters reaching a certain threshold, the simulation engine can call the corresponding simulation-level template for hot replacement, ensuring the model is always in an optimal operating state. In actual deployment, this mechanism supports simultaneous modeling and resource scheduling of dozens of chips in large-scale IoT systems, greatly improving the scalability and operational efficiency of the simulation platform, and is one of the key technologies for realizing environment-aware logic simulation.

[0037] In this embodiment, step S5 includes the following steps: Multi-precision parallel simulation is performed based on a hierarchical simulation configuration file, and the logic state output results of each logic module are collected. Error detection is performed on the output results of the logic state, and errors in the logic transition state are marked. Perform timing error rate quantification calculation on the logical transition state error results to generate a logical error probability curve; Error type clustering analysis is performed based on the logical transition state error results to obtain the logical state type; Confidence interval statistics are performed based on logic state types and logic error probability curves to construct a probabilistic verification report; Simulation logic encapsulation and design optimization are performed based on probabilistic verification reports.

[0038] In this embodiment, based on the previously constructed hierarchical simulation configuration file, the system will formally initiate the multi-precision parallel simulation process. This configuration file defines in detail the simulation precision levels of the chip's internal logic paths, including transistor level, gate level, and functional level, and specifies their corresponding hardware resource mappings, compensation model parameters, and scheduling time windows. The simulation engine, according to this configuration, launches multi-threaded or heterogeneous computing units, such as GPU computing cores and high-concurrency CPU task units, to undertake simulation subtasks at different precision levels. During simulation execution, the system will periodically collect the state output results of each logic module. These states include basic "high / low level" outputs, intermediate uncertain states during voltage fluctuations, and logic delay records in some paths. The data acquisition frequency is synchronized with the chip clock domain to ensure consistency between the simulation state and the actual operating scenario. This step also includes real-time monitoring of abnormal module behavior signals, such as state latch failure, output drift, and voltage gating failure, and timestamping all data. In the experiment, a minimum simulation cycle of 10 nanoseconds is typically used, and behavior sampling is performed on all paths for at least 1000 cycles to provide a high-precision, structured logic output dataset for subsequent error analysis and statistical clustering. Through this hierarchical parallel simulation approach, the system achieves comprehensive modeling of complex chip logic behavior under resource-constrained conditions. After collecting the output results of all logic modules, error detection and labeling are performed to identify which state transition results deviate from the design expectations, thereby constructing a complete sequence of erroneous behaviors. Error detection first compares the degree of matching between the simulated output and the theoretical output based on the logic truth table or state transition diagram of each module in the design schematic. For example, if a gate-level module outputs a "low level" when the input conditions satisfy the logical "AND" operation, this state will be identified as an erroneous result. Furthermore, for transistor-level and gate-level precision models, a voltage threshold reference table is introduced to determine whether the module's logic output fails due to insufficient voltage. On timing-sensitive paths, the system further checks whether state transitions exceed the set delay tolerance range. If a signal's transition from input excitation to output response exceeds the timing window, it is considered a "delay error" rather than a "logic error," and both will be classified and marked separately. All detected error states will be timestamped and have path identification information added, forming a "logic transition state error record." This record consists of module number, state input combination, output result, error type, and error timing, serving as the core data source for subsequent probabilistic modeling and type identification. The entire detection process employs an automated comparison mechanism to ensure efficiency and accuracy in large-scale path scenarios. In multiple experimental scenarios, it was found that the timing error rate increases significantly under the combination of high humidity and EMI interference, indicating that environmental changes are one of the key factors in the reliability analysis of logical behavior.

[0039] After identifying and recording all logic transfer errors, these error states are statistically and quantitatively processed. The frequency of error occurrence for each logic path under different environmental and energy conditions is calculated, and logic error probability curves are plotted accordingly. Specifically, for each path, the frequency of error states occurring within the total simulation cycle is statistically analyzed, and its average error rate per unit time is calculated. The error rate data includes not only the overall error rate but also the proportion of specific error types, such as "logic inversion error," "gate-level unstable output," and "timing drift exceeding limits." Subsequently, the trend of error rate for each path changing with external conditions is modeled; for example, the trend of error rate change for a certain path is analyzed after the temperature rises from 25℃ to 45℃. By summarizing and fitting simulation results from multiple environmental scenarios, a complete set of logic error probability curves can be formed. These curves can intuitively reflect the stability level of the chip's logic paths under different disturbance conditions. In experiments, a common method is to sort the error rates of all paths by frequency and plot cumulative probability maps and segmented heatmaps based on distribution characteristics, thereby quickly identifying which paths are most prone to anomalies under different operating scenarios. This step provides a quantitative basis for subsequent error clustering analysis, confidence interval statistics and optimization, and is the core foundation in logical reliability modeling.

[0040] Based on the obtained logic error probability curves, to more clearly identify the causes and propagation patterns of errors, cluster analysis of error states is needed to classify different types of logic anomalies into several "logic state types." Cluster analysis uses feature vectors to represent each error event, with features including error occurrence time, triggering conditions, path number, module precision level, voltage trigger point, and environmental parameter values. By classifying error events using unsupervised learning methods (such as K-means or density clustering), errors can be automatically divided into several categories, each representing a logic anomaly state with similar characteristics. For example, one type of error occurs mainly in high-temperature environments and only in gate-level models, with consistent excessive output signal delay; this can be classified as "temperature-controlled delay drift." Another type mainly occurs in transistor-level models, exhibiting instantaneous logic flips and recovery; this can be classified as "voltage disturbance-type short-term logic inversion." Finally, these clustering results are mapped to a set of standardized "logic state type" labels, enabling subsequent verification processes to perform probability modeling and confidence interval analysis based on categories. This step is particularly important in root cause analysis of logic failures. It can help designers make structural improvements, power supply adjustments or logic redundancy deployments for specific failure types, thereby improving the overall stability and resilience of the chip.

[0041] Using each logical state as the unit of analysis, the confidence interval of its error rate is calculated to assess the probability range of logical anomalies occurring in actual use. During the statistical process, firstly, based on the sample size, error frequency, and distribution pattern of each type of error, an appropriate statistical method (such as quantile method or bias estimation method) is selected for interval estimation. Subsequently, the upper and lower confidence limits of each type of error are compared under different energy densities and environmental scenarios to mark high-risk paths and boundary-sensitive logic points. In the experiment, through three rounds of environmental disturbance experiments (stable room temperature, electromagnetic interference introduction, and combined increase in temperature and humidity), five high-risk states with confidence interval fluctuations exceeding 30% were identified, mainly concentrated in the rectifier control module and address decoding module. These results are organized into a standardized probabilistic verification report, including: logical path identification number, state type label, error probability interval, affected conditions, recommended simulation level, etc. This report serves as the basis for subsequent logic encapsulation and design optimization, and can also be integrated into the system-level verification process for intelligent verification strategy decision-making and automated test case generation.

[0042] In this embodiment, the specific steps for performing simulation logic encapsulation and design optimization based on the probabilistic verification report are as follows: Probabilistic verification reports are used to identify chip reliability bottlenecks and mark performance hotspots and weak points. Numerical sensitivity modeling is performed on the performance hotspots and weak points to construct the influence relationship matrix between design parameters and performance indicators; The influence relationship matrix is ​​solved by multi-objective optimization to obtain the optimal solution set of the circuit topology; simulation logic encapsulation and design optimization are performed based on the optimal solution set of the circuit topology.

[0043] In this embodiment, a comprehensive analysis is performed on the logic state types, error probability curves, and confidence interval distributions marked in the report to identify reliability bottlenecks in the chip circuit and further mark performance hotspots and weak logic links. This analysis process is based on comparing multiple sets of simulation data results, combining multiple dimensions such as state trigger frequency, upper bound of failure probability, and output fluctuation amplitude to rank the reliability of each logic path and module. Performance hotspots mainly refer to areas with frequent state transitions, high logic load density, and sensitivity to power supply changes under actual workloads, often concentrated in modules such as clock distribution, address decoding, and data caching. Weak links refer to logic paths that repeatedly exhibit logic errors in multiple simulation scenarios, with their upper limit of failure probability confidence intervals far exceeding the average level, often caused by problems such as power supply coupling, delayed gating response, and unstable internal feedback links. In actual testing, under interference scenarios with a 3.5cm RF power supply distance, an ambient temperature of 40℃, and 80% humidity, the control signal synchronization module of a certain type of tag chip showed a stability offset fluctuation of over 43% in five simulations, clearly classified as a weak link. All hotspots and weak points are ultimately located to specific modules through a numbering and path mapping table, guiding subsequent structural modeling and optimization deployment. After identifying the performance hotspots and weak paths within the chip, numerical sensitivity modeling is performed on these key logic regions to establish the causal relationship between their design parameters and simulation performance indicators. This modeling process uses module structural parameters (such as the number of logic gates, connection topology depth, register trigger time, voltage response characteristics, etc.) as input variables, and the performance output includes multiple performance indicators such as logic error probability, delay drift, power consumption stability, and output jitter amplitude. A large number of parameter combination samples are generated using Latin hypercube sampling (LHS) or Sobol sequences, and high-precision gate-level and transistor-level co-simulations are performed on each set of parameters on the simulation platform to construct a high-dimensional input-output dataset. During the experiment, 300 sets of valid simulation samples were selected to conduct structural parameter perturbation experiments on a certain hotspot module. The results show that there is a significant nonlinear coupling effect between the input gate delay time and voltage fluctuation of this module, which is very likely to cause state flip errors. After data acquisition, partial least squares regression (PLSR) or a gradient boosting tree-based regression model (such as XGBoost) is applied for sensitivity modeling. This outputs the contribution weights between each parameter and performance index, ultimately forming a "design parameter - performance index" influence matrix. This matrix serves as the basis for structural optimization, clearly indicating the types of parameters that need to be adjusted first and the sensitive areas, and is a key technical foundation driving subsequent multi-objective circuit optimization.

[0044] Multi-objective optimization is performed to solve multiple performance metrics (such as minimum error rate, minimum power consumption, shortest latency, and maximum fluctuation tolerance) to obtain the optimal set of circuit topologies that meet the chip stability design goals. This process employs multi-objective evolutionary algorithms (such as NSGA-II or MOEA / D) to search for the Pareto Front in a high-dimensional design parameter space to balance the conflicting relationships between various design objectives. In practical applications, to ensure the feasibility and engineering constraints of the optimized solutions, the optimization algorithm integrates structural rule constraints, such as maximum gate layer limits, wiring coupling distance requirements, and capacitive load limits. In one experiment, the NSGA-II algorithm was used to optimize a communication control unit, with objectives including a logic error rate of less than 1%, latency of less than 1.5 ns, and voltage response difference of less than 50 mV. After 600 generations of population iteration, 42 sets of non-dominated topology solutions meeting the conditions were obtained. These solutions include different gate configurations, transistor size ratios, and feedback path structures, and their distribution characteristics form the basis for the diversity of the optimal solution set, providing optional schemes for subsequent simulation and packaging. While outputting the optimal solution set, the system also performs resource evaluation and power consumption prediction for each solution group to assist designers in weighing and selecting solutions from a feasibility perspective. These candidate structural solutions are then encapsulated into simulation logic models for subsequent deployment, guiding specific chip design optimization tasks. The encapsulation process first verifies each topology solution at the module level to confirm its logical functional integrity and simulation feasibility. Then, it adapts and packages solutions according to simulation accuracy levels, generating transistor-level, gate-level, and behavioral-level encapsulation models respectively. Simultaneously, based on the simulation platform resources and chip design requirements, encapsulation parameters such as simulation priority, environment adaptation range, and output fault tolerance strategy are configured for each model. Subsequently, based on the design goals of different application scenarios (such as low-power mode, high-stability mode, wide-temperature operating mode, etc.), the system selects corresponding subsets from the optimal solution set, constructs targeted optimized versions of chip structure sketches, and outputs editable design suggestion documents for hardware designers to further optimize circuit layout, adjust power supply strategies, or implement logic refactoring. In an experimental optimization, the five topology solutions with the lowest error rates were selected to reconstruct the synchronous triggering module of the tag chip. After simulation, the error rate dropped from 4.6% to 0.7%, significantly improving stability. The entire optimization and packaging process forms a complete logic simulation design closed loop, from reliability analysis to design implementation, ensuring the stable operation and long-term reliability of the passive IoT tag chip in complex energy environments.

[0045] In this embodiment, a voltage logic simulation design system for a passive IoT tag chip is provided, used to execute the voltage logic simulation design method for a passive IoT tag chip as described above, including: The characteristic measurement module is used to measure the energy characteristics of the tag chip, calculate voltage fluctuations and logic gate trigger probabilities, and obtain energy logic state mapping data. The probability distribution module is used to perform state transition probability distribution mapping based on energy logic state mapping data and construct a transition probability distribution tensor. The interference compensation module is used to collect measurement environment parameters during the energy characteristic measurement process and perform dynamic environmental interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor. The requirement allocation module is used to allocate simulation accuracy requirements based on the interference compensation distribution tensor and to build a hierarchical simulation configuration file. The parallel simulation module is used to perform multi-precision parallel simulations based on hierarchical simulation configuration files and generate probabilistic verification reports.

[0046] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0047] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein are implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A voltage logic simulation design method for a passive IoT tag chip, characterized in that, Includes the following steps: Step S1: Measure the energy characteristics of the tag chip, calculate the voltage fluctuation and logic gate trigger probability, and obtain energy logic state mapping data; Step S2: Map the state transition probability distribution based on the energy logic state mapping data and construct the transition probability distribution tensor; Step S3: Collect measurement environment parameters during the energy characteristic measurement process, and perform dynamic environmental interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; Step S4: Allocate simulation accuracy requirements based on the interference compensation distribution tensor and construct a hierarchical simulation configuration file; Step S5: Perform multi-precision parallel simulation based on the hierarchical simulation configuration file and generate a probabilistic verification report.

2. The voltage logic simulation design method for the passive IoT tag chip according to claim 1, characterized in that, The specific steps of step S1 are as follows: Energy characteristics of passive IoT tag chips were measured under different radio frequency power densities and distances, and real-time voltage data of the chips were collected. Calculate the transient voltage values ​​of the chip's real-time voltage data at different power densities; The transient voltage value is fitted with a time-series voltage variation to obtain a voltage time-domain waveform curve; Multi-scale power spectral density calculations are performed on the voltage time-domain waveform curves to generate multi-scale power spectral density features; The trigger probability of logic gates and the trigger response delay parameters under different energy densities are calculated based on the multi-scale power spectral density characteristics to obtain energy logic state mapping data.

3. The voltage logic simulation design method for a passive IoT tag chip according to claim 1, characterized in that, The specific steps of step S2 are as follows: Identify the internal logic module of a passive IoT tag chip; Based on the energy logic state mapping data, perform logic gate cascade path analysis to extract voltage connection logic; Based on the voltage connection logic, the internal logic modules are analyzed to perform inter-module connection logic parsing, and the inter-module connection relationships and signal propagation paths are extracted. Based on the connection relationships between modules and the signal propagation path, a directed graph model of the propagation path is constructed to build a node-edge adjacency graph; Based on the logic gate triggering probability, a state transition probability distribution is mapped to the node-edge adjacency graph to construct a transition probability distribution tensor.

4. The voltage logic simulation design method for a passive IoT tag chip according to claim 1, characterized in that, Step S3 is as follows: During the energy characteristic measurement process, environmental parameters are collected simultaneously, including temperature, relative humidity, and electromagnetic interference signals. Calculate the measurement interference intensity of the measured environmental parameters; Based on the measured interference intensity, a cross-analysis of environmental interference factors is performed to generate a nonlinear mapping relationship between interference factors and voltage fluctuations. A neural network was trained on the nonlinear mapping relationship between interference factors and voltage fluctuations to obtain multidimensional environmental correction coefficients; Dynamic environmental disturbance compensation is performed on the transition probability distribution tensor based on the multidimensional environmental correction coefficient, generating the disturbance compensation distribution tensor.

5. The voltage logic simulation design method for a passive IoT tag chip according to claim 1, characterized in that, The specific steps of step S4 are as follows: Voltage-sensitive path identification and analysis is performed based on interference compensation distribution tensor to extract critical and non-critical logic paths. Accuracy requirements are allocated to critical and non-critical logic paths to obtain three levels of simulation accuracy, including transistor level, gate level, and functional level. Calculate the memory requirements and simulation time for the three simulation accuracy levels to obtain the simulation resource requirements; Dynamic resource scheduling optimization is performed based on simulation resource requirements, and simulation configuration coding is carried out to build a hierarchical simulation configuration file.

6. The voltage logic simulation design method for a passive IoT tag chip according to claim 1, characterized in that, The specific steps of step S5 are as follows: Multi-precision parallel simulation is performed based on a hierarchical simulation configuration file, and the logic state output results of each logic module are collected. Error detection is performed on the output results of the logic state, and errors in the logic transition state are marked. Perform timing error rate quantification calculation on the logical transition state error results to generate a logical error probability curve; Error type clustering analysis is performed based on the logical transition state error results to obtain the logical state type; Confidence interval statistics are performed based on logic state types and logic error probability curves to construct a probabilistic verification report; Simulation logic encapsulation and design optimization are performed based on probabilistic verification reports.

7. The voltage logic simulation design method for a passive IoT tag chip according to claim 6, characterized in that, The specific steps for performing simulation logic encapsulation and design optimization based on the probabilistic verification report are as follows: Probabilistic verification reports are used to identify chip reliability bottlenecks and mark performance hotspots and weak points. Numerical sensitivity modeling is performed on the performance hotspots and weak points to construct the influence relationship matrix between design parameters and performance indicators; The influence relationship matrix is ​​solved by multi-objective optimization to obtain the optimal solution set of the circuit topology; Simulation logic encapsulation and design optimization are performed based on the optimal solution set of circuit topology.

8. A voltage logic simulation design system for a passive IoT tag chip, characterized in that, The voltage logic simulation design method for executing the passive IoT tag chip as described in claim 1 includes: The characteristic measurement module is used to measure the energy characteristics of the tag chip, calculate voltage fluctuations and logic gate trigger probabilities, and obtain energy logic state mapping data. The probability distribution module is used to map the state transition probability distribution based on the energy logic state mapping data and construct the transition probability distribution tensor. The interference compensation module is used to collect measurement environment parameters during the energy characteristic measurement process and perform dynamic environmental interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor. The requirement allocation module is used to allocate simulation accuracy requirements based on the interference compensation distribution tensor and to build a hierarchical simulation configuration file. The parallel simulation module is used to perform multi-precision parallel simulations based on hierarchical simulation configuration files and generate probabilistic verification reports.

Images