Method for determining reference voltage, electronic device, storage medium and program product

Abstract

The application discloses a reference voltage determination method, an electronic device, a storage medium and a program product, relates to the technical field of computers, detects N preset reference voltages of N preset reference potentials corresponding to a flash memory unit, and the preset reference potential is a potential in M reference potentials of the flash memory unit and is used as a reference for a predicted reference voltage; a current word line position and a current erase-write times corresponding to the flash memory unit are acquired; according to the current word line position and the current erase-write times, a plurality of parameter values corresponding to a plurality of adjustment parameters are determined, the plurality of adjustment parameters including a position-related parameter, an aging parameter and a position compensation parameter; and according to the plurality of parameter values and the N preset reference voltages, at least one predicted reference voltage corresponding to at least one predicted reference potential is determined, the at least one predicted reference potential being a potential in the M reference potentials other than the N preset reference potentials. The efficiency of adjusting the reference voltage can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to methods for determining reference voltage, electronic devices, storage media, and program products. Background Technology

[0002] A NAND flash memory cell can include multiple memory cells, each storing data via a floating-gate transistor. The threshold voltage state of a memory cell can be determined by reading a reference voltage (Vref) between the threshold voltages (Vth) of each floating-gate transistor. However, as solid-state drives (SSDs) are used over time, the distribution of threshold voltages can shift, increasing the read error rate and necessitating adjustment of the reference voltage.

[0003] In related technologies, a full voltage scan can be used to obtain the distribution of multiple threshold voltages, thereby determining the current reference voltage between each threshold voltage and adjusting the reference voltage. However, performing a full voltage scan on the flash memory cells consumes a long time, resulting in low efficiency in adjusting the reference voltage. Summary of the Invention

[0004] This application provides a method for determining a reference voltage, an electronic device, a storage medium, and a program product to at least solve the problem of low efficiency in adjusting the reference voltage in related technologies.

[0005] In a first aspect, this application provides a method for determining a reference voltage, comprising:

[0006] Detect N preset reference voltages corresponding to N preset reference potentials of the flash memory cell. The preset reference potentials are the potentials used as references for prediction reference voltages among the M reference potentials of the flash memory cell. N is an integer greater than or equal to 1, and M is an integer greater than N.

[0007] Obtain the current word line position and current erase / write count corresponding to the flash memory cell;

[0008] Based on the current word line position and the current number of erase / write cycles, determine multiple parameter values ​​corresponding to multiple adjustment parameters, including position-related parameters, aging parameters, and position compensation parameters;

[0009] Based on the multiple parameter values ​​and the N preset reference voltages, at least one predicted reference voltage corresponding to at least one predicted reference potential is determined, wherein the at least one predicted reference potential is a potential other than the N preset reference potentials among the M reference potentials.

[0010] Secondly, this application also provides a reference voltage determination device, including a first detection module, a first acquisition module, a first determination module, and a second determination module:

[0011] The first detection module is used to detect N preset reference voltages of N preset reference potentials corresponding to the flash memory cell. The preset reference potentials are the potentials used as the reference for prediction reference voltages among the M reference potentials of the flash memory cell. N is an integer greater than or equal to 1, and M is an integer greater than N.

[0012] The first acquisition module is used to acquire the current word line position and the current erase / write count corresponding to the flash memory cell;

[0013] The first determining module is used to determine multiple parameter values ​​corresponding to multiple adjustment parameters based on the current word line position and the current number of erase / write cycles. The multiple adjustment parameters include position-related parameters, aging parameters, and position compensation parameters.

[0014] The second determining module is used to determine at least one predicted reference voltage corresponding to at least one predicted reference potential based on the plurality of parameter values ​​and the N preset reference voltages, wherein the at least one predicted reference potential is a potential other than the N preset reference potentials among the M reference potentials.

[0015] Thirdly, this application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of determining any of the aforementioned reference voltage methods.

[0016] Fourthly, this application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the method for determining any of the above-described reference voltages.

[0017] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of determining any of the aforementioned reference voltages.

[0018] The reference voltage determination method, electronic device, storage medium, and program product provided in this application can detect N preset reference voltages corresponding to N preset reference potentials of a flash memory cell, obtain the current word line position and current erase / write count corresponding to the flash memory cell, determine multiple parameter values ​​corresponding to multiple adjustment parameters based on the current word line position and current erase / write count, and determine at least one predicted reference voltage corresponding to at least one predicted reference potential based on the multiple parameter values ​​and the N preset reference voltages. Only N preset reference voltages out of M reference potentials need to be detected; other predicted reference voltages can be derived from these N preset reference voltages without requiring a full voltage scan of each reference potential, thus improving the efficiency of reference voltage adjustment. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram illustrating an application scenario provided in an embodiment of this application;

[0021] Figure 2 A flowchart illustrating a method for determining a reference voltage provided in an embodiment of this application;

[0022] Figure 3 A flowchart illustrating another method for determining a reference voltage provided in an embodiment of this application;

[0023] Figure 4 A flowchart illustrating an update processing method provided in an embodiment of this application;

[0024] Figure 5 A flowchart illustrating another method for determining a reference voltage provided in an embodiment of this application;

[0025] Figure 6 A schematic diagram of the architecture of a method for determining a reference voltage provided in an embodiment of this application;

[0026] Figure 7 A schematic diagram of a reference voltage determination device provided in an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, other embodiments obtained by those of ordinary skill in the art without creative effort are all within the protection scope of this application.

[0029] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0030] Solid-state drives (SSDs) are plug-and-play storage products that encapsulate components such as NAND flash memory chips, controller chips, and cache chips (optional). They are used to replace traditional hard disk drives (HDDs) and provide faster read and write speeds and higher reliability.

[0031] NAND flash memory is the core storage chip of solid-state drives. It is a non-volatile storage chip based on floating-gate transistors, and its internal circuit structure is similar to NAND logic gates.

[0032] The reference voltage (Vref) is a standard voltage value generated by the SSD controller chip. It is compared with the threshold voltage (Vth) of the NAND flash memory cell to determine whether the cell stores 0 or 1. As the number of NAND flash memory cycles increases (erasing and writing wears down the insulating layer, causing Vth to drift), the controller dynamically adjusts the value of Vref to ensure the accuracy of data reading.

[0033] Figure 1 This is a schematic diagram illustrating an application scenario provided by an embodiment of this application. Please refer to [link / reference]. Figure 1 The solid-state drive 100 may include multiple flash memory cells 101, which may be NAND flash memory cells. Each flash memory cell 101 may include multiple memory cells, and each memory cell stores data through a floating gate transistor. By applying a reference voltage (Vref) to the floating gate transistor, the conduction state of the transistor can be detected, and the threshold voltage (Vth) range of the memory cell can be deduced, thereby determining the threshold voltage state of the memory cell.

[0034] Taking flash memory cell 101 as an example of a triple-level cell (TLC) flash memory, TLC is a multi-level cell technology where each memory cell can store 3 bits of data, corresponding to 8 consecutive threshold voltage (Vth) intervals (i.e., 8 threshold voltage states). The critical potential between two adjacent threshold voltage intervals serves as a reference potential (Vref), requiring a total of 7 reference potentials to distinguish these 8 intervals. These 8 threshold voltage (Vth) states can be distinguished by applying different reference voltages (Vref) to the memory cell and detecting whether the transistor is conducting.

[0035] As the number of erase and write cycles of the flash memory cells 101 increases during the use of the solid-state drive 100, the distribution of the threshold voltage will shift (such as interval overlap and boundary drift), which will increase the data read error rate. Therefore, the reference voltage needs to be dynamically adjusted.

[0036] In related technologies, a full voltage scan can be performed, which involves traversing multiple possible voltage values ​​and detecting transistor conductance to obtain the distribution of each threshold voltage range, thereby determining the current reference voltage between each threshold voltage and adjusting the reference voltage. However, performing a full voltage scan on flash memory cells requires traversing a large number of voltage points, which consumes a considerable amount of time, resulting in low efficiency in adjusting the reference voltage.

[0037] The reference voltage determination method provided in this application can detect N preset reference voltages corresponding to N preset reference potentials for a flash memory cell. The preset reference potentials are potentials among multiple reference potentials of the flash memory cell used as a reference for predicting other reference voltages. The method can obtain the current word line position and the current erase / write count corresponding to the flash memory cell; determine multiple parameter values ​​corresponding to multiple adjustment parameters based on the current word line position and the current erase / write count; and determine at least one predicted reference voltage corresponding to at least one predicted reference potential based on the multiple parameter values ​​and the N preset reference voltages. The at least one predicted reference potential is a potential other than the N preset reference potentials among M reference potentials.

[0038] In the above process, only N preset reference voltages among the M reference potentials need to be detected. Other predicted reference voltages can be derived from the N preset reference voltages without the need for a full voltage scan of each reference potential, which can improve the efficiency of adjusting the reference voltage.

[0039] Figure 2 This is a schematic flowchart illustrating a method for determining a reference voltage according to an embodiment of this application. Please refer to... Figure 2 The method may include:

[0040] S201. Detect the N preset reference voltages corresponding to the N preset reference potentials of the flash memory cell.

[0041] The preset reference potential can be one of the M reference potentials of the flash memory cell, used as a reference voltage for prediction.

[0042] N is an integer greater than or equal to 1, and M is an integer greater than N.

[0043] For example, taking TLC flash memory as an example, the flash memory cell has a total of 7 reference potentials. 3 of the 7 reference potentials are determined as preset reference potentials, that is, M is 7 and N is 3.

[0044] N preset reference potentials out of M reference potentials can be determined using a pre-trained neural network module.

[0045] For example, if the flash memory cell is TLC flash memory, TLC flash memory distinguishes data through 8 threshold voltage states (i.e., Er, A, B, C, D, E, F, G). A pre-trained neural network module can determine 3 preset reference potentials (Vref1-Vref3). Point 1 (Vref1) is located at the boundary between the Er and A states, which is the most sensitive area for charge leakage. Dynamically adjusting this voltage point based on parameters such as temperature (e.g., automatically increasing from 2.3V to 2.45V at 85℃) can better monitor charge leakage. Point 2 (Vref2) covers the B / C / D state transition region, where the drift amplitude is largest. Determining an appropriate voltage to cover this region can effectively quantify the broadening amplitude of intermediate states. Point 3 (Vref3) is anchored at the F / G state separation boundary, which is a high-temperature overlapping region. Voltage compensation based on factors such as temperature (e.g., 150mV compensation at -40℃) can assess the risk of high-temperature overlap.

[0046] S202. Obtain the current word line position and current erase / write count corresponding to the flash memory cell.

[0047] In the structure of NAND flash memory, the word line (WL) is the row control line. By applying a specific voltage, a floating gate transistor in a particular row can be selected. Together with the bit line (BL), i.e., the column control line, they locate and access individual memory cells. Due to differences in NAND chip manufacturing processes, the threshold voltage Vth of memory cells corresponding to different word line positions varies significantly with the shift during use.

[0048] Meanwhile, the number of erase / write cycles (P / E cycle) is the core factor causing the threshold voltage Vth shift. Each erase / write operation causes minor wear to the insulating layer of the floating gate, leading to a gradual decrease in the stability of electron injection / extraction. The more erase / write cycles, the greater the shift in the threshold voltage Vth distribution and the stronger the range dispersion. The degree of influence of different erase / write cycles on the threshold voltage shift varies significantly.

[0049] Therefore, in this application, the current word line position and the current erase / write count corresponding to the flash memory cell can be obtained, and the parameter value corresponding to the adjustment parameter can be determined based on the current word line position and the current erase / write count.

[0050] S203. Based on the current word line position and the current number of erase / write cycles, determine the values ​​of multiple adjustment parameters.

[0051] Multiple adjustment parameters can include location-related parameters, aging parameters, and location compensation parameters.

[0052] The parameter values ​​corresponding to the position-related parameters are determined by the word line position grouping corresponding to the current word line position, and are used to reflect the charge coupling effect between word lines (i.e., the threshold voltage shift caused by mutual interference of charges between adjacent memory cells). This parameter value can be pre-calibrated by performing threshold voltage mutual interference tests on flash memory cells of different word line position groups and stored in the corresponding sub-coefficient table.

[0053] The aging parameter value is determined by the erase / write cycle group corresponding to the current erase / write cycle, and is used to describe the degree of degradation of the charge trap layer. This parameter value can be determined by conducting accelerated aging tests on different erase / write cycle groups and stored in the corresponding sub-coefficient table.

[0054] The position compensation parameter value is determined by the word line position group corresponding to the current word line position and the number of erase / write cycles. It is used to correct the systematic threshold voltage offset caused by differences in manufacturing processes and aging effects in different word line position groups. This parameter value can be initially determined by performing a full word line threshold voltage benchmark test on the NAND chip before it leaves the factory, and then dynamically adjusted in combination with aging data.

[0055] Specifically, the target word line position group corresponding to the current word line position can be determined based on the multiple word line position groups corresponding to the flash memory cell; the target erase / write count group corresponding to the current erase / write count can be determined based on the multiple erase / write count groups corresponding to the flash memory cell; and multiple parameter values ​​can be determined based on the target word line position group and the target erase / write count group.

[0056] In this application, the parameter values ​​corresponding to multiple adjustment parameters are determined by grouping the target word line positions and the target erase / write times, and then the optimized reference voltage is calculated by combining the preset reference voltage, which can effectively improve the accuracy and efficiency of reference voltage adjustment.

[0057] In some possible implementations, in addition to the current word line position and the current number of erase / write cycles, a data retention time can also be considered. The data retention time is the longest time that data can be safely retained without bit flipping after being written to a flash memory cell without power.

[0058] The parameter values ​​corresponding to each adjustment parameter are determined by using the current word line position, the current number of erase / write cycles, and the data retention time. The specific determination process can be found in the execution process provided in the embodiments of this application, which uses the current word line position and the current number of erase / write cycles to determine the parameter values ​​corresponding to each adjustment parameter; it will not be repeated here.

[0059] S204. Based on multiple parameter values ​​and N preset reference voltages, determine at least one predicted reference voltage corresponding to at least one predicted reference potential.

[0060] At least one predicted reference potential is a potential other than the N preset reference potentials among the M reference potentials.

[0061] Based on the threshold voltage distribution characteristics of the flash memory cells, N preset reference potentials can be selected. These N preset reference potentials can include drift-sensitive potentials, linear drift potentials, and saturation drift potentials.

[0062] The drift-sensitive potential is the reference potential with the highest voltage drift sensitivity among the M reference potentials; the linear drift potential is the reference potential with the highest correlation between the drift amount and the average value of the full reference voltage among the M reference potentials; and the saturation drift potential is the reference potential with the lowest voltage drift sensitivity among the M reference potentials.

[0063] For example, if the flash memory cell is TLC flash memory, TLC flash memory distinguishes data through 8 threshold voltage states (i.e., Er, A, B, C, D, E, F, G), corresponding to 7 reference potentials (boundaries between adjacent states), i.e., M is 7. If N is 3, then the 7 reference potentials include 3 preset reference potentials and 4 predicted reference potentials. The 3 preset reference potentials can be selected as follows: the drift-sensitive potential is the boundary of the Er-A threshold voltage; the linear drift potential is the boundary of the CD threshold voltage (its drift amount has a correlation of up to 0.92 with the average of all reference voltages); and the saturation drift potential is the boundary of the EF threshold voltage.

[0064] The reference voltage determination method provided in this application embodiment can derive other predicted reference voltages by detecting N preset reference voltages among M reference potentials, without needing to perform a full voltage scan on each reference potential, thus improving the efficiency of adjusting the reference voltage.

[0065] Figure 3 This is a flowchart illustrating another method for determining a reference voltage provided in an embodiment of this application. Please refer to... Figure 3 The method may include:

[0066] S301. Detect the N preset reference voltages corresponding to the N preset reference potentials of the flash memory cell.

[0067] S302. Obtain the current word line position and current erase / write count corresponding to the flash memory cell.

[0068] For details on the execution process of S301-S302, please refer to the execution process of S201-S202, which will not be repeated here.

[0069] S303. Based on the multiple word line position groups corresponding to the flash memory cell, determine the target word line position group corresponding to the current word line position.

[0070] Multiple word line position groups can be determined by comprehensively considering the charge coupling effect, process variation, and position characteristics corresponding to the flash memory cell.

[0071] Multiple word line position groups can include edge effect groups, linear drift groups, and process variation groups.

[0072] Edge effect grouping includes floating gate transistors at the source / drain edges, which are significantly affected by electric field interference, and their threshold voltage drift is typically 40-60% higher than that at the middle word line location.

[0073] The linear drift group can be further divided into multiple sub-linear groups. These sub-linear groups are divided according to the gradient characteristics of charge coupling strength, and the group boundaries are determined by electric field simulation results.

[0074] The process variation group can be further divided into multiple sub-process groups. This group mainly addresses the problem of threshold voltage distribution broadening caused by uneven oxide layer thickness at the top word line position, and is grouped according to the differences in process batches.

[0075] For example, if there are 192 word line positions in total, designated WL0-WL191, the edge effect grouping can include WL0-WL5 (6 word line positions in total). The linear drift grouping corresponds to WL6-WL113 (108 word line positions in total), with each group consisting of 6 word line positions (WL6-WL11, WL12-WL17, etc.), resulting in 18 sub-linear groups. The process variation grouping corresponds to WL114-WL191 (78 word line positions in total), with each group consisting of 8 word line positions (WL114-WL121, WL122-WL12, etc.), resulting in 10 sub-process groups (the last group consists of 7 word lines, WL184-WL191).

[0076] S304. Determine the target erase / write count group corresponding to the current erase / write count based on the multiple erase / write count groups corresponding to the flash memory cell.

[0077] Multiple erase / write cycles can be grouped based on the degradation curves of the charge trap layers corresponding to the flash memory cells.

[0078] The charge trapping layer is a critical structure in NAND flash memory, and its degradation (such as the formation of interface traps and charge accumulation) is exacerbated by the number of erase and write operations.

[0079] The degradation curves describe the relationship between the degradation of the charge trap layer and the number of erase / write cycles. By analyzing the degradation curves, the grouping threshold for erase / write cycles can be determined, thereby identifying multiple erase / write cycle groups.

[0080] For example, the erase / write counts are divided into 8 groups (PEG0-PEG7), with a grouping threshold of 1000 erase / write counts per group. PEG0 is 1-1000 times, PEG1 is 1001-2000 times, ..., and PEG7 is 7000 times and above. If the current erase / write count is 850, then the corresponding target erase / write count group is PEG0.

[0081] S305. Group the target word line positions and target erasure times to determine multiple parameter values.

[0082] In some possible embodiments, a parameter coefficient table is obtained; multiple parameter values ​​are determined in multiple coefficient tables of the parameter coefficient table based on the target word line position and the target erase / write count.

[0083] The parameter coefficient table can include multiple sub-coefficient tables corresponding to multiple adjustment parameters. Each sub-coefficient table includes multiple parameter values, and each parameter value is associated with its corresponding word line position group and erase / write count group.

[0084] When the adjustment parameters include position-related parameters, aging parameters, and position compensation parameters, the parameter coefficient table can include three sub-coefficient tables: the sub-coefficient table corresponding to the position-related parameters, the sub-coefficient table corresponding to the aging parameters, and the sub-coefficient table corresponding to the position compensation parameters.

[0085] Specifically, based on the target word line position group and the target erase / write count group, the parameter values ​​corresponding to the position-related parameters are matched from the sub-coefficient table corresponding to the position-related parameters; based on the target word line position group and the target erase / write count group, the parameter values ​​corresponding to the position compensation parameters are matched from the sub-coefficient table corresponding to the position compensation parameters; based on the target word line position group and the target erase / write count group, the parameter values ​​corresponding to the aging parameters are matched from the sub-coefficient table corresponding to the aging parameters.

[0086] In this application, by setting corresponding sub-coefficient tables for different adjustment parameters and performing precise matching based on target word line position grouping and target erase / write count grouping, the reliability of parameter value determination can be improved, thereby enhancing the accuracy of reference voltage adjustment.

[0087] S306. For any given predicted reference voltage, among N preset reference voltages, determine the first reference voltage and the second reference voltage corresponding to the predicted reference voltage.

[0088] Specifically, the first reference potential and the second reference potential corresponding to the predicted reference voltage can be determined, the voltage corresponding to the first reference potential is determined as the first reference voltage, and the voltage corresponding to the second reference potential is determined as the second reference voltage.

[0089] Among them, the first reference potential and the second reference potential associated with the predicted reference potential can be selected from N preset reference potentials, and must satisfy the requirement that they have a strong correlation with the predicted reference potential (verified through pre-testing).

[0090] For example, assume the voltages corresponding to the three preset reference potentials are Vref1, Vref3, and Vref5, and the predicted reference voltages to be predicted are Vref2, Vref4, Vref6, and Vref7. The first reference potential corresponding to Vref2 is Vref1, and the second reference voltage is Vref3; the first reference potential corresponding to Vref4 is Vref3, and the second reference voltage is Vref5; the first reference potential corresponding to Vref6 is Vref4, and the second reference voltage is Vref5; the first reference potential corresponding to Vref7 is Vref5, and the second reference voltage is Vref6, where Vref6 has already been predicted through the previous steps.

[0091] S307. Determine the word line position difference and erase / write cycle difference corresponding to the flash memory cell.

[0092] In some possible embodiments, the reference word line position and reference erase / write count corresponding to the flash memory cell are obtained; the difference between the current word line position and the reference word line position is determined as the word line position difference; and the difference between the current erase / write count and the reference erase / write count is determined as the erase / write count difference.

[0093] The word line position difference is used to describe the spatial offset of the current word line position relative to the reference word line position, and can quantify the degree of change in charge coupling effect caused by the difference in physical distance between different word line positions.

[0094] The erase / write cycle difference is used to describe the cumulative aging amount of the current erase / write cycle relative to the baseline erase / write cycle, and can characterize the incremental degree of charge trap layer degradation of the flash memory cell during use.

[0095] The reference erase / write count and reference word line position can be obtained through pre-testing. The reference word line position is usually selected from the middle region word line where the charge coupling effect is most stable (such as the middle word line of linear drift grouping). The reference erase / write count is generally set to the number of erase / write counts in the initial state of the device (such as the initial erase / write stage within 100 times).

[0096] In this application, word line position difference and erase / write cycle difference can be introduced as dynamic adjustment variables to achieve differentiated parameter compensation for flash memory cells at different usage stages and spatial locations, thereby improving the precision and adaptability of reference voltage adjustment.

[0097] S308. Determine the predicted reference voltage based on multiple parameter values, the first reference voltage, the second reference voltage, the word line position difference, and the erase / write cycle difference.

[0098] In some embodiments, a first adjustment value is determined based on the first reference voltage, the second reference voltage, and the corresponding parameter value of the position-related parameter; a second adjustment value is determined by multiplying the difference in erase / write cycles and the corresponding parameter value of the aging parameter; a third adjustment value is determined by multiplying the word line position difference and the corresponding parameter value of the position compensation parameter; and the sum of the first reference voltage, the first adjustment value, the second adjustment value, and the third adjustment value is determined as the predicted reference voltage.

[0099] Specifically, the first adjustment value can be determined as follows: the difference between the first reference voltage and the second reference voltage is determined as the first adjustment voltage; the product of the parameter value corresponding to the position-related parameter and the first adjustment voltage is determined as the first adjustment value.

[0100] The calculation formula for any predicted reference voltage is as follows:

[0101]

[0102] in, Predicted reference voltage, To predict the first reference voltage corresponding to the reference voltage, To predict the second reference voltage corresponding to the reference voltage, This represents the difference in the number of erase / write cycles. This is the difference in the position of the character lines. For location-related parameters, For aging parameters, These are the position compensation parameters.

[0103] The correspondence between each part of the formula and the adjustment value is as follows: Corresponding to the first adjustment value, Corresponding to the second adjustment value, This corresponds to the third adjustment value.

[0104] This application constructs a multi-parameter prediction model involving word line position, erase / write cycles, and aging degree, organically combining the reference voltage with dynamic compensation terms to achieve accurate calculation of the predicted reference voltage. It retains the reference characteristics of the preset reference voltage while quantifying the impact of position offset and aging accumulation on the voltage through a difference compensation mechanism, effectively improving the dynamic adaptability and computational efficiency of reference voltage adjustment. This model is suitable for threshold voltage calibration requirements of high-capacity flash memory devices throughout their entire lifecycle.

[0105] The reference voltage determination method provided in this application obtains the current word line position and current erase / write count corresponding to the flash memory cell by detecting N preset reference voltages corresponding to N preset reference potentials; determines the target word line position group corresponding to the current word line position and the target erase / write count group corresponding to the current erase / write count, and then determines multiple parameter values; for any predicted reference voltage, the predicted reference voltage can be determined based on the first and second reference voltages corresponding to the predicted reference voltage, as well as multiple parameter values, word line position difference, and erase / write count difference. Only N preset reference voltages need to be detected to derive the remaining MN predicted reference voltages, significantly reducing the workload of direct detection and significantly improving the reference voltage adjustment efficiency while ensuring accuracy.

[0106] After obtaining the M reference voltages corresponding to the flash memory cells, if the bit error rate (BER) is too high, it indicates that the predicted reference voltage among the M reference voltages may be deviated. The reference voltages need to be recalibrated, and the parameters updated and adjusted based on the detection results. Based on the above embodiments, the following... Figure 4 The update process will be explained in detail.

[0107] Figure 4 This is a schematic flowchart illustrating an update processing method provided in an embodiment of this application. Please refer to [link / reference]. Figure 4 The method may include:

[0108] S401. Obtain the current bit error rate corresponding to the flash memory cell.

[0109] Bit error rate (BER) is usually defined as the ratio of the number of erroneous bits to the total number of bits. The current BER can be calculated by using the ECC (Error Check and Correction) module built into the flash memory controller to count the number of erroneous bits and the total number of transmitted bits in real time.

[0110] S402. If the current bit error rate is greater than the preset value, then detect at least one actual reference voltage corresponding to at least one predicted reference potential.

[0111] For example, the preset value corresponding to the bit error rate can be set according to the flash memory type and application scenario. For example, TLC flash memory can usually be set to 0. (i.e., 0.01%~0.1%), QLC flash memory can be set to a higher threshold (e.g. This application does not impose specific restrictions on preset values. In scenarios with low data reliability requirements (such as consumer-grade storage), larger preset values ​​can be set, while in industrial-grade high-reliability scenarios, smaller values ​​should be set.

[0112] S403. Update the parameter values ​​corresponding to each adjustment parameter based on at least one predicted reference voltage and at least one actual reference voltage.

[0113] In some embodiments, the voltage difference between the predicted reference voltage and the actual reference voltage corresponding to each predicted reference potential can be determined; for any adjustment parameter, the parameter value corresponding to the adjustment parameter is updated based on the voltage difference corresponding to each predicted reference potential.

[0114] Each adjustment parameter can be updated by using the voltage difference corresponding to each predicted reference potential.

[0115] It can obtain the adjustment coefficient corresponding to the adjustment parameter; determine the average voltage value of the voltage difference corresponding to each predicted reference potential; and determine the updated adjustment parameter value by summing the product of the parameter value corresponding to the adjustment parameter and the adjustment coefficient and the average voltage value.

[0116] Taking the adjustment of position-related parameters as an example, the following formula can be used to determine the update parameters:

[0117]

[0118] in, The updated position-related parameter values ​​are the parameter values ​​corresponding to the updated position. The parameter values ​​corresponding to the position-related parameters before the update. These are the adjustment coefficients corresponding to the location-related parameters. This is the average voltage.

[0119]

[0120] in, Where N is the total number of reference potentials, and N is the number of preset reference potentials. To predict the number of reference potentials, The actual reference voltage for the first predicted reference potential. The predicted reference voltage for the first predicted reference potential. For the first The actual reference voltage of the predicted reference potential. For the first The predicted reference voltage for each predicted reference potential.

[0121] The method provided in this application, after predicting each reference voltage of the flash memory cell, if the current bit error rate is detected to be greater than a preset value, can detect the actual reference voltage corresponding to the predicted reference potential, and then adjust each adjustment parameter by using the predicted reference voltage and the actual reference voltage, thereby correcting the adjustment parameters, improving the accuracy of subsequent predictions, and thus improving the reliability of determining the reference voltage.

[0122] Because the operating temperature of a solid-state drive (SSD) dynamically changes with environmental conditions, read / write load, and runtime, and temperature fluctuations significantly affect the threshold voltage stability of flash memory cells, low temperatures may cause the threshold voltage to increase, while high temperatures may cause it to decrease. This temperature sensitivity directly affects the accuracy of reference voltage prediction. Therefore, based on the above embodiments, it is necessary to introduce a temperature compensation mechanism to correct the impact of temperature changes on the reference voltage. The following section combines... Figure 5 The process of incorporating temperature factors into the reference voltage prediction system is explained.

[0123] Figure 5 This is a flowchart illustrating another method for determining a reference voltage provided in an embodiment of this application. Please refer to... Figure 5 The method may include:

[0124] S502. Determine the current temperature of the solid-state drive corresponding to the flash memory unit.

[0125] The current temperature of the solid-state drive (SSD) can be obtained through the temperature sensor inside the SSD.

[0126] S503: Obtain the reference temperature corresponding to the solid-state drive.

[0127] The reference temperature can be the temperature of the solid-state drive under normal operating conditions, for example, the reference temperature can be 502℃.

[0128] The normal operating conditions are: ambient temperature 25℃±2℃, sequential write load 50% of maximum bandwidth, thermal equilibrium reached after 30 minutes of continuous operation, and no forced air cooling.

[0129] S504. Based on the current temperature and the reference temperature, perform compensation processing on at least one predicted reference voltage.

[0130] In some embodiments, for any predicted reference voltage, a reference compensation coefficient can be obtained; the temperature difference between the current temperature and the reference temperature can be determined; the product of the reference compensation coefficient and the temperature difference can be used to determine the temperature compensation value; and the sum of the predicted reference voltage and the temperature compensation value can be used to determine the compensated predicted reference voltage.

[0131] The reference compensation coefficient can be the coefficient corresponding to the reference temperature, with the unit being mV / ℃. Its value is equal to the amount of reference voltage change that the read channel needs to adjust to ensure that the original bit error rate remains unchanged when the disk temperature is increased by 1℃ under normal operating conditions.

[0132] The formula for calculating temperature compensation for any predicted reference voltage is as follows:

[0133]

[0134] in, The compensated predicted reference voltage, The predicted reference voltage before compensation. The current temperature. As the reference temperature, This is the baseline compensation coefficient.

[0135] In some possible embodiments, after compensation, 1% of flash memory cells can be randomly selected for scanning and verification. If a certain flash memory cell... This triggers a local reconstruction (adjusting only the parameters corresponding to that flash memory cell). If the global error is greater than 8%, a global reconstruction is initiated.

[0136] The method provided in this application embodiment can take into account the influence of temperature on the predicted reference voltage of flash memory cells, and correct the predicted reference voltage by using temperature compensation values, thereby improving the accuracy of reference voltage prediction, reducing the read error rate, and thus improving the reliability of solid-state drives.

[0137] Figure 6 This is a schematic diagram illustrating the architecture of a method for determining a reference voltage provided in an embodiment of this application. Please refer to... Figure 6 Through local voltage detection, parameter mapping, and adaptive compensation, the reference voltage for the threshold voltage of flash memory cells can be precisely controlled in real time. The entire process is executed silently in the background by the SSD controller, achieving complete decoupling from user read and write operations and ensuring no impact on front-end performance.

[0138] The specific process is as follows: Obtain the current word line position, current erase / write count, and current temperature corresponding to the flash memory cell, and detect the N preset reference voltages for N preset reference potentials. Determine the parameter values ​​corresponding to each adjustment parameter based on the current word line position and current erase / write count, and then determine the predicted reference voltage corresponding to each predicted reference potential. Compensate the predicted reference voltage using the current temperature to obtain the actual reference voltage corresponding to each reference potential and complete the update. Obtain the current bit error rate corresponding to the flash memory cell. If the current bit error rate is greater than a preset value, update the parameter values ​​corresponding to each adjustment parameter; if the current bit error rate is less than or equal to the preset value, end the process.

[0139] Figure 7This is a schematic diagram of a reference voltage determination device provided in an embodiment of this application. Please refer to... Figure 7 The reference voltage determination device 700 includes a first detection module 701, a first acquisition module 702, a first determination module 703, and a second determination module 704.

[0140] The first detection module 701 is used to detect N preset reference voltages of N preset reference potentials corresponding to the flash memory cell. The preset reference potential is the potential used as the reference for the predicted reference voltage among the M reference potentials of the flash memory cell. N is an integer greater than or equal to 1, and M is an integer greater than N.

[0141] The first acquisition module 702 is used to acquire the current word line position and the current erase / write count corresponding to the flash memory cell;

[0142] The first determining module 703 is used to determine multiple parameter values ​​corresponding to multiple adjustment parameters based on the current word line position and the current number of erase / write cycles. The multiple adjustment parameters include position-related parameters, aging parameters, and position compensation parameters.

[0143] The second determining module 704 is used to determine at least one predicted reference voltage corresponding to at least one predicted reference potential based on multiple parameter values ​​and N preset reference voltages, wherein the at least one predicted reference potential is a potential other than the N preset reference potentials among the M reference potentials.

[0144] In some possible embodiments, the first determining module 703 is specifically used for:

[0145] Based on the multiple word line position groups corresponding to the flash memory cell, determine the target word line position group corresponding to the current word line position;

[0146] Based on the multiple erase / write count groups corresponding to the flash memory cell, determine the target erase / write count group corresponding to the current erase / write count;

[0147] Grouping by target word line position and target erasure count, multiple parameter values ​​are determined.

[0148] In some possible embodiments, the first determining module 703 is specifically used for:

[0149] Obtain the parameter coefficient table, which includes multiple sub-coefficient tables corresponding to multiple adjustment parameters. Each sub-coefficient table includes multiple parameter values, and each parameter value has its corresponding word line position grouping and erase / write count grouping.

[0150] Based on the target word line position and the target erasure count, multiple parameter values ​​are determined in multiple coefficient tables.

[0151] In some possible embodiments, for any given predicted reference voltage; the second determining module 704 is specifically used for:

[0152] Among N preset reference voltages, determine the first reference voltage and the second reference voltage corresponding to the predicted reference voltage;

[0153] Determine the word line position difference and erase / write cycle difference corresponding to the flash memory cell;

[0154] The predicted reference voltage is determined based on multiple parameter values, the first reference voltage, the second reference voltage, the word line position difference, and the erase / write cycle difference.

[0155] In some possible embodiments, the second determining module 704 is specifically used for:

[0156] Obtain the reference word line position and reference erase / write cycles corresponding to the flash memory cell;

[0157] The difference between the current character line position and the reference character line position is determined as the character line position difference;

[0158] The difference between the current number of erase / write cycles and the baseline number of erase / write cycles is defined as the erase / write cycle difference.

[0159] In some possible embodiments, the second determining module 704 is specifically used for:

[0160] The first adjustment value is determined based on the first reference voltage, the second reference voltage, and the corresponding parameter values ​​of the position-related parameters;

[0161] The product of the difference in the number of erase / write cycles and the corresponding value of the aging parameter is determined as the second adjustment value;

[0162] The product of the word line position difference and the corresponding parameter value of the position compensation parameter is determined as the third adjustment value;

[0163] The sum of the first reference voltage, the first adjustment value, the second adjustment value, and the third adjustment value is determined as the predicted reference voltage.

[0164] In some possible embodiments, the apparatus further includes a second acquisition module, a second detection module, and an update processing module:

[0165] The second acquisition module is used to acquire the current bit error rate corresponding to the flash memory cell;

[0166] The second detection module is used to detect at least one actual reference voltage corresponding to at least one predicted reference potential if the current bit error rate is greater than a preset value.

[0167] The update processing module is used to update the parameter values ​​corresponding to each adjustment parameter based on at least one predicted reference voltage and at least one actual reference voltage.

[0168] In some possible embodiments, the update processing module is specifically used for:

[0169] Determine the voltage difference between the predicted reference voltage and the actual reference voltage corresponding to each predicted reference potential;

[0170] For any given adjustment parameter, the parameter value is updated based on the voltage difference corresponding to each predicted reference potential.

[0171] In some possible embodiments, the update processing module is specifically used for:

[0172] Obtain the adjustment coefficients corresponding to the adjustment parameters;

[0173] Determine the average voltage value of the voltage difference corresponding to each predicted reference potential;

[0174] The sum of the product of the parameter value corresponding to the adjustment parameter and the adjustment coefficient and the average voltage value is determined as the parameter value corresponding to the updated adjustment parameter.

[0175] In some possible embodiments, the apparatus further includes a third determining module, a third acquiring module, and a compensation processing module:

[0176] The third determining module is used to determine the current temperature of the solid-state drive corresponding to the flash memory unit;

[0177] The third acquisition module is used to acquire the reference temperature corresponding to the solid-state drive;

[0178] The compensation processing module is used to compensate for at least one predicted reference voltage based on the current temperature and the reference temperature.

[0179] For a description of the features in the embodiment corresponding to the reference voltage determination device, please refer to the relevant description in the embodiment corresponding to the reference voltage determination method, which will not be repeated here.

[0180] Figure 8 This is a schematic diagram of the structure of an electronic device provided in this application. Figure 8 As shown, the electronic device 800 provided in this embodiment includes at least one processor 801 and a memory 802. Optionally, the electronic device 800 further includes a communication component 803. The processor 801, memory 802, and communication component 803 are connected via a bus.

[0181] In a specific implementation, at least one processor 801 executes computer execution instructions stored in memory 802, causing at least one processor 801 to execute the above-described method embodiment for determining the reference voltage.

[0182] The specific implementation process of processor 801 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0183] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0184] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0185] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0186] Embodiments of this application also provide a computer-readable storage medium storing a computer program configured to execute the steps in any of the above-described methods for determining a reference voltage.

[0187] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0188] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described methods for determining a reference voltage.

[0189] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described methods for determining a reference voltage.

[0190] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0191] The method for determining a reference voltage provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for determining a reference voltage, characterized in that, include: Detect N preset reference voltages corresponding to N preset reference potentials of the flash memory cell. The preset reference potentials are the potentials used as references for prediction reference voltages among the M reference potentials of the flash memory cell. N is an integer greater than or equal to 1, and M is an integer greater than N. Obtain the current word line position and current erase / write count corresponding to the flash memory cell; Based on the current word line position and the current number of erase / write cycles, determine multiple parameter values ​​corresponding to multiple adjustment parameters, including position-related parameters, aging parameters, and position compensation parameters; Based on the multiple parameter values ​​and the N preset reference voltages, at least one predicted reference voltage corresponding to at least one predicted reference potential is determined, wherein the at least one predicted reference potential is a potential other than the N preset reference potentials among the M reference potentials; For any given predicted reference voltage; Determining the predicted reference voltage based on the plurality of parameter values ​​and the N preset reference voltages includes: Among the N preset reference voltages, a first reference voltage and a second reference voltage corresponding to the predicted reference voltage are determined; the word line position difference and erase / write cycle difference corresponding to the flash memory cell are determined; and the predicted reference voltage is determined based on the multiple parameter values, the first reference voltage, the second reference voltage, the word line position difference, and the erase / write cycle difference.

2. The method according to claim 1, characterized in that, Based on the current character line position and the current number of erase / write cycles, determine multiple parameter values ​​corresponding to multiple adjustment parameters, including: Based on the multiple word line position groups corresponding to the flash memory cell, determine the target word line position group corresponding to the current word line position; Based on the multiple erase / write count groups corresponding to the flash memory cell, determine the target erase / write count group corresponding to the current erase / write count; The multiple parameter values ​​are determined based on the target word line position grouping and the target erase / write count grouping.

3. The method according to claim 2, characterized in that, Based on the target word line position grouping and the target erase / write count grouping, the multiple parameter values ​​are determined, including: Obtain a parameter coefficient table, which includes multiple sub-coefficient tables corresponding to the multiple adjustment parameters. Each sub-coefficient table includes multiple parameter values, and each parameter value has its corresponding word line position grouping and erase / write count grouping. Based on the target word line position grouping and the target erase / write count grouping, the multiple parameter values ​​are determined in the multiple coefficient tables.

4. The method according to claim 1, characterized in that, Determining the word line position difference and erase / write cycle difference corresponding to the flash memory cell includes: Obtain the reference word line position and reference erase / write count corresponding to the flash memory cell; The difference between the current character line position and the reference character line position is determined as the character line position difference; The difference between the current number of erase / write cycles and the baseline number of erase / write cycles is defined as the erase / write cycle difference.

5. The method according to claim 1, characterized in that, The predicted reference voltage is determined based on the plurality of adjustment parameters, the first reference voltage, the second reference voltage, the word line position difference, and the erase / write cycle difference, including: The first adjustment value is determined based on the first reference voltage, the second reference voltage, and the corresponding parameter values ​​of the position-related parameters; The product of the difference in the number of erase / write cycles and the corresponding parameter value of the aging parameter is determined as the second adjustment value; The product of the word line position difference and the corresponding parameter value of the position compensation parameter is determined as the third adjustment value; The sum of the first reference voltage, the first adjustment value, the second adjustment value, and the third adjustment value is determined as the predicted reference voltage.

6. The method according to claim 1, characterized in that, After determining at least one predicted reference voltage corresponding to at least one predicted reference potential based on the plurality of parameter values ​​and the N preset reference voltages, the method further includes: Obtain the current bit error rate corresponding to the flash memory cell; If the current bit error rate is greater than a preset value, then detect at least one actual reference voltage corresponding to the at least one predicted reference potential; The parameter values ​​corresponding to each adjustment parameter are updated based on the at least one predicted reference voltage and the at least one actual reference voltage.

7. The method according to claim 6, characterized in that, Based on the at least one predicted reference voltage and the at least one actual reference voltage, the parameter values ​​corresponding to each adjustment parameter are updated, including: Determine the voltage difference between the predicted reference voltage and the actual reference voltage corresponding to each predicted reference potential; For any given adjustment parameter, the parameter value corresponding to the adjustment parameter is updated based on the voltage difference corresponding to each predicted reference potential.

8. The method according to claim 7, characterized in that, Based on the voltage difference corresponding to each predicted reference potential, the parameter values ​​corresponding to the adjustment parameters are updated, including: Obtain the adjustment coefficient corresponding to the adjustment parameter; Determine the average voltage value of the voltage difference corresponding to each predicted reference potential; The sum of the product of the parameter value corresponding to the adjustment parameter and the product of the adjustment coefficient and the average voltage value is determined as the parameter value corresponding to the updated adjustment parameter.

9. The method according to claim 1, characterized in that, After determining at least one predicted reference voltage corresponding to at least one predicted reference potential based on the plurality of parameter values ​​and the N preset reference voltages, the method further includes: Determine the current temperature of the solid-state drive corresponding to the flash memory unit; Obtain the reference temperature corresponding to the solid-state drive; The at least one predicted reference voltage is compensated based on the current temperature and the reference temperature.

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