Synchronous self-refreshing tri-mode hardened trigger and memory unit resistant to single-event upsets

Abstract

The application relates to a synchronous self-refresh triple-mode hardened flip-flop and storage unit against single event upset, wherein the commonly used flip-flop in the art is triple-backed, the output of each path is filtered and combined by a voter filter combination circuit to vote and filter, and the final Q value is output. When the enable signal is at a low level, the flip-flop can also be synchronously held and self-refreshed to effectively increase the single event upset resistance of the flip-flop in combination with the aforementioned circuit backup design.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit rugged design technology, and relates to a synchronous self-refreshing tri-mode rugged trigger and memory cell that resists single-event upsets. Background Technology

[0002] As semiconductor processes advance to deep submicron and nanometer scales, the sensitivity of integrated circuits to single-event effects (SEE) has increased significantly. Among these, SEE is the most common radiation effect, manifested as data bit flipping caused by high-energy particles impacting the sensitive nodes of memory cells. In the aerospace field, SEE can have catastrophic consequences, making the development of reliable radiation-hardened triggers an urgent need. When a high-energy particle enters the sensitive node of a trigger, the particle generates a large number of electron-hole pairs through ionization along its track. Under the strong electric field of a reverse-biased PN junction, these charges rapidly drift, diffuse, and are collected. The collected charges alter the node potential, generating transient pulses. If the abnormal potential disturbance at the node persists long enough, it can propagate through a feedback loop to the complementary node, ultimately disrupting the node's original steady state and causing a SEE event in the trigger, resulting in trigger malfunction. Therefore, how to harden the design of triggers has become a pressing technical problem. Summary of the Invention

[0003] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a synchronous self-refreshing tri-mode hardened trigger with latch anti-single-event upset and a data storage unit, which can effectively realize the hardened design of the trigger.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, a synchronous self-refreshing tri-mode hardened trigger that resists single-event upsets is provided, including inverter INV1, inverter INV2, inverter INV3, signal transmission unit, three-way trigger unit and voting filter combination circuit;

[0006] The input of inverter INV1 is used to receive the enable signal and connect to the enable terminal of the signal transmission unit. The output of inverter INV1 is connected to the inverting enable terminal of the signal transmission unit. The input of inverter INV2 is used to receive the clock signal. The output of inverter INV2 is connected to the input of inverter INV3, the first clock terminal of the signal transmission unit, and the first clock terminal of the three-way flip-flop unit. The output of inverter INV3 is connected to the second clock terminal of the signal transmission unit and the second clock terminal of the three-way flip-flop unit. The input of the signal transmission unit is used to receive the data signal D. The output DN of the signal transmission unit is connected to the first input of the three-way flip-flop unit. The output of the three-way flip-flop unit is used to output the final result of the flip-flop. The output of the voting filter combination circuit is connected to the second input of the three-way flip-flop unit and the latch control terminal of the signal transmission unit. The input of the voting filter combination circuit is connected to the output of the three-mode flip-flop.

[0007] In one embodiment, the voter filter combination circuit includes AND gate AND1, AND gate AND2, AND gate AND3, AND gate AND4, AND gate AND5, AND gate AND6, OR gate OR1, OR gate OR2, XOR gate XOR, tri-state gate TP, first capacitor C1 and second capacitor C2.

[0008] The two inputs of AND gate AND1 are used to connect to the first flip-flop output Q0 and the second flip-flop output Q1, respectively. The two inputs of AND gate AND2 are used to connect to the third flip-flop output Q2 and the first flip-flop output Q0, respectively. The two inputs of AND gate AND3 are used to connect to the second flip-flop output Q1 and the third flip-flop output Q2, respectively. The outputs of AND gate AND1, AND gate AND2 and AND gate AND3 are connected to the three inputs of OR gate OR1, respectively. The output of OR gate OR1 is connected to one input of XOR gate and one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded.

[0009] The two inputs of AND gate AND4 are used to connect to the first flip-flop output Q0 and the second flip-flop output Q1, respectively. The two inputs of AND gate AND5 are used to connect to the third flip-flop output Q2 and the first flip-flop output Q0, respectively. The two inputs of AND gate AND6 are used to connect to the second flip-flop output Q1 and the third flip-flop output Q2, respectively. The outputs of AND gate AND4, AND gate AND5 and AND gate AND6 are connected to the three inputs of OR gate OR2, respectively. The output of OR gate OR2 is connected to the other input of XOR gate XOR, one end of second capacitor C2 and the input of tri-state gate TP, respectively. The other end of second capacitor C2 is grounded.

[0010] The enable terminal of the tri-state gate TP is connected to the output terminal of the XOR gate, and the output terminal of the tri-state gate TP is connected to the second input terminal of the three-way flip-flop unit and the latch control terminal of the signal transmission unit, respectively.

[0011] In one embodiment, the signal transmission unit includes transistors MP1, MP2, MP3, MP4, MP5, MN1, MN2, MN3, MN4, and MN5.

[0012] The sources of transistors MP1 and MP3 are both connected to the power supply. The gates of transistors MP1 and MN4 are both connected to the output of inverter INV1. The gates of transistors MP3 and MN2 are both connected to the input of inverter INV1. The drain of transistor MP1 is connected to the source of transistor MP2. The drain of transistor MP3 is connected to the source of transistor MP4. The gates of transistors MP2 and MN1 are both used to input the data signal D. The gates of transistors MP4 and MN3 are both connected to the output of the voting filter combination circuit.

[0013] The sources of transistors MP2 and MP4 are both connected to the drain of transistor MP5. The gate of transistor MP5 is connected to the output of inverter INV3. The source of transistor MP5 and the drain of transistor MN5 are both connected to the first input of the three-way flip-flop unit. The gate of transistor MN5 is connected to the output of inverter INV2. The source of transistor MN5 is connected to the drain of transistors MN1 and MN3 respectively. The source of transistor MN1 is connected to the drain of transistor MN2. The source of transistor MN3 is connected to the drain of transistor MN4. The sources of transistors MN2 and MN4 are both grounded.

[0014] In one embodiment, the three-way trigger unit includes inverters INV4, INV5, INV6, and INV7, transmission gates TG1, TG2, and TG3.

[0015] The input of inverter INV4 is connected to the output DN of the signal transmission unit. The output of inverter INV4 is connected to the input of inverter INV5 and the input of transmission gate TG2. The output of inverter INV5 is connected to the input of inverter INV4 through transmission gate TG1. The output of transmission gate TG2 is connected to the input of inverter INV6 and the output of transmission gate TG3. The input of transmission gate TG3 is connected to the output of the voter filter combination circuit. The output of inverter INV6 is connected to the input of inverter INV7. The output of inverter INV7 is used to output the final result of the flip-flop.

[0016] The first clock inputs of transmission gates TG1 and TG2 are both connected to the output of inverter INV2. The second clock inputs of transmission gates TG1 and TG2 are both connected to the output of inverter INV3. The first clock input of transmission gate TG3 is connected to the output of inverter INV3, and the second clock input of transmission gate TG3 is connected to the output of inverter INV2.

[0017] On the other hand, a data storage unit is also provided, including the aforementioned synchronous self-refreshing tri-mode hardened trigger that resists single-event upsets.

[0018] One of the above technical solutions has the following advantages and beneficial effects:

[0019] The aforementioned synchronous self-refreshing tri-mode hardened trigger and memory unit, designed to resist single-event upsets, provides three-way backups for commonly used triggers in the field. Each output is voted on and filtered by a voting filter combination circuit before outputting the final Q value. When the enable signal is low, the trigger can also synchronously maintain and perform self-refreshing outputs, thus effectively increasing the trigger's resistance to single-event upsets in conjunction with the aforementioned circuit backup design. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a synchronous self-refreshing tri-mode hardened trigger that resists single-event upsets in one embodiment.

[0022] Figure 2 This is a schematic diagram of the voting filter combination circuit in one embodiment. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0024] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various locations throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0025] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0026] In one embodiment, such as Figure 1 As shown, a synchronous self-refreshing tri-mode hardened trigger resistant to single-event upsets is provided, including inverters INV1, INV2, and INV3, a signal transmission unit 001, a three-way trigger unit 002, and a voting filter combination circuit 003. The input terminal of inverter INV1 is used to receive the enable signal EN and is connected to the enable terminal EN of the signal transmission unit 001. The output terminal of inverter INV1 is connected to the inverting enable terminal ENB of the signal transmission unit 001. The input terminal of inverter INV2 is used to receive the clock signal CLK. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3, the first clock terminal clkn of signal transmission unit 001, and the first clock terminal clkn of three-way flip-flop unit 002. The output terminal of inverter INV3 is connected to the second clock terminal clkb of signal transmission unit 001 and the second clock terminal clkb of three-way flip-flop unit 002. The input terminal of signal transmission unit 001 is used to receive the data signal D. The output terminal DN of signal transmission unit 001 is connected to the first input terminal of three-way flip-flop unit 002. The output terminal of three-way flip-flop unit 002 is used to output the final result Q[0\1\2] of the flip-flop. The output terminal of voting filter combination circuit 003 is connected to the second input terminal of three-way flip-flop unit 002 and the latch control terminal Q of signal transmission unit 001. The input terminal of voting filter combination circuit 003 is connected to the output of three-mode flip-flops (i.e., Q0, Q1, and Q2). The final result Q[0\1\2] of the trigger represents an output of one of Q0, Q1, and Q2.

[0027] The signal transmission unit 001 is used to convert the data signal D into the data signal DN for output. The voting filter combination circuit is used to vote and filter the output of the three-mode flip-flop. The three-way flip-flop unit 002 is used to output the final Q value after voting and filtering by the voting filter combination circuit to remove single-particle transients, or the self-refreshed Q value.

[0028] It is understood that in this embodiment, the commonly used triggers in the art are backed up in three ways. The output of each way is voted on and filtered by the voting filter combination circuit 003 before outputting the final Q value (such as Q[0\1\2]). When the enable signal EN is low, the trigger can synchronously maintain and perform self-refresh output, thereby effectively increasing the trigger's resistance to single-event upsets in combination with the aforementioned circuit backup design. The voting filter combination circuit 003 can be designed according to the actual engineering situation, as long as it can achieve the required voting and filtering functions.

[0029] Specifically, the aforementioned synchronous self-refreshing tri-mode hardened flip-flop with single-event upset resistance expands the traditional master-slave D flip-flop structure with three-way backup circuitry, enabling redundant data storage. Furthermore, when a single-event upset occurs in any of the three flip-flops, for example, when Q0 experiences a single-event upset, but the other two outputs Q1 and Q2 remain correct, the voting process of the voting filter combination circuit 003 ensures that only one output flipping does not change the final output's Q value. Since voting requires at least two outputs to change the final output through "voting," the correct Q value is maintained, thus achieving single-event upset resistance.

[0030] Furthermore, if any one of the three flip-flops experiences a single-event transient, or if the voting filter combination circuit 003 experiences a single-event transient, filtering can be used to ensure the correct Q value is still output. By controlling the enable signal EN to be low, the redundant three channels read the correct Q value and can then self-refresh before outputting. In other words, the improved circuit also adds synchronization hold and self-refresh functions.

[0031] In one embodiment, such as Figure 2 As shown, the voting filter combination circuit 003 includes AND gate AND1, AND gate AND2, AND gate AND3, AND gate AND4, AND gate AND5, AND gate AND6, OR gate OR1, OR gate OR2, XOR gate XOR, tri-state gate TP, first capacitor C1 and second capacitor C2.

[0032] The two inputs of AND gate AND1 are used to connect the first flip-flop output Q0 and the second flip-flop output Q1, respectively. The two inputs of AND gate AND2 are used to connect the third flip-flop output Q2 and the first flip-flop output Q0, respectively. The two inputs of AND gate AND3 are used to connect the second flip-flop output Q1 and the third flip-flop output Q2, respectively. The outputs of AND gates AND1, AND gate AND2, and AND gate AND3 are connected to the three inputs of OR gate OR1, respectively. The output of OR gate OR1 is connected to one input of XOR gate XOR and one end of the first capacitor C1, with the other end of the first capacitor C1 grounded.

[0033] The two inputs of AND gate AND4 are used to connect to the first flip-flop output Q0 and the second flip-flop output Q1, respectively. The two inputs of AND gate AND5 are used to connect to the third flip-flop output Q2 and the first flip-flop output Q0, respectively. The two inputs of AND gate AND6 are used to connect to the second flip-flop output Q1 and the third flip-flop output Q2, respectively. The outputs of AND gates AND4, AND gate AND5, and AND gate AND6 are connected to the three inputs of OR gate OR2, respectively. The output of OR gate OR2 is connected to the other input of XOR gate XOR, one end of the second capacitor C2, and the input of tri-state gate TP, respectively. The other end of the second capacitor C2 is grounded. The enable terminal of tri-state gate TP is connected to the output of XOR gate XOR, and the output of tri-state gate TP is connected to the second input of the three-way flip-flop unit and the latch control terminal of the signal transmission unit, respectively.

[0034] It is understood that this embodiment employs... Figure 2 The structure design of the voting filter combination circuit 003 shown is designed to achieve efficient voting and filtering functions, resist single-event upsets, and at the same time, to achieve miniaturization of the circuit unit by utilizing the gate circuit structure design.

[0035] Specifically, in the outputs Q0, Q1, and Q2 of the three-mode flip-flop, Q0, Q1, and Q2 are connected in pairs to the AND gates of the voting filter combination circuit 003, and then through the corresponding OR gates to output multiple values ​​to realize the voting function. However, the voting result (QB2) may have transient glitches, so after a delay by the first capacitor C1, the result QB1 is obtained, and the other redundant circuit outputs the result QB2 after a delay by the second capacitor C2. The result QB1 and the result QB2 are XORed by the XOR gate. When the voltage states of QB1 and QB2 are the same, for example, both are high level (1), the XOR gate outputs a low level (corresponding to the normal operating condition), and the low level enables, so QB2 is directly output to Q. When the voltage states of QB1 and QB2 are different, for example, QB1 is high level (1) and QB2 is low level (0), the XOR gate outputs a high level (corresponding to the working condition of high-energy particle bombardment), the enable BUF (i.e. the three-state gate TP buffer) is not turned on, so QB2 cannot output to Q. At this time, the output of the three-state gate TP is a high-impedance state, which can also be called the previous state, thereby effectively filtering out single-particle transients and purifying the value of Q.

[0036] Due to design constraints, the delay of the second capacitor C2 must be greater than the propagation delay of the XOR gate itself, but less than the delay of the first capacitor C1 plus the propagation delay of the XOR gate itself, to ensure the accuracy of the subsequent output. It should be noted that both the first capacitor C1 and the second capacitor C2 can be designed using MOS transistors. In a MOS transistor, the gate and substrate are separated by a thin oxide insulating layer. When a voltage is applied to the gate, a charge is induced in the semiconductor substrate below the gate, forming a capacitor called a MOS capacitor. Its capacitance is related to factors such as the gate area, the thickness of the oxide insulating layer, and the characteristics of the semiconductor material. Therefore, in this embodiment, both the first capacitor C1 and the second capacitor C2 can be constructed from a single MOS transistor or by stacking multiple MOS capacitors. By using a capacitor design with a MOS transistor structure, the circuit's response speed and accuracy can be further improved while effectively reducing the circuit area. Correspondingly, the tri-state gate TP in this embodiment is a low-level enabled tri-state buffer.

[0037] In one embodiment, such as Figure 1 As shown, the signal transmission unit 001 includes transistors MP1, MP2, MP3, MP4, MP5, MN1, MN2, MN3, MN4, and MN5. The sources of transistors MP1 and MP3 are connected to the power supply Vdd. The gates of transistors MP1 and MN4 are connected to the output of inverter INV1. The gates of transistors MP3 and MN2 are connected to the input of inverter INV1. The drain of transistor MP1 is connected to the source of transistor MP2, and the drain of transistor MP3 is connected to the source of transistor MP4. The gates of transistors MP2 and MN1 are used to receive the data signal D. The gates of transistors MP4 and MN3 are connected to the output of the voting filter combination circuit.

[0038] The sources of transistors MP2 and MP4 are both connected to the drain of transistor MP5. The gate of transistor MP5 is connected to the output of inverter INV3. The source of transistor MP5 and the drain of transistor MN5 are both connected to the first input of the three-way flip-flop unit. The gate of transistor MN5 is connected to the output of inverter INV2. The source of transistor MN5 is connected to the drain of transistors MN1 and MN3 respectively. The source of transistor MN1 is connected to the drain of transistor MN2. The source of transistor MN3 is connected to the drain of transistor MN4. The sources of transistors MN2 and MN4 are both grounded (gnd).

[0039] It can be understood that transistor MN refers to an N-channel MOS transistor, and transistor MP refers to a P-channel MOS transistor. This embodiment uses... Figure 1 The circuit structure design of the signal transmission unit 001 shown can efficiently achieve the above-mentioned signal transmission function with a relatively simple circuit structure, and can also efficiently support the implementation of self-refresh:

[0040] First, EN is controlled by an external asynchronous signal. When EN is low (0), the signal transmission unit 001 inputs the state of the previous Q, realizing the synchronization holding function controlled by the clock signal CLK.

[0041] Next, when CLK is high, the Q output is in the D state. When CLK is low, Q0, Q1, and Q2 are input to transmission gate TG3 through the voter filter combination circuit 003. Transmission gate TG3 is open, thus realizing the self-refresh function. The Q value of the self-refresh input has been voted on and is therefore the correct value.

[0042] Furthermore, the aforementioned design of the synchronous self-refreshing tri-mode hardened trigger with single-event upset resistance also incorporates a clock margin. This clock margin refers to the ability of the hardened circuit, when applied in practical engineering scenarios with long-path data input, to self-refresh and wait for the next clock cycle if synchronous sampling cannot be performed within one clock cycle. This effectively increases the time margin. Through the coordinated operation of various circuit units, the circuit's resistance to single-event transients and single-event upsets can be effectively improved.

[0043] In one embodiment, such as Figure 1 As shown, the three-way trigger unit 002 includes inverters INV4, INV5, INV6, and INV7, transmission gates TG1, TG2, and TG3. The input of inverter INV4 is connected to the output DN of the signal transmission unit. The output of inverter INV4 is connected to the input of inverter INV5 and the input of transmission gate TG2. The output of inverter INV5 is connected to the input of inverter INV4 through transmission gate TG1. The output of transmission gate TG2 is connected to the input of inverter INV6 and the output of transmission gate TG3. The input of transmission gate TG3 is connected to the output of the voting filter combination circuit. The output of inverter INV6 is connected to the input of inverter INV7. The output of inverter INV7 is used to output the final result Q[0\1\2] of the trigger.

[0044] The first clock inputs of transmission gates TG1 and TG2 are both connected to the output of inverter INV2. The second clock inputs of transmission gates TG1 and TG2 are both connected to the output of inverter INV3. The first clock input of transmission gate TG3 is connected to the output of inverter INV3, and the second clock input of transmission gate TG3 is connected to the output of inverter INV2.

[0045] It is understood that this embodiment adopts Figure 1 The circuit structure design of the three-way trigger unit 002 shown can efficiently realize the above-mentioned output control function with a relatively simple circuit structure, and reliably achieve anti-single-event upset when combined with the voting unit filter combination circuit 003.

[0046] In one embodiment, a data storage unit is also provided, including the aforementioned single-event upset resistant synchronous self-refreshing tri-mode hardened trigger.

[0047] The aforementioned data storage unit, by applying the aforementioned synchronous self-refreshing tri-mode hardened trigger with anti-single-event upset capability, effectively enhances the anti-single-event upset capability of the storage unit, thereby improving the reliability of the storage unit under high-energy particle irradiation environment.

[0048] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A synchronous self-refreshing tri-mode hardened trigger resistant to single-event upsets, characterized in that, The filter combination circuit comprises an inverter INV1, an inverter INV2, an inverter INV3, a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP4, a transistor MP5, a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a transistor MN5, a three-way flip-flop unit and a voter filter combination circuit. The source of the transistor MP1 and the source of the transistor MP3 are connected to a power supply, the gate of the transistor MP1 and the gate of the transistor MN4 are connected to the output of the inverter INV1, the gate of the transistor MP3 and the gate of the transistor MN2 are connected to the input of the inverter INV1, the drain of the transistor MP1 is connected to the source of the transistor MP2, the drain of the transistor MP3 is connected to the source of the transistor MP4, and the gate of the transistor MP2 and the gate of the transistor MN1 are connected to a data signal D. The source of the transistor MP2 and the source of the transistor MP4 are connected to the drain of the transistor MP5, the source of the transistor MN5 is connected to the drain of the transistor MN1 and the drain of the transistor MN3, the source of the transistor MN1 is connected to the drain of the transistor MN2, the source of the transistor MN3 is connected to the drain of the transistor MN4, the source of the transistor MN2 and the source of the transistor MN4 are connected to ground, the input of the inverter INV1 is connected to an enable signal, the input of the inverter INV2 is connected to a clock signal, the output of the inverter INV2 is connected to the input of the inverter INV3, the gate of the transistor MN5 and the first clock end of the three-way flip-flop unit, the output of the inverter INV3 is connected to the gate of the transistor MP5 and the second clock end of the three-way flip-flop unit, the source of the transistor MP5 and the drain of the transistor MN5 are connected to the first input end of the three-way flip-flop unit, the output of the three-way flip-flop unit is used to output a final result of the flip-flop, and the output of the voter filter combination circuit is connected to the second input end of the three-way flip-flop unit, the gate of the transistor MP4 and the gate of the transistor MN3, and the input of the voter filter combination circuit is connected to the output of the three-mode flip-flop.

2. The single event upset immune synchronous self-refresh triple modular hardened flip-flop of claim 1, wherein, The filter combination circuit comprises an inverter INV1, an inverter INV2, an inverter INV3, a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP4, a transistor MP5, a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a transistor MN5, a three-way flip-flop unit and a voter filter combination circuit. The two inputs of the AND gate AND1 are connected to the output Q0 of the first flip-flop and the output Q1 of the second flip-flop, the two inputs of the AND gate AND2 are connected to the output Q2 of the third flip-flop and the output Q0 of the first flip-flop, the two inputs of the AND gate AND3 are connected to the output Q1 of the second flip-flop and the output Q2 of the third flip-flop, the outputs of the AND gate AND1, the AND gate AND2 and the AND gate AND3 are connected to the three inputs of the OR gate OR1, the output of the OR gate OR1 is connected to one input of the XOR gate and one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to ground. The two input terminals of the AND gate AND4 are connected to the output Q0 of the first flip-flop and the output Q1 of the second flip-flop respectively, the two input terminals of the AND gate AND5 are connected to the output Q2 of the third flip-flop and the output Q0 of the first flip-flop respectively, the two input terminals of the AND gate AND6 are connected to the output Q1 of the second flip-flop and the output Q2 of the third flip-flop respectively, the output terminals of the AND gate AND4, the AND gate AND5 and the AND gate AND6 are connected to the three input terminals of the OR gate OR2 respectively, the output terminal of the OR gate OR2 is connected to the other input terminal of the XOR gate, one end of the second capacitor C2 and the input terminal of the tri-state gate TP respectively, and the other end of the second capacitor C2 is grounded; The enable terminal of the tri-state gate TP is connected to the output terminal of the XOR gate, and the output terminal of the tri-state gate TP is connected to the second input terminal of the three flip-flop unit and the gate of the transistor MP4 and the transistor MN3 respectively.

3. The single event upset immune synchronous self-refresh triple modular robust flip-flop according to claim 1 or 2, characterized in that The three flip-flop unit comprises an inverter INV4, an inverter INV5, an inverter INV6, an inverter INV7, a transmission gate TG1, a transmission gate TG2 and a transmission gate TG3; The input terminal of the inverter INV4 is connected to the source of the transistor MP5 and the drain of the transistor MN5 respectively, the output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5 and the input terminal of the transmission gate TG2 respectively, the output terminal of the inverter INV5 is connected to the input terminal of the inverter INV4 through the transmission gate TG1, the output terminal of the transmission gate TG2 is connected to the input terminal of the inverter INV6 and the output terminal of the transmission gate TG3 respectively, the input terminal of the transmission gate TG3 is connected to the output terminal of the filter combination circuit of the voter, the output terminal of the inverter INV6 is connected to the input terminal of the inverter INV7, and the output terminal of the inverter INV7 is used to output the final result of the flip-flop; The first clock terminals of the transmission gates TG1 and TG2 are connected to the output terminal of the inverter INV2, the second clock terminals of the transmission gates TG1 and TG2 are connected to the output terminal of the inverter INV3, the first clock terminal of the transmission gate TG3 is connected to the output terminal of the inverter INV3, and the second clock terminal of the transmission gate TG3 is connected to the output terminal of the inverter INV2.

4. A data storage unit, characterized by The anti-single event upset synchronous self-refresh three-mode hardened flip-flop comprises the anti-single event upset synchronous self-refresh three-mode hardened flip-flop according to any one of claims 1 to 3.

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