Method of improving channel carrier mobility and semiconductor structure

Abstract

The application discloses a method for improving channel carrier mobility and a semiconductor structure, and belongs to the semiconductor field. First, a first recess is etched in an active region of a semiconductor substrate, then a piezoelectric material is filled in the first recess to form a piezoelectric material layer; a second recess is etched in the piezoelectric material layer; a semiconductor material of the same type as a well region of the active region is epitaxially formed in the second recess to form a compensation semiconductor layer; a gate oxide layer is prepared on the compensation semiconductor layer; and a gate is prepared on the gate oxide layer. The semiconductor structure prepared by the method has the piezoelectric material inserted into both ends of a channel region, and the channel carrier mobility is unexpectedly improved by the inverse piezoelectric effect of the piezoelectric material by using a high voltage electric field existing in a drain without additional voltage; and the piezoelectric material also has an insulating isolation effect, thereby further improving the insulation between the gate and the drain and reducing the carrier thermal effect at the drain.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, and relates to a complementary metal oxide semiconductor device manufacturing technology, in particular to a method for improving channel carrier mobility and a semiconductor structure. BACKGROUND

[0002] With the complementary metal oxide semiconductor device (CMOS) process size being scaled down to deep submicron size, due to the fact that the power supply voltage cannot be reduced in proportion with the decrease of the device channel length, junction depth and gate oxide thickness and the increase of the substrate doping concentration, the channel lateral electric field and longitudinal electric field are significantly increased. The high electric field will accelerate the movement of carriers, thereby making the carriers become hot carriers with high energy, and further causing the phenomenon of device performance degradation, which is generally referred to as channel hot carrier effect (CHC).

[0003] The causes of channel hot carrier effect are as follows:

[0004] When the device works in the high drain voltage (V DS ) and saturation region near the drain of the MOSFET, a very strong lateral electric field (up to 10 6 V / cm order) will be formed in the channel pinch-off region. The electric field will accelerate the carriers (such as electrons in NMOS) in the channel, so that they obtain high kinetic energy and become hot carriers. These high-energy carriers may:

[0005] Impact ionization: high-energy electrons collide with lattice atoms to generate additional electron-hole pairs (secondary carriers); holes are absorbed by the substrate (forming substrate current I SUB I), and electrons can be collected by the drain.

[0006] Gate oxide injection: part of the hot carriers obtain enough energy to overcome the Si-SiO2 potential barrier (~3.2 eV for electrons and ~4.5 eV for holes), and are injected into the gate oxide layer; these trapped charges will cause threshold voltage (V th ) drift, transconductance (g m ) drop and other degradation.

[0007] Interface traps: high-energy carriers destroy the Si-SiO2 interface and generate defect states (interface traps), which further affect the device characteristics.

[0008] One important direction to improve the channel hot carrier effect is to use the strain silicon technology, by applying stress to the channel region to improve the carrier mobility of the channel region, reduce the operating voltage, indirectly reduce the high-energy carrier, so as to achieve the purpose of improving the channel hot carrier effect.

[0009] Piezoelectric materials can generate electric field due to mechanical deformation (piezoelectric effect), or mechanical deformation due to electric field (inverse piezoelectric effect), this inherent machine-electric coupling effect makes piezoelectric materials widely used in engineering; Because there is an electric field in the complementary metal oxide semiconductor device itself, plus the strain silicon technology can improve the carrier mobility, so the piezoelectric material is used in the complementary metal oxide semiconductor device, in theory, it can improve the channel carrier mobility, so as to achieve the effect of improving the channel hot carrier effect.

[0010] The prior art CN116247087A discloses a trench power device with enhanced charge carrier mobility, an insulating structure is provided between a transistor gate and a sidewall of a gate trench, the insulating structure is configured to electrically insulate the transistor gate from a channel region extending along the sidewall of the gate trench, the insulating structure includes a piezoelectric material layer or a combination layer of a pressure material layer and other insulating material; In fact, it is to replace the original gate oxide layer with a combination layer of piezoelectric material layer or pressure material layer and other insulating material; The inverse piezoelectric effect is generated by the gate electric field to improve the carrier mobility of the channel; It has a certain effect; However, as a basic common sense, the insulating performance of piezoelectric material is usually weaker than that of traditional gate oxide, so after replacing the gate oxide layer with a piezoelectric material layer, the insulating performance will definitely decrease, even if AlN with very good insulating property is used, according to the technology, it needs about 2.5 times the thickness of the gate oxide to achieve the same voltage blocking effect; As can be seen, the use of strain silicon technology in this technology causes the insulating function of the "gate oxide layer" to weaken, or in order to meet the basic requirements, the thickness of the "gate oxide layer" must be increased; The insufficient insulating property of the gate oxide layer will cause gate leakage, which will accelerate the aging of the gate oxide layer, and the local electric field concentration will cause the accumulation of micro defects, and eventually cause dielectric breakdown (shorten the service life); Leakage may enhance the channel high-energy carrier injection into the gate oxide layer, further causing the generation of interface state Si-SiO2 interface traps; Thus, the effect of improving the carrier mobility by the inverse piezoelectric effect disappears; Therefore, this technology uses the strain silicon technology to bring technical progress, but also leaves technical risks, before finding a piezoelectric material with excellent insulating property, the application scenario of this technology is very low.

[0011] The prior art CN115020427A discloses a semiconductor structure with a transistor on a semiconductor wafer on an insulator and a forming and operating method thereof, specifically, a piezoelectric material layer is arranged below the channel, and two electrodes are additionally arranged at both ends of the piezoelectric material, the piezoelectric material layer is deformed by applying a voltage to the two electrodes, and the deformed piezoelectric material layer generates stress on the channel to improve the carrier mobility of the channel; this technology not only has a complex manufacturing process, but also increases many structures, and the manufacturing cost is very high, and then an additional voltage needs to be applied when in use, resulting in high device energy consumption and low reliability.

[0012] The prior art CN119497564A discloses a power device and a preparation method, a power module, a power conversion circuit and a vehicle, specifically, a first piezoelectric material is arranged above the gate to cover it, a first electrode and a second piezoelectric material layer are arranged below the channel to replace the substrate, the second piezoelectric material layer and the first electrode replace the substrate, on the one hand, the substrate resistance is saved, and the on-resistance is reduced; on the other hand, the first piezoelectric material layer and the second piezoelectric material layer are deformed by applying a voltage thereto, and an additional electric field is generated on the gate structure, thereby improving the mobility and conductivity of charge carriers in the semiconductor structure, and improving the switching speed and conductivity of the device; although this technology utilizes the piezoelectric effect of the piezoelectric material to improve the carrier mobility of the channel region, the technology also needs to additionally set electrodes and electric fields, which not only has a complex structure, but also has high energy consumption.

[0013] Therefore, although the piezoelectric material has some applications in improving the carrier mobility of the channel, there are still various problems, and therefore how to set a suitable piezoelectric material layer to improve the carrier mobility of the channel still needs a lot of research. SUMMARY

[0014] One of the purposes of the present application is to provide a method for improving the carrier mobility of the channel, by inserting a piezoelectric material at a specific position in the channel through a specific process sequence, utilizing the inverse piezoelectric effect of the piezoelectric material under the high electric field of the drain to generate stress on the channel region, thereby improving the carrier mobility of the channel, and the piezoelectric material also increases the insulation of the gate oxide layer, avoiding the electron migration between the gate and the channel; thereby greatly improving the channel hot carrier effect.

[0015] Another purpose of the present application is to use the above-mentioned method for improving the carrier mobility of the channel to prepare a semiconductor structure, so that the prepared semiconductor structure has a higher limit use voltage, better electrical performance and durability.

[0016] In order to solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0017] In one aspect, the present application provides a method for improving channel carrier mobility, comprising the following steps:

[0018] providing a semiconductor substrate having a plurality of active regions separated by isolation structures;

[0019] etching a first recess on the surface of the active region;

[0020] filling the first recess with piezoelectric material to form a piezoelectric material layer;

[0021] etching a second recess in the piezoelectric material layer;

[0022] epitaxially growing a compensation semiconductor layer in the second recess with the same type of semiconductor material as the well region of the active region;

[0023] forming a gate oxide layer on the compensation semiconductor layer;

[0024] forming a gate on the gate oxide layer.

[0025] Further, the piezoelectric material includes any one or a combination of MoS2, AlN, AlScN, and ZnO.

[0026] Further, the first recess is formed on the surface of the active region by dry etching or wet etching.

[0027] Further, the process of filling the first recess with piezoelectric material includes chemical vapor deposition (CVD), physical vapor deposition (PVD), and solution method.

[0028] Further, the depth of the first recess is 10 angstroms-2000 angstroms.

[0029] Further, the second recess is formed in the piezoelectric material layer by dry etching.

[0030] Further, after etching the second recess, the minimum width of the sidewall of the second recess and the sidewall of the first recess is 10 angstroms-1500 angstroms.

[0031] Further, the gate oxide layer is formed on the compensation semiconductor layer by furnace tube gate oxidation method, and the thickness of the formed gate oxide layer is 10 angstroms-1000 angstroms.

[0032] In another aspect, the present application provides a semiconductor structure, comprising a substrate, a well region formed in the substrate, a gate oxide layer and a gate formed above the well region, source and drain formed in the well region on both sides of the gate, the well region between the source and the drain being a channel region, a piezoelectric material layer arranged between the gate oxide layer and / or the gate and the drain, the piezoelectric material layer forming stress for improving carrier mobility of the channel region by high electric field of the drain.

[0033] Further, piezoelectric material layers are arranged at both ends of the channel region.

[0034] In another aspect, the application provides a method for preparing a semiconductor structure, comprising the following steps:

[0035] A semiconductor substrate is provided, and the semiconductor substrate has a plurality of active regions separated by isolation structures;

[0036] A first recess is etched on the surface of the active region;

[0037] A piezoelectric material is filled in the first recess to form a piezoelectric material layer;

[0038] A second recess is etched in the piezoelectric material layer;

[0039] A semiconductor material of the same type as the well region of the active region is epitaxially formed in the second recess to form a compensation semiconductor layer;

[0040] A gate oxide layer is prepared on the compensation semiconductor layer;

[0041] A gate is prepared on the gate oxide layer;

[0042] A source and a drain are prepared to obtain a semiconductor structure.

[0043] Compared with the prior art, the application has the following advantages:

[0044] The application inserts piezoelectric material into one end or both ends of the channel region by changing the process sequence, and the unexpected technical effect is that the application can not only improve the channel carrier mobility by using the inverse piezoelectric effect of the piezoelectric material, but also improve the channel carrier mobility by using the high voltage field of the drain to generate stress on the channel region by the inverse piezoelectric effect of the piezoelectric material without additional voltage; when the drain field is increased, the inverse piezoelectric effect is increased, the stress generated on the channel region is further increased, the effect of improving the carrier mobility is further improved, and within a certain range of the drain field, the application has a self-regulating effect, can improve the upper limit of the drain field under the same conditions, or can improve the reliability of the device; in addition, the piezoelectric material of the application also has an insulating isolation effect, which further improves the insulation between the gate and the drain, reduces the possibility of leakage, and also reduces the carrier thermal effect at the drain. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 The flowchart of the method for improving the channel carrier mobility in Example 1 of the application is shown.

[0046] Figure 2 The schematic diagram of the semiconductor substrate provided in Example 1 of the application is shown.

[0047] Figure 3A schematic diagram of etching a single NMOS with a first recess in step S200 of embodiment 1 of the present application.

[0048] Figure 4 A schematic diagram of filling the first recess with piezoelectric material in step S300 of embodiment 1 of the present application.

[0049] Figure 5 A schematic diagram of planarizing the piezoelectric material before making a second recess in step S400 of embodiment 1 of the present application.

[0050] Figure 6A A schematic diagram of etching a second recess in step S400 of embodiment 1 of the present application.

[0051] Figure 6B A schematic diagram of etching a second recess directly on the piezoelectric material layer in step S400 of embodiment 1 of the present application.

[0052] Figure 7A A schematic diagram of epitaxial semiconductor material in the second recess made in step S400 of embodiment 1 of the present application.

[0053] Figure 7B A schematic diagram of epitaxial semiconductor material in the second recess made in step S400 of embodiment 1 of the present application.

[0054] Figure 8 A schematic diagram of planarizing the epitaxial semiconductor material to obtain a compensation semiconductor layer in step S500 of embodiment 1 of the present application.

[0055] Figure 9 A schematic diagram of making a gate oxide layer in the compensation semiconductor layer in step S600 of embodiment 1 of the present application.

[0056] Figure 10 A schematic diagram of making a dummy gate structure on the gate oxide layer in step S710 of embodiment 1 of the present application.

[0057] Figure 11 A schematic diagram of depositing a dielectric layer on the gate oxide layer in step S720 of embodiment 1 of the present application.

[0058] Figure 12 A schematic diagram of removing the excess dielectric layer to form a gate with a side wall by anisotropic etching process in step S730 of embodiment 1 of the present application.

[0059] Figure 13 A schematic diagram of continuing to make a source and a drain to obtain a semiconductor structure in embodiment 2 of the present application.

[0060] 100 - semiconductor substrate, 110 - active region, 120 - shallow trench isolation structure; 130 - first recess;

[0061] 200 - piezoelectric material layer, 201 - piezoelectric material, 210 - second recess;

[0062] 300 - compensating semiconductor layer, 310 - semiconductor material;

[0063] 400 - gate oxide layer;

[0064] 500 - gate, 510 - dummy gate structure, 520 - side wall, 521 - dielectric layer;

[0065] 610 - source, 620 - drain. DETAILED DESCRIPTION

[0066] Embodiments of the present application will be further described below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present application, but cannot be used to limit the scope of the present application.

[0067] In the description of the present application, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0068] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "connected", "connected" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0069] Example 1: As shown in the present application, a method for improving channel carrier mobility is provided, comprising the following steps: Figure 1

[0070] S100, providing a semiconductor substrate, the semiconductor substrate having a plurality of active regions isolated by an isolation structure;

[0071] S200, etching a first recess on the surface of the active region; ​

[0072] S300: Fill the first groove with piezoelectric material to form a piezoelectric material layer;

[0073] S400, Etch a second groove in the piezoelectric material layer;

[0074] S500, a semiconductor material of the same type as the well region of the active region is epitaxially grown inside and outside the second groove to form a compensation semiconductor layer;

[0075] S600. Prepare a gate oxide layer on the compensation semiconductor layer;

[0076] S700: The gate is fabricated on the gate oxide layer.

[0077] This invention, by setting a compensating semiconductor layer, creatively inserts piezoelectric material into the end of the channel region (without completely covering the channel region in depth to meet the requirements of carrier migration in the channel region). An unexpected technical effect is that this invention does not require an additional electric field; it utilizes the high-voltage electric field of the drain to generate stress in the channel region through the inverse piezoelectric effect of the piezoelectric material, improving the carrier mobility in the channel region. When the drain electric field increases, the inverse piezoelectric effect increases, further increasing the stress generated in the channel region and further improving the carrier mobility. Within a certain range of the drain electric field, it has a self-regulating effect, and under the same conditions, it can increase the upper limit of the drain electric field or improve device reliability. In addition, the piezoelectric material of this invention also has an insulating effect, further improving the insulation between the gate and the drain, reducing the possibility of leakage, and also reducing the carrier thermal effect at the drain.

[0078] In step S100, the material of the semiconductor substrate 100 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. The semiconductor substrate 100 may also be a multilayer structure composed of these semiconductors, or may be silicon on insulator (SOI), silicon on insulator stacked on insulator (SSOI), silicon on insulator stacked on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0079] The processes for forming the well region differ depending on the semiconductor material used, but this does not affect the technical problem solved by this invention. For example, when Si semiconductor material is used as the semiconductor substrate 100, such as... Figure 2 As shown, a shallow trench isolation structure 120 (STI) can be used to isolate and form the active region 110; generally, the active region 110 includes the active region of the P-type well region and the active region of the N-type well region, corresponding to NMOS (N-type field-effect transistor) and PMOS (P-type field-effect transistor), respectively, as shown. Figure 2 As shown,Figure 2 The example shows a semiconductor structure with one NMOS and one PMOS. In reality, the number of NMOS and PMOS depends on the needs of the device. Figure 2 This is for illustrative purposes only.

[0080] S200, see also Figure 3 As shown, Figure 3 A schematic diagram of a single NMOS is shown. The method for etching the first groove 130 on the surface of the active region 110 can employ dry etching or wet etching. Before etching, photoresist is coated on the semiconductor substrate 100, and then the area to be etched is exposed in the active region 110 through exposure and development. Afterwards, dry etching or wet etching can be used. The etched first groove 130 is shown as... Figure 3 As shown; common dry etching methods include reactive ion etching (RIE) and deep reactive ion etching (DRIE). The depth of the first groove 130 basically determines the thickness of the subsequent piezoelectric material filling. If the piezoelectric material thickness is too small, the generated stress is insufficient, and the effect of improving the channel carrier mobility is limited. In addition, the insulation performance is also limited, resulting in a limited effect of improving the carrier thermal effect at the drain. If the depth of the first groove 130 is too large, it will affect the channel setting and squeeze the channel space. Therefore, a suitable depth of the first groove 130 can set a suitable piezoelectric material layer, thereby maximizing the function of the piezoelectric material. Therefore, the depth of the first groove 130 is selected in the range of 10 angstroms to 2000 angstroms. The depth is different for different types of devices. For example, for low-voltage devices (LV), the depth should be 10-100 angstroms; for medium-voltage devices (MV), it is generally around 100-1000 angstroms; and for high-voltage devices (HV), the depth is generally around 1000-2000 angstroms. The width or cross-sectional dimensions of the first groove 130 are not required. Generally, it should be approximately equal to the cross-sectional area of ​​the gate. That is, the orthogonal projection of the gate on the semiconductor substrate 100 is the starting region and shape of the first groove 130. Of course, whether the first groove 130 is slightly larger or smaller than the orthogonal projection of the gate does not affect the technical problem solved by the present invention, that is, it does not affect the role of the piezoelectric material in adaptively increasing the carrier migration rate in the present invention.

[0081] S300, see also Figure 4 As shown, before filling the first groove 130 with piezoelectric material 201, the photoresist etching the first groove 130 should be removed, and then the piezoelectric material layer 200 should be formed (e.g., ...). Figure 5As shown in FIG. 1, the common piezoelectric material 201 includes MoS2 (molybdenum disulfide), AlN (aluminum nitride), AlScN (scandium-doped aluminum nitride), ZnO (zinc oxide), and the same or different material processes can be used to fill one or a combination of the materials. In general, when filling, the first recess 130 needs to be completely filled, that is, the height is higher than the two sides of the first recess 130.

[0082] For example, MoS2 can be filled by a chemical vapor deposition (CVD) process. Molybdenum precursor such as (MoO3) and sulfur source (such as S powder) are introduced into the reaction chamber to react at high temperature (650-850°C) to generate a MoS2 material layer. The specific steps are as follows:

[0083] Step 1, precursor placement:

[0084] Place MoO3 powder (or Mo film) in the high-temperature zone (center position);

[0085] Place sulfur powder in the upstream low-temperature zone (about 15-20 cm away from the Mo source);

[0086] Place the semiconductor substrate with the first recess upside down on the Mo source in the CVD device reaction chamber (or at the edge of the downstream high-temperature zone).

[0087] Step 2, vacuum pumping:

[0088] Pump the reaction chamber to a low vacuum (~10 -2 Torr) and flush with Ar / N2 three times.

[0089] Step 3, temperature rising stage:

[0090] Rise the temperature to 150-200°C in the sulfur source zone (sulfur sublimation) at a rate of 10-20°C / min;

[0091] Rise the temperature to 650-850°C in the molybdenum source zone (MoO x , x<3) is reduced to MoO

[0092] Step 4, growth stage:

[0093] Maintain the temperature for 10-30 minutes, and the sulfur vapor reacts with MoO x to generate MoS2;

[0094] Carrier gas flow: 50-100 sccm (low-pressure growth can reduce nucleation density);

[0095] Step 5, cooling stage:

[0096] Cool naturally to below 200°C and take out the semiconductor substrate filled with piezoelectric material.

[0097] It should be noted that after the deposition of molybdenum disulfide is completed, annealing treatment can be performed to improve the deposition quality of the piezoelectric material. Specifically, annealing is performed at 300-400°C for 1 hour in an Ar / H2 (5%) atmosphere to reduce sulfur vacancies and improve the deposition quality of the piezoelectric material.

[0098] For example, taking AlN as the piezoelectric material, a physical vapor deposition (PVD) process can be used to fill the first groove 130 by sputtering or evaporating aluminum to react to form an aluminum nitride film in a nitrogen environment. Taking reactive magnetron sputtering as an example, the specific steps are as follows:

[0099] Step 1: Vacuum and pre-sputtering

[0100] The semiconductor substrate with the first groove is loaded into the cavity of the PVD device and fixed on the heating table (substrate temperature adjustable, usually 300-500°C).

[0101] Vacuum to base pressure ≤5×10 -6 Torr (ensure no oxygen, water vapor interference).

[0102] Pre-sputtering:

[0103] Introduce Ar (20-30 sccm), gas pressure 2-5 mTorr.

[0104] Turn on DC / RF power (power 100-200 W), pre-sputter aluminum target for 10-15 minutes (remove target surface oxide).

[0105] Step 2: Reactive sputtering deposition

[0106] Gas introduction:

[0107] Introduce N2 (flow rate and Ar ratio need to be optimized, typical N2:Ar=1:1 to 1:4).

[0108] Maintain working pressure 2-10 mTorr (low pressure for dense film, high pressure for high deposition rate).

[0109] Sputtering parameters:

[0110] Sputtering power: DC 150-300 W or RF 100-200 W (avoid target poisoning).

[0111] Substrate temperature: 300-500°C (high temperature improves crystal quality, but AlN decomposition needs to be avoided).

[0112] Deposition time: 1-2 hours (film thickness ~100-500 nm, rate ~0.5-2 nm / min).

[0113] Step 3: Cooling and taking out

[0114] After the deposition, the power and the gas are turned off, and the sample is naturally cooled under vacuum to below 150°C.

[0115] The normal pressure is restored by introducing high-purity N2 or Ar, and the sample is removed.

[0116] In S400, there are two process paths for etching the second groove. In a first embodiment, the filled piezoelectric material is first planarized by a CMP (chemical mechanical polishing) process before etching the second groove. After planarization, the second groove 210 is etched as shown in FIG. 2B, and the piezoelectric material layer 200 is planarized again after the subsequent deposition of the semiconductor material 310. Figure 5 Figure 6A In a second embodiment, the filled piezoelectric material 201 is not planarized, and the second groove 210 is directly etched thereon as shown in FIG. 2C, and the piezoelectric material layer 200 is planarized again after the subsequent deposition of the semiconductor material 310. Figure 6B The process of etching the second groove 210 in the two process paths is similar to the etching process of the first groove 130, and both need to first coat a photoresist on the semiconductor substrate 100, then expose the area to be etched by exposure and development, and then use dry etching or wet etching, and then clean the photoresist after etching to obtain the second groove 210. The depth of the second groove 210 is generally the same as that of the first groove 130, i.e., the piezoelectric material layer 200 needs to be etched through. The width or cross-sectional area of the second groove 210 directly affects the amount of remaining piezoelectric material, i.e., the width of the piezoelectric material layer 200 inserted into the channel region. It should be noted that since the present application mainly utilizes the high electric field of the drain 620, the piezoelectric material layer 200 needs to be inserted at least at one end of the channel region close to the drain 620, and the width of the inserted piezoelectric material layer 200 is 5 angstroms-1000 angstroms to meet the requirements of generating sufficient stress and insulation. Of course, in order to facilitate manufacturing and control, the piezoelectric material layer 200 can be inserted at both ends of the channel region, i.e., the second groove 210 is arranged centrally relative to the first groove 130 as shown in FIGS. 2D and 2E, where the left and right directions are the width directions, and the width of the piezoelectric material on the left and right sides determines the amount of remaining piezoelectric material, i.e., affects the inverse piezoelectric effect of the piezoelectric material and the increased insulation performance. Generally, the width of the remaining piezoelectric material on one side should be 5 angstroms-1000 angstroms, and the specific selection needs to be based on the voltage type of the device. Generally, the width ratio of the second groove 210 to the first groove 130 should be selected between 4-8:10. Figure 6A Figure 6B

[0117] ​​​Step S500, epitaxial semiconductor material 310 of the same type as the well region of the active region 110 in the second groove 210, form a compensation semiconductor layer 300, for example, NMOS, the well region is P-type semiconductor material, in this embodiment, P-type semiconductor material should be epitaxial, for the first process path after the planarization of the piezoelectric material 201, as shown in Figure 7A for the second process path without planarization of the piezoelectric material, as shown in Figure 7B after epitaxy, the two process paths are basically the same in epitaxy process, which can adopt chemical vapor deposition (CVD) to epitaxial P-type semiconductor material, the silicon source is silane (SiH4) or dichlorosilane (SiH2Cl2), and the doping source is trimethylboron (B(CH3)3, TMB) or diborane (B2H6); for epitaxial N-type semiconductor material, replace the corresponding doping source.

[0118] After epitaxial semiconductor material 310, planarization is needed (planarization of P-type semiconductor material by CMP process, or planarization of P-type semiconductor material and piezoelectric material together), after planarization, as shown in Figure 8 a special structure of compensation semiconductor layer 300 in the middle and piezoelectric material layer 200 at both ends is formed, in fact, it is equivalent to inserting the piezoelectric material into the channel region at both ends, the piezoelectric material layer 200 formed by the process of the application not only can fully utilize the high electric field of the drain 620 to produce inverse piezoelectric effect to produce strain on the channel region, but also can improve the insulation between the gate 500 and the drain 620, avoid the hot effect of the drain 620 under the double action mechanism, and greatly improve the limit voltage of the drain 620 in the use process of the device; It has unexpected function and effect; in addition, it also has self-adaptive adjustment effect, with the increase of the electric field of the drain 620, the inverse piezoelectric effect will also increase, the stress on the channel region will increase, within a certain range, the self-adaptive adjustment effect of improving the channel carrier mobility; The technical advantage is very obvious.

[0119] It should be noted that the inverse piezoelectric effect of different piezoelectric materials has direction difference, that is, under the electric field in a certain direction, part of the material is tensile strain, and part of the material is compressive strain, for the application, the strain direction of PMOS and NMOS channel is different, but since the electric field direction of the drain 620 of PMOS and NMOS is different, only one kind of piezoelectric material needs to be selected, which can be used for PMOS and NMOS at the same time.

[0120] In S600, the furnace tube gate oxidation method is adopted to prepare the gate oxide layer 400 on the compensation semiconductor layer 300, and the obtained gate oxide layer 400 is as shown in Figure 9As shown, the furnace tube gate oxidation method is a common gate oxide layer preparation method, which can be applied to the present application to prepare the gate oxide layer 400 in the area surrounded by the piezoelectric material layer, further improve the insulation performance of the gate oxide layer 400, improve the breakdown voltage (Breakdown Voltage, BV), and avoid the occurrence of tunneling current (Fowler-Nordheim) or direct tunneling during device use.

[0121] In S700, the gate 500 is prepared on the gate oxide layer 400, which can adopt the existing technology. For example, the present application provides a sidewall process to prepare the gate 500. The specific steps are as follows:

[0122] In S710, the pseudo-gate structure 510 is prepared on the gate oxide layer 400 by using an epitaxial process, as shown in Figure 10 The material of the pseudo-gate structure 510 can be polysilicon, high-K material or a combination of multiple materials.

[0123] For example, after the semiconductor substrate with the gate oxide layer 400 is prepared, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) process is used to deposit polysilicon.

[0124] The photoresist is coated, and the photoresist is patterned by exposure and development technology, and the photoresist above the pseudo-gate structure 510 is reserved.

[0125] The excess polysilicon is removed by etching.

[0126] The photoresist pattern is cleaned to obtain a polysilicon layer as the pseudo-gate structure 510, as shown in Figure 10 Of course, other high-K materials or a combination of high-K materials and polysilicon can also be used as the pseudo-gate structure 510.

[0127] In S720, an epitaxial dielectric layer 521 is epitaxially prepared on the polysilicon layer and the semiconductor substrate 100, as shown in Figure 11 The epitaxial material can be silicon nitride (Si3N4), silicon oxide (SiO2) or a combination of the two; the deposition process is chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0128] In S730, the dielectric layer 521 on the top of the polysilicon layer and other areas is removed by anisotropic etching process, the dielectric layer 521 on the sidewall of the polysilicon layer is reserved, the sidewall 520 is formed, and the complete gate 500 is obtained, as shown in Figure 12 .

[0129] In embodiment 2, a semiconductor structure preparation method is provided, which is based on embodiment 1. The source 610 and the drain 620 are prepared in the well area on both sides of the gate 500 to obtain a semiconductor structure, as shown in Figure 13As shown.

[0130] Example 3: This invention also protects a semiconductor structure, such as Figure 13 As shown, the device includes a substrate, a well region formed within the substrate, a gate oxide layer 400 and a gate 500 located above the well region, a source 610 and a drain 620 formed in the well regions on both sides of the gate 500, and the well region between the source 610 and the drain 620 is a channel region. A piezoelectric material layer 200 is disposed between the gate oxide layer 400 and / or the gate 500 and the drain 620. The piezoelectric material layer 200 forms stress on the channel region to improve the carrier mobility through the high electric field of the drain 620.

[0131] The above embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Although the invention has been described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications, or equivalent substitutions of the technical solutions of the invention do not depart from the spirit and scope of the invention and should be covered within the scope of the claims of the invention.

Claims

1. A method of improving channel carrier mobility, characterized by, The method comprises the following steps: providing a semiconductor substrate with a plurality of active regions isolated by isolation structures; etching a first recess on the surface of the active region; filling the first recess with piezoelectric material to form a piezoelectric material layer; etching a second recess in the piezoelectric material layer; forming a compensation semiconductor layer by epitaxially growing semiconductor material of the same type as the well region of the active region in the second recess, the second recess penetrating the piezoelectric material layer so that the compensation semiconductor layer is in contact with the active region; preparing a gate oxide layer on the compensation semiconductor layer; preparing a gate on the gate oxide layer.

2. The method of claim 1, wherein the channel carrier mobility is improved by: The piezoelectric material comprises any one of MoS2, AlN, AlScN and ZnO or a combination of several thereof.

3. The method of claim 1, wherein the channel carrier mobility is improved by: The first recess is formed on the surface of the active region by dry etching or wet etching.

4. The method for improving channel carrier mobility according to claim 1, wherein The process of filling the first recess with piezoelectric material comprises chemical vapor deposition, physical vapor deposition and solution method.

5. The method for improving channel carrier mobility as claimed in claim 1, wherein The second recess is formed in the piezoelectric material layer by dry etching.

6. The method for improving channel carrier mobility as claimed in claim 1, wherein After etching the second recess, the minimum width of the sidewall of the second recess and the sidewall of the first recess is 10 angstroms-1500 angstroms.

7. The method for improving channel carrier mobility as claimed in claim 1, wherein The gate oxide layer is prepared on the compensation semiconductor layer by furnace tube gate oxidation method, and the thickness of the prepared gate oxide layer is 10 angstroms-1000 angstroms.

8. A semiconductor structure produced by the method of any one of claims 1 to 7, said semiconductor structure comprising a substrate, a well region formed in the substrate, a gate oxide layer and a gate formed over the well region, source and drain regions formed in the well region on either side of the gate, the well region between the source and drain regions being a channel region, characterised in that, The piezoelectric material layer is arranged at least near one end of the channel region of the drain, and the piezoelectric material layer forms stress on the channel region to improve the carrier mobility through the high electric field of the drain.

9. The semiconductor structure of claim 8, wherein, The piezoelectric material layer is arranged at both ends of the channel region.

10. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a semiconductor substrate with a plurality of active regions isolated by isolation structures; etching a first recess on the surface of the active region; filling the first recess with piezoelectric material to form a piezoelectric material layer; etching a second recess in the piezoelectric material layer; forming a compensation semiconductor layer by epitaxially growing semiconductor material of the same type as the well region of the active region in the second recess, the second recess penetrating the piezoelectric material layer so that the compensation semiconductor layer is in contact with the active region; preparing a gate oxide layer on the compensation semiconductor layer; preparing a gate on the gate oxide layer; preparing a source and a drain to obtain a semiconductor structure.

Images