Semiconductor element

Abstract

The invention discloses a semiconductor element which comprises an epitaxial structure, a first electrode, an insulating structure, a barrier layer and a second electrode. The epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and an active region between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer has a first portion and a second portion. The width of the second part is smaller than that of the first part, and the first part is provided with a first side surface. The first electrode is located under the first semiconductor layer. The insulating structure is distributed on the first side surface and is provided with an opening, and the opening corresponds to the first electrode. The barrier layer covers the insulating structure distributed on the first side surface. The second electrode is located on the second semiconductor layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor optoelectronic device. Background Technology

[0002] Semiconductor components are widely used in lighting, medical, display, communication, sensing, and power systems, and research and development of related materials and products continues. III-V group semiconductor materials, including group III and group V elements, can be used in various semiconductor optoelectronic components, such as light-emitting diodes (LEDs) and laser diodes (LDs), light-absorbing components such as photodetectors or solar cells, or power components such as switching devices or rectifiers. Taking LEDs or laser diodes as examples, their basic structure includes a p-type semiconductor, an n-type semiconductor, and an active region between them. When current is applied, charge carriers combine in the active region to emit light, and the wavelength of the emitted light depends on the semiconductor material used. With technological advancements, there remains a significant demand for further research and development in semiconductor optoelectronic components. Summary of the Invention

[0003] This invention provides a semiconductor device including an epitaxial structure, a first electrode, an insulating structure, a barrier layer, and a second electrode. The epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and an active region located between the first and second semiconductor layers. The second semiconductor layer has a first portion and a second portion. The width of the second portion is smaller than the width of the first portion, and the first portion has a first side surface. The first electrode is located below the first semiconductor layer. The insulating structure is distributed on the first side surface and has an opening corresponding to the first electrode. The barrier layer covers the insulating structure distributed on the first side surface. The second electrode is located on the second semiconductor layer.

[0004] According to one embodiment of the present invention, the barrier layer fills the opening and is in direct contact with the first electrode.

[0005] According to one embodiment of the present invention, the first portion is closer to the active region than the second portion.

[0006] According to one embodiment of the present invention, the first electrode has a lower surface, and an insulating structure is distributed on a portion of the lower surface.

[0007] According to one embodiment of the present invention, the barrier layer covers an insulating structure distributed on a portion of the lower surface.

[0008] According to one embodiment of the present invention, the first electrode and the barrier layer may contain the same material.

[0009] According to one embodiment of the present invention, the material of the barrier layer comprises a metal oxide.

[0010] According to one embodiment of the present invention, the width of the second electrode is smaller than the width of the second portion.

[0011] According to one embodiment of the present invention, it further includes conductive bumps covering the second electrode.

[0012] According to one embodiment of the present invention, an adhesion layer is further included, located between the second electrode and the conductive bump. Attached Figure Description

[0013] Figure 1A This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0014] Figure 1B This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0015] Figure 1C This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0016] Figure 1D This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0017] Figure 1E This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0018] Figure 1F This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 1G This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 1H This is a partially enlarged schematic diagram of a semiconductor element according to an embodiment of the present invention;

[0021] Figure 1I This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0022] Figure 1J This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0023] Figure 1K This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0024] Figure 1L This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0025] Figure 1M This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0026] Figure 1N This is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention;

[0027] Figures 2A to 2I This is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0028] Figure 3A This is a cross-sectional structural diagram of a semiconductor component according to an embodiment of the present invention;

[0029] Figure 3B This is a cross-sectional structural diagram of a semiconductor component according to an embodiment of the present invention;

[0030] Figure 4A This is a top view schematic diagram of a display device according to an embodiment of the present invention;

[0031] Figure 4B This is a cross-sectional structural diagram of a display device according to an embodiment of the present invention.

[0032] Symbol Explanation

[0033] 10, 10', 20, 30, 40, 50, 60, 70, 80, 90A, 90B, 90C: Semiconductor components

[0034] 81: Target Carrier

[0035] 82: Pixel unit

[0036] 84: First semiconductor element

[0037] 86: Second semiconductor element

[0038] 88: Third semiconductor element

[0039] 100: Extensional structure

[0040] 100a: First semiconductor structure

[0041] 100a1: First semiconductor layer

[0042] 100a2: First contact layer

[0043] 100b: Second semiconductor structure

[0044] 100b1: Second semiconductor layer

[0045] 100b2: Second contact layer

[0046] 100c: Active region

[0047] 100s, 104s, 106s: lower surface

[0048] 100p: Contact part

[0049] 102: Insulation Structure

[0050] 102a, 104a: Open

[0051] 102t, 104t: Upper surface of the end

[0052] 104w: End side surface

[0053] 104: Barrier Layer

[0054] 106: First electrode

[0055] 108: Second electrode

[0056] 108d1: Sidewall

[0057] 108p: Electrode section

[0058] 110: Conductive bump

[0059] 112: Adhesion layer

[0060] 110s, 108d2, t1: Upper surface

[0061] 200: Joint structure

[0062] 201: First bonding layer

[0063] 202: Second bonding layer

[0064] 203: Third bonding layer

[0065] 300: Semiconductor Components

[0066] 320: Adhesive structure

[0067] 320': Sticky body

[0068] 400: Display device

[0069] 420: Dielectric structure

[0070] 440: Conductive wire

[0071] D1, D2, D3: Distance

[0072] d1: Interval

[0073] d2: Vertical distance

[0074] L: Length

[0075] W, D4: Width

[0076] R1, R2: Regions

[0077] θ1: First included angle

[0078] M1: First Platform Structure

[0079] θ2: Second included angle

[0080] M2: Second Platform Structure

[0081] p1: Part 1

[0082] w1: First width

[0083] p2: Part Two

[0084] w2: Second width

[0085] w3: Third width

[0086] w4: Fourth width

[0087] w5: Fifth width

[0088] w6: Sixth width

[0089] w7: Seventh width

[0090] w8: Eighth width

[0091] w9: Ninth width

[0092] w10: Tenth Width

[0093] s1: First side surface

[0094] s2: Second side surface

[0095] s3: Third side surface

[0096] s4: Fourth side surface

[0097] s5: Fifth side surface

[0098] c1, c2: Connecting surfaces

[0099] GS: Growth substrate

[0100] BS: Bonding substrate

[0101] TS: Temporary carrier

[0102] X-X', Y-Y', Z-Z': Lines

[0103] x, y: axes Detailed Implementation

[0104] To make the description of the present invention more detailed and complete, the following will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments of the semiconductor device used to illustrate the present invention below do not limit the present invention to the following embodiments. In the drawings or the description, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or dimensions of the components in the drawings are only for illustration and are not limited thereto in practice. It should be particularly noted that the components not described in the figures may be in forms known to those skilled in the art.

[0105] The semiconductor device of the present invention is, for example, a semiconductor optoelectronic device. The semiconductor optoelectronic device includes a light-emitting device (e.g., a light-emitting diode, a laser diode), a light-absorbing device (e.g., a photodetector), or other non-light-emitting devices. The composition and dopant of each layer included in the semiconductor device of the present invention can be analyzed by any suitable method, such as a secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

[0106] Those with ordinary knowledge in the art should understand that other components can be added based on the embodiments described below. For example, in the case where it is not specifically stated, similar descriptions such as "the first layer (structure) is located on the second layer (structure)" can include embodiments where the first layer (structure) is in direct contact with the second layer (structure), and can also include embodiments where there are other structures between the first layer (structure) and the second layer (structure) and they are not in direct contact with each other. In addition, it should be understood that the vertical and horizontal positional relationships of each layer (structure) may change depending on the viewing direction.

[0107] Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P, where 0 < x0 < 1; the general formula AlInP represents Al x1 In 1-x1 P, where 0 < x1 < 1; the general formula InGaN represents In x2 Ga 1-x2 N, where 0 < x2 < 1; the general formula AlGaN represents Al x3 Ga 1- x3N, where 0 < x3 < 1; the general formula AlGaInP represents Al x4 Ga x5 In 1-x4-x5 P, where 0 < x4 < 1 and 0 < x5 < 1; the general formula InGaAsP represents In x6 Ga 1-x6 As x7 P 1-x7 , where 0 < x6 < 1, 0 < x7 < 1; the general formula AlGaInAs represents Al x8 Ga x9 In 1-x8-x9 As, where 0 < x8 < 1, 0 < x9 < 1; the general formula InGaAs represents In x10 Ga 1-x10 As, where 0 < x10 < 1; the general formula AlGaAs represents Al x11 Ga 1-x11 As, where 0 < x11 < 1.

[0108] Figure 1A is a top view schematic diagram of the semiconductor element 10 according to an embodiment of the present invention. Figure 1B is Figure 1A a schematic cross-sectional structure diagram of the semiconductor element 10 along the X-X' line. Figure 1C is Figure 1A a schematic cross-sectional structure diagram of the semiconductor element 10 along the Y-Y' line. As Figures 1A to 1C shown, the semiconductor element 10 includes an epitaxial structure 100, an insulating structure 102, and a blocking layer 104. The epitaxial structure 100 includes a first semiconductor structure 100a, a second semiconductor structure 100b, and an active region 100c. As Figure 1B shown, the second semiconductor structure 100b is located on the first semiconductor structure 100a. The active region 100c is located between the first semiconductor structure 100a and the second semiconductor structure 100b. The first semiconductor structure 100a has a first conduction type, and the second semiconductor structure 100b has a second conduction type different from the first conduction type. The first semiconductor structure 100a and the second semiconductor structure 100b can respectively provide electrons and holes (or holes and electrons). For example, the first conduction type is n-type and the second conduction type is p-type, or the first conduction type is p-type and the second conduction type is n-type. The conduction types of the first semiconductor structure 100a and the second semiconductor structure 100b can be adjusted by adding different dopants. For example, the first semiconductor structure 100a includes a first dopant, and the second semiconductor structure 100b includes a second dopant different from the first dopant. The first dopant and the second dopant can be elements of Group II, Group IV, or Group VI in the periodic table of elements, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si), or tellurium (Te), etc.

[0109] According to one embodiment, when the semiconductor element 10 is a light-emitting element, electrons and holes can combine in the active region 100c to emit light with a peak wavelength. This light can be visible or invisible. Specifically, the peak wavelength may depend on the material composition of the active region 100c. For example, when the material of the active region 100c contains AlGaN, it can emit ultraviolet light with a peak wavelength of 250nm to 400nm; when the material of the active region 100c contains InGaN, it can emit deep blue or blue light with a peak wavelength of 400nm to 490nm, or green or yellow light with a peak wavelength of 490nm to 550nm, or red light with a peak wavelength of 560nm to 650nm; when the material of the active region 100c contains InGaP or AlGaInP, it can emit yellow, orange, or red light with a peak wavelength of 530nm to 700nm; when the material of the active region 100c contains InGaAs, InGaAsP, AlGaAs, or AlGaInAs, it can emit infrared light with a peak wavelength of 700nm to 1700nm.

[0110] like Figure 1A As shown, the semiconductor element 10 may have a length L and a width W. The length L and width W may be less than or equal to 500 μm, for example, less than or equal to 450 μm, 400 μm, 350 μm, 300 μm, 250 μm, 200 μm, 150 μm, 100 μm, 50 μm, 30 μm, or 10 μm, and may be greater than or equal to 1 μm. Viewed from above, the semiconductor element 10 may be rectangular or circular. In one embodiment, the length L and width W of the semiconductor element 10 may be approximately equal, forming a square. In one embodiment, the top-view area (L × W) of the semiconductor element 10 is 10000 μm. 2 Below, for example at 1μm 2 Up to 5000μm 2 Within the range (e.g., 100μm) 2 625μm 2 1250μm 2 2000μm 2 Or 2500μm 2 In one embodiment, viewed from above, the diagonal length of the semiconductor element 10 may be greater than 1 μm and less than 100 μm. According to one embodiment, the total thickness of the epitaxial structure 100 is, for example, in the range of 1 μm to 5 μm, to further reduce the element thickness and facilitate element miniaturization.

[0111] The first semiconductor structure 100a may include a first semiconductor layer 100a1 and a first contact layer 100a2. The first semiconductor layer 100a1 is closer to the active region 100c than the first contact layer 100a2. The second semiconductor structure 100b may include a second semiconductor layer 100b1 and a second contact layer 100b2. The second semiconductor layer 100b1 is closer to the active region 100c than the second contact layer 100b2. Figure 1B As shown, a first semiconductor layer 100a1 and a second semiconductor layer 100b1 may be adjacent to the active region 100c. The second semiconductor layer 100b1 has a first portion p1 and a second portion p2. The second portion p2 is located on and connected to the first portion p1. The first portion p1 is closer to the active region 100c than the second portion p2. In this embodiment, the first portion p1 has a first width w1, and the second portion p2 has a second width w2. The first width w1 is, for example, the maximum width of the first portion p1. The second width w2 is, for example, the maximum width of the second portion p2. The second width w2 may be smaller than the first width w1. The first portion p1 may also have a third width w3 different from the first width w1. The second portion p2 may also have a fourth width w4 different from the second width w2. The third width w3 is, for example, the minimum width of the first portion p1. The fourth width w4 is, for example, the minimum width of the second portion p2. The fourth width w4 may be smaller than the third width w3.

[0112] like Figure 1B As shown, the first portion p1 has a first side surface s1, the second portion p2 has a second side surface s2, and the first portion p1 may optionally have a connecting surface c1 located between the first side surface s1 and the second side surface s2 to connect the first side surface s1 and the second side surface s2. In this embodiment, the active region 100c may have a third side surface s3, the first semiconductor layer 100a1 may have a fourth side surface s4, and the first contact layer 100a2 may have a fifth side surface s5. Figure 1B As shown, the first side surface s1, the third side surface s3, the fourth side surface s4, and the fifth side surface s5 are connected. The extension structure 100 may have a lower surface 100s. The lower surface 100s may be connected to the fifth side surface s5.

[0113] An insulating structure 102 covers a portion of the surface of the epitaxial structure 100, thereby providing insulation and protection for the epitaxial structure 100. The insulating structure 102 can be a single-layer or multi-layer structure. For example... Figure 1BAs shown, the insulating structure 102 may be distributed on the first side surface s1, the third side surface s3, the fourth side surface s4, and the fifth side surface s5. The insulating structure 102 may be distributed on a portion or the entire first side surface s1. The insulating structure 102 may be selectively distributed on a portion of the lower surface 100s. In this embodiment, the insulating structure 102 is continuously distributed on a portion of the lower surface 100s, the fifth side surface s5, the fourth side surface s4, the third side surface s3, and the first side surface s1. In one embodiment, the material of the insulating structure 102 may include oxides (such as silicon oxide (SiO2)). x ) or aluminum oxide (AlO x )), nitrides (such as aluminum nitride (AlN), silicon nitride (SiN) x )) or fluorides (such as magnesium fluoride (MgF) x The thickness of the insulating structure 102 is, for example, in... Within the range. According to one embodiment, the insulating structure 102 may have multiple layers, such as including a first insulating layer (not shown) and a second insulating layer (not shown), the first insulating layer directly contacting the epitaxial structure 100 while the second insulating layer covering the first insulating layer, the density of the first insulating layer may be higher than that of the second insulating layer, which helps to further improve the protective effect. For example, the first insulating layer may be formed by atomic layer deposition (ALD), and the second insulating layer may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) (such as plasma-enhanced chemical vapor deposition (PECVD)). In one embodiment, the first insulating layer may contain alumina (AlO2). x The second insulating layer may contain silicon oxide (SiO2). x The insulating structure 102 may also optionally include a third insulating layer (not shown) covering the second insulating layer. The density of the third insulating layer may be higher than that of the second insulating layer, for example, it may contain alumina (Al₂O₃). x Furthermore, it is formed using atomic layer deposition (ALD), which helps to further improve the protective effect.

[0114] The barrier layer 104 may cover a portion or the entire insulating structure 102 and may serve as an etching barrier layer. The insulating structure 102 may be located between the barrier layer 104 and the epitaxial structure 100 and may be in direct contact with the barrier layer 104. By providing the barrier layer 104 in the semiconductor device 10, for example when the semiconductor device 10 needs to be subjected to processing such as laser to transfer the semiconductor device 10, the barrier layer 104 can further protect the insulating structure 102 and the epitaxial structure 100, preventing damage to the insulating structure 102 and the active region 100c of the semiconductor device 10. The barrier layer 104 may be a single layer or a multilayer structure. The material of the insulating structure 102 and the material of the barrier layer 104 may be different. For example, according to one embodiment, the barrier layer 104 may have better etching resistance than the insulating structure 102 for fluorine-containing gases (such as carbon tetrafluoride (CF4)). The barrier layer 104 may cover the insulating structure 102 distributed at different locations. For example, as Figure 1B As shown, the insulating structure 102 distributed on the lower surface 100s, the fifth side surface s5, the fourth side surface s4, the third side surface s3, and / or the first side surface s1 can be covered by the barrier layer 104. In this embodiment, the barrier layer 104 continuously covers the insulating structure 102.

[0115] like Figure 1B As shown, the insulating structure 102 may have an end upper surface 102t, and the barrier layer 104 may have an end upper surface 104t. The end upper surfaces 102t and 104t may be flush or not flush. In some embodiments, a portion of the barrier layer 104 may extend to cover the end upper surface 102t, or a portion of the insulating structure 102 may extend to cover the end upper surface 104t. Figure 1B As shown, the insulating structure 102 and the barrier layer 104 may not cover the second side surface s2 and the connecting surface c1. In some embodiments, the barrier layer 104 may not cover the first side surface s1, the second side surface s2, the third side surface s3, the fourth side surface s4, and / or the fifth side surface s5. In one embodiment, the barrier layer 104 is located only at the lower surface 100s.

[0116] The thickness of the barrier layer 104 is, for example, in Within the range. The material of the barrier layer 104 can be a conductive material or an insulating material. In this embodiment, the material of the barrier layer 104 is conductive, and the barrier layer 104 can simultaneously have protective and conductive functions. According to one embodiment, the conductive material may include metal oxides. Metal oxides are, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO), etc. In one embodiment, the material of the insulating structure 102 is an oxide or nitride (such as aluminum oxide (AlOx), silicon nitride (SiNx), or silicon oxide (SiOx)), while the material of the barrier layer 104 is a metal oxide (such as indium tin oxide (ITO)). According to one embodiment, when the material of the barrier layer 104 is a metal oxide, static electricity can be avoided during the device fabrication process, improving the stability of the fabrication process.

[0117] like Figure 1A and Figure 1B As shown, the semiconductor element 10 further includes a first electrode 106 and a second electrode 108. The first electrode 106 is located below the first semiconductor structure 100a and can directly contact the first contact layer 100a2 to form an electrical connection. The second electrode 108 is located on the second semiconductor structure 100b and can directly contact the second contact layer 100b2 to form an electrical connection. The first electrode 106 and the second electrode 108 can be single-layer or multi-layer structures, respectively. In this embodiment, the lower surface 100s of the epitaxial structure 100 is also the lower surface of the first contact layer 100a2. The first electrode 106 can cover all or part of the lower surface 100s. Figure 1B As shown, the first electrode 106 can cover the entire lower surface 100s. The first electrode 106 has a lower surface 106s, and the insulating structure 102 can be distributed on a portion of the lower surface 106s. In one embodiment, the barrier layer 104 can also cover the insulating structure 102 distributed on a portion of the lower surface 106s. According to one embodiment, when the semiconductor element 10 is a light-emitting element, the material of the barrier layer 104 can be transparent to the light emitted by the active region 100c, and the light emitted by the active region 100c can, for example, pass through the first semiconductor structure 100a, the first electrode 106, the insulating structure 102, and the barrier layer 104 before being emitted. In some embodiments, the lower surface 104s of the barrier layer 104 can serve as the main light-emitting surface of the semiconductor element 10.

[0118] like Figure 1B As shown, the insulating structure 102 may have an opening 102a corresponding to the first electrode 106, thereby providing the current path required for the operation of the semiconductor device 10. Figure 1BAs shown, the barrier layer 104 can fill the opening 102a and directly contact the first electrode 106. In one embodiment, one side of the barrier layer 104 is in direct contact with the first electrode 106, and the other side (lower surface 104s) can be in direct contact with an external conductive structure (not shown) to form an electrical connection. The first electrode 106 may have a fifth width w5. The opening 102a may have a sixth width w6. The second electrode 108 may have a seventh width w7. The sixth width w6 may be less than or equal to the fifth width w5. In this embodiment, the first width w1 > the fifth width w5 > the second width w2 > the sixth width w6 > the seventh width w7. The materials of the first electrode 106 and the second electrode 108 may be the same or different. The first electrode 106 and the second electrode 108 may, for example, contain a transparent conductive material, a metal, or an alloy. Transparent conductive materials include metal oxides, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin zinc oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). Metals may include, for example, gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), copper (Cu), or nickel (Ni). Alloys may contain at least two elements selected from the group consisting of the aforementioned metals, such as germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc. According to one embodiment, the first electrode 106 and the barrier layer 104 may contain the same material. Therefore, the first electrode 106 and the barrier layer 104 can have better adhesion, preventing the barrier layer 104 from easily peeling off. For example, the materials of the first electrode 106 and the barrier layer 104 both include metal oxides, such as indium tin oxide (ITO).

[0119] Semiconductor element 10 may optionally include conductive bumps 110 covering the second electrode 108. Specifically, conductive bumps 110 may cover the sidewalls 108d1 and the upper surface 108d2 of the second electrode 108. Conductive bumps 110 can be used to form electrical and / or physical connections with external circuits (such as circuit boards). As shown in Figure 2B, the upper surface 110s of conductive bumps 110 may not be parallel to the upper surface 108d2 of the second electrode 108. In this embodiment, the upper surface 110s of conductive bumps 110 may be arc-shaped. In some embodiments, conductive bumps 110 may also have other cross-sectional shapes such as trapezoidal, rectangular, or irregular shapes. The material of conductive bumps 110 may include metals or alloys, and for example, low-melting-point metals or alloys with low liquefaction melting points. The aforementioned low melting point or low liquefaction temperature is, for example, below 210°C. Specifically, the aforementioned metal or alloy includes, for example, bismuth (Bi), tin (Sn), indium (In), or alloys thereof. According to one embodiment, when the semiconductor element 10 needs to be transferred, the upper surface 110s of the conductive bump 110 has a convex arcuate design, which allows the semiconductor element 10 to be easily fixed to a bonding substrate (not shown) by embedding a bonding structure (not shown) on the side of the conductive bump 110 away from the second electrode 108, thus facilitating subsequent transfer fabrication processes of the semiconductor element 10. The conductive bump 110 is located on the second semiconductor layer 100b1 and the second contact layer 100b2.

[0120] like Figure 1B As shown, in cross-section, the upper surface t1 of the second portion p2 may have an eighth width w8, and in this embodiment, the eighth width w8 is the minimum width of the second portion p2, therefore the eighth width w8 is equal to the fourth width w4. In other embodiments, the eighth width w8 may be greater than or less than the fourth width w4. The conductive bump 110 may have a ninth width w9. The ninth width w9 may be greater than, less than, or equal to the eighth width w8. In this embodiment, the eighth width w8 may be equal to the ninth width w9, or the width difference between the eighth width w8 and the ninth width w9 may be less than or equal to 5% of the eighth width w8. According to one embodiment, the top view area of ​​the conductive bump 110 is, for example, within 10% to 80% of the top view area of ​​the semiconductor element 10.

[0121] The semiconductor element 10 may optionally include an adhesion layer 112 located between the second electrode 108 and the conductive bump 110. The adhesion layer 112 can directly contact the second electrode 108 and the conductive bump 110 to improve the adhesion stability between the second electrode 108 and the conductive bump 110, preventing insufficient adhesion strength between the second electrode 108 and the conductive bump 110 from peeling off from the semiconductor element 10. According to one embodiment, the adhesion layer 112 and the barrier layer 104 may contain the same material. Specifically, the adhesion layer 112 may contain a conductive material, such as a metal oxide. Examples of metal oxides include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO).

[0122] Figure 1D This is a cross-sectional structural diagram of a semiconductor device 20 according to an embodiment of the present invention. In the semiconductor device 20, the barrier layer 104 is made of an insulating material. Therefore, the barrier layer 104 can simultaneously provide both protection and insulation. The insulating material may include oxides, nitrides, or fluorides, such as aluminum oxide (AlOx), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx). Figure 1D As shown, the barrier layer 104 may have an opening 104a, which corresponds to the opening 102a of the first electrode 106 and the insulating structure 102. The opening 104a has a tenth width w10. The tenth width w10 may be less than or equal to the sixth width w6. Thus, the barrier layer 104 can sufficiently cover the insulating structure 102 to provide protection. In this embodiment, a portion of the lower surface 106s of the first electrode 106 may directly contact an external conductive structure (not shown) to form an electrical connection. The positions, relative relationships, material compositions, and structural variations of the layers or structures in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0123] Figure 1EThis is a cross-sectional structural diagram of a semiconductor element 30 according to an embodiment of the present invention. In the semiconductor element 30, the ninth width w9 of the conductive bump 110 is smaller than the eighth width w8. According to one embodiment, the top-view area of ​​the conductive bump 110 is, for example, within 10% to 50% of the top-view area of ​​the semiconductor element 10. In some embodiments, by adjusting the ninth width w9 and the top-view area of ​​the conductive bump 110 to the above range, the fabrication process margin can be improved, and the yield reduction caused by inaccurate alignment during the formation of the conductive bump 110 can be avoided. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in previous embodiments and will not be repeated here.

[0124] Figure 1F This is a cross-sectional structural diagram of a semiconductor element 40 according to an embodiment of the present invention. In the semiconductor element 40, the ninth width w9 of the conductive bump 110 may be greater than the eighth width w8. In this embodiment, the conductive bump 110 may cover and directly contact the second side surface s2 of the second portion p2. Specifically, the conductive bump 110 may cover a portion or the entire second side surface s2. In other embodiments, the conductive bump 110 may further cover a portion or the entire connection surface c1. Figure 1F As shown, conductive bumps 110 continuously cover the second side surface s2 and the upper surface t1 of the second portion p2. In some embodiments, by having the conductive bumps 110 cover and directly contact the second side surface s2, the contact area between the conductive bumps 110 and the epitaxial structure 100 can be further increased, which helps to further improve the conductivity. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0125] Figure 1G This is a cross-sectional structural diagram of a semiconductor element 50 according to an embodiment of the present invention. Figure 1H This is an enlarged schematic diagram of region R1 in semiconductor element 50. (See diagram below.) Figure 1G and Figure 1H As shown, in this embodiment, the connecting surface c1 is not flush with the end upper surface 102t and / or the end upper surface 104t. Figure 1G and Figure 1HAs shown, the cross-section of the connecting surface c1 can be arc-shaped. In some embodiments, the cross-section of the connecting surface c1 can also have other cross-sectional shapes, such as irregular shapes. Specifically, the cross-sectional shape of the connecting surface c1 is formed, for example, by etching. In this embodiment, the connecting surface c1 can be lower than the end upper surface 102t and / or the end upper surface 104t. In the vertical direction, the maximum distance D1 between the connecting surface c1 and the end upper surface 102t and / or the end upper surface 104t is, for example, in the range of 0.3 μm to 1 μm. Thus, a portion of the insulating structure 102 near the end upper surface 102t is not connected to the epitaxial structure 100. Figure 1H As shown, the ends of the insulating structure 102 and the ends of the barrier layer 104 can form a region R2 that does not directly contact the epitaxial structure 100. In the horizontal direction, the maximum distance D2 between the region R2 and the epitaxial structure 100 is, for example, in the range of 0.5 μm to 2 μm.

[0126] exist Figure 1H In one embodiment, the upper end surface 102t is flush with the upper end surface 104t. In another embodiment, the upper end surface 102t may be lower than or higher than the upper end surface 104t. Figure 1H As shown, the insulating structure 102 may have a first included angle θ1 with an imaginary horizontal line passing through the upper end surface 102t, where 30° < θ1 < 90°. The first side surface s1 and the connecting surface c1 may have a second included angle θ2. In this embodiment, 0° < θ2 < 60°. In one embodiment, the insulating structure 102 and / or the barrier layer 104 have a width that gradually decreases from the first portion p1 to the second portion p2; that is, the width of the insulating structure 102 near the upper end surface 102t is smaller than the width away from the upper end surface 102t, and / or the width of the barrier layer 104 near the upper end surface 104t is smaller than the width away from the upper end surface 104t. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in previous embodiments and will not be repeated here.

[0127] Figure 1I This is a schematic cross-sectional view of a semiconductor element 60 according to an embodiment of the present invention. In the semiconductor element 60, as... Figure 1IAs shown, the second electrode 108 may include a plurality of electrode portions 108p that are separated from each other. The second contact layer 100b2 may also include a plurality of contact portions 100p that are separated from each other and correspond to the portions of the second electrode 108. The number of electrode portions 108p and contact portions 100p may be between 2 and 10, respectively. From a top view, the plurality of electrode portions 108p may be arranged symmetrically or asymmetrically with respect to the geometric center of the second semiconductor structure 100b. According to some embodiments, by providing a plurality of electrode portions 108p and a plurality of contact portions 100p, the electrical performance of the semiconductor element 60 can be further optimized. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0128] Figure 1J This is a schematic cross-sectional view of a semiconductor element 70 according to an embodiment of the present invention. In the semiconductor element 70, as... Figure 1J As shown, the first side surface s1 of the first portion p1 and the second side surface s2 of the second portion p2 can be directly connected (i.e., there is no connecting surface c1). In this embodiment, the first width w1 is equal to the second width w2. The upper surface t1 of the second portion p2 may have a bump structure. The bump structure is, for example, the morphology left after removing the growth substrate by growing the epitaxial structure 100 on a patterned growth substrate (not shown), or by etching the epitaxial structure 100 (e.g., dry etching or wet etching). The second contact layer 100b2 and the second electrode 108 can conformally cover the bump structure of the upper surface t1.

[0129] Figure 1K This is a schematic cross-sectional view of a semiconductor element 80 according to an embodiment of the present invention. In the semiconductor element 80, as... Figure 1K As shown, the first side surface s1 of the first part p1 and the second side surface s2 of the second part p2 can be directly connected (i.e., there is no connecting surface c1). The first width w1 is equal to the second width w2. The third width w3 is less than the fourth width w4. In this embodiment, the third side surface s3, the fourth side surface s4, and the fifth side surface s5 are inclined surfaces, that is, the absolute value of the slope of the third side surface s3, the fourth side surface s4, and the fifth side surface s5 is greater than 0. The third side surface s3, the fourth side surface s4, and the fifth side surface s5 may have the same or different slopes. In some embodiments, the lower surface 100s of the epitaxial structure 100 may also have a roughened structure to further improve the light extraction efficiency. The above-mentioned roughened structure includes, for example, a plurality of protrusions arranged regularly or irregularly, as detailed below. Figures 1L to 1N Examples of implementations.

[0130] Figure 1LThis is a schematic cross-sectional view of a semiconductor device 90A according to an embodiment of the present invention. In the semiconductor device 90A, the lower surface 100s of the epitaxial structure 100 may have a roughened structure Rs. In this embodiment, as... Figure 1L As shown, the first electrode 106 may discontinuously cover the lower surface 100s. Specifically, this structure is formed, for example, by etching (e.g., dry etching or wet etching) a portion of the first electrode 106 and the first contact layer 100a2 after forming the first electrode 106 covering the entire lower surface 100s of the epitaxial structure 100, thereby forming the roughened structure Rs. Furthermore, the insulating structure 102 conformally covers a portion of the roughened structure Rs, and the barrier layer 104 also conformally covers the insulating structure 102 and the roughened structure Rs.

[0131] Figure 1M This is a schematic cross-sectional view of a semiconductor device 90B according to an embodiment of the present invention. In the semiconductor device 90B, the lower surface 100s of the epitaxial structure 100 may have a roughened structure Rs. In this embodiment, as... Figure 1M As shown, the first electrode 106 can continuously cover the lower surface 100s. Specifically, this structure is formed, for example, by first etching (e.g., dry etching or wet etching) the lower surface 100s of the epitaxial structure 100 to form a roughened structure Rs, and then forming the first electrode 106 that continuously covers the lower surface 100s. Similarly, the first electrode 106 conformally covers the roughened structure Rs, the insulating structure 102 conformally covers a portion of the first electrode 106, and the barrier layer 104 also conformally covers the insulating structure 102 and the first electrode 106.

[0132] The semiconductor device in the embodiments of the present invention may also have other different states, such as Figure 1N The diagram shown is a cross-sectional view of a semiconductor element 90C according to an embodiment of the present invention. In the semiconductor element 90C, the second width w2 is greater than the first width w1, and the fourth width w4 is greater than the third width w3. The second portion p2 may also optionally have a connecting surface c2 located between the first side surface s1 and the second side surface s2, connecting the first side surface s1 and the second side surface s2. In this embodiment, the insulating structure 102 is continuously distributed on a portion of the lower surface 100s, the fifth side surface s5, the fourth side surface s4, the third side surface s3, the first side surface s1, and the connecting surface c2. The insulating structure 102 may not cover the second side surface s2.

[0133] In this embodiment, the barrier layer 104 and the first electrode 106 are located on different sides of the epitaxial structure 100. For example... Figure 1NAs shown, the barrier layer 104 covers the upper surface t1 of the second portion p2, and also covers the second electrode 108 and the second contact layer 100b2. Specifically, the barrier layer 104 may continuously cover the upper surface t1, the sidewalls 108d1 and 108d2 of the second electrode 108. The semiconductor device 90C may also optionally include conductive bumps 110 covering the first electrode 106 and a portion of the insulating structure 102. Figure 1N As shown, the semiconductor device 90C may optionally include a reflective structure 114. The reflective structure 114 is, for example, located between the conductive bump 110 and the first electrode 106, thereby reflecting light emitted from the active region 100c so that light exits from the upper surface t1 and forms an electrical connection with the first electrode 106. The reflective structure 114 may fill the opening 102a and directly contact the first electrode 106. The reflective structure 114 may be a single-layer or multi-layer structure. Specifically, the material of the reflective structure 114 may include metals. Examples of metals include chromium (Cr), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), copper (Cu), or nickel (Ni).

[0134] The upper surface t1 of the second portion p2 may selectively have a roughened structure Rs'. For example, before or after the formation of the second electrode 108, an etching process (such as dry etching or wet etching) is performed to remove a portion of the second semiconductor layer 100b1, thereby forming the roughened structure Rs'. The barrier layer 104 may conformally cover the roughened structure Rs'. In this embodiment, the roughened structure Rs' has a plurality of protrusions Rs1, and the shortest distance D3 between the protrusions Rs1 and the second side surface s2 in the horizontal direction is greater than the width D4 of the connecting surface c2, thereby enhancing the structural stability of the second portion p2 near the second side surface s2. In another embodiment, the shortest distance D3 may be less than or equal to the width D4. The shortest distance D3 is, for example, in the range of 0.5 μm to 4 μm. The width D4 is, for example, in the range of greater than 0 μm to less than or equal to 2.5 μm. In one embodiment, the second portion p2 has a thickness k1, which is, for example, in the range of greater than 0.5 μm to less than or equal to 2.5 μm.

[0135] In this embodiment, by providing a barrier layer 104 on the upper surface t1, the barrier layer 104 can protect the epitaxial structure 100, for example, when it is necessary to apply a process such as laser to the semiconductor element 90C from the upper surface t1 side to transfer the semiconductor element 90C. On the other hand, by providing a reflective structure 114, light can be emitted from the upper surface t1, and the light emission efficiency can be further improved by roughening the structure Rs'. In this embodiment, the material of the barrier layer 104 is conductive, and it can have both protective and conductive functions. In another embodiment, when it is desired to use an insulating material as the barrier layer 104, an opening (not shown) corresponding to the second electrode 108 can be further formed in the barrier layer 104, so that the second electrode 108 can directly contact an external conductive structure (not shown) to form an electrical connection. Figures 1J to 1N The positions, relative relationships, material composition, and structural variations of each layer or structure in the embodiments have been described in detail in the previous embodiments and will not be repeated here.

[0136] Based on the above, in the present invention, for example, by providing a barrier layer in the element, a good structural protection can be formed for the element, and it can have the effect of improving production yield. The above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, semiconductor element 20 may also have a conductive bump 110 structure as in semiconductor element 30 or semiconductor element 40, a region R1 structure as in semiconductor element 50, a second electrode 108 and second contact layer 100b2 structure as in semiconductor element 60, a concave-convex structure as in semiconductor element 70, an epitaxial structure contour as in semiconductor element 80, or a roughened structure as in semiconductor element 90A or semiconductor element 90B; semiconductor element 30 or semiconductor element 40 may also have a region R1 structure as in semiconductor element 50, a second electrode 108 and second contact layer 100b2 structure as in semiconductor element 60, a concave-convex structure as in semiconductor element 70, an epitaxial structure contour as in semiconductor element 80, or a roughened structure as in semiconductor element 90A or semiconductor element 90B. The roughened structure in 0B; the semiconductor element 50 may also have a structure such as the second electrode 108 and the second contact layer 100b2 in the semiconductor element 60, a concave-convex structure such as the semiconductor element 70, an epitaxial structure outline such as the semiconductor element 80, or a roughened structure such as the semiconductor element 90A or semiconductor element 90B; the semiconductor element 60 may also have a concave-convex structure such as the semiconductor element 70, an epitaxial structure outline such as the semiconductor element 80, or a roughened structure such as the semiconductor element 90A or semiconductor element 90B; the semiconductor element 70 may also have an epitaxial structure outline such as the semiconductor element 80, or a roughened structure such as the semiconductor element 90A or semiconductor element 90B; the semiconductor element 80 may also have a roughened structure such as the semiconductor element 90A or semiconductor element 90B, etc.

[0137] Figures 2A to 2I This is a schematic diagram illustrating a method for manufacturing a semiconductor element 10' according to an embodiment of the present invention. First, a growth substrate GS is provided. For example... Figure 2A As shown, an epitaxial structure 100 and a first electrode 106 are formed on a growth substrate GS. The epitaxial structure 100 sequentially includes a second contact layer 100b2, a second semiconductor layer 100b1, an active region 100c, a first semiconductor layer 100a1, and a first contact layer 100a2. The first electrode 106 is formed on the first semiconductor structure 100a1 and is in direct contact with the first contact layer 100a2. The method for forming the first electrode 106 is, for example, electron beam evaporation or sputtering. The material of the growth substrate GS is, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), sapphire, germanium (Ge), or silicon (Si). After forming the first electrode 106, a heat treatment may be performed on the first electrode 106 to form a good electrical contact (e.g., an ohmic contact) between the first electrode 106 and the first contact layer 100a2. The aforementioned heating treatment is, for example, rapid thermal annealing (RTA) or heating in a furnace tube.

[0138] Then, as Figure 2B As shown, a first etching process is performed to remove a portion of the epitaxial structure 100 and the first electrode 106. Specifically, a portion of the second semiconductor layer 100b1, a portion of the active region 100c, a portion of the first semiconductor layer 100a1, a portion of the first contact layer 100a2, and a portion of the first electrode 106 can be removed to form a first platform structure M1.

[0139] like Figure 2C As shown, an insulating structure 102 is formed on the epitaxial structure 100. Methods for forming the insulating structure 102 include, for example, chemical vapor deposition (CVD), such as plasma-enhanced chemical vapor deposition (PECVD) and / or atomic layer deposition (ALD). Figure 2C As shown, the formed insulating structure 102 can cover and directly contact the second semiconductor layer 100b1, the active region 100c, the first semiconductor layer 100a1, the first contact layer 100a2, and the first electrode 106.

[0140] Then, as Figure 2D As shown, an opening 102a corresponding to the first electrode 106 is formed in the insulating structure 102. The method for forming the opening 102a is, for example, performing a second etching process on the insulating structure 102. In this embodiment, when performing the second etching process to form the opening 102a, the first electrode 106 can serve as an etching stop layer.

[0141] Then as Figure 2E As shown, a barrier layer 104 is formed on the insulating structure 102. Methods for forming the barrier layer 104 include, for example, chemical vapor deposition (CVD), such as plasma-enhanced chemical vapor deposition (PECVD) and / or atomic layer deposition (ALD). Figure 2E As shown, the formed barrier layer 104 can cover and directly contact the insulating structure 102 distributed on the second semiconductor layer 100b1, the active region 100c, the first semiconductor layer 100a1, the first contact layer 100a2, and the first electrode 106. After forming the barrier layer 104, a heat treatment may be optionally performed on the barrier layer 104 to improve its light transmittance, such as rapid thermal annealing (RTA) or heating in a furnace. In one embodiment, the temperature of the heat treatment of the barrier layer 104 may be lower than the temperature of the heat treatment of the first electrode 106.

[0142] Next, as Figure 2F As shown, a bonding fabrication process is performed to connect the epitaxial structure 100 to the bonding substrate BS via a bonding structure 200. The bonding substrate BS is made of materials such as sapphire, germanium (Ge), or silicon (Si). According to some embodiments, the bonding structure 200 may be made of oxides (such as silicon oxide (SiO2)). x ) or aluminum oxide (AlO x )), nitrides (such as aluminum nitride (AlN), silicon nitride (SiN) xAlternatively, polymers (such as benzocyclobutene (BCB), epoxy resin, polyimide, silicone resin, or SOG (Spin On Glass)) may be used. The bonding structure 200 can be a single-layer or multi-layer structure. In this embodiment, the bonding structure 200 may sequentially include a first bonding layer 201, a second bonding layer 202, and a third bonding layer 203. The thickness of the first bonding layer 201 and the third bonding layer 203 may both be less than that of the second bonding layer 202. The second bonding layer 202 may be made of a different material than the first bonding layer 201 or the third bonding layer 203, while the first bonding layer 201 or the third bonding layer 203 may have the same material. In one embodiment, the first bonding layer 201 and the third bonding layer 203 comprise oxides or nitrides, and the second bonding layer 202 comprises a polymer. In another embodiment, the bonding structure 200 is a single-layer structure and comprises a polymer.

[0143] Then, the growth substrate GS is removed and flipped. One method for removing the growth substrate GS is, for example, performing a third etching process on the growth substrate GS. Figure 2G As shown, after flipping, a second electrode 108 is formed above the second semiconductor structure 100b. In this step, the second contact layer 100b2 can be selectively patterned. For example, as... Figure 2G As shown, the portion of the second contact layer 100b2 that does not overlap with the second electrode 108 in the vertical direction can be removed to form a patterned second contact layer 100b2. In another embodiment, the second contact layer 100b2 may not be patterned, but the portion of the second contact layer 100b2 that does not overlap with the second electrode 108 in the vertical direction may be retained.

[0144] After that, as Figure 2H As shown, a fourth etching process can be performed on the second semiconductor structure 100b, the insulating structure 102, the barrier layer 104, and the bonding structure 200. In this step, a portion of the second semiconductor structure 100b, a portion of the insulating structure 102, a portion of the barrier layer 104, and a portion of the bonding structure 200 can be removed to form a second platform structure M2. Specifically, the second platform structure M2 includes a second contact layer 100b2 and a portion of the second semiconductor layer 100b1. In one embodiment, an adhesion layer 112 can be selectively formed on the second semiconductor structure 100b before or after the fourth etching process. The method for forming the adhesion layer 112 is, for example, electron beam evaporation or sputtering. Figure 2HThe diagram shows a structure formed by forming an adhesion layer 112 on the second semiconductor structure 100b followed by a fourth etching process, but it is not actually limited to this. By adjusting the conditions of the fourth etching process, the first part p1, the second part p2, the insulating structure 102, and the barrier layer 104 can be formed as shown. Figure 2I The appearance shown can also be formed as follows: Figures 1B to 1G , Figures 1I to 1M The appearance shown in each embodiment. Figure 2H As shown, in this embodiment, the barrier layer 104 may have an end upper surface 104t and an end side surface 104w, and a portion of the insulating structure 102 extends to cover the end upper surface 104t but not the end side surface 104w.

[0145] Then, as Figure 2I As shown, conductive bumps 110 can be selectively formed above the second electrode 108. Methods for forming conductive bumps 110 include, for example, electron beam evaporation or sputtering. In this embodiment, the illustration is intended to depict a single semiconductor element 10', but in practice, multiple semiconductor elements 10' can be formed simultaneously following the steps described above.

[0146] In this embodiment, the semiconductor element 10' embedded in the bonding structure 200 can be formed through the above steps, which facilitates the transfer of the semiconductor element 10'. After the transfer fabrication process is completed, the bonding structure 200 can be further removed. Specifically, during the subsequent transfer of the semiconductor element 10', the barrier layer 104 in the semiconductor element 10' can further protect the insulating structure 102 and the epitaxial structure 100, preventing damage to the insulating structure 102 and the active region 100c of the semiconductor element 10', thereby improving manufacturing yield. For further information on the effectiveness of the barrier layer 104, please refer to... Figure 3A and Figure 3B Examples and corresponding paragraphs.

[0147] Specifically, the first / second / third / fourth etching processes described above may include dry etching or wet etching. The dry etching process may be, for example, electron cyclotron resonance (ECR), inductively coupled plasma (ICP), or reactive ion etching (RIE). In this invention, for example, the above-described manufacturing methods can provide good structural protection for the device and can improve production yield, reduce manufacturing steps, and lower production costs.

[0148] Figures 3A to 3BThis is a schematic diagram illustrating a method for manufacturing a semiconductor component 300 according to an embodiment of the present invention. In this embodiment, the method for manufacturing a semiconductor component 300 comprising a structure including multiple semiconductor elements 10 is described as an example, but the method is not limited thereto. The semiconductor component 300 may include multiple semiconductor elements as described in any embodiment of the present invention (such as semiconductor elements 10, 10', 20, 30, 40, 50, 60, 70, 80, 90A, 90B, 90C). Figure 3A As shown, specifically, for example, refer to Figures 2A to 2G The steps are as follows: Figure 2H The fourth etching process conditions shown are used to form it. Figure 1B After the appearance is determined, the following steps are taken: Figure 2I After forming multiple semiconductor elements 10 simultaneously on the bonding substrate BS, the multiple semiconductor elements 10 can be further connected to a temporary carrier TS via the adhesive structure 320, and the bonding structure 200 and the bonding substrate BS can be removed. During the removal of the bonding structure 200, the insulating structure 102 and the epitaxial structure 100 are protected by the barrier layer 104, preventing damage to structures such as the insulating structure 102 and the active region 100c. The material of the temporary carrier TS may include glass, sapphire, or silicon (Si). According to some embodiments, the adhesive structure 320 may include thermal release tape, UV release tape, chemical release tape, heat-resistant tape, tape with a dynamic release layer (DRL), or blue tape. The material of the adhesive structure 320 may include polyimide, benzocyclobutene (BCB), epoxy resin, silicone resin, acrylic resin, polyester, or a combination thereof.

[0149] like Figure 3A As shown, a portion of the conductive bump 110 in the semiconductor element 10 can be embedded in the adhesive structure 320. Then, as... Figure 3BAs shown, a portion of the adhesive structure 320 (e.g., the adhesive structure 320 located between multiple semiconductor elements 10) can be further removed to form a semiconductor assembly 300 comprising multiple adhesive bodies 320'. In this embodiment, each adhesive body 320' corresponds to a single semiconductor element 10. However, this is not a limitation; each adhesive body 320' can correspond to multiple semiconductor elements 10 as needed. Specifically, a portion of the adhesive structure 320 can be removed by methods such as dry etching, wet etching, laser lift-off, heating, or UV light. Similarly, when removing a portion of the adhesive structure 320, the barrier layer 104 can also protect the insulating structure 102 and the epitaxial structure 100, preventing damage to structures such as the insulating structure 102 and the active region 100c, thereby improving manufacturing yield. According to one embodiment, when the material of the barrier layer 104 is conductive, after removing a portion of the adhesive structure 320, a portion of the barrier layer 104 can also be selectively removed, for example, the barrier layer 104 covering the first side surface s1, the third side surface s3, the fourth side surface s4 and the fifth side surface s5 can be removed, thereby further preventing short circuits during subsequent component operation.

[0150] Figure 4A This is a top view schematic diagram of a display device 400 according to an embodiment of the present invention. Figure 4B For along Figure 4A A schematic diagram of the cross-sectional structure of the Z-Z' line. (See diagram below.) Figure 4A As shown, the display device 400 may include a target carrier 81 and a plurality of pixel units 82 located on the target carrier 81. The plurality of pixel units 82 are arranged in an array along directions parallel to the x-axis and y-axis, and are arranged at a interval d1 in the direction parallel to the x-axis. The target carrier 81 may be a single-layer or multi-layer structure. The target carrier 81 may be a printed circuit board (PCB) or a thin-film transistor (TFT) substrate. The material of the target carrier 81 may include glass, polyester, polyimide (PI), BT (Bismaleimide Triazine) resin, PTFE (Polytetrafluoroethylene) resin, phenolic (PF) resin, or glass fiber epoxy resin (FR4). The number of pixel units 82 may be adjusted as needed; for example, in one embodiment, the plurality of pixel units 82 included in the display device 400 may provide a resolution of 1920 × 1080 pixels. In one embodiment, the interval d1 can be less than 1.4 mm; for example, the interval d1 is between 0.2 mm and 1.3 mm, specifically 0.75 mm, 0.8 mm, 1 mm, and 1.25 mm. Figure 4AAs shown, each pixel unit 82 includes a first semiconductor element 84, a second semiconductor element 86, and a third semiconductor element 88 arranged along a direction parallel to the y-axis. Specifically, one or more of the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 may be semiconductor elements as described in the previous embodiments (e.g., semiconductor elements 10, 20, 30, 40, 50). In one embodiment, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 are all light-emitting elements and can emit red light, green light, and blue light, respectively. In one embodiment, the arrangement order of these light-emitting elements can also be adjusted as needed; for example, the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 can emit red light, blue light, and green light, respectively. Each pixel unit 82 can be electrically connected to a circuit (not shown) on the surface of the target carrier 81, so that the light-emitting elements therein can receive external signals and emit light according to the external signals. In one embodiment, the target carrier 81 is bendable and can withstand a curvature radius of less than 50 mm, such as 25 mm or 32 mm.

[0151] For ease of explanation, Figure 4B The diagram below illustrates the structure of semiconductor element 10 as an example. Figure 4B As shown, the target carrier 81 may have a conductive structure 80a. The conductive structure 80a may comprise metal. The first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 can be connected to the conductive structure 80a via conductive bumps 110, thereby fixing them to the target carrier 81. The display device 400 may also include a dielectric structure 420. The dielectric structure 420 covers the target carrier 81 and covers the side surfaces of the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88. Figure 4B As shown, the dielectric structure 420 fills the space between the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88. The dielectric structure 420 may comprise an opaque material or a reflective material. In one embodiment, the material of the dielectric structure 420 may comprise a matrix and a black material. The matrix may comprise silicone, epoxy, or a mixture thereof. The black material may comprise carbon black.

[0152] The display device 400 may also include conductive lines 440. For example... Figure 4B As shown, conductive line 440 may cover and be electrically connected to dielectric structure 420, first semiconductor element 84, second semiconductor element 86, and third semiconductor element 88. Conductive line 440 may conformally cover dielectric structure 420. Figure 4BAs shown, in this embodiment, the conductive line 440 and the barrier layer 104 can directly contact each other to form an electrical connection. Alternatively, in another embodiment, for example, when the first semiconductor element 84, the second semiconductor element 86, and the third semiconductor element 88 are semiconductor elements 20 as described in the previous embodiment, the conductive line 440 and the first electrode 106 can directly contact each other to form an electrical connection. Figure 4B As shown, the upper edge of the dielectric structure 420 may have a vertical distance d2 between it and the upper edges of the first semiconductor element 84, the second semiconductor element 86, and / or the third semiconductor element 88. This vertical distance d2 is, for example, less than 1 / 2 or 1 / 3 of the thickness of the first semiconductor element 84, the second semiconductor element 86, or the third semiconductor element 88, thereby avoiding the problem of the conductive line 440 easily breaking due to an excessively large vertical distance. The conductive line 440 may be transparent and conductive, for example, containing metal oxides, metals, or alloys. Metal oxides include, for example, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). Metals may include, for example, gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), copper (Cu), or nickel (Ni). The alloy may contain at least two elements selected from the group consisting of the aforementioned metallic elements, such as germanium-gold-nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc. According to one embodiment, the conductive line 440 and the barrier layer 104 may contain the same material, thereby ensuring good adhesion between the conductive line 440 and the barrier layer 104 and contributing to improved structural stability of the display device 400.

[0153] In summary, embodiments of the present invention provide a semiconductor element, a semiconductor assembly, a display device, and a method for manufacturing the same. For example, by providing a barrier layer in the semiconductor element, a good structural protection can be achieved, resulting in improved production yield, reduced manufacturing steps, and lower production costs. Specifically, it can prevent damage to the semiconductor element during manufacturing processes such as transfer, thus avoiding electrical abnormalities, which is beneficial for elements requiring miniaturization. The semiconductor element and semiconductor assembly of the present invention can be applied to products in the fields of lighting, display, communication, and power systems, such as lamps, monitors, automotive dashboards, televisions, computers, traffic signals, and outdoor displays.

[0154] While the present invention has been disclosed above by way of embodiments, some modifications or changes may be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims. The above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the relevant parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor element, comprising: An epitaxial structure includes a first semiconductor layer, a second semiconductor layer, and an active region located between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer has a first portion and a second portion, the width of the second portion being smaller than the width of the first portion, and the first portion having a first side surface. The first electrode is located below the first semiconductor layer; An insulating structure is distributed on the first side surface and has an opening corresponding to the first electrode; A barrier layer covering the insulating structure distributed on the first side surface; as well as The second electrode is located on the second semiconductor layer.

2. The semiconductor device of claim 1, wherein the barrier layer fills the opening and is in direct contact with the first electrode.

3. The semiconductor device of claim 1, wherein the first portion is closer to the active region than the second portion.

4. The semiconductor device of claim 1, wherein the first electrode has a lower surface and the insulating structure is distributed on a portion of the lower surface.

5. The semiconductor element of claim 4, wherein the barrier layer covers the insulating structure distributed on a portion of the lower surface.

6. The semiconductor device of claim 1, wherein the first electrode and the barrier layer may comprise the same material.

7. The semiconductor device of claim 1, wherein the material of the barrier layer comprises a metal oxide.

8. The semiconductor element of claim 1, wherein the width of the second electrode is smaller than the width of the second portion.

9. The semiconductor element of claim 1, further comprising conductive bumps covering the second electrode.

10. The semiconductor element of claim 9, further comprising an adhesion layer located between the second electrode and the conductive bump.

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