Ultrahigh-speed level conversion circuit of digital circuit
By designing a DC-DC high-side drive module and a level conversion module, the problem of signal level conversion delay in DC-DC converters is solved, realizing ultra-high-speed conversion from low-voltage input signals to high-voltage output signals, and improving the system's high bandwidth and fast response capability.
Patent Information
- Application Number
- CN202511023206.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-24
- Publication Date
- 2025-11-04
AI Technical Summary
In high-voltage, high-current, and high-bandwidth applications, the signal level conversion delay of existing DC-DC converters has become a key bottleneck in digital signal transmission, affecting the system's high bandwidth and fast response.
The system employs a DC-DC high-side drive module and a level conversion module, including a high-level converter, clamping diode, upper power transistor driver, bootstrap capacitor, upper power transistor, output inductor and capacitor, combined with low-voltage inverters and OR gate logic gates, to achieve ultra-high-speed level conversion from low-voltage input signals to high-voltage output signals.
This achieves a delay time of less than 50 ps from low-voltage input signal to high-voltage output signal, improves signal level conversion speed, reduces digital signal transmission delay, and enhances the high-bandwidth performance of DC-DC conversion system.
Smart Images
Figure CN120896584A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a level conversion technology field of direct current to direct current application, in particular to a digital circuit super-high-speed level conversion circuit. BACKGROUND
[0002] With more and more high-current high-speed DC-DC converters in product applications, the power stage determines the power conversion efficiency and the production cost of the entire DC-DC converter.
[0003] In order to realize high-efficiency high-frequency switching and low-cost products, nmos is usually used as an upper edge switch tube in the power stage design, so that the on-resistance is very low under the same physical area compared with pmos as the upper edge switch tube, and the gate capacitance is very low under the same on-resistance, so that the system design can be converted at high speed, thereby reducing the size of the entire system.
[0004] Using nmos as an upper power switch tube, the gate voltage needs to be higher than the input voltage, so that there is a correct square wave from vin to ground at the sw point of the power stage output.
[0005] With more and more applications of DC-DC high-voltage high-current high-bandwidth, especially the increasing AI computing power and data bandwidth, the requirement for fast response of DC-DC is also more and more demanding, which requires the bandwidth of DC-DC to be larger and larger, the switching frequency to be higher and higher, and the signal transmission to be faster and faster. In the DC-DC converter, the level conversion delay of the signal is the most critical factor in the entire digital signal transmission. Increasing the level conversion speed of the signal can greatly reduce the transmission delay of the digital signal, and make the high bandwidth of the DC-DC conversion system possible. Therefore, the application patent provides a digital circuit super-high-speed level conversion circuit to realize super-high-speed level conversion. SUMMARY
[0006] The application provided by the application aims to provide a digital circuit super-high-speed level conversion circuit to solve the problems in the background technology. The low-voltage input signal hs_in_lv is driven by the inverters inv1 and inv2 to drive c_fly1 and c_fly2, and the driving delay is less than 50pS. The transmission delay of the self-boosting of c_fly1 and c_fly2 can be ignored. The driving delay of the logic gate from inn_hv and inp_hv to the output hs_in_hv is less than 50pS. The delay from the low-voltage input signal hs_in_lv to the high-voltage output signal hs_in_hv is the transmission delay between digital gates, and the transmission delay is less than 100pS.
[0007] To achieve the above object, the application is implemented by the following technical solutions: a digital circuit super-high-speed level conversion circuit, characterized in that it comprises:
[0008] The DC-DC high-side driving module is used for super-high-speed level conversion, and comprises a high-level converter, a clamping diode, an upper side power tube driver drv_hs, a bootstrap capacitor c_bst, an upper side power tube ldnmos_hs, an output inductor L_out, an output capacitor c_out and a freewheeling diode Diode_asyn, one end of the high-level converter is electrically connected to one end of the clamping diode, the other end of the clamping diode is electrically connected to one end of the high-level converter, one end of the clamping diode is electrically connected to one end of the bootstrap capacitor c_bst, one end of the bootstrap capacitor c_bst is electrically connected to one end of the output inductor L_out, one end of the high-level converter is electrically connected to one end of the upper side power tube driver drv_hs, one end of the clamping diode is electrically connected to one end of the upper side power tube driver drv_hs, one end of the upper side power tube driver drv_hs is electrically connected to one end of the output inductor L_out, one end of the upper side power tube ldnmos_hs is electrically connected to one end of the freewheeling diode Diode_asyn, one end of the upper side power tube ldnmos_hs is electrically connected to one end of the output inductor L_out, one end of the output inductor L_out is electrically connected to one end of the output capacitor c_out, one end of the high-level converter is electrically connected to one end of the output capacitor c_out, and one end of the high-level converter is electrically connected to the upper side power tube ldnmos_hs.
[0009] The level conversion module is arranged on the DC-DC high-side driving module and is used for solving the delay of rising and falling edges when the low-voltage input signal is converted to the high-voltage output signal.
[0010] Further, the level conversion module comprises a low-voltage inverter inv1, a low-voltage inverter inv2, a capacitor c_fly1, a capacitor c_fly2, an NMOS transistor nm1, an NMOS transistor nm2, an inverter inv3, an inverter inv4, an inverter inv5, an inverter inv6, an NOR gate nor1, an NOR gate nor2, an NOR gate nor3, an NOR gate nor4, an NOR gate nor5, and an inverter inv7, one end of the low-voltage inverter inv1 is electrically connected to one end of the low-voltage inverter inv2, one end of the low-voltage inverter inv2 is electrically connected to the capacitor c_fly2, one end of the low-voltage inverter inv1 is electrically connected to the capacitor c_fly1, one end of the capacitor c_fly1 is electrically connected to the NMOS transistor nm1, one end of the NMOS transistor nm1 is electrically connected to the inverter inv3, one end of the capacitor c_fly2 is electrically connected to the NMOS transistor nm2, one end of the capacitor c_fly2 is electrically connected to the inverter inv3, one end of the capacitor c_fly2 is electrically connected to the inverter inv6, one end of the capacitor c_fly2 is electrically connected to the inverter inv4, one end of the NMOS transistor nm1 is electrically connected to the inverter inv5, one end of the inverter inv4 is electrically connected to the inverter inv5, one end of the inverter inv5 is electrically connected to the NOR gate nor2, one end of the inverter inv5 is electrically connected to the NOR gate nor1, one end of the inverter inv6 is electrically connected to the NOR gate nor1, one end of the inverter inv6 is electrically connected to the NOR gate nor3, one end of the NOR gate nor1 is electrically connected to the NOR gate nor2, one end of the NOR gate nor1 is electrically connected to the NOR gate nor3, one end of the NOR gate nor2 is electrically connected to the NOR gate nor4, one end of the NOR gate nor4 is electrically connected to the NOR gate nor5, one end of the NOR gate nor3 is electrically connected to the NOR gate nor5, one end of the NOR gate nor5 is electrically connected to the inverter inv7, and one end of the NOR gate nor4 is electrically connected to the inverter inv7.
[0011] Further, one end of the high-level converter is connected to a low-voltage input signal hs_in_lv, and the high-level converter generates a low-voltage source vdd, a ground voltage gnd, a potential sw, and a high-voltage output signal hs_in_hv.
[0012] Further, the upper edge power tube driver drv_hs generates an hsg signal, which is a gate driving signal of the upper edge power tube ldnmos_hs.
[0013] Further, the drain of the upper edge power tube ldnmos_hs is connected to an input power source vin, and the source of the upper edge power tube ldnmos_hs is connected to the negative electrode of a current diode Diode_asyn, i.e. the output point potential sw of the power stage.
[0014] Further, one end of the low-voltage inverter inv1 is connected with the low-voltage input signal hs_in_lv, and the low-voltage inverter inv1 outputs the low-voltage signal inn_lv to drive the capacitor c_fly1 to obtain the high-voltage signal inn_hv controlled by the nm1 and set to the potential sw.
[0015] Further, one end of the low-voltage inverter inv2 is connected with the high-voltage signal inn_hv, and the low-voltage inverter inv2 outputs the low-voltage output signal inp_lv to drive the capacitor c_fly2 to obtain the high-voltage signal inp_hv controlled by the nm2 and set to the potential sw.
[0016] Further, the high-voltage signal inn_hv and the high-voltage signal inp_hv are latched and clamped through the inverters inv3 and inv4, and the high-voltage signal inn_hv and the high-voltage signal inp_hv are obtained through the inverters inv5 and inv6 to obtain the high-voltage signals inp_hv_a and inn_hv_a.
[0017] Further, the high-voltage signals inp_hv_a and inn_hv_a are obtained through the NOR gate nor1 to output the set control signal rst to the gates of the nm1 and the nm2, and the rst, inp_hv_ah, and inn_hv_a signals are obtained through the NOR gate nor2 and the NOR gate nor3 to generate the set_hv and reset_hv signals acting on the NOR gate nor4, the NOR gate nor5, and the inverter inv7.
[0018] Further, one end of the inverter inv7 outputs the high-voltage output signal hs_in_hv.
[0019] The application provides a digital circuit super-high-speed level conversion circuit, which has the following beneficial effects:
[0020] (1) The digital circuit super-high-speed level conversion circuit, through the low-voltage input signal hs_in_lv, the inverters inv1 and inv2 drive c_fly1 and c_fly2, and the driving delay of the logic gate is easily made to be below 50pS, the transmission delay of the c_fly1 and c_fly2 self-boosting can be ignored, the inn_hv and inp_hv to the output hs_in_hv are the driving delays of the logic gate, which are easily made to be below 50pS, and the delay of the low-voltage input signal hs_in_lv to the high-voltage output signal hs_in_hv is the transmission delay between the digital gates, which is easily made to be below 100pS. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 The application provides a DC-DC high-side drive application d circuit diagram of the digital circuit super-high-speed level conversion circuit.
[0022] Figure 2 A digital circuit super high-speed level conversion circuit diagram of the digital circuit super high-speed level conversion circuit of the present application
[0023] Figure 3 A system waveform of the digital circuit super high-speed level conversion circuit of the present application Figure 1 ;
[0024] Figure 4 A signal waveform schematic diagram of the digital circuit super high-speed level conversion circuit of the present application
[0025] In the figure: 1, DC-DC high side drive module; 101, high level converter, 102, clamping diode; 103, upper side power tube driver drv_hs; 104, bootstrap capacitor c_bst; 105, upper side power tube ldnmos_hs; 106, output inductor L_out; 107, output capacitor c_out; 108, freewheeling diode Diode_asyn; 2, level conversion module; 201, low voltage inverter inv1; 202, capacitor c_fly1; 203, low voltage inverter inv2; 204, nm2; 205, nm1; 206, inverter inv3; 207, capacitor c_fly2; 208, inverter inv6; 209, inverter inv4; 210, inverter inv5; 211, nor gate nor2; 212, nor gate nor1; 213, nor gate nor4; 214, inverter inv7; 215, nor gate nor5; 216, nor gate nor3. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.
[0027] Examples of the described embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.
[0028] The present application will be further described below in combination with the drawings and embodiments:
[0029] Please refer to Figures 1-4 , the present application provides a technical solution: a digital circuit super high-speed level conversion circuit, characterized in that, comprising:
[0030] The DC-DC high-side drive module 1 is used for super-high-speed level conversion, and includes a high-level converter 101, a clamping diode 102, an upper side power tube driver drv_hs 103, a bootstrap capacitor c_bst 104, an upper side power tube ldnmos_hs 105, an output inductor L_out 106, an output capacitor c_out 107, and a freewheeling diode Diode_asyn 108. One end of the high-level converter 101 is electrically connected to one end of the clamping diode 102, and the other end of the clamping diode 102 is electrically connected to one end of the high-level converter 101. One end of the clamping diode 102 is electrically connected to one end of the bootstrap capacitor c_bst 104, and one end of the bootstrap capacitor c_bst 104 is electrically connected to one end of the output inductor L_out 106. One end of the high-level converter 101 is electrically connected to one end of the upper side power tube driver drv_hs 103, and one end of the clamping diode 102 is electrically connected to one end of the upper side power tube driver drv_hs 103. One end of the upper side power tube driver drv_hs 103 is electrically connected to one end of the output inductor L_out 106. One end of the upper side power tube ldnmos_hs 105 is electrically connected to one end of the freewheeling diode Diode_asyn 108, and one end of the upper side power tube ldnmos_hs 105 is electrically connected to one end of the output inductor L_out 106. One end of the output inductor L_out 106 is electrically connected to one end of the output capacitor c_out 107, and one end of the high-level converter 101 is electrically connected to one end of the output capacitor c_out 107. One end of the high-level converter 101 is electrically connected to the upper side power tube ldnmos_hs 105.
[0031] The level conversion module 2 is arranged on the DC-DC high-side drive module 1, and is used to solve the delay of rising and falling edges when the low-voltage input signal is converted to a high-voltage output signal.
[0032] Specifically, the level conversion module 2 includes a low voltage inverter inv1 201, a low voltage inverter inv2 203, a capacitor c_fly1 202, a capacitor c_fly2 207, an nm1 205, an nm2 204, an inverter inv3 206, an inverter inv4 209, an inverter inv5 210, an inverter inv6 208, a nor gate nor1 212, a nor gate nor2 211, a nor gate nor3 216, a nor gate nor4 213, a nor gate nor5 215, and an inverter inv7 214, one end of the low voltage inverter inv1 201 is electrically connected to one end of the low voltage inverter inv2 203, one end of the low voltage inverter inv2 203 is electrically connected to the capacitor c_fly2 207, one end of the low voltage inverter inv1 201 is electrically connected to the capacitor c_fly1 202, one end of the capacitor c_fly1 202 is electrically connected to the nm1 205, one end of the nm1 205 is electrically connected to the inverter inv3 206, one end of the capacitor c_fly2 207 is electrically connected to the nm2 204, one end of the capacitor c_fly2 207 is electrically connected to the inverter inv3 206, one end of the capacitor c_fly2 207 is electrically connected to the inverter inv6 208, one end of the capacitor c_fly2 207 is electrically connected to the inverter inv4 209, one end of the nm1 205 is electrically connected to the inverter inv5 210, one end of the inverter inv4 209 is electrically connected to the inverter inv5 210, one end of the inverter inv5 210 is electrically connected to the nor gate nor2 211, one end of the inverter inv5 210 is electrically connected to the nor gate nor1 212, one end of the inverter inv6 208 is electrically connected to the nor gate nor1 212, one end of the inverter inv6 208 is electrically connected to the nor gate nor3 216, one end of the nor gate nor1 212 is electrically connected to the nor gate nor2 211, and one end of the nor gate nor2 211 is electrically connected to the nor gate nor4 213, one end of the nor gate nor4 213 is electrically connected to the nor gate nor5 215, one end of the nor gate nor5 215 is electrically connected to the inverter inv7 214, one end of the nor gate nor3 216 is electrically connected to the inverter inv7 214, one end of the nor gate nor4 213 is electrically connected to the inverter inv7 214.
[0033] Specifically, one end of the high level converter 101 is connected to the low voltage input signal hs_in_lv, and the high level converter 101 generates the low voltage source vdd, the ground voltage gnd, the potential sw, and the high voltage output signal hs_in_hv.
[0034] Specifically, the upper power tube driver drv_hs 103 generates the hsg signal, and the hsg signal is the gate driving signal of the upper power tube ldnmos_hs 105.
[0035] Specifically, the drain of the upper power transistor ldnmos_hs 105 is connected to the input power vin, and the source of the upper power transistor ldnmos_hs 105 is connected to the negative electrode of the diode Diode_asyn 108, that is, the output point potential sw of the power stage.
[0036] Specifically, one end of the low-voltage inverter inv 1201 is connected to the low-voltage input signal hs_in_lv, and the low-voltage inverter inv 1201 outputs the low-voltage signal inn_lv to drive the capacitor c_fly 1202 to obtain the high-voltage signal inn_hv controlled by the nm 1205 and set to the potential sw.
[0037] Specifically, one end of the low-voltage inverter inv 2203 is connected to the high-voltage signal inn_hv, and the low-voltage inverter inv 2203 outputs the low-voltage output signal inp_lv to drive the capacitor c_fly 2207 to obtain the high-voltage signal inp_hv controlled by the nm 2204 and set to the potential sw.
[0038] Specifically, the high-voltage signal inn_hv and the high-voltage signal inp_hv are latched and clamped through the inverter inv 3206 and the inverter inv 4209, and the high-voltage signal inn_hv and the high-voltage signal inp_hv are obtained through the inverter inv 5210 and the inverter inv 6208. High-voltage signals inp_hv_a and inn_hv_a.
[0039] Specifically, the high-voltage signal inp_hv_a and the high-voltage signal inn_hv_a pass through the nor gate nor 1212 to obtain the output set control signal rst to the gates of the nm 1205 and the nm 2204, and the rst, inp_hv_ah, and inn_hv_a signals pass through the nor gate nor 2211 and the nor gate nor 3216 to generate the set_hv and reset_hv signals acting on the nor gate nor 4213, the nor gate nor 5215, and the inverter inv 7214.
[0040] Specifically, one end of the inverter inv 7214 outputs the high-voltage output signal hs_in_hv.
[0041] A digital circuit super-high-speed level conversion circuit:
[0042] Figure 1In the middle, low-voltage input signal hs_in_lv to the low-level signal to the high-level converter, 002 of the low-voltage source vdd, high-voltage source bst, ground voltage gnd and potential sw, 002 of the high-voltage output signal hs_in_hv, wherein the high-voltage bst is generated by the low-voltage source vdd through the clamping diode diode for the bootstrap capacitor c_bst bias voltage while the bootstrap voltage is generated by sw, 002 of the output high voltage is the input of the upper edge power tube driver drv_hs, wherein the upper edge power tube driver 010 is powered by the bootstrap voltage 005 and the power stage output sw, the output hsg of the upper edge power tube driver is the gate drive signal of the upper edge power tube ldnmos_hs, wherein the drain of the upper edge power tube 012 is connected to the input power source vin of the system, and the negative electrode of the freewheeling diode Diode_asyn of the power stage is connected to the output point sw of the power stage, the output sw of the power stage is the high-voltage signal of the low-to-high voltage converter and the high-voltage signal of the upper edge power tube driver, and it is also one end of the output inductor L_out, the other end of the output inductor 015 is connected to the output capacitor c_out, the upper edge power tube ldnmos_hs, the power tube input voltage vin, the freewheeling diode Diode_asyn of the power stage, the output inductor L_out, the output capacitor C_out, and the output voltage vout.
[0043] The working process is as follows: the low-voltage control input signal hs_in_lv of the high-side power tube 012 is converted into a high-voltage signal hs_in_hv after low-to-high voltage level conversion, and the output hsg of the driving capability amplifier 010 is connected to the gate control of the high-side power tube 012 to control the opening and closing of the high-side power tube 012. The high potential of the driving capability amplifier 010 is obtained by the bootstrap capacitor 009 at the bias voltage of vdd-vth_diode to bootstrap the low potential of sw
[0044] Figure 3 In the middle, the rising edge of the low-voltage input signal hs_in_lv to the high-voltage output signal hs_in_hv has a delay of t_r_dly and the falling edge has a delay of t_f_dly.
[0045] Figure 2In the above-mentioned drive control, the low-voltage input signal hs_in_lv is input to the low-voltage inverter inv1, which is powered by the low-voltage power supply vdd and the ground power supply gnd. The low-voltage signal inn_lv output by inv1 drives capacitor c_fly1 to obtain the high-voltage signal inn_hv, which is set to sw by control nm1. At the same time, the low-voltage signal inn_lv serves as the input to the low-voltage inverter inv2, which is powered by the low-voltage power supply vdd and the ground power supply gnd, to obtain the low-voltage output signal inp_lv. The low-voltage signal inp_lv drives capacitor c_fly2 to obtain the high-voltage signal inp_hv, which is set to sw by control nm2. The high-voltage signals inn_hv and inp_hv are then passed through the inverter powered by bst and sw. The voltage converters inv3 and inv4 latch and clamp the voltages. After low-voltage bootstrapping to high-voltage inn_hv and inp_hv, the inverters inv5 and inv6, powered by bst and sw, produce high-voltage signals inp_hv_a and inn_hv_a. These high-voltage signals inp_hv_a and inn_hv_a are then passed through NOR gate NOR1 to obtain the output set control signal rst, which is sent to the gates of nm1 and nm2. Simultaneously, the rst signal, along with inp_hv_a and inn_hv_a, are passed through NOR gates NOR2 and NOR3 to generate set_hv and reset_hv signals, which are applied to the set and reset terminals of the RS flip-flop composed of NOR4, NOR5, and inv7. The high-voltage output signal of the RS flip-flop is hs_in_hv. This describes the signal and device connections of the entire low-voltage to high-voltage potential converter of this invention.
[0046] The low-voltage input signal hs_in_lv is bootstrapped by flip-flops 105 and 106 to the high-voltage signals inn_hv and inp_hv. RST feedback control generates rising edge pulses, which are then latched by RS flip-flops composed of 118, 119, and 120 to produce the high-voltage output signal hs_in_hv. The transmission from the low-voltage hs_in_lv input to the high-voltage hs_in_hv output involves logic signal transmission, thus achieving high-speed signal level conversion.
[0047] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.
Claims
1. A digital circuit ultra-high-speed level conversion circuit, characterized in that, include: A DC-DC high-side drive module (1) is used for ultra-high-speed level conversion. The DC-DC high-side drive module (1) includes a high-level converter (101), a clamping diode (102), an upper power transistor driver drv_hs (103), a bootstrap capacitor c_bst (104), an upper power transistor ldnmos_hs (105), an output inductor L_out (106), an output capacitor c_out (107), and a freewheeling diode Diode_asyn (108). One end of the high-level converter (101) is electrically connected to one end of the clamping diode (102), and the other end of the clamping diode (102) is electrically connected to one end of the high-level converter (101). One end of the clamping diode (102) is electrically connected to one end of the bootstrap capacitor c_bst (104), and one end of the bootstrap capacitor c_bst (104) is electrically connected to one end of the output inductor L_out (106) (016). One end of the device (101) is electrically connected to one end of the upper power transistor driver drv_hs (103), one end of the clamping diode (102) is electrically connected to one end of the upper power transistor driver drv_hs (103), one end of the upper power transistor driver drv_hs (103) is electrically connected to one end of the output inductor L_out (106), and one end of the upper power transistor ldnmos_hs (105) is electrically connected to the freewheeling diode Diode_asyn (106). One end of the upper power transistor ldnmos_hs (105) is electrically connected to one end of the output inductor L_out (106), one end of the output inductor L_out (106) is electrically connected to one end of the output capacitor c_out (107), one end of the high-level converter (101) is electrically connected to one end of the output capacitor c_out (107), and one end of the high-level converter (101) is electrically connected to the upper power transistor ldnmos_hs (105); and The level conversion module (2) is located on the DC-DC high-side drive module (1) to solve the delay of rising and falling edges when the low-voltage input signal is converted to the high-voltage output signal.
2. The ultra-high-speed level conversion circuit for digital circuits according to claim 1, characterized in that, The level conversion module (2) includes a low-voltage inverter inv1 (201), a low-voltage inverter inv2 (203), capacitors c_fly1 (202), c_fly2 (207), nm1 (205), nm2 (204), inverter inv3 (206), inverter inv4 (209), inverter inv5 (210), inverter inv6 (208), NOR gate nor1 (212), NOR gate nor2 (211), NOR gate nor3 (216), NOR gate nor4 (213), NOR gate nor5 (215), and inverter inv7 (214). One end of the low-voltage inverter inv1 (201) is electrically connected to... One end of the low-voltage inverter inv2 (203) is electrically connected to capacitor c_fly2 (207). One end of the low-voltage inverter inv1 (201) is electrically connected to capacitor c_fly1 (202). One end of capacitor c_fly1 (202) is electrically connected to nm1 (205). One end of nm1 (205) is electrically connected to inverter inv3 (206). One end of capacitor c_fly2 (207) is electrically connected to nm2 (204). One end of capacitor c_fly2 (207) is electrically connected to inverter inv3 (206). The inverter inv6 (208), one end of the capacitor c_fly2 (207) is electrically connected to the inverter inv4 (209), one end of the nm1 (205) is electrically connected to the inverter inv5 (210), one end of the inverter inv4 (209) is electrically connected to the inverter inv5 (210), one end of the inverter inv5 (210) is electrically connected to the NOR gate nor2 (211), one end of the inverter inv5 (210) is electrically connected to the NOR gate nor1 (212), one end of the inverter inv6 (208) is electrically connected to the NOR gate nor3 (212), and one end of the inverter inv6 (208) is electrically connected to the NOR gate nor3 (212). 216), one end of the NOR gate nor1 (212) is electrically connected to the NOR gate nor2 (211), and one end of the NOR gate nor1 (212) is electrically connected to the NOR gate nor3 (216), one end of the NOR gate nor2 (211) is electrically connected to the NOR gate nor4 (213), one end of the NOR gate nor4 (213) is electrically connected to the NOR gate nor5 (215), one end of the NOR gate nor3 (216) is electrically connected to the NOR gate nor5 (215), one end of the NOR gate nor5 (215) is electrically connected to the inverter inv7 (214), and one end of the NOR gate nor4 (213) is electrically connected to the inverter inv7 (214).
3. The ultra-high-speed level conversion circuit for digital circuits according to claim 1, characterized in that, One end of the high-level converter (101) is connected to the low-voltage input signal hs_in_lv, and the high-level converter (101) generates a low-voltage source vdd, a ground voltage gnd, a potential sw, and a high-voltage output signal hs_in_hv.
4. The ultra-high-speed level conversion circuit for digital circuits according to claim 1, characterized in that, The upper power transistor driver drv_hs(103) generates the hsg signal, which is the gate drive signal of the upper power transistor ldnmos_hs(105).
5. A digital circuit ultra-high-speed level conversion circuit according to claim 1, characterized in that, The drain of the upper power transistor ldnmos_hs(105) is connected to the input power supply vin, and the source of the upper power transistor ldnmos_hs(105) is connected to the negative terminal of the freewheeling diode Diode_asyn(108), which is the output potential sw of the power stage.
6. The ultra-high-speed level conversion circuit for digital circuits according to claim 1, characterized in that, One end of the low-voltage inverter inv1 (201) is connected to the low-voltage input signal hs_in_lv, and the low-voltage inverter inv1 (201) outputs the low-voltage signal inn_lv to drive the capacitor c_fly1 (202) to obtain the high-voltage signal inn_hv controlled by nm1 (205) to be set to the potential sw.
7. The ultra-high-speed level conversion circuit for digital circuits according to claim 1, characterized in that, One end of the low-voltage inverter inv2 (203) is connected to the high-voltage signal inn_hv, and the low-voltage inverter inv2 (203) outputs a low-voltage output signal inp_lv to drive capacitor c_fly2 (207) to obtain the high-voltage signal inp_hv controlled by nm2 (204) to be set to potential sw.
8. The ultra-high-speed level conversion circuit for digital circuits according to claim 1, characterized in that, The high-voltage signals inn_hv and inp_hv are latched and clamped by inverters inv3 (206) and inv4 (209), and the high-voltage signals inn_hv and inp_hv are obtained by inverters inv5 (210) and inv6 (208) to obtain high-voltage signals inp_hv_a and inn_hv_a.
9. A digital circuit ultra-high-speed level conversion circuit according to claim 1, characterized in that, The high voltage signals inp_hv_a and inn_hv_a are passed through NOR gate nor1 (212) to obtain the output set control signal rst to the gates of nm1 (205) and nm2 (204). The rst, inp_hv_ah, and inn_hv_a signals are passed through NOR gate nor2 (211) and NOR gate nor3 (216) to generate set_hv and reset_hv signals, which are applied to NOR gate nor4 (213), NOR gate nor5 (215) and inverter inv7 (214).
10. A digital circuit ultra-high-speed level conversion circuit according to claim 1, characterized in that, One end of the inverter inv7 (214) outputs a high-voltage output signal hs_in_hv.