Storage device and manufacturing method thereof

Abstract

The invention discloses a storage device and a manufacturing method thereof. The memory device includes a substrate structure, a first metal structure, a second metal structure, and a dielectric layer. The resistive random access memory comprises a first electrode, a resistive reaction layer and a second electrode which are stacked in the first direction. The dielectric layer comprises an electrode hole, the side wall of the electrode hole surrounds to form a first opening and a second opening which are opposite in the first direction, the first opening exposes the first metal structure, and the second opening is located on the surface of the side, away from the first metal structure, of the dielectric layer; in a second direction intersecting with the first direction, the size of the second opening is larger than that of the first opening; the first electrode is completely located in the electrode hole and comprises a first electrode part and a second electrode part, the first electrode part is located on the surface of the side, away from the substrate structure, of the first metal structure, and the second electrode part is located on the side wall; at least part of the resistive reaction layer extends beyond the edge of the first electrode in the second direction. Therefore, the reliability of the storage device is improved.

Description

TECHNICAL FIELD

[0001] At least one embodiment of the present disclosure relates to a storage device and a manufacturing method thereof. BACKGROUND

[0002] Resistive random access memory (RRAM), also known as memristor. As a new type of non-volatile memory, RRAM has the advantages of process compatibility, low process cost, low power consumption and good scalability, and has broad application prospects. SUMMARY

[0003] At least one embodiment of the present disclosure provides a storage device and a manufacturing method thereof.

[0004] At least one embodiment of the present disclosure provides a storage device, comprising: a substrate structure; a first metal structure on the substrate structure; a second metal structure on a side of the first metal structure away from the substrate structure; a dielectric layer at least partially between the first metal structure and the second metal structure; a resistive random access memory (RRAM) comprising a first electrode, a resistive switching layer and a second electrode stacked in a first direction, the resistive switching layer being between the first electrode and the second electrode; wherein the dielectric layer comprises an electrode hole, a sidewall of the electrode hole surrounding a first opening and a second opening opposite in the first direction, the first opening exposing the first metal structure, and the second opening being on a side surface of the dielectric layer away from the first metal structure; in a second direction intersecting the first direction, the size of the second opening is greater than the size of the first opening; the first electrode is completely located in the electrode hole, the first electrode comprises a first electrode part and a second electrode part connected to each other, the first electrode part is located on a side surface of the first metal structure away from the substrate structure, and the second electrode part is located on the sidewall; at least part of the resistive switching layer extends beyond the edge of the first electrode in the second direction.

[0005] For example, according to at least one embodiment of the present disclosure, in a plane perpendicular to the second direction, the orthographic projection of the first electrode is located within the orthographic projection of the sidewall.

[0006] For example, according to at least one embodiment of the present disclosure, the ratio of the thickness of the first electrode part to the thickness of the second electrode part is 0.9-1.1.

[0007] For example, according to at least one embodiment of the present disclosure, on the substrate structure, the orthographic projection of the first electrode is completely located within the orthographic projection of the resistive switching layer, and there is a spacing between the edge of the orthographic projection of the first electrode and the edge of the orthographic projection of the resistive switching layer.

[0008] For example, according to at least one embodiment of the present disclosure, the sidewall comprises a main portion and a first arc-shaped portion connected between the main portion and a side surface of the first metal structure away from the substrate structure; a side edge of the first arc-shaped portion away from the main portion is formed around the first opening.

[0009] For example, according to at least one embodiment of the present disclosure, the sidewall comprises a main portion and a second arc-shaped portion connected between the main portion and a side surface of the dielectric layer except for the electrode hole away from the substrate structure; a side edge of the second arc-shaped portion away from the main portion is formed around the second opening.

[0010] For example, according to at least one embodiment of the present disclosure, a maximum dimension of the first opening in the second direction is 5-100 nm.

[0011] For example, according to at least one embodiment of the present disclosure, in a plane perpendicular to the second direction, a projection of the resistance change reaction layer overlaps with a projection of the sidewall.

[0012] For example, according to at least one embodiment of the present disclosure, in a plane perpendicular to the second direction, a projection of the second electrode overlaps with a projection of the sidewall.

[0013] For example, according to at least one embodiment of the present disclosure, in a plane perpendicular to the first direction, a projection of the second electrode coincides with a projection of the resistance change reaction layer.

[0014] For example, according to at least one embodiment of the present disclosure, a side surface of the second electrode away from the substrate structure has a recess, and a portion of the second metal structure is located in the recess.

[0015] For example, according to at least one embodiment of the present disclosure, the storage device further comprises a first insulating layer and a second insulating layer; the first insulating layer surrounds a portion of the first metal structure, and the second insulating layer surrounds a portion of the resistance change memory and a portion of the second metal structure.

[0016] For example, according to at least one embodiment of the present disclosure, the dielectric layer comprises a first region overlapping with the resistance change reaction layer in the first direction and a second region except for the first region; a maximum thickness of the first region in the first direction is greater than a maximum thickness of the second region in the first direction.

[0017] The at least one embodiment of the present disclosure provides a method for manufacturing a memory device, comprising: sequentially forming a first metal structure and a first dielectric material layer on a substrate structure; forming an electrode hole in the first dielectric material layer by a first photolithography process to obtain a second dielectric material layer; wherein the electrode hole comprises a sidewall surrounding a first opening and a second opening opposite to each other in a first direction, the first opening exposes the first metal structure, and the second opening is located on a side surface of the second dielectric material layer away from the first metal structure; in a second direction perpendicular to the first direction, a size of the second opening is greater than a size of the first opening; forming a first electrode in the electrode hole; wherein the first electrode is completely located in the electrode hole, the first electrode comprises a first electrode part and a second electrode part connected to each other, the first electrode part is located on a side surface of the first metal structure away from the substrate structure, and the second electrode part is located on the sidewall; forming a resistive switching reaction layer and a second electrode arranged in a stack on a side of the first electrode away from the substrate structure to form a resistive switching memory; wherein at least part of the resistive switching reaction layer extends beyond an edge of the first electrode in the second direction; and forming a second metal structure on a side of the resistive switching memory away from the substrate structure to form the memory device.

[0018] For example, according to at least one embodiment of the present disclosure, forming the first electrode in the electrode hole comprises: forming a first electrode material layer in the electrode hole and on a side of the second dielectric material layer away from the substrate structure; forming a sacrificial layer on a side of the first electrode material layer away from the substrate structure; performing a planarization process to remove the sacrificial layer except for a part located in the electrode hole and to remove the first electrode material layer except for a part located in the electrode hole; and removing the part of the sacrificial layer in the electrode hole to obtain the first electrode.

[0019] For example, according to at least one embodiment of the present disclosure, a material of the sacrificial layer comprises spin-on carbon.

[0020] For example, according to at least one embodiment of the present disclosure, on the substrate structure, a projection of the first electrode is completely located in a projection of the resistive switching reaction layer, and there is a spacing between an edge of the projection of the first electrode and an edge of the projection of the resistive switching reaction layer.

[0021] For example, according to at least one embodiment of the present disclosure, forming the second metal structure on a side of the resistive switching memory away from the substrate structure comprises: forming an insulating material layer on a side of the resistive switching memory and the second dielectric material layer away from the substrate structure; and forming an insulating layer and the second metal structure located in the insulating layer by a damascene process.

[0022] For example, according to at least one embodiment of the present disclosure, forming the resistive switching reaction layer and the second electrode stacked on the side of the first electrode away from the substrate structure includes: forming a resistive switching reaction material layer and a second electrode material layer stacked on the side of the first electrode away from the substrate structure and the side of the second dielectric material layer away from the substrate structure; removing a portion of the resistive switching reaction material layer and a portion of the second electrode material layer by a second photolithography process to form the resistive switching reaction layer and the second electrode to form the resistive switching memory.

[0023] For example, according to at least one embodiment of the present disclosure, before forming the second metal structure on the side of the resistive switching memory away from the substrate structure, the method further includes: removing a portion of the second dielectric material layer by the second photolithography process to form a dielectric layer; wherein, the portion is the part of the second dielectric material layer excluding the portion that overlaps with the resistive switching reaction layer in the first direction. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] FIG. 1 This is a schematic diagram of a storage device.

[0026] FIG. 2A and FIG. 2B This is a schematic diagram of some film layers of different RRAMs.

[0027] FIG. 3 This is a schematic diagram of a storage device provided as an example in at least one embodiment of the present disclosure.

[0028] FIG. 4 This is a partial structural schematic diagram of a storage device provided as an example in at least one embodiment of the present disclosure.

[0029] FIG. 5 This is a schematic flowchart illustrating a method for manufacturing a storage device provided in at least one embodiment of the present disclosure.

[0030] FIG. 6A to FIG. 6H for FIG. 3 The diagram shows the manufacturing process of the storage device. Detailed Implementation

[0031] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings for the embodiments of the present disclosure to clearly and completely describe the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present disclosure.

[0032] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms "comprise", "include" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects.

[0033] The terms "parallel", "perpendicular" and "same" and the like used in the present disclosure include the strict "parallel", "perpendicular", "same" and the like, and "approximately parallel", "approximately perpendicular", "approximately same" and the like with a certain error, which, considering the measurement and the error related to the measurement of a specific quantity (that is, the limitation of the measurement system), represents the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. The "center" in the embodiments of the present disclosure can include the position strictly located at the geometric center and the position approximately at the center within a small area around the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0034] Compared with the memory such as embedded Flash memory (eFlash) and other new memory such as Magnetoresistive Random Access Memory (MRAM), Phase-Change Random Access Memory (PCRAM) and the like, RRAM has many advantages.

[0035] For example, because RRAM is fabricated using a back-end process located within the metal interconnect layer, it is compatible with unconventional processes such as High Voltage (HV) CMOS and Bipolar-CMOS-DMOS (BCD) processes, which is beneficial for large-scale integration. For example, fabricating RRAM only requires approximately 2-3 additional mask layers on top of the logic process, making its fabrication cost significantly lower than that of eFlash. For example, RRAM does not require the high voltages needed for eFlash internally, resulting in lower operating voltages and programming currents, making it ideal for low-power applications. For example, RRAM can be shrunk to below 10 nanometers, breaking the miniaturization limits of eFlash devices, and still maintains good applicability in advanced processes such as FinFET and Fully Depleted Silicon-On-Insulator (FD-SOI).

[0036] With the advancement of process nodes, embedded resistive random access memory (eRRAM) is regarded as the ideal choice for next-generation embedded storage IP and in-memory computing applications. At the same time, emerging application scenarios also place higher demands on the integration density, consistency and reliability of RRAM.

[0037] FIG. 1 This is a schematic diagram of a storage device. FIG. 2A and FIG. 2B This is a schematic diagram of some film layers of different RRAMs.

[0038] refer to FIG. 1The storage device can be embedded between the metal layer 21 and the metal layer 22 in a back end of line (BEOL) interconnection structure. For example, the metal layer 22 is located on a side of the metal layer 21 away from the substrate structure 10. For example, a short via can be formed in the metal diffusion barrier layer 30 between the metal layer 21 and the metal layer 22 by using a photolithography process, and a material with good conductivity and hole filling ability can be deposited in the short via to form the conductive material layer 14, thereby realizing electrical interconnection of the device. Then, the lower electrode material layer, the resistive switching material layer, and the upper electrode material layer can be formed on the conductive material layer 14, and a lower electrode (BE) 11-resistive core layer (RCL) 12-top electrode (TE) 13 sandwich structure can be formed by one etching process, that is, an RRAM device is formed. Subsequently, a dielectric material layer and a metal interconnection can be deposited to form a dielectric layer 40 and a metal layer 22. For example, the resistive core layer 12 can include a resistive switching layer (RSL) 12a and a metal capping layer (MCL) 12b.

[0039] The inventors of the present application found in research that the above-mentioned RRAM device is formed by one etching process, but due to the above-mentioned process which is realized by physical bombardment and chemical reaction of high-energy plasma on the RRAM film layer, plasma induced damage (PID) is difficult to avoid in the etching process. Referring to FIG. 2A As shown in a of FIG. 1, the surface around the resistive core layer 12 of the RRAM device and the interface between the film layers can be damaged in the etching process, resulting in concentration of electric field. At the same time, unnecessary dangling bonds can be generated on the surface of the film layer in the process of etching the resistive core layer 12 and the lower electrode 11, thereby causing short circuit breakdown of the RRAM device by adsorbing charged ions.

[0040] Moreover, due to the stacking property of the RRAM device film layer, the resistive switching layer 12a is exposed to the environment in the process of etching the lower electrode 11. Referring to FIG. 2A As shown in b of FIG. 1, after bombardment of the plasma, the conductive metal of the lower electrode 11 can be re-deposited on the resistive switching layer 12a. Due to the thin thickness of the resistive switching layer 12a of the RRAM device, a conductive path can be formed on the sidewall of the resistive switching layer 12a, resulting in short circuit breakdown.

[0041] Therefore, it is known that FIG. 2AThe two failure mechanisms shown in a and b of FIG. 1 can likely cause initial low resistance of some devices, resulting in fluctuation of RRAM array devices, and further reflecting reliability degradation of RRAM chips.

[0042] To improve the above problems, with reference to FIG. 2B A passivation process, such as thermal oxidation process, can be used to form a passivation part 12c on a part of the sidewall, thereby weakening the negative effects caused by etching damage and improving the consistency among RRAM devices. However, the process shown in FIG. 2 can consume the metal covering layer 12b, reducing the effective size of the RRAM device and increasing the forming voltage. FIG. 2B The process shown in FIG. 2 can consume the metal covering layer 12b, reducing the effective size of the RRAM device and increasing the forming voltage. FIG. 2B The process shown in FIG. 2 can consume the metal covering layer 12b, reducing the effective size of the RRAM device and increasing the forming voltage.

[0043] At least one embodiment of the present disclosure provides a storage device, comprising: a substrate structure; a first metal structure on the substrate structure; a second metal structure on a side of the first metal structure away from the substrate structure; a dielectric layer at least partially between the first metal structure and the second metal structure; a resistive random access memory (RRAM) comprising a first electrode, a resistive switching layer and a second electrode stacked in a first direction, the resistive switching layer being between the first electrode and the second electrode; wherein the dielectric layer comprises an electrode hole, a sidewall of the electrode hole surrounding a first opening and a second opening opposite to each other in the first direction, the first opening exposing the first metal structure, and the second opening being on a side surface of the dielectric layer away from the first metal structure; in a second direction intersecting the first direction, a size of the second opening is greater than a size of the first opening; the first electrode is completely in the electrode hole, the first electrode comprising a first electrode part and a second electrode part connected to each other, the first electrode part being on a side surface of the first metal structure away from the substrate structure, and the second electrode part being on the sidewall; at least a part of the resistive switching layer extends beyond an edge of the first electrode in the second direction.

[0044] The manufacturing method of the storage device comprises the following steps: sequentially forming a first metal structure and a first dielectric material layer on a substrate structure; forming an electrode hole in the first dielectric material layer by a first photolithography process to obtain a second dielectric material layer; wherein the electrode hole comprises a sidewall surrounding a first opening and a second opening opposite to each other in a first direction, the first opening exposes the first metal structure, and the second opening is located on a side surface of the second dielectric material layer away from the first metal structure; in a second direction perpendicular to the first direction, the size of the second opening is greater than the size of the first opening; forming a first electrode in the electrode hole; wherein the first electrode is completely located in the electrode hole, the first electrode comprises a first electrode part and a second electrode part connected to each other, the first electrode part is located on a side surface of the first metal structure away from the substrate structure, and the second electrode part is located on the sidewall; forming a resistive switching reaction layer and a second electrode arranged in a stack on a side of the first electrode away from the substrate structure to form a resistive switching memory; wherein at least part of the resistive switching reaction layer extends beyond the edge of the first electrode in the second direction; and forming a second metal structure on a side of the resistive switching memory away from the substrate structure to form the storage device.

[0045] The storage device and the manufacturing method thereof provided by at least one embodiment of the present disclosure are advantageous in that the first opening and the second opening of the electrode hole in the dielectric layer have different sizes, so that the sidewall of the electrode hole is inclined, which is beneficial to forming the first electrode in the electrode hole. Moreover, the region where the resistive switching reaction layer contacts the first electrode comprises an electric field resistive switching region, and since the resistive switching reaction layer extends beyond the edge of the first electrode, it is beneficial to limit the range of the electric field resistive switching region and prevent short circuit in other undesired regions. In this way, the reliability of the resistive switching memory and the consistency between devices are improved, and the overall size of the storage device can be reduced. Meanwhile, under the same other design process conditions, the size of the resistive switching memory cell can be increased and the operating voltage can be reduced, which is beneficial to improving the consistency and reliability of the storage device.

[0046] The storage device and the manufacturing method thereof will be described below in combination with the accompanying drawings and some embodiments.

[0047] FIG. 3 The schematic diagram of the storage device provided for an example in at least one embodiment of the present disclosure.

[0048] Reference FIG. 3The storage device includes a substrate structure 500, a first metal structure 300, a second metal structure 400, a dielectric layer 200, and a resistive random access memory 100. The first metal structure 300 is located on the substrate structure 500, and the second metal structure 400 is located on a side of the first metal structure 300 away from the substrate structure 500. At least part of the dielectric layer 200 is located between the first metal structure 300 and the second metal structure 400. The resistive random access memory 100 includes a first electrode 110, a resistive switching layer 130, and a second electrode 120 stacked in a first direction, and the resistive switching layer 130 is located between the first electrode 110 and the second electrode 120. Thus, the resistive random access memory 100 can form a stacked sandwich structure of the first electrode 110-resistive switching layer 130-second electrode 120.

[0049] With reference to FIG. 3 The dielectric layer 200 includes an electrode hole 201, and a sidewall 210 of the electrode hole 201 surrounds a first opening 201A and a second opening 201B formed opposite in the first direction, the first opening 201A exposes the first metal structure 300, and the second opening 201B is located on a side surface of the dielectric layer 200 away from the first metal structure 300. In a second direction intersecting the first direction, the size of the second opening 201B is greater than the size of the first opening 201A. For example, by setting the first opening 201A and the second opening 201B with different sizes, at least part of the sidewall 210 of the electrode hole 201 can be inclined relative to the side surface of the dielectric layer 200 away from the first metal structure 300.

[0050] With reference to FIG. 3 The first electrode 110 is completely located in the electrode hole 201, and the first electrode 110 includes a first electrode part 111 and a second electrode part 112 connected to each other, the first electrode part 111 is located on a side surface of the first metal structure 300 away from the substrate structure 500, and the second electrode part 112 is located on the sidewall 210. At least part of the resistive switching layer 130 extends beyond the edge of the first electrode 110 in the second direction.

[0051] With reference to FIG. 3 The storage device provided by the embodiments of the present disclosure is advantageous in forming the first electrode 110 in the electrode hole 201, because the first opening 201A and the second opening 201B of the electrode hole 201 in the dielectric layer 200 have different sizes, so that the sidewall 210 of the electrode hole 201 is inclined. Moreover, the area where the resistive switching layer 130 contacts the first electrode 110 includes an electric field resistive switching region, because the resistive switching layer 130 extends beyond the edge of the first electrode 110, so that the range of the electric field resistive switching region is limited, and short circuit in other undesired areas is prevented.

[0052] Compared with the RRAM device shown in FIG. 1 to FIG. 2B , inFIG. 3 In the storage device shown, the first electrode 110 of the resistive memory 100 is disposed in the electrode hole 201, and no electrode is disposed on the side wall of the electrode hole 201. The conductive material layer 14 shown is advantageous in reducing the size of the storage device in the first direction. Moreover, the resistive switching layer 130 is disposed to extend beyond the edge of the first electrode 110. The resistive switching layer 130 and the first electrode 110 can be formed by two processes respectively, so that the risk of short circuit caused by damage to the resistive switching layer 130 by etching can be reduced. Moreover, no side wall passivation process is needed. In this way, the reliability of the resistive memory 100 and the consistency among devices can be improved, and the overall size of the storage device can be reduced. Meanwhile, under the same other design and process conditions, the size of the resistive memory cell can be increased and the operating voltage can be reduced, which is advantageous in improving the consistency and reliability of the storage device. FIG. 1

[0053] Reference is made to FIG. 1C, which shows a cross-sectional view of the storage device shown in FIG. 1A. The resistive memory 100 can be considered as a resistive switching via between the first metal structure 300 and the second metal structure 400. For example, the first metal structure 300 and the second metal structure 400 can be two adjacent metal structures in a back-end-of-line interconnection structure. FIG. 3

[0054] Reference is made to FIG. 1D, which shows a cross-sectional view of the storage device shown in FIG. 1A. The resistive memory 100 can store data by changing the state of the conductive fiber or oxygen vacancy in the resistive switching layer 130. For example, the initial state of the resistive memory 100 is in a high resistance state. By applying a large positive operating voltage to the resistive memory 100, the resistive switching layer 130 between the first electrode 110 and the second electrode 120 forms a conductive filament due to soft dielectric breakdown, and the resistive memory 100 switches from the high resistance state to a low resistance state. This process is called a forming process. The set process is similar, but the required positive operating voltage is relatively small. By applying a reverse operating voltage to the resistive memory 100, the conductive filament cannot be connected to the electrodes, so that the resistive memory 100 switches from the low resistance state to the high resistance state, which is called a reset process. FIG. 3

[0055] ​​​For example, the storage device can include one or more transistors (not shown in the figures) and can include one or more resistive switching memory elements (e.g., resistive switching memory 100), for example, the transistors are denoted as T and the resistive switching memory elements are denoted as R, can include but not limited to 1T1R, 2T1R, 2T2R, etc. For example, the transistor has a gate, a source and a drain, and the resistive switching memory element can be connected with the source or the drain of the transistor. For example, the gate of the transistor is connected with a word line (WL), the source is connected with a source line (SL), the drain is connected with the resistive switching memory element and is connected with a bit line (BL) through the resistive switching memory element. It should be understood that the positions of the source and the drain of the transistor and the connection manner can be interchangeable with each other.

[0056] For example, the substrate structure can include a substrate and an element layer formed on the substrate. For example, the substrate can be or include a semiconductor substrate, for example, can be a bulk silicon substrate, a silicon on insulation (SOI) substrate, etc. For example, the element layer can include active elements such as transistors, passive elements such as capacitors or a combination thereof. For example, the transistor can be formed by a front end of line (FEOL) process. For example, the substrate structure includes a transistor (not shown) electrically connected with the resistive switching memory, for example, the source or the drain of the transistor can be electrically connected with the first electrode.

[0057] Reference is made to FIG. 3 For example, the dielectric layer 200 can be an inter-layer dielectric (ILD). For example, the dielectric layer 200 can act as a metal diffusion barrier layer to block the diffusion of metal. For example, the material of the dielectric layer 200 can include silicon carbon nitride (SiCN), silicon nitride (SiN), aluminum nitride (AlN), etc.

[0058] Reference is made to FIG. 3 For example, the sidewall 210 of the electrode hole 201 has a certain slope angle to facilitate the formation of the first electrode 110. For example, the first opening 201A is opposite to the second direction in the first direction, for example, the orthographic projection of the first opening 201A on the substrate structure 500 is completely located within the range surrounded by the orthographic projection of the second opening 201B on the substrate structure 500.

[0059] Reference is made to FIG. 3 For example, the first opening 201A exposes the first metal structure 300, so that the first electrode 110 located in the electrode hole 201 can be electrically connected with the first metal structure 300 through the first electrode part 111.

[0060] Reference is made to FIG. 3 For example, the first direction can beFIG. 3 The direction indicated by the Y-direction arrow, or the direction opposite to the direction indicated by the arrow. For example, the second direction could be... FIG. 3 The direction indicated by the X-direction arrow, or the direction opposite to the direction indicated by the arrow. For example, the first direction and the second direction can be perpendicular. It is understood that the second direction can also be a direction perpendicular to the Y-direction and intersecting the X-direction; this disclosure does not impose any restrictions on this.

[0061] refer to FIG. 3 For example, the dimension of the first opening 201A in the second direction can be the maximum dimension of the first opening 201A. For example, the outer contour shape of the first opening 201A can be approximately circular, and the maximum dimension of the first opening 201A can be the diameter of the first opening 201A. Of course, this disclosure is not limited to this; for example, the outer contour shape of the first opening can be approximately rectangular. For example, when the outer contour shape of the first opening is rectangular, the maximum dimension of the first opening can be the dimension of the longer side of the first opening.

[0062] refer to FIG. 3 For example, the dimension of the second opening 201B in the second direction can be the maximum dimension of the second opening 201B. For example, the outer contour shape of the second opening 201B can be approximately circular, and the maximum dimension of the second opening 201B can be the diameter of the second opening 201B. Of course, this disclosure is not limited to this; for example, the outer contour shape of the second opening can be approximately rectangular. For example, when the outer contour shape of the second opening is rectangular, the maximum dimension of the second opening can be the dimension of the longer side of the second opening.

[0063] refer to FIG. 3 It is understood that the dimensions of the first opening 201A and the second opening 201B in the X direction can be measured in a cross-section taken from the storage device by a reference plane. The reference plane can be a plane parallel to the XY plane. It is understood that dimensions such as thickness, mentioned later, can be measured in this cross-section, and will not be elaborated further.

[0064] refer to FIG. 3 In some examples, on the substrate structure 500, the orthographic projection of the first electrode 110 may lie entirely within the orthographic projection of the resistive switching layer 130, and there is a gap between the edge of the orthographic projection of the first electrode 110 and the edge of the orthographic projection of the resistive switching layer 130. For example, the periphery of the resistive switching layer 130 may extend completely beyond the first electrode 110. This better prevents short circuits at the edges of the resistive switching layer 130. For example, a portion of the resistive switching layer 130 may be located on the first electrode 110, and another portion may be located on the surface of the dielectric layer 200 away from the substrate structure 500.

[0065] However, the present disclosure is not limited thereto, for example, in the second direction, only a part of the resistance-switching reaction layer can extend beyond the edge of the first electrode, and the other part can coincide with the edge of the first electrode, so that the edge of the resistance-switching reaction layer can also be prevented from short-circuiting to some extent.

[0066] Reference is made to FIG. 3 For example, the circumferential side of the first metal structure 300 and the circumferential side of the second metal structure 400 can be provided with a metal diffusion barrier layer to block the diffusion of metal into the insulating layer. For example, the first metal structure 300 and the second metal structure 400 can be metal conductive lines. For example, the present disclosure schematically shows that the interconnection structure includes the first metal structure 300 and the second metal structure 400, but the present disclosure is not limited thereto. For example, the interconnection structure can include multiple layers of conductive lines and conductive vias. Multiple elements in the element layer can be connected through the interconnection structure to form a functional circuit. For example, the resistance-switching memory 100 can be located between any two layers of conductive layers.

[0067] Reference is made to FIG. 3 For example, the resistance-switching reaction layer 130 can include a resistance-switching layer 131 and a metal capping layer 132. The metal capping layer 132 can be electrically connected with the second electrode 120. The resistance-switching reaction layer 130 is configured to realize the conversion between the high-resistance state and the low-resistance state under the action of the electric field between the first electrode 110 and the second electrode 120. For example, the erasing and writing characteristics of the RRAM can be realized by the oxygen exchange between the resistance-switching layer 131 and the metal capping layer 132 in the resistance-switching reaction layer 130. By providing the metal capping layer 132, the stability of the resistance-switching memory 100 can be improved.

[0068] However, the present disclosure is not limited thereto, for example, the metal capping layer can also be omitted, and the erasing and writing of the RRAM can be realized by the oxygen exchange between the resistance-switching layer and the second electrode.

[0069] Reference is made to FIG. 3 In some examples, in a plane perpendicular to the second direction, the orthographic projection of the first electrode 110 is located within the orthographic projection of the sidewall 210. Thus, the first electrode 110 can be completely confined within the electrode hole 201 by the dielectric layer 200. Reference is made to FIG. 3 For example, in a plane perpendicular to the second direction, the edge of the orthographic projection of the first electrode 110 can coincide with the edge of the orthographic projection of the sidewall 210. It can be understood that the first electrode 110 does not substantially extend beyond the electrode hole 201, i.e., does not substantially extend to the side surface of the dielectric layer 200 away from the substrate structure 500 other than the electrode hole 201.

[0070] Reference is made to FIG. 3In some examples, the ratio of the thickness of the first electrode portion 111 to the thickness of the second electrode portion 112 is 0.9-1.1. For example, the film layer thickness of the first electrode 110 is substantially uniform, i.e., the thickness of the first electrode portion 111 is substantially the same as the thickness of the second electrode portion 112.

[0071] With reference to FIG. 3 For example, the first electrode 110 which is substantially uniform in thickness as a whole can surround a portion of the variable resistance reaction layer 130 in the circumferential direction. For example, the variable resistance memory 100 including the first electrode 110 in the surrounding structure can be referred to as a Fin RRAM device. Thus, by using the first electrode 110 in the surrounding structure, the area of the electric field variable resistance region, i.e., the effective area of the variable resistance memory 100, can be increased under the same layout design area. Thus, the device size of the variable resistance memory 100 and the memory device including the variable resistance memory 100 can be favorably scaled down.

[0072] With reference to FIG. 3 In some examples, the orthogonal projection of the variable resistance reaction layer 130 on a plane perpendicular to the second direction overlaps the orthogonal projection of the sidewall 210. For example, the variable resistance reaction layer 130 can have a portion of the structure located in the space surrounded by the sidewall 210 of the electrode hole 201. Thus, the area of the electric field variable resistance region, i.e., the effective area of the variable resistance memory 100, can be increased under the same layout design area.

[0073] With reference to FIG. 4 For example, the film layer thickness of the first electrode 110 is substantially uniform, so that the first electrode 110 formed in the electrode hole 201 can be conformal to the electrode hole 201. Thus, the first electrode portion 111 and the second electrode portion 112 can substantially form a groove structure. The film layer thickness of the variable resistance reaction layer 130 formed on the first electrode 110 is substantially uniform, so that the variable resistance reaction layer 130 can have a portion located in the groove structure formed by the first electrode 110.

[0074] For example, conformal means that the thickness of each portion of the film layer in the direction perpendicular to the extension direction thereof is substantially equal, which will not be described hereinafter.

[0075] With reference to FIG. 3 and FIG. 3For example, on a plane perpendicular to the second direction, the orthographic projection of the resistive switching layer 130 can overlap with the orthographic projection of the second arcuate portion 212 of the sidewall 210. Thus, the thinner resistive switching layer 130 can be better formed on the first electrode 110 and the dielectric layer 200. For example, the orthographic projection of the resistive switching layer 130 can also overlap with the orthographic projection of the first arcuate portion 211 of the sidewall 210. For example, the shape and size of the resistive switching layer 130 can be determined by designing parameters such as the size of the electrode hole 201 and the thickness of the first electrode 110; this disclosure does not impose any limitations on this.

[0076] refer to FIG. 3 In some examples, the orthographic projection of the second electrode 120 overlaps with the orthographic projection of the sidewall 210 on a plane perpendicular to the second direction. For example, a portion of the structure of the second electrode 120 may be located within the space surrounded by the sidewall 210 of the electrode hole 201. Thus, with the same layout design area, the area of ​​the electric field resistive switching region can be increased, i.e., the effective area of ​​the resistive switching memory 100 can be increased.

[0077] refer to FIG. 4 For example, the film thickness of the first electrode 110 is substantially uniform, so that the first electrode 110 formed within the electrode hole 201 can conform to the electrode hole 201. Simultaneously, the film thickness of the resistive switching layer 130 is substantially uniform, so that the resistive switching layer 130 can conform to the first electrode 110, such as forming a groove structure. Therefore, a portion of the second electrode 120 formed on the resistive switching layer 130 can be located within the groove structure formed by the resistive switching layer 130.

[0078] Refer to the examples described later. FIG. 3 and FIG. 3 For example, on a plane perpendicular to the second direction, the orthographic projection of the second electrode 120 can overlap with the orthographic projection of the second arcuate portion 212 of the sidewall 210. Thus, the second electrode 120 can be better formed on the resistive switching layer 130. For example, the orthographic projection of the second electrode 120 can also overlap with the orthographic projection of the first arcuate portion 211 of the sidewall 210. For example, the shape and size of the second electrode 120 can be determined by designing parameters such as the size of the electrode hole 201, the thickness of the first electrode 110, and the thickness of the resistive switching layer 130; this disclosure does not impose any limitations on this.

[0079] refer to FIG. 4 In some examples, the orthographic projection of the second electrode 120 coincides with the orthographic projection of the resistive switching layer 130 on a plane perpendicular to the first direction. For example, the edge of the second electrode 120 is flush with the edge of the resistive switching layer 130. Thus, the electric field resistive switching region formed between the first electrode 110, the resistive switching layer 130, and the second electrode 120 can be maximized.

[0080] Reference is made to FIG. 4 In some examples, the second electrode 120 has a recess 121 away from one side surface of the substrate structure 500, and a portion of the second metal structure 400 is located in the recess 121. For example, the first electrode 110 is conformal to the electrode hole 201, the resistive switching reaction layer 130 is conformal to the first electrode 110, and the second electrode 120 is conformal to the resistive switching reaction layer 130. Thus, the second electrode 120 forms the recess 121 away from one side of the substrate structure 500. By setting the second metal structure 400 to have a portion located in the recess 121, the electrical connection reliability between the second metal structure 400 and the second electrode 120 can be improved.

[0081] FIG. 3 A partial structure schematic diagram of a storage device provided for an example in at least one embodiment of the present disclosure is shown. FIG. 4 The storage device shown is different from FIG. 3 The storage device shown is different from FIG. 4 The electrode hole of the storage device shown is different from FIG. 4 The electrode hole of the storage device shown.

[0082] It can be understood that, in the case of setting the electrode hole as shown in FIG. 3 The first electrode formed in the electrode hole, and the resistive switching reaction layer and the second electrode laminated on the first electrode, can also be different from FIG. 4 The first electrode, the resistive switching reaction layer, and the second electrode shown in FIG. 3 The first electrode formed in the electrode hole shown in FIG. 4 The electrode hole, the resistive switching reaction layer can be conformal to the first electrode, the second electrode can be conformal to the first electrode, etc., and the present disclosure does not limit this.

[0083] Reference is made to FIG. 3 and FIG. 4 In some examples, the side wall 210 includes a main body portion 213 and a first arc-shaped portion 211 connected between the main body portion 213 and one side surface of the substrate structure 500 away from the first metal structure 300. The side edge of the first arc-shaped portion 211 away from the main body portion 213 surrounds the first opening 201A. By setting the first arc-shaped portion 211, the deposition effect of the first electrode 110 in the electrode hole 201 can be improved, and the uniform distribution of the electric field and the stress can be ensured. At the same time, it is also beneficial to the formation of the resistive switching reaction layer 130 and the second electrode 120.

[0084] Reference is made to FIG. 3 and FIG. 4For example, the slope angle between the sidewall 210 of the electrode hole 201 and the surface of the first metal structure 300 can be regarded as the included angle between the main body part 213 in the sidewall 210 and the surface of the first metal structure 300.

[0085] With reference to FIG. 3 and FIG. 4 For example, the slope angle between the sidewall 210 of the electrode hole 201 and the surface of the first metal structure 300 can be regarded as the included angle between the main body part 213 in the sidewall 210 and the surface of the first metal structure 300.

[0086] With reference to FIG. 3 and FIG. 3 In some examples, the maximum dimension D of the first opening 201A in the second direction is 5-100 nm. By setting the size range of the first opening 201A, the deposition effect of the first electrode part 111 and the second electrode part 112 in the electrode hole 201 can be improved while ensuring good contact between the first electrode 110 and the first metal structure 300.

[0087] With reference to FIG. 3 and FIG. 3 In some examples, the sidewall 210 includes the main body part 213 and a second arc-shaped part 212, the second arc-shaped part 212 being connected between the main body part 213 and the side surface of the dielectric layer 200 excluding the electrode hole 201 away from the substrate structure 500, and the side edge of the second arc-shaped part 212 away from the main body part 213 surrounding to form a second opening 201B. By setting the second arc-shaped part 212, the deposition effect of the first electrode 110 and the resistance change reaction layer 130 can be improved, and the uniform distribution of electric field and stress can be ensured. At the same time, it is also conducive to the formation of the second electrode 120.

[0088] With reference to FIG. 5 and FIG. 6A to FIG. 6H For example, the slope angle between the sidewall 210 of the electrode hole 201 and the surface of the first metal structure 300 can be regarded as the included angle between the main body part 213 in the sidewall 210 and the surface of the first metal structure 300.

[0089] With reference to FIG. 3In some examples, the storage device further includes a first insulating layer 610 and a second insulating layer 620. The first insulating layer 610 surrounds a portion of the first metal structure 300, and the second insulating layer 620 surrounds a portion of the resistive random access memory 100 and a portion of the second metal structure 400. For example, the resistive random access memory 100 and the second metal structure 400 can be surrounded by the same layer of insulating layer. It can be appreciated that the resistive random access memory 100 has a smaller size in the first direction, e.g., does not occupy a whole layer of metal structure.

[0090] Reference is made to FIG. 5 to FIG. 6H For example, the first insulating layer 610 and the second insulating layer 620 can be an Inter-Metal Dielectric (IMD).

[0091] Reference is made to FIG. 6A to FIG. 6H In some examples, the dielectric layer 200 includes a first region Z1 overlapping the resistive switching layer 130 in the first direction and a second region Z2 other than the first region Z1. The maximum thickness of the first region Z1 in the first direction is greater than the maximum thickness of the second region Z2 in the first direction. For example, in the process of forming the resistive switching layer 130 and the second electrode 120, the dielectric layer 200 can have a smaller thickness in the second region Z2 due to over-etching. By properly over-etching the second region Z2, it can be ensured that the resistive switching layer 130 can be completely removed; at the same time, since the first electrode 110 is located inside the edge of the resistive switching layer 130 in the planar direction (e.g., the second direction), after over-etching, it can be ensured that the first electrode 110 is not easy to form a short circuit structure with the second electrode 120.

[0092] Reference is made to FIG. 3 For example, in the plane perpendicular to the second direction, the orthographic projection of the first electrode 110 overlaps the second insulating layer 620. For example, in the second direction, the dielectric layer 200 can have a portion between the second electrode portion 112 and the second insulating layer 620. For example, the dielectric layer 200 can form a step structure at the position flush with the edge of the resistive switching layer 130.

[0093] FIG. 5 to FIG. 6H A flowchart of a manufacturing method of a storage device provided in an example of at least one embodiment of the present disclosure is shown. FIG. 4 A flowchart of a manufacturing process of a storage device is shown. FIG. 3 A flowchart of a manufacturing process of a storage device is shown.

[0094] Reference is made to FIG. 5 The manufacturing method of the storage device provided in an example of at least one embodiment of the present disclosure is shown.

[0095] Step S10: sequentially forming a first metal structure 300 and a first dielectric material layer 2001 on a substrate structure 500.

[0096] Step S20: forming an electrode hole 201 in the first dielectric material layer 2001 by a first photolithography process to obtain a second dielectric material layer 2002; the electrode hole 201 includes a sidewall 210 surrounding a first opening 201A and a second opening 201B opposite in a first direction, the first opening 201A exposes the first metal structure 300, and the second opening 201B is located on a side surface of the second dielectric material layer 2002 away from the first metal structure 300; in a second direction perpendicular to the first direction, the size of the second opening 201B is greater than the size of the first opening 201A.

[0097] Step S30: forming a first electrode 110 in the electrode hole 201; the first electrode 110 is completely located in the electrode hole 201, and the first electrode 110 includes a first electrode part 111 and a second electrode part 112 connected to each other, the first electrode part 111 is located on a side surface of the first metal structure 300 away from the substrate structure 500, and the second electrode part 112 is located on the sidewall 210.

[0098] Step S40: forming a resistive switching reaction layer 130 and a second electrode 120 in a stacked manner on a side of the first electrode 110 away from the substrate structure 500 to form a resistive random access memory 100; in the second direction, at least part of the resistive switching reaction layer 130 extends beyond the edge of the first electrode 110 in the second direction.

[0099] Step S50: forming a second metal structure 400 on a side of the resistive random access memory 100 away from the substrate structure 500 to form a storage device.

[0100] Since the manufacturing method of the storage device according to the embodiments of the present disclosure is used to manufacture the above-mentioned storage device, it also has corresponding beneficial technical effects, which will not be repeated here. It should be noted that the manufacturing method of the storage device provided by the embodiments of the present disclosure basically does not need to introduce additional process flow and special materials, and is process-friendly and material-friendly.

[0101] It can be understood that, FIG. 6A Only the manufacturing process schematic diagram of the storage device as FIG. 3 shown is schematically shown. But the present disclosure is not limited thereto. For example, the storage device including the electrode hole including the circular arc part as FIG. 5 shown can also be manufactured by a method basically the same as the manufacturing method shown in FIG. 6A , and the present disclosure does not limit this.

[0102] Reference is made to FIG. 6B , FIG. 3 and FIG. 5For example, in step S10, a first dielectric material layer 2001 can be deposited on a side of the first metal structure 300 away from the substrate structure 500, and a material of the first dielectric material layer 2001 can include silicon carbon nitride (SiCN), silicon nitride (SiN), aluminum nitride (AlN), etc.

[0103] Referring to FIG. 6C , FIG. 6D , FIG. 6E and FIG. 6F For example, in step S20, a photoresist layer can be formed on the first dielectric material layer 2001, and the photoresist layer can be patterned by a photolithography process using a first mask to define a mask pattern. Then, the first dielectric material layer 2001 can be etched using the mask pattern as an etching mask to form a second dielectric material layer 2002 including an electrode hole 201. Then, the mask pattern can be removed, for example, by a stripping process.

[0104] Referring to FIG. 6C , FIG. 6C , FIG. 6D In some examples, step S30 includes the following steps: forming a first electrode material layer 1101 on a side of the second dielectric material layer 2002 away from the substrate structure 500 and in the electrode hole 201. Referring to FIG. 6E forming a sacrificial layer 7001 on a side of the first electrode material layer 1101 away from the substrate structure 500. Referring to FIG. 6D performing a planarization process to remove portions of the sacrificial layer 7001 except for a portion located in the electrode hole 201 and to remove portions of the first electrode material layer 1101 except for a portion located in the electrode hole 201. Referring to FIG. 6E removing the portion of the sacrificial layer 7001 in the electrode hole 201 to obtain a first electrode 110.

[0105] Referring to FIG. 3 For example, the first electrode material layer 1101 can be deposited by a physical vapor deposition (PVD) process. For example, a thickness of the first electrode material layer 1101 can be 10 angstroms to 1000 angstroms.

[0106] Referring to FIG. 4 For example, a material of the first electrode material layer 1101 can include at least one of tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), platinum (Pt), gold (Au), tungsten (W), tungsten nitride (WN), aluminum copper alloy (AlCu), tantalum (Ta), molybdenum (Mo), palladium (Pd), cobalt (Co), nickel (Ni), iridium (Ir), iron (Fe), beryllium (Be), chromium (Cr), zirconium (Zr), aluminum (Al), titanium (Ti). However, the present disclosure is not limited thereto.

[0107] Referring to FIG. 6D and FIG. 6E For example, the planarization process can include a Chemical Mechanical Polishing (CMP) process or an Etch Back process, etc. For example, after the planarization process is performed, the remaining part of the sacrificial layer 7001 away from the one side surface of the substrate structure 500, the remaining part of the electrode material layer 1101 away from the one side surface of the substrate structure 500, and the second dielectric material layer 2002 away from the one side surface of the substrate structure 500 can be substantially flush in a direction parallel to the main surface of the substrate structure 500.

[0108] Referring to FIG. 3 and FIG. 5 In some examples, the material of the sacrificial layer 7001 includes Spin On Carbon (SOC). Thus, in the step of subsequently removing the sacrificial layer 7001, the sacrificial layer 7001 can be removed by an ashing process, i.e. by a controlled reaction with oxygen in an oxygen-containing environment. By setting the material of the sacrificial layer 7001 as Spin On Carbon, the risk of the sacrificial layer 7001 remaining is lower. In the case that the first electrode 110 is a special structure as shown in FIG. 1C (or a special structure formed in the electrode hole 201 as shown in FIG. 1D), since the sacrificial layer 7001 substantially does not remain, the first electrode 110 can have good surface properties, such as the first electrode 110 having a smooth surface and substantially no surface impurity contamination. Of course, the sacrificial layer 7001 can also be removed by other cleaning processes, which are not limited by the present disclosure. FIG. 6G FIG. 6H Referring to and

[0109] For example, the deposition thickness of the sacrificial layer 7001 can be 1000 angstroms to 2000 angstroms. FIG. 6G FIG. 6H Referring to ,

[0110] and FIG. 6G In some examples, the step S40 includes: forming the resistive switching reaction material layer 1301 and the second electrode material layer 1201 in a stacked manner on the one side of the first electrode 110 away from the substrate structure 500 and on the one side of the second dielectric material layer 2002 away from the substrate structure 500. Referring to FIG. 6G , a part of the resistive switching reaction material layer 1301 and a part of the second electrode material layer 1201 are removed by a second photolithography process to form the resistive switching reaction layer 130 and the second electrode 120, thereby forming the resistive switching memory 100. FIG. 6G FIG. 6G Referring to and

[0111] In some examples, the step S40 includes: forming the resistive switching reaction material layer 1301 and the second electrode material layer 1201 in a stacked manner on the one side of the first electrode 110 away from the substrate structure 500 and on the one side of the second dielectric material layer 2002 away from the substrate structure 500. Referring to FIG. 6G , a part of the resistive switching reaction material layer 1301 and a part of the second electrode material layer 1201 are removed by a second photolithography process to form the resistive switching reaction layer 130 and the second electrode 120, thereby forming the resistive switching memory 100. FIG. 6HFor example, the resistive switching reaction material layer 1301 can include a resistive switching material layer 1311 and a metal covering material layer 1321. For example, the resistive switching material layer 1311 can be deposited by an atom layer deposition (ALD) process. Of course, the present disclosure is not limited thereto, and a PVD process or a pulsed laser deposition (PLD) process, etc. can also be used.

[0112] Referring to FIG. 6G For example, the material of the resistive switching material layer 1311 can include at least one of hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum oxide (AlO x ), silicon oxide (SiO x ). However, the present disclosure is not limited thereto.

[0113] Referring to FIG. 6H For example, the thickness of the resistive switching material layer 1311 can be 5 angstroms to 50 angstroms.

[0114] Referring to FIG. 3 For example, the material of the metal covering material layer 1321 can include at least one of tantalum (Ta), titanium (Ti), hafnium (Hf), aluminum (Al), platinum (Pt), titanium oxide (TiO x ), germanium oxide (GeO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ). However, the present disclosure is not limited thereto.

[0115] Referring to FIG. 5 For example, the material of the second electrode material layer 1201 can include at least one of titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), aluminum (Al), tungsten (W), ruthenium (Ru), vanadium (V), copper (Cu), beryllium (Be), cobalt (Co), osmium (Os). However, the present disclosure is not limited thereto.

[0116] Referring to FIG. 6A to FIG. 6H and FIG. 6G For example, the above removing the resistive switching reaction material layer 1301 means removing the resistive switching material layer 1311 and the metal covering material layer 1321. Thereby, a resistive switching reaction layer 130 including a resistive switching layer 131 and a metal covering layer 132 can be formed.

[0117] Referring to FIG. 6H and FIG. 6HFor example, a photoresist layer can be formed on the second electrode material layer 1201, and the photoresist layer is patterned by a photolithography process to define a mask pattern using a second mask. Then, the second electrode material layer 1201, the resistive switching reaction material layer 1301 including the resistive switching material layer 1311 and the metal covering material layer 1321 are etched using the mask pattern as an etching mask to remove the portions of these material layers not covered by the mask pattern, and the remaining portions together with the first electrode 110 form the resistive switching memory 100 in a stacked structure. Then, the mask pattern can be removed by a stripping process, for example.

[0118] Referring to FIG. 3 , FIG. 6H and FIG. 3 , it is known from the above steps S10 to S40 that the first electrode 110 and the resistive switching reaction layer 130 and the second electrode 120 are formed by two processes, but without the need for additional masks. Thus, the manufacturing method of the storage device provided by the present disclosure does not require additional cost overhead and has good adaptability to some large-scale production platforms. At the same time, since the first electrode 110 is manufactured separately from the resistive switching reaction layer 130, the device reliability problem caused by continuous etching processes can be effectively prevented.

[0119] Referring to FIG. 6H and FIG. 3 , in some examples, before step S50, further comprising: removing a portion of the second dielectric material layer 2002 by a second photolithography process to form the dielectric layer 200; the portion is a portion of the second dielectric material layer 2002 other than the portion overlapping the resistive switching reaction layer 130 in the first direction. For example, when the second electrode material layer 1201 and the resistive switching reaction material layer 1301 are etched, a portion of the second dielectric material layer 2002 can be removed due to over-etching.

[0120] Referring to FIG. 3 and FIG. 3 , in some examples, step S50 includes forming an insulating material layer on a side of the resistive switching memory 100 and the second dielectric material layer 2002 away from the substrate structure 500, and forming the insulating layer and the second metal structure 400 in the insulating layer by a damascene process.

[0121] Referring to FIG. 6H and FIG. 3 , for example, the insulating material layer with low dielectric constant can be grown on the side of the dielectric layer 200 away from the substrate structure 500 and the side of the resistive switching memory 100 away from the substrate structure 500 by chemical vapor deposition (CVD).

[0122] Referring to FIG. 6H and FIG. 3For example, the material of the insulating layer can include at least one of silicon dioxide (SiO 2 ), carbon-doped silicon oxide (SiOCH), phosphorus silicon glass (PSG), boron phosphorus silicon glass (BPSG). But the present disclosure is not limited thereto. For example, the insulating layer formed in the step S50 described above can be the second insulating layer 620 in the storage device shown in FIG. 6. For example, ​ ​ The material of the first insulating layer 610 and the material of the second insulating layer 620 in the storage device shown in FIG. 6 can be the same or different, and the present disclosure is not limited thereto.

[0123] For example, the damascene process can be a Damascene process.

[0124] Referring to ​ and ​ For example, the metal material can be deposited in the via of the second insulating layer 620 by a PVD process to fill the via in the second insulating layer 620, while forming the upper metal line. For example, the metal material can include at least one of titanium (Ti), aluminum (Al), tungsten (W), copper (Cu), titanium nitride (TiN). But the present disclosure is not limited thereto.

[0125] Referring to ​ and ​ For example, the first metal structure 300 can also be formed in the first insulating layer 610 by the damascene process described above, which will not be described here. For example, the material of the first metal structure 300 can be the same as or different from the material of the second metal structure 400, and the present disclosure is not limited thereto.

[0126] The storage device and the manufacturing method thereof provided by the embodiments of the present disclosure can meet the hardware application of high-density storage or storage calculation, meet the heat budget of the subsequent process, have no additional size overhead, and have the advantage of process-friendly. Through flexible configuration of the film layer in the storage device, a device system for different application scenarios can be realized, and the storage device has strong universality.

[0127] The following points need to be explained:

[0128] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can be referred to the general design.

[0129] (2) In the case of no conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0130] The above description is only exemplary embodiments of the present disclosure, and is not intended to limit the protection scope of the present disclosure, and the protection scope of the present disclosure is determined by the appended claims.​

Claims

1. A memory device, comprising: a substrate structure; a first metal structure on the substrate structure; a second metal structure on a side of the first metal structure distal to the substrate structure; a dielectric layer at least partially between the first metal structure and the second metal structure; a resistive switching memory comprising a first electrode, a resistive switching layer, and a second electrode stacked along a first direction, the resistive switching layer being between the first electrode and the second electrode; wherein the dielectric layer comprises an electrode hole, a sidewall of the electrode hole surrounding a first opening and a second opening opposite to each other in the first direction, the first opening exposing the first metal structure, and the second opening being on a side surface of the dielectric layer distal to the first metal structure; in a second direction intersecting the first direction, a dimension of the second opening is greater than a dimension of the first opening; the first electrode is entirely within the electrode hole, the first electrode comprising a first electrode portion and a second electrode portion connected to each other, the first electrode portion being on a side surface of the first metal structure distal to the substrate structure, and the second electrode portion being on the sidewall; at least a portion of the resistive switching layer extends beyond an edge of the first electrode in the second direction.

2. The memory device of claim 1, wherein, in a plane perpendicular to the second direction, a footprint of the first electrode is within a footprint of the sidewall.

3. The memory device of claim 2, wherein, a ratio of a thickness of the first electrode portion to a thickness of the second electrode portion is 0.9-1.

1.

4. The memory device of claim 1, wherein, in the substrate structure, a footprint of the first electrode is entirely within a footprint of the resistive switching layer, and there is a spacing between an edge of the footprint of the first electrode and an edge of the footprint of the resistive switching layer.

5. The memory device of any one of claims 1-4, wherein, the sidewall comprises a main portion and a first arc portion, the first arc portion being connected between the main portion and a side surface of the first metal structure distal to the substrate structure; a side edge of the first arc portion distal to the main portion surrounds the first opening.

6. The memory device of any one of claims 1-4, wherein, the sidewall comprises a main portion and a second arc portion, the second arc portion being connected between the main portion and a side surface of the dielectric layer distal to the substrate structure except for the electrode hole; a side edge of the second arc portion distal to the main portion surrounds the second opening.

7. The memory device of any one of claims 1-4, wherein, a maximum dimension of the first opening in the second direction is 5-100 nm.

8. The memory device of any one of claims 1-4, wherein, in a plane perpendicular to the second direction, a footprint of the resistive switching layer overlaps with a footprint of the sidewall.

9. The memory device of any one of claims 1-4, wherein, in a plane perpendicular to the second direction, a footprint of the second electrode overlaps with a footprint of the sidewall.

10. The memory device of claim 9, wherein, in a plane perpendicular to the first direction, a footprint of the second electrode coincides with a footprint of the resistive switching layer.

11. The memory device of claim 9, wherein, a side surface of the second electrode distal to the substrate structure has a recess, and a portion of the second metal structure is within the recess. 12.The memory device of any one of claims 1-4, further comprising a first insulating layer and a second insulating layer. The first insulating layer surrounds a portion of the first metal structure, and the second insulating layer surrounds a portion of the resistive random access memory and a portion of the second metal structure.

13. The memory device of claim 12, wherein, The dielectric layer includes a first region overlapping the resistive reactive layer in the first direction and a second region other than the first region; A maximum thickness of the first region in the first direction is greater than a maximum thickness of the second region in the first direction.

14. A method for manufacturing a memory device, comprising: forming a first metal structure and a first dielectric material layer on a substrate structure in sequence; forming an electrode hole in the first dielectric material layer by a first photolithography process to obtain a second dielectric material layer; wherein the electrode hole includes a sidewall surrounding a first opening and a second opening formed opposite in the first direction, the first opening exposes the first metal structure, and the second opening is located on a side surface of the second dielectric material layer away from the first metal structure; in a second direction perpendicular to the first direction, a size of the second opening is greater than a size of the first opening; forming a first electrode in the electrode hole; wherein the first electrode is completely located in the electrode hole, the first electrode includes a first electrode part and a second electrode part connected to each other, the first electrode part is located on a side surface of the first metal structure away from the substrate structure, and the second electrode part is located on the sidewall; forming a resistive reactive layer and a second electrode arranged in a stack on a side of the first electrode away from the substrate structure to form a resistive random access memory; wherein at least a portion of the resistive reactive layer extends beyond an edge of the first electrode in the second direction; forming a second metal structure on a side of the resistive random access memory away from the substrate structure to form the memory device.

15. The method of claim 14, wherein, forming the first electrode in the electrode hole includes: forming a first electrode material layer on a side of the second dielectric material layer away from the substrate structure and in the electrode hole; forming a sacrificial layer on a side of the first electrode material layer away from the substrate structure; performing a planarization process to remove a portion of the sacrificial layer other than a portion located in the electrode hole and to remove a portion of the first electrode material layer other than a portion located in the electrode hole; removing the portion of the sacrificial layer in the electrode hole to obtain the first electrode.

16. The method of claim 15, wherein, a material of the sacrificial layer includes spin-on carbon.

17. The method of claim 14, wherein, a projection of the first electrode on the substrate structure is completely located within a projection of the resistive reactive layer, and there is a spacing between an edge of the projection of the first electrode and an edge of the projection of the resistive reactive layer.

18. The method of claim 14, wherein, forming the second metal structure on a side of the resistive random access memory away from the substrate structure includes: forming an insulating material layer on a side of the resistive random access memory and the second dielectric material layer away from the substrate structure; forming an insulating layer and the second metal structure located in the insulating layer by a damascene process.

19. The method of claim 14, wherein, forming the resistive reactive layer and the second electrode arranged in a stack on a side of the first electrode away from the substrate structure includes: forming a resistive switching reaction material layer and a second electrode material layer in a stacked manner on a side of the first electrode away from the substrate structure and on a side of the second dielectric material layer away from the substrate structure; forming the resistive switching memory by removing a portion of the resistive switching reaction material layer and a portion of the second electrode material layer through a second photolithography process to form the resistive switching reaction layer and the second electrode.

20. The method of claim 19, wherein, Before forming the second metal structure on a side of the resistive switching memory away from the substrate structure, further comprising: removing a portion of the second dielectric material layer through the second photolithography process to form a dielectric layer, wherein the portion is a portion of the second dielectric material layer other than a portion overlapping the resistive switching reaction layer in the first direction.

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