Thin film transistor
By employing high boron concentration doped source and drain regions and undoped channel regions in thin-film transistors, and introducing hydrogen elements into the insulating layer, the problems of electrical inhomogeneity and decreased drain potential barrier in thin-film transistors after reducing channel size are solved, thereby improving carrier mobility and reliability.
Patent Information
- Application Number
- CN202511038580.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-04
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-04
AI Technical Summary
While existing thin-film transistors have improved carrier mobility after the channel size has been reduced, they also face problems such as electrical inhomogeneity and a decrease in the potential barrier caused by the drain, which leads to easy conduction at large trans-voltages.
The design employs a semiconductor layer and a buffer layer, forming a high-boron-concentration source and drain region through boron doping, combined with an undoped channel region, and introducing hydrogen elements into the gate insulating layer and interlayer insulating layer to optimize electrical contacts and defect repair.
It improves the carrier mobility and reliability of thin-film transistors, reduces the resistance of the source and drain regions, improves electrical uniformity, and enhances the performance of thin-film transistors.
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Figure CN120897490A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor device, and more particularly to a thin film transistor. BACKGROUND
[0002] Generally, many semiconductor devices are included in an electronic device. For example, many thin film transistors are included in a display device. The thin film transistors are formed by depositing various thin films (e.g., semiconductor, metal, dielectric layer, etc.) on a substrate. In a display device, the thin film transistors can be disposed in a pixel structure or a driving circuit.
[0003] Currently, the trend of display devices is toward micro light emitting diode (uLED) products with high current. Therefore, it is imperative to improve the carrier mobility of thin film transistors. Although reducing the channel size of a thin film transistor can improve the on current (Ion) and carrier mobility, it is accompanied by problems such as electrical non-uniformity (e.g., threshold voltage (Vth) divergence) across the substrate and drain induced barrier lowering (DIBL) effect leading to easy conduction at large voltage.
[0004] Therefore, how to improve the carrier mobility of a thin film transistor while maintaining its channel size is still one of the goals of related manufacturers seeking improvement. SUMMARY
[0005] One embodiment of the present application proposes a thin film transistor including a semiconductor layer and a buffer layer located on one side of the semiconductor layer. The semiconductor layer includes a source region, a drain region, and a channel region, wherein the source region and the drain region are boron-doped, and the channel region is located between the source region and the drain region. The buffer layer includes a first region, a second region, and a third region. The first region and the second region are boron-doped and overlap the source region and the drain region, respectively. The third region is located between the first region and the second region and overlaps the channel region, wherein the third region is not boron-doped.
[0006] In one embodiment of the present application, the semiconductor layer described above includes a metal oxide semiconductor material.
[0007] In one embodiment of the present application, the boron concentration of the first region of the buffer layer is higher than that of the source region, and the boron concentration of the second region of the buffer layer is higher than that of the drain region.
[0008] In one embodiment of the present application, the thin film transistor described above further includes a bottom gate, wherein the buffer layer is located between the bottom gate and the semiconductor layer.
[0009] In an embodiment of the present application, the thin film transistor further comprises a top gate and a gate insulating layer, wherein the gate insulating layer is located on the side of the semiconductor layer opposite to the buffer layer, and the gate insulating layer is located between the channel region of the semiconductor layer and the top gate.
[0010] In an embodiment of the present application, the gate insulating layer completely overlaps the channel region of the semiconductor layer.
[0011] In an embodiment of the present application, the gate insulating layer is not boron-doped.
[0012] In an embodiment of the present application, the thin film transistor further comprises an interlayer insulating layer, the interlayer insulating layer physically contacts the source region and the drain region of the semiconductor layer, and the interlayer insulating layer is rich in hydrogen.
[0013] In an embodiment of the present application, the thin film transistor further comprises a source and a drain, the source and the drain are electrically connected to the source region and the drain region respectively through the interlayer insulating layer.
[0014] In an embodiment of the present application, the gate insulating layer overlaps the channel region, the source region and the drain region of the semiconductor layer.
[0015] In an embodiment of the present application, the part of the gate insulating layer overlapping the source region and the drain region is boron-doped.
[0016] In an embodiment of the present application, the thin film transistor further comprises an interlayer insulating layer, the interlayer insulating layer covers the top gate and the gate insulating layer, and the gate insulating layer separates the semiconductor layer and the interlayer insulating layer.
[0017] In an embodiment of the present application, the thin film transistor further comprises a source and a drain, the source and the drain are electrically connected to the source region and the drain region respectively through the interlayer insulating layer and the gate insulating layer.
[0018] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figures 1A-1E is a cross-sectional schematic diagram of a step flow of a manufacturing method of a thin film transistor according to an embodiment of the present application.
[0020] Figures 2A-2C is a cross-sectional schematic diagram of a step flow of a manufacturing method of a thin film transistor according to another embodiment of the present application.
[0021] Figures 3A-3G is a cross-sectional schematic diagram of a step flow of a manufacturing method of a thin film transistor according to another embodiment of the present application.
[0022] In the drawings:
[0023] 10,20,30: thin film transistor
[0024] 102: substrate
[0025] 104: insulating layer
[0026] 106: bottom gate
[0027] 108: buffer layer
[0028] 108a, 108d: first region
[0029] 108b, 108e: second region
[0030] 108c: undoped region
[0031] 110: semiconductor layer
[0032] 110a: first region
[0033] 110b: second region
[0034] 110c: channel region
[0035] 110d: source region
[0036] 110e: drain region
[0037] 112, 112': gate insulating layer
[0038] 112a: first region
[0039] 112b: second region
[0040] 112c: undoped region
[0041] 114: top gate
[0042] 118, 218: interlayer insulating layer
[0043] 120: source
[0044] 122: drain
[0045] 124: passivation layer
[0046] BD, BD1, BD2: boron doping process
[0047] IA: doping process
[0048] PR: patterned photoresist
[0049] V1, V2: via DETAILED DESCRIPTION
[0050] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. Like reference numerals can be used to denote like elements throughout the specification and drawings. It should be understood that when a layer, film, region, or substrate is referred to as being "on" or "connected to" another layer, film, region, or substrate, it can be directly on or connected to the other layer, film, region, or substrate, or intervening layers can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" can mean physically and / or electrically connected. Further, "electrically connected" or "coupled" can be between two elements.
[0051] It should be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element," "component," "region," "layer," or "section" discussed below could be termed a second "element," "component," "region," "layer," or "section" without departing from the teachings herein.
[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms, including "at least one," unless the content clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be understood by those within the art that, in some aspects of this disclosure, terms such as "including," and "having," etc., are intended to mean "including but not limited to," "comprising but not limited to," or "having but not limited to," and are not intended to exclude other
[0053] Moreover, relative terms, such as "lower" or "bottom" and "upper" or "top," can be used herein to describe one element's or portion's relationship to another element or portion as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The exemplary term "lower" can therefore encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary term "below" or "beneath" can therefore encompass both an orientation of "below" and "above," depending on the particular orientation of the figure.
[0054] "about," "approximately," or "substantially" as used herein include the stated value and average within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value. Further, "about," "approximately," or "substantially" as used herein can select an acceptable range of deviation or standard deviation for optical properties, etching properties, or other properties, and can not apply one standard deviation to all properties.
[0055] Figures 1A-1E is a cross-sectional schematic diagram of a step flow of a method of fabricating a thin film transistor 10 according to an embodiment of the present application. Hereinafter, the method of fabricating the thin film transistor 10 is described with reference to Figures 1A-1E
[0056] Referring to Figure 1A First, a substrate 102 is provided. The material of the substrate 102 can include glass, quartz, organic polymer, or non-transparent / reflective material (e.g., conductive material, metal, wafer, ceramic, or other applicable material) or other applicable material, for example.
[0057] Next, an insulating layer 104 is formed on the substrate 102. The method of forming the insulating layer 104 can include physical vapor deposition, chemical vapor deposition, or other suitable method. The insulating layer 104 can be a single layer or multiple layers of insulating layer, and can include silicon oxide (SiOx), silicon nitride (SiNx), oxynitrides (SiONx), or other suitable material or stack of the above-mentioned materials.
[0058] Next, a bottom gate 106 is formed on the insulating layer 104. The method of forming the bottom gate 106 can include the following steps. First, a gate metal layer (not shown) is formed on the insulating layer 104. Next, a patterned photoresist (not shown) is formed on the gate metal layer using photolithography. Then, the gate metal layer is etched using a wet or dry etching process with the patterned photoresist as a mask to form the bottom gate 106. After that, the patterned photoresist is removed.
[0059] The material of the bottom gate 106 can include a metal, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or an alloy of any combination thereof, or a stack of the above metals and / or alloys, but the present application is not limited thereto. The bottom gate 106 can also use other conductive materials, such as a nitride of a metal, an oxide of a metal, an oxynitride of a metal, a stack of a metal and other conductive materials, or other materials having conductive properties.
[0060] Next, a buffer layer 108 is formed on the bottom gate 106 and the insulating layer 104. The method of forming the buffer layer 108 can be, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The buffer layer 108 can be a single layer or multiple layers of insulating layers, and the insulating layers can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), or other suitable materials or a stack of the above materials.
[0061] Next, a semiconductor layer 110 is formed on the bottom gate 106. For example, the method of forming the semiconductor layer 110 can include the following steps: first, forming a blanket semiconductor material layer (not shown) on the buffer layer 108; then, using photolithography to form a patterned photoresist (not shown) on the semiconductor material layer; next, using the patterned photoresist as a mask, performing a wet or dry etching process on the semiconductor material layer to form the semiconductor layer 110; and then, removing the patterned photoresist. The buffer layer 108 can store oxygen atoms to repair oxygen vacancies (Vo) of the semiconductor layer 110 in subsequent thermal processes.
[0062] The orthographic projection of the semiconductor layer 110 on the substrate 102 can overlap the orthographic projection of the bottom gate 106 on the substrate 102. The semiconductor layer 110 can include a metal oxide semiconductor material. In some embodiments, the semiconductor layer 110 can include at least one of a metal element such as an indium element, a zinc element, an aluminum element, a tungsten element, a tin element, a gallium element, etc. For example, the material of the semiconductor layer 110 can include indium zinc oxide (InZnO, IZO), indium gallium zinc oxide (InGaZnO, IGZO), indium aluminum zinc oxide (InAlZnO, IAZO), indium tungsten oxide (InWO, IWO), indium tungsten zinc oxide (InWZnO, IWZO), indium zinc tin oxide (InZnSnO, IZTO), indium gallium tin oxide (InGaSnO, IGTO), or indium gallium zinc tin oxide (InGaZnSnO, IGZTO), but the present application is not limited thereto.
[0063] Next, a gate insulating layer 112 is formed on the semiconductor layer 110 and the buffer layer 108. The method of forming the gate insulating layer 112 can be, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The gate insulating layer 112 can be a single layer or multiple layers of insulating layers, and the insulating layers can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), or other suitable materials or stacks of the above-mentioned materials. The material of the gate insulating layer 112 can be different from the material of the buffer layer 108.
[0064] Next, a top gate 114 is formed on the semiconductor layer 110. The method of forming the top gate 114 can include the following steps. First, a gate metal layer (not shown) is formed on the gate insulating layer 112. Next, a patterned photoresist (not shown) is formed on the gate metal layer using photolithography. Then, the gate metal layer is etched using a wet or dry etching process with the patterned photoresist as a mask to form the top gate 114. After that, the patterned photoresist is removed.
[0065] The top gate 114 overlaps the semiconductor layer 110 in the orthographic projection of the substrate 102. The material of the top gate 114 can include a metal, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or an alloy of any combination of the above-mentioned metals, or a stack of the above-mentioned metals and / or alloys, but is not limited thereto. The top gate 114 can also use other conductive materials, such as nitrides of metals, oxides of metals, oxynitrides of metals, stacks of metals and other conductive materials, or other materials with conductive properties. The material of the top gate 114 can be the same as or different from the material of the bottom gate 106.
[0066] Referring to Figure 1B Next, part of the gate insulating layer 112 is removed using the top gate 114 as a mask to form a gate insulating layer 112'. After the formation of the gate insulating layer 112', part of the semiconductor layer 110 not overlapped by the top gate 114 is exposed. The method of removing the gate insulating layer 112 can use an etching process or other suitable methods. For example, the above-mentioned etching process can use an etchant that has relatively high etching selectivity for the gate insulating layer 112 but is not easy to etch the semiconductor layer 110.
[0067] Referring to Figure 1C, and then a boron doping process BD is performed. The boron doping process BD can utilize the top gate 114 as a mask to dope the semiconductor layer 110 and the buffer layer 108. After the boron doping process BD, the portion of the semiconductor layer 110 overlapping the top gate 114 can form a channel region 110c, and the first region 110a and the second region 110b of the semiconductor layer 110 not overlapping the top gate 114 can have a higher boron (B) concentration than the channel region 110c. In some embodiments, the first region 110a and the second region 110b of the semiconductor layer 110 are boron-doped, and the channel region 110c is between the first region 110a and the second region 110b and is not boron-doped. The boron doping process BD can implant boron elements into the first region 110a and the second region 110b of the semiconductor layer 110, thereby breaking the covalent bonds between metal atoms and oxygen atoms therein and knocking out oxygen atoms, and the boron atoms can further form stable bonds with the knocked-out oxygen atoms, thereby generating more oxygen vacancies (Vo) to reduce the resistance of the first region 110a and the second region 110b and to improve the Ion and carrier mobility of the thin film transistor.
[0068] After the boron doping process BD, the portion of the buffer layer 108 overlapping the top gate 114 can form a non-boron-doped region 108c, and the first region 108a and the second region 108b of the buffer layer 108 not overlapping the top gate 114 can have a higher boron concentration than the non-boron-doped region 108c. In other words, the first region 108a and the second region 108b of the buffer layer 108 are boron-doped, and the non-boron-doped region 108c is between the first region 108a and the second region 108b and is not boron-doped. The boron doping process BD can implant boron elements into the first region 108a and the second region 108b of the buffer layer 108, thereby causing the boron atoms to form stable bonds with the extra oxygen atoms (exO) therein to avoid the exO continuously repairing defects of the first region 110a and the second region 110b of the semiconductor layer 110 during subsequent processes, thereby avoiding the resistance of the first region 110a and the second region 110b from rising and avoiding the Ion and carrier mobility of the thin film transistor from decreasing. In addition, the non-boron-doped region 108c can still repair defects in the channel region 110c of the semiconductor layer 110 during subsequent processes, thereby improving the reliability of the thin film transistor.
[0069] The implantation depth of boron elements can be proportional to the implantation energy used in the boron doping process BD. In some embodiments, the implantation energy used in the boron doping process BD is about 10 keV to 40 keV, such as about 20 keV or 30 keV. In some embodiments, the implantation dose used in the boron doping process BD is about 8.00E+11 ions / cm 2 to 1.20E+15 ions / cm 2, for example, about 1.20E+13 ions / cm 2 or 1.20E+14 ions / cm 2 .
[0070] In some embodiments, the first region 108a of the buffer layer 108 has a boron concentration higher than that of the first region 110a of the semiconductor layer 110, and the second region 108b of the buffer layer 108 has a boron concentration higher than that of the second region 110b of the semiconductor layer 110. In some embodiments, the boron concentration of the first region 108a and the second region 108b of the buffer layer 108 is about 450% to 14500% higher than that of the first region 110a and the second region 110b of the semiconductor layer 110. For example, the boron concentration of the first region 108a of the buffer layer 108 is about 4.5 times to 145 times higher than that of the first region 110a of the semiconductor layer 110. Alternatively, the boron concentration of the second region 108b of the buffer layer 108 can be about 4.5 times to 145 times higher than that of the second region 110b of the semiconductor layer 110. In some embodiments, the boron concentration of the first region 108a and / or the second region 108b of the buffer layer 108 is about 10 times to 100 times higher than that of the first region 110a and / or the second region 110b of the semiconductor layer 110.
[0071] Referring to Figure 1D Next, an interlayer insulating layer 118 is formed on the top gate 114, the gate insulating layer 112', the semiconductor layer 110 and the buffer layer 108. The method for forming the interlayer insulating layer 118 can be, for example, physical vapor deposition, chemical vapor deposition or other suitable methods. In this embodiment, the reactants used to form the interlayer insulating layer 118 can contain hydrogen elements, so that the interlayer insulating layer 118 is a hydrogen-rich insulating layer. The interlayer insulating layer 118 can be a single layer or multiple layers of insulating layers, and the material of the insulating layer can include, for example, silicon nitride (SiNx).
[0072] During the formation of the interlayer insulating layer 118 or in a subsequent heat treatment process, hydrogen elements can migrate or diffuse from the interlayer insulating layer 118 into the semiconductor layer 110, thereby adjusting the hydrogen content of the first region 110a and the second region 110b of the semiconductor layer 110, and thus improving the conductivity thereof. In this way, the first region 110a and the second region 110b can be converted into a source region 110d and a drain region 110e, respectively, with a higher hydrogen concentration, and the source region 110d and the drain region 110e have a higher conductivity than the first region 110a and the second region 110b, so as to be able to form ohmic contacts with the subsequently formed source and drain, respectively.
[0073] Referring to Figure 1EAfterwards, vias V1, V2 are formed in the ILD 118, and the vias V1, V2 can respectively expose the source region 110d and the drain region 110e of the semiconductor layer 110. For example, a photoresist (not shown) is formed on the ILD 118 by a photolithography process. Then, the ILD 118 is etched by a wet or dry etching process using the photoresist as a mask to form the vias V1, V2 through the ILD 118. After that, the photoresist is removed.
[0074] Afterwards, a source 120 is formed on the ILD 118 and in the via V1, and a drain 122 is formed on the ILD 118 and in the via V2. The source 120 can be electrically connected to the source region 110d of the semiconductor layer 110 through the via V1, and the drain 122 can be electrically connected to the drain region 110e of the semiconductor layer 110 through the via V2, so as to form a thin film transistor 10, and the thin film transistor 10 can be a dual gate thin film transistor.
[0075] For example, the source 120 and the drain 122 can be formed by the following steps. First, a conductive layer (not shown) is formed on the substrate 102 by a chemical vapor deposition or a physical vapor deposition. Then, a photoresist (not shown) is formed on the conductive layer by a photolithography process. After that, the conductive layer is etched by a wet or dry etching process using the photoresist as a mask to form the source 120 and the drain 122. Finally, the photoresist is removed. The source 120 and the drain 122 can belong to the same film layer. The material of the source 120 and the drain 122 can include chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, an alloy of the above-mentioned metals, or a stack of the above-mentioned metals and / or alloys, or other conductive materials.
[0076] In some embodiments, a passivation layer 124 can also be formed on the source 120, the drain 122, and the ILD 118. The passivation layer 124 can be formed by a plasma chemical vapor deposition or other suitable processes, and the material of the passivation layer 124 can include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials or a stack of the above-mentioned materials.
[0077] Figure 1Eis a cross-sectional schematic view of a thin film transistor 10 according to an embodiment of the present application. The thin film transistor 10 can be disposed on a substrate 102 and include a semiconductor layer 110 and a buffer layer 108, where the buffer layer 108 can be located between the substrate 102 and the semiconductor layer 110. The semiconductor layer 110 can include a source region 110d, a drain region 110e, and a channel region 110c located between the source region 110d and the drain region 110e, and the source region 110d and the drain region 110e are boron-doped, and the channel region 110c is not boron-doped, such that the boron concentration of the source region 110d and the drain region 110e can be higher than the boron concentration of the channel region 110c. The boron-doping can break the covalent bonds between metal atoms and oxygen atoms in the source region 110d and the drain region 110e and knock out oxygen atoms, and the boron atoms can further form stable bonds with the knocked-out oxygen atoms, thereby generating more oxygen vacancies, and thus reducing the resistance of the source region 110d and the drain region 110e, and increasing the Ion and carrier mobility of the thin film transistor 10.
[0078] The buffer layer 108 is located on one side, such as the lower side, of the semiconductor layer 110. The buffer layer 108 can include a first region 108a, a second region 108b, and a non-boron-doped region 108c located between the first region 108a and the second region 108b, and the first region 108a and the second region 108b are boron-doped, and the non-boron-doped region 108c is not boron-doped. The boron concentration of the first region 108a and the second region 108b can be higher than the boron concentration of the non-boron-doped region 108c, such that the extra oxygen atoms in the first region 108a and the second region 108b can form stable bonds with boron atoms to avoid these extra oxygen atoms continuously repairing defects of the source region 110d and the drain region 110e of the semiconductor layer 110 during subsequent processes, thereby avoiding the resistance of the source region 110d and the drain region 110e of the semiconductor layer 110 from increasing. In addition, the non-boron-doped region 108c can still repair defects in the channel region 110c of the semiconductor layer 110 during subsequent processes, thereby improving the reliability of the thin film transistor 10.
[0079] In some embodiments, the first region 108a completely overlaps the source region 110d, the second region 108b completely overlaps the drain region 110e, and the non-boron-doped region 108c completely overlaps the channel region 110c. In some embodiments, the boron concentration of the first region 108a is higher than the boron concentration of the source region 110d, and the boron concentration of the second region 108b is higher than the boron concentration of the drain region 110e.
[0080] The thin film transistor 10 can further include a bottom gate 106, and a buffer layer 108 can be located between the bottom gate 106 and the semiconductor layer 110. In some embodiments, the thin film transistor 10 can further include a gate insulating layer 112' and a top gate 114, wherein the gate insulating layer 112' is located on a side of the semiconductor layer 110 opposite to the buffer layer 108, in other words, the semiconductor layer 110 can be located between the buffer layer 108 and the gate insulating layer 112'. The gate insulating layer 112' can be located entirely between the top gate 114 and the semiconductor layer 110. For example, the gate insulating layer 112' completely overlaps the top gate 114, and thus the gate insulating layer 112' is not boron-doped. The gate insulating layer 112' can completely overlap the channel region 110c of the semiconductor layer 110, and not overlap the source region 110d and the drain region 110e of the semiconductor layer 110.
[0081] The thin film transistor 10 can further include a hydrogen-rich interlayer insulating layer 118, and the interlayer insulating layer 118 can cover the top gate 114, the gate insulating layer 112', the semiconductor layer 110, and the buffer layer 108. For example, the interlayer insulating layer 118 can physically contact the upper surface and the side surface of the top gate 114, the side surface of the gate insulating layer 112', the upper surface and the side surface of the source region 110d and the drain region 110e of the semiconductor layer 110, and the upper surface of the portion of the buffer layer 108 not overlapping the semiconductor layer 110.
[0082] The thin film transistor 10 can further include a source 120 and a drain 122, and the source 120 and the drain 122 can be electrically connected to the source region 110d and the drain region 110e of the semiconductor layer 110, respectively, through the interlayer insulating layer 118. In some embodiments, the thin film transistor 10 further includes an insulating layer 104 located between the bottom gate 106 and the substrate 102 to avoid impurities in the substrate 102 diffusing into other film layers of the thin film transistor 10. In some embodiments, the thin film transistor 10 further includes a passivation layer 124, and the passivation layer 124 can cover the source 120, the drain 122, and the interlayer insulating layer 118 to provide protection for the film layers of the thin film transistor 10.
[0083] Figure 2A-2C is a cross-sectional schematic view of a step flow of a manufacturing method of a thin film transistor 20 according to another embodiment of the present application. It must be noted that, Figures 2A-2C the embodiment of Figure 1A is performed after the steps of Figures 2A-2C the embodiment of Figures 1A-1E uses the element labels and some contents of the embodiment of
[0084] Please refer toFigure 2A In such Figure 1A After forming the insulating layer 104, bottom gate 106, buffer layer 108, semiconductor layer 110, gate insulating layer 112, and top gate 114 on the substrate 102, the top gate 114 can be used as a mask to perform a boron doping process BD on the gate insulating layer 112, semiconductor layer 110, and buffer layer 108. After the boron doping process BD, the portion of the buffer layer 108 overlapping the top gate 114 can form an undoped region 108c, and the first region 108a and the second region 108b of the buffer layer 108 without overlapping the top gate 114 can have a higher boron concentration than the undoped region 108c. Furthermore, after the boron doping process BD, the portion of the semiconductor layer 110 overlapping the top gate 114 can form a channel region 110c, and the first region 110a and the second region 110b of the semiconductor layer 110 without overlapping the top gate 114 can have a higher boron concentration than the channel region 110c. Furthermore, after the boron doping process BD, the portion of the gate insulating layer 112 that overlaps the top gate 114 can form an undoped region 112c, and the first region 112a and the second region 112b of the gate insulating layer 112 that do not overlap the top gate 114 can have a higher boron concentration than the undoped region 112c.
[0085] Please refer to Figure 2B Next, the top gate 114 can be used as a mask to perform a doping process IA on the semiconductor layer 110. After the doping process IA, the first region 110a and the second region 110b of the semiconductor layer 110 that do not overlap with the top gate 114 can be transformed into the source region 110d and the drain region 110e, respectively, and the source region 110d and the drain region 110e have lower resistance than the channel region 110c. In some embodiments, the doping process IA is a hydrogen plasma process, and the doping process IA can implant hydrogen elements into the first region 110a and the second region 110b of the semiconductor layer 110, so that the first region 110a and the second region 110b are transformed into the source region 110d and the drain region 110e with higher hydrogen concentrations, and the source region 110d and the drain region 110e have improved carrier mobility. In some embodiments, an ohmic contact can be formed between the source region 110d of the semiconductor layer 110 and the subsequently formed source 120, and an ohmic contact can be formed between the drain region 110e of the semiconductor layer 110 and the subsequently formed drain 122.
[0086] Please refer to Figure 2CAfterwards, an interlayer insulating layer 218 is formed on the top gate 114 and the gate insulating layer 112, and then the interlayer insulating layer 218 and the gate insulating layer 112 are patterned. For example, a blanket dielectric material layer (the interlayer insulating layer 218 before patterning) is formed on the substrate 102 by chemical vapor deposition or physical vapor deposition. Then, a patterned photoresist (not shown) is formed on the dielectric material layer by photolithography. Then, the interlayer insulating layer 218 before patterning and the gate insulating layer 112 are etched by wet or dry etching process using the patterned photoresist as a mask to form the vias V1, V2. Afterwards, the patterned photoresist is removed.
[0087] The patterned interlayer insulating layer 218 and the gate insulating layer 112 have the vias V1, V2 penetrating through the interlayer insulating layer 218 and the gate insulating layer 112. For example, the via V1 penetrates through the first region 112a of the interlayer insulating layer 218 and the gate insulating layer 112, and exposes an exposed portion of the source region 110d of the semiconductor layer 110, and the via V2 penetrates through the second region 112b of the interlayer insulating layer 218 and the gate insulating layer 112, and exposes an exposed portion of the drain region 110e of the semiconductor layer 110.
[0088] In this embodiment, the material of the interlayer insulating layer 218 can include silicon nitride, silicon oxide, silicon oxynitride, organic polymer, or other suitable material, or a stack of the above-mentioned materials. In some embodiments, the reactants used to form the interlayer insulating layer 218 can contain hydrogen element, and the hydrogen element can migrate or diffuse to the source region 110d and the drain region 110e of the semiconductor layer 110 during the formation of the interlayer insulating layer 218 or in subsequent patterning or heat treatment processes, thereby adjusting the hydrogen content in the source region 110d and the drain region 110e, and improving the conductivity thereof.
[0089] Then, the source 120 is formed on the interlayer insulating layer 218 and in the via V1, and the drain 122 is formed on the interlayer insulating layer 218 and in the via V2, thereby forming the thin film transistor 20. For example, the source 120 can be electrically connected to the source region 110d through the via V1, the drain 122 can be electrically connected to the drain region 110e through the via V2, and the source 120 and the drain 122 can form ohmic contacts with the source region 110d and the drain region 110e, respectively. In some embodiments, a passivation layer 124 can also be formed on the source 120, the drain 122, and the interlayer insulating layer 218.
[0090] Figure 2Cis a cross-sectional schematic view of a thin film transistor 20 according to an embodiment of the present application. The thin film transistor 20 can include a substrate 102, a gate insulating layer 104, a bottom gate 106, a buffer layer 108, a semiconductor layer 110, a gate insulating layer 112, a top gate 114, an interlayer insulating layer 218, a source 120, a drain 122, and a passivation layer 124.
[0091] Compared with the thin film transistor 10 as shown in Figure 1E , Figure 2C the difference between the thin film transistor 20 as shown in
[0092] For example, a first region 112a of the gate insulating layer 112 overlaps a source region 110d of the semiconductor layer 110, and a second region 112b of the gate insulating layer 112 overlaps a drain region 110e of the semiconductor layer 110. In addition, the gate insulating layer 112 can also cover side surfaces of the semiconductor layer 110 and an upper surface of a portion of the buffer layer 108 that does not overlap the semiconductor layer 110.
[0093] In some embodiments, a first region 112a and a second region 112b of the gate insulating layer 112 that do not overlap the top gate 114 are boron-doped, a non-boron-doped region 112c of the gate insulating layer 112 overlaps the top gate 114 and is between the first region 112a and the second region 112b, and the first region 112a and the second region 112b can have a higher boron concentration than the non-boron-doped region 112c.
[0094] Figures 3A-3G is a cross-sectional schematic view of a step flow of a method of manufacturing a thin film transistor 30 according to another embodiment of the present application. It must be noted that Figures 3A-3G the embodiment of Figures 2A-2C uses the same or similar reference numerals to represent the same or similar elements as the embodiment of and omits the description of the same technical content. The description of the omitted part can be referred to the foregoing embodiment, which will not be described here.
[0095] Figure 3AThe insulating layer 104 can be formed on the substrate 102 by a thin film deposition process such as physical vapor deposition or chemical vapor deposition. Then, the bottom gate 106 can be formed on the insulating layer 104 by a deposition process, a lithography process and an etching process. Then, the buffer layer 108 can be formed on the bottom gate 106 and the insulating layer 104 by physical vapor deposition, chemical vapor deposition or other suitable methods. Then, a patterned photoresist PR can be formed on the buffer layer 108 by a spin coating process, a lithography process and an ashing process.
[0096] Referring to Figure 3B , then, the buffer layer 108 is subjected to a first boron doping process BD1 using the patterned photoresist PR as a mask. After the first boron doping process BD1, the portion of the buffer layer 108 overlapping the patterned photoresist PR can form a non-boron-doped region 108c, and the first region 108a and the second region 108b of the buffer layer 108 not overlapping the patterned photoresist PR can have a higher boron concentration than the non-boron-doped region 108c. Referring to Figure 3C , then, the patterned photoresist PR is removed.
[0097] Referring to Figure 3D , then, the semiconductor layer 110 can be formed on the first region 108a, the second region 108b and the non-boron-doped region 108c of the buffer layer 108 by a deposition process, a lithography process and an etching process. Then, the gate insulating layer 112 can be formed on the semiconductor layer 110 and the buffer layer 108 by physical vapor deposition, chemical vapor deposition or other suitable methods. Then, the top gate 114 can be formed on the gate insulating layer 112 by a deposition process, a lithography process and an etching process.
[0098] Referring to Figure 3E, the second boron doping process BD2 can be performed on the buffer layer 108, the semiconductor layer 110 and the gate insulating layer 112 using the top gate 114 as a mask. After the second boron doping process BD2, the first region 108a of the buffer layer 108 not overlapped by the top gate 114 can be converted into a first region 108d having a higher boron concentration, and the second region 108b of the buffer layer 108 not overlapped by the top gate 114 can be converted into a second region 108e having a higher boron concentration, in other words, the boron concentration of the first region 108d is higher than that of the first region 108a, and the boron concentration of the second region 108e is higher than that of the second region 108b. In addition, after the second boron doping process BD2, the portion of the semiconductor layer 110 overlapped by the top gate 114 can form a channel region 110c, and the first region 110a and the second region 110b of the semiconductor layer 110 not overlapped by the top gate 114 can have a higher boron concentration than the channel region 110c. Furthermore, after the second boron doping process BD2, the portion of the gate insulating layer 112 overlapped by the top gate 114 can form an undoped region 112c, and the first region 112a and the second region 112b of the gate insulating layer 112 not overlapped by the top gate 114 can have a higher boron concentration than the undoped region 112c.
[0099] Please refer to Figure 3F , the doping process IA can be performed on the semiconductor layer 110 using the top gate 114 as a mask. After the doping process IA, the first region 110a and the second region 110b of the semiconductor layer 110 not overlapped by the top gate 114 can be converted into a source region 110d and a drain region 110e, respectively, and the source region 110d and the drain region 110e have a lower resistance than the channel region 110c. In some embodiments, the doping process IA is a hydrogen plasma treatment, and the doping process IA can implant hydrogen elements into the first region 110a and the second region 110b of the semiconductor layer 110, so that the first region 110a and the second region 110b are converted into the source region 110d and the drain region 110e having a higher hydrogen concentration, respectively. In this way, the source region 110d and the drain region 110e can have a reduced resistance, so that the thin film transistor 30 has an improved Ion and carrier mobility.
[0100] Please refer to Figure 3G , then an interlayer insulating layer 218 is formed on the top gate 114 and the gate insulating layer 112, and then the interlayer insulating layer 218 and the gate insulating layer 112 are patterned to form vias V1, V2 in the interlayer insulating layer 218 and the gate insulating layer 112, and the vias V1, V2 respectively expose the source region 110d and the drain region 110e of the semiconductor layer 110.
[0101] Then, a source electrode 120 is formed on the interlayer insulating layer 218 and in the via V1, and a drain electrode 122 is formed on the interlayer insulating layer 218 and in the via V2, so as to form the thin film transistor 30. The source electrode 120 can be electrically connected to the source region 110d through the via V1, the drain electrode 122 can be electrically connected to the drain region 110e through the via V2, and the source electrode 120 and the drain electrode 122 can form ohmic contacts with the source region 110d and the drain region 110e, respectively. In some embodiments, a passivation layer 124 can also be formed on the source electrode 120, the drain electrode 122, and the interlayer insulating layer 218.
[0102] Figure 3G is a cross-sectional schematic view of a thin film transistor 30 according to an embodiment of the present application. The thin film transistor 30 can include a substrate 102, a gate insulating layer 104, a bottom gate electrode 106, a buffer layer 108, a semiconductor layer 110, a gate insulating layer 112, a top gate electrode 114, an interlayer insulating layer 218, a source electrode 120, a drain electrode 122, and a passivation layer 124.
[0103] Compared with the thin film transistor 20 as shown in Figure 2C , the difference between the thin film transistor 30 as shown in Figure 3G mainly lies in that the boron concentration of the first region 108d of the buffer layer 108 of the thin film transistor 30 is higher than the boron concentration of the first region 108a of the buffer layer 108 of the thin film transistor 20, and the boron concentration of the second region 108e of the buffer layer 108 of the thin film transistor 30 is higher than the boron concentration of the second region 108b of the buffer layer 108 of the thin film transistor 20, because the first region 108d and the second region 108e of the buffer layer 108 of the thin film transistor 30 have undergone two boron doping processes, i.e., a first boron doping process BD1 and a second boron doping process BD2, so as to avoid the problem of insufficient implantation depth of the boron doping process, and to ensure that the first region 108d and the second region 108e of the buffer layer 108 have a high enough boron concentration to avoid the oxygen atoms continuously repairing the defects of the source region 110d and the drain region 110e of the semiconductor layer 110 in the subsequent process, so as to avoid the resistance of the source region 110d and the drain region 110e of the semiconductor layer 110 from rising.
[0104] In summary, the thin film transistor of the present application can break the covalent bond between metal atoms and oxygen atoms by implanting boron atoms into the source region and the drain region of the semiconductor layer, and the boron atoms can further form stable bonds with the broken oxygen atoms, thereby generating more oxygen vacancies, reducing the resistance of the source region and the drain region, and improving the Ion and carrier mobility of the thin film transistor. In addition, the thin film transistor of the present application further implants boron atoms into the first region and the second region of the non-overlapping top gate of the buffer layer, and the boron atoms form stable bonds with the extra oxygen atoms (exO) therein, thereby avoiding the exO continuously repairing the defects of the source region and the drain region of the semiconductor layer during subsequent processes, avoiding the resistance of the source region and the drain region increasing, and avoiding the Ion and carrier mobility of the thin film transistor decreasing. Furthermore, the non-boron-doped region of the overlapping top gate of the buffer layer can still repair the defects in the channel region of the semiconductor layer during subsequent processes, thereby improving the reliability of the thin film transistor.
[0105] Although the present application has been disclosed with the above embodiments, it is not intended to limit the present application, and anyone with ordinary knowledge in the art can make some modifications and refinements without departing from the spirit and scope of the present application, and the protection scope of the present application shall be defined by the appended patent claims.
Claims
1. A thin-film transistor, characterized in that, include: Semiconductor layer, including: The source and drain regions are boron-doped; and The channel region is located between the source region and the drain region; and A buffer layer, located on one side of the semiconductor layer, includes: The first and second regions are boron-doped and overlap the source and drain regions, respectively; and A third region is located between the first and second regions and overlaps with the channel region, wherein the third region is undoped with boron.
2. The thin-film transistor as claimed in claim 1, characterized in that, The semiconductor layer comprises a metal oxide semiconductor material.
3. The thin-film transistor as claimed in claim 1, characterized in that, The boron concentration in the first region of the buffer layer is higher than that in the source region, and the boron concentration in the second region of the buffer layer is higher than that in the drain region.
4. The thin-film transistor as claimed in claim 1, characterized in that, It also includes a bottom gate, wherein the buffer layer is located between the bottom gate and the semiconductor layer.
5. The thin-film transistor as claimed in claim 1, characterized in that, It also includes a top gate and a gate insulating layer, wherein the gate insulating layer is located on the side of the semiconductor layer opposite to the buffer layer, and the gate insulating layer is located between the channel region of the semiconductor layer and the top gate.
6. The thin-film transistor as claimed in claim 5, characterized in that, The gate insulating layer completely overlaps the channel region of the semiconductor layer.
7. The thin-film transistor as claimed in claim 6, characterized in that, The gate insulating layer therein is not boron-doped.
8. The thin-film transistor as claimed in claim 6, characterized in that, It also includes an interlayer insulating layer that physically contacts the source region and the drain region of the semiconductor layer, and the interlayer insulating layer is rich in hydrogen.
9. The thin-film transistor as claimed in claim 8, characterized in that, It also includes a source and a drain, which are electrically connected to the source region and the drain region respectively through the interlayer insulating layer.
10. The thin-film transistor as claimed in claim 5, characterized in that, The gate insulating layer overlaps the channel region, the source region, and the drain region of the semiconductor layer.
11. The thin-film transistor as claimed in claim 10, characterized in that, The portion of the gate insulating layer overlapping the source region and the drain region is boron-doped.
12. The thin-film transistor as claimed in claim 10, characterized in that, It also includes an interlayer insulating layer that covers the top gate and the gate insulating layer, and the gate insulating layer separates the semiconductor layer from the interlayer insulating layer.
13. The thin-film transistor as claimed in claim 12, characterized in that, It also includes a source and a drain, which are electrically connected to the source region and the drain region respectively through the interlayer insulating layer and the gate insulating layer.