SiC component, power semiconductor device, and method for manufacturing SiC component for power semiconductor device

Abstract

An assembly (1) for a power semiconductor device (10) is provided, where the assembly (1) comprises a SiC-based body (1M) and a plurality of vias (1V) based on an electrically conductive material. The body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), the second thickness (12T) being smaller than the first thickness (11T). The first layer (11) and the second layer (12) are formed of SiC, and the first layer (11) has a higher n-type doping concentration than the second layer (12). The through-hole (1V) extends partially into the first layer (11) from the bottom side (11B) of the first layer (11) towards the second layer (12) in the vertical direction, and the through-hole (1V) does not extend into the second layer (12). The assembly further comprises a SiC substrate (5) wherein the second layer (12) is arranged between the SiC substrate (5) and the first layer (11). The SiC substrate (5) has a vertical thickness (5T), and a ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is from 1.5 to 250. The SiC substrate (5) is free of any via formed of a conductive material. Furthermore, a power semiconductor device (10) comprising such an assembly (1) and a method for manufacturing such an assembly (1) and a method are provided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a SiC assembly, a power semiconductor device and a method for manufacturing a SiC assembly for a power semiconductor device. BACKGROUND

[0002] Conventional low voltage SiC devices provide very low on-state voltage drops required for certain applications, such as event switching applications. However, the switch should be able to withstand high current pulses over an extended time range from several microseconds to several seconds. This puts a high demand on the so-called "single event" turn-off capability, not only because of the high turn-off current density and / or long pulse length, but also because the temperature fluctuations of the entire switch are very large, affecting both the chip and the package.

[0003] The latest SiC technology and material properties field complicates this situation, because due to the crystal defect density and its limiting effect on yield and thus wafer cost, the current wafer size is limited to typical values, for example not more than 50 mm 2 In the current situation, it is therefore desirable to fully optimize the potential of SiC devices (e.g. SiC switches) with respect to the on-state resistance. Therefore, for economic reasons, to keep the SiC wafer area as low as possible, the current density under normal operating conditions should be pushed as high as possible. However, this results in a very high current density during high current events, resulting in strong self-heating of the semiconductor chip and its package.

[0004] While the semiconductor material SiC is very capable of operating at high temperatures, up to 600 K or higher in vacuum, the current process level of packages and materials used to manufacture these packages will not allow for more than the maximum operating temperature of silicon devices. In the case of SiC devices, for example in event switching applications, there is therefore a strong interest in increasing the thermal capacity of the device as much as possible. The present disclosure aims to achieve this goal by making use of a highly heat conductive SiC layer on which a voltage- withstanding drift layer of for example a power semiconductor device (e.g. a switch device) is applied or grown. SUMMARY

[0005] For example, embodiments of the present disclosure, as claimed in the independent claims, solve the above-mentioned drawbacks in the art, in whole or in part. Further embodiments of a SiC assembly, a power semiconductor device and a method for manufacturing a SiC assembly for a power semiconductor device are subject of further claims.

[0006] According to an embodiment of the assembly for a power semiconductor device, the assembly comprises a SiC-based main body and a plurality of vias based on an electrically conductive material. The main body comprises a first layer having a first thickness and a second layer having a second thickness, wherein the second thickness is smaller than the first thickness. The first layer and the second layer are formed of SiC. The first layer can have a higher n-type doping concentration than the second layer. The vias extend partially into the first layer along a vertical direction from a bottom side of the first layer towards the second layer, wherein the vias do not extend into the second layer.

[0007] The first layer and the second layer have different n-type doping concentrations. However, the first layer and the second layer can be formed of the same material, for example of 4H-SiC. However, it is possible that the second layer is formed of 4H-SiC and the first layer is formed of 3C-SiC or polycrystalline SiC. For example, the second layer is a drift layer. Such a drift layer can be epitaxially grown on the first layer. The first layer can be a substrate that carries the second layer and mechanically stabilizes the assembly.

[0008] The vias can be trenches that are completely filled with the electrically conductive material. It is also possible that the vias are trenches that are partially filled with the electrically conductive material. For example, only the inner walls of the trenches are covered with the electrically conductive material. In this case, the trenches can comprise a region that is filled with a gaseous medium, for example air.

[0009] It is an object of the present disclosure to make use of a thicker first layer, thereby allowing to reduce the self-heating without the drawback of simultaneously increasing the overall resistance of the arrangement, for example of a power semiconductor device. This object is achieved by providing holes or trenches in the first layer in a two- or three-dimensional arrangement, which are filled with a metal having a high electrical and thermal conductivity, for example with aluminum, copper or silver due to their inherently high electrical conductivity or with graphite in an appropriate form. The number of holes or trenches per assembly can be at least 4, 6, 8, 10, 16, 20, 50 or at least 100.

[0010] According to a further embodiment of the assembly, the ratio of the vertical first thickness to the vertical second thickness is from 1.5 to 250. The first thickness can be from 100 pm to 1000 pm. The second thickness can be from 2 pm to 200 pm.

[0011] The vertical direction is understood to mean a direction that is directed perpendicular to a bottom surface of the first layer. The lateral direction is understood to mean a direction that is parallel to the bottom surface of the first layer. The vertical direction and the lateral direction are orthogonal to each other. The bottom surface of the first layer is at the bottom side of the first layer and is a lateral surface that can be defined by one vector along the length of the assembly and another vector along the width of the assembly.

[0012] According to a further embodiment of the assembly, the maximum vertical distance between the second layer and the via is from 0.6 pm to 250 pm, for example from 1 pm to 250 pm. For example, the first thickness is greater than or equal to 300 pm or 350 pm. The second thickness is for example less than or equal to 55 pm or 25 pm or 10 pm. However, the first thickness and the second thickness are not limited thereto.

[0013] According to a further embodiment of the assembly, the ratio of the average vertical height of the via to the first thickness of the first layer is at least 0.5, for example at least 0.6, 0.7, 0.8 or at least 0.9. In other words, the via extends at least 50%, 60%, 70%, 80% or at least 90% of the total vertical thickness of the first layer. However, the via does not extend through the first layer along the vertical direction. In this sense, the via extends only partially into the first layer along the vertical direction from the bottom side of the first layer towards the second layer.

[0014] According to a further embodiment of the assembly, the average lateral width of the via is from 3 pm to 150 pm, for example from 6 pm to 150 pm or from 10 pm to 150 pm. The average lateral length of the via is greater than the average lateral width. Along the lateral direction, at least some or all of the vias can be completely or partially enclosed by the first layer. However, it is possible that along one lateral direction, at least some or all of the vias can extend from one first side surface of the first layer to another side surface of the first layer (for example opposite the first side surface of the first layer). In this case, the via can not only be exposed at the bottom side of the first layer, but can also be at least partially exposed on one side surface of the first layer or on both side surfaces.

[0015] According to a further embodiment of the assembly, along the lateral direction, the via is completely surrounded by the first layer. In this case, the via is not exposed on the side surface of the first layer.

[0016] According to a further embodiment of the assembly, the first layer has a first side surface and a second side surface. Along the lateral direction, at least one, several or all of the vias can extend from the first side surface to the second side surface of the first layer. For example, the first side surface is opposite the second side surface. In this case, it is possible that the lateral length of the via is equal to or greater than the lateral width or the lateral length of the first layer. Along the lateral direction, the via can extend along the width or along the length of the first layer. It is also possible that the first side surface is adjacent to the second side surface. In this case, along the lateral direction, the via can extend from the first side surface to the adjacent second side surface. Along the lateral direction, the via is not parallel to the direction of the width or the length of the first layer.

[0017] According to a further embodiment of the assembly, the assembly further comprises a heat sink, e.g. formed of a metal. The body is arranged on the heat sink, e.g. directly on the heat sink. The heat sink has a vertical thickness, which is e.g. larger than the sum of the first thickness and the second thickness.

[0018] The heat sink can be a thick metal plate, e.g. a copper plate, which serves as an efficient primary heat sink for the assembly or for the semiconductor device. The heat sink can have dimensions of the same width and / or length as the body. The vertical thickness of the heat sink can be equal to or larger than 500 pm, 1000 pm, 2000 pm, 3000 pm or 4000 pm.

[0019] According to a further embodiment of the assembly, the heat sink has a larger cross section than the body, such that in a top view of the heat sink, the body is fully overlaid by the heat sink. However, the heat sink can also have an equal or substantially equal cross section compared to the cross section of the body.

[0020] According to a further embodiment of the assembly, the assembly further comprises a SiC substrate, wherein the second layer is arranged between the SiC substrate and the first layer. The SiC substrate has a vertical thickness, wherein the ratio of the SiC substrate to the second thickness can be from 1.5 to 250. The SiC substrate is e.g. free of any via formed of an electrically conductive material.

[0021] The SiC substrate and the body can be separated by a metal layer, e.g. an aluminum layer or a copper layer, which can constitute an electrode, e.g. a cathode of the assembly or of the power semiconductor device. The SiC substrate acts as a top side cooler and is e.g. not electrically active. For this reason, no via, hole or trench is formed within the SiC to reduce a possible resistive voltage drop. A thermal boundary electrode is e.g. present at the bottom side of the assembly.

[0022] According to a further embodiment of the assembly, the vias have a size of a cross section which varies along a vertical direction. For example, the size of the cross section of each of the vias increases with a distance from the bottom side of the first layer. Due to this geometry of the vias, the vias can be filled with an electrically conductive material in an efficient and simplified manner.

[0023] According to one embodiment of a power semiconductor device, the power semiconductor device comprises a component, in particular a component as described herein in the present disclosure. The component comprises a SiC-based body and a plurality of vias based on an electrically conductive material. The body comprises a first layer having a first thickness and a second layer having a second thickness, wherein the second thickness is smaller than the first thickness. The first layer and the second layer are formed of SiC, wherein the first layer has a higher n-type doping concentration than the second layer. The vias partially extend into the first layer along a vertical direction from a bottom side of the first layer towards the second layer, wherein the vias do not extend into the second layer. The second layer comprises functional areas configured to implement a functionality of the power semiconductor device. These functional areas can comprise, for example, p-regions and n-regions of a transistor. For example, the second layer is formed as a drift layer.

[0024] According to a further embodiment of a power semiconductor device, the power semiconductor device is formed as a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), a Schottky diode, a junction- barrier-Schottky (JBS) diode, or a SiC power device for event switching. The second layer can comprise functional areas of such transistors or diodes.

[0025] According to one embodiment of a method for manufacturing a component for a power semiconductor device, a wafer is provided. The wafer comprises at least one body based on SiC. The wafer or the body comprises a first layer having a first thickness and a second layer having a second thickness, wherein the second thickness is smaller than the first thickness. The first layer and the second layer are formed of SiC. The first layer can have a higher n-type doping concentration than the second layer. According to the method, a plurality of trenches is formed partially extending into the first layer along a vertical direction from a bottom side of the first layer towards the second layer, wherein the trenches do not extend into the second layer. The trenches are filled with an electrically conductive material for forming a plurality of vias, wherein the vias partially extend into the first layer along the vertical direction from the bottom side of the first layer towards the second layer and do not extend into the second layer.

[0026] According to a further embodiment of the method, the wafer is singulated into a plurality of bodies along singulating lines, wherein at least some of the singulating lines cut through the vias such that at least some of the singulated bodies comprise side surfaces comprising side surfaces of the vias.

[0027] According to a further embodiment of the method, the wafer is singulated into a plurality of bodies along singulating lines, wherein at least some of the singulating lines do not cut through the vias such that at least some of the singulated bodies comprise all side surfaces without side surfaces of the vias.

[0028] The present disclosure comprises several aspects based on which embodiments and examples are implemented: an assembly for a power semiconductor device, a power semiconductor device comprising such an assembly, and a method for manufacturing such an assembly for such a power semiconductor device. Each feature described in relation with one of these aspects is also disclosed herein in relation with another aspect, even if the respective feature is not explicitly mentioned in the context of a particular aspect. For example, the methods described in the present disclosure are directed to a method for manufacturing the assemblies described herein, and the power semiconductor devices described in the present disclosure can comprise the assemblies described herein. Thus, features and advantages described in relation with the assembly can be used for the method and for the power semiconductor device, and vice versa.

[0029] While the disclosure can be susceptible to various modifications and alternative forms, the details herein are shown by way of specific examples in the drawings and will be described in detail. It should be understood, however, that there is no intent to limit the disclosure to the particular, described embodiments and examples. On the contrary, it is intended to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure as defined by the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding. In the drawings, like reference numerals refer to like technical features throughout. It will be understood that the examples shown in the drawings are diagrammatic representations and are not necessarily to scale.

[0031] FIG. 1A The general concept of an assembly for a power semiconductor device according to examples of the present disclosure is schematically shown in a cross-sectional view.

[0032] FIG. 1B and FIG. 1C Different arrangements of vias according to different examples of the assembly are shown in a top view on the bottom side of the assembly.

[0033] FIG. 2 , FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 and FIG. 7 Further examples of assemblies or power semiconductor devices are shown.

[0034] FIG. 8A , FIG. 8B , FIG. 8C and FIG. 8D Some simulation results for different examples of assemblies are shown.

[0035] FIG. 9A , FIG. 9B and FIG. 9CSome exemplary method steps are shown for a method for manufacturing at least one component for a power semiconductor device.

[0036] FIG. 10A , FIG. 10B , FIG. 11A , FIG. 11B , FIG. 12 and FIG. 13 Some exemplary method steps are shown for different examples of a method for manufacturing a plurality of components for a power semiconductor device. DETAILED DESCRIPTION

[0037] FIG. 1A A cross-sectional view of a component 1 for a power semiconductor device 10 according to one exemplary embodiment is shown. The component 1 comprises a body 1M comprising a first layer 11 having a first thickness 11T and a second layer 12 having a second thickness 12T. The body 1M is based on SiC. The first layer 11 is formed of SiC, e.g. of 4H-SiC, 3C-SiC or poly-SiC. The second layer 12 is formed of SiC, e.g. of 4H-SiC. The first layer 11 has a higher n-type doping concentration than the second layer 12. As shown in FIG. 1A The second thickness 12T is smaller than the first thickness 11T, as shown in

[0038] The ratio 11T / 12T of the first thickness 11T to the second thickness 12T can be from 1.5 to 250, e.g. from 5 to 250, from 5 to 200, from 5 to 100, from 5 to 50, from 5 to 25, from 5 to 25. For example, the ratio 11T / 12T is greater than or equal to 5, 10, 30, 50 or 100. For example, the ratio 11T / 12T is greater than or equal to 1.5 and 5, but can be less than or equal to 10, 15, 20, 30, 50 or 100.

[0039] The first thickness 11T can be from 100 pm to 1000 pm, e.g. from 100 pm to 800 pm, from 100 pm to 600 pm, from 100 pm to 400 pm. For example, the first thickness 11T is 600 pm ± 300 pm or 600 pm ± 200 pm or 600 pm ± 50 pm.

[0040] The second thickness 12T can be from 2 pm to 200 pm, e.g. from 2 pm to 100 pm, from 2 pm to 50 pm, from 2 pm to 10 pm. For example, the second thickness 12T is 50 pm ± 10 pm or 30 pm ± 10 pm or 10 pm ± 5 pm.

[0041] For example, the first thickness 11T is greater than or equal to 300 pm or 500 pm, and the second thickness 12T is less than or equal to 55 pm, 35 pm, 20 pm or 10 pm.

[0042] The assembly 1 comprises a plurality of vias 1V based on an electrically conductive material. For example, the vias 1V are trenches filled with, for example, aluminum, copper or silver. The vias 1V extend partially into the first layer 11 from the bottom side 11B of the first layer 11 towards the second layer 12 along a vertical direction, wherein the vias 1V do not extend into the second layer 12 but stop in front of the second layer 12.

[0043] The maximum vertical distance between the second layer 12 and the vias 1V can be from 0.6 pm to 250 pm, for example from 1 pm to 250 pm, for example from 1 pm to 150 pm, from 1 pm to 100 pm, from 1 pm to 50 pm, from 1 pm to 30 pm or from 1 pm to 10 pm.

[0044] As shown in FIG. 1A The vias 1V extend only partially into the first layer. It is possible that the ratio of the average vertical height of the vias 1V to the first thickness 11T of the first layer 11 is at least 0.5, 0.6, 0.7, 0.8 or at least 0.9, for example between 0.8 and 0.98.

[0045] The lateral average width of the vias 1V can be from 3 pm to 150 pm, for example from 6 pm to 150 pm, from 10 pm to 150 pm, for example from 10 pm to 100 pm, from 10 pm to 80 pm, from 10 pm to 60 pm, from 10 pm to 40 pm or from 10 pm to 20 pm. The vias 1V can have a lateral average length which is greater than the lateral average width. The lateral of the vias 1V can be the lateral length or the lateral width of the assembly 1.

[0046] For example, as shown in, for example FIG. 1B and FIG. 1C In a top view onto the bottom side 11B of the first layer 11, the vias 1V are in a strip shape. The vias 1V are parallel to each other. The ratio of the lateral length to the lateral width of one via 1V or of the plurality of vias 1V can be from 1.5 to 50, 1.5 to 30, 1.5 to 10 or 1.5 to 5. It is also possible that, in a top view onto the bottom side 11B of the first layer 11, the vias 1V can have another shape, for example a square shape, a circular shape, a trapezoidal shape or other regular and irregular shapes.

[0047] As shown in FIG. 1A The assembly 1 comprises a plurality of vias 1V, for example eight vias 1V, as shown in FIG. 1BAs shown, the plurality of through-holes extend laterally from a first side surface 11F of the first layer 11 to a second side surface 11S, wherein the first side surface 11F and the second side surface 11S are opposite each other. Therefore, the lateral length of the through-hole 1V can be equal to or approximately equal to the width of the first layer 11. The through-hole 1V can be partially exposed on the first side surface 11F and / or the second side surface 11S. The eight through-holes 1V are parallel to each other.

[0048] and FIG. 1B The via 1V may be rotated by 90°. In this case, the lateral length of the via 1V may be equal to or approximately equal to the length of the first layer 11. Other directions of the via 1V are also possible. For example, along the lateral direction, the via 1V may extend from the first side surface 11F or from the second side surface 11S to another side surface of the first layer 11, wherein the other side surface of the first layer is adjacent to either the first side surface 11F or the second side surface 11S.

[0049] and FIG. 1B Compared to the through hole 1V in the first layer 11, in the top view of the bottom side 11B of the first layer 11, FIG. 1C The through holes 1V in the holes have the same lateral direction. However, FIG. 1C The through-hole 1V does not extend to any side surface of the first layer 11. Therefore, in the lateral direction, the through-hole 1V is completely enclosed or completely surrounded by the first layer 11.

[0050] and FIG. 1C In the event of a phase deviation, it is possible that the through-hole 1V may have other orientations along the lateral direction, such as the through-hole 1V being rotated by 90° or other angles.

[0051] and FIG. 1A , FIG. 1B and FIG. 1C Phase deviation, other arrangements, and / or other numbers of through-holes 1V are also possible. For example, the number of through-holes 1V may be greater than or less than eight, such as greater than 10, 15, 20, 30, 40, or 50. FIG. 1B and FIG. 1C The combinations of vias 1V shown are also possible. In a top view of the bottom side 11B of the first layer 11, the vias 1V can be arranged in a matrix manner, that is, they can be arranged in multiple columns and rows. It is also possible that some of the vias 1V have only one or both ends partially exposed on the side surface of the first layer 11, and other vias 1V are completely surrounded by the first layer 11 and therefore not exposed on any of the side surfaces of the first layer 11.

[0052] FIG. 2 The component 1 or power semiconductor device 10 shown is with FIG. 1AThe component 1 or power semiconductor device 10 shown are basically the same, except that FIG. 2 Only the four through-holes 1V are shown.

[0053] FIG. 3 The component 1 or power semiconductor device 10 shown is with FIG. 1A The component 1 or power semiconductor device 10 shown is substantially the same, except that the cross-sectional dimensions of the vias 1V vary along the vertical direction. The cross-sectional dimensions of each of the vias 1V increase as the distance from the bottom side 11B of the first layer 11 decreases. Here, the inner walls of the vias 1V may be inclined to facilitate metallization, for example, at the end of semiconductor processing. Thus, at the bottom side 11B, each of the vias 1V has the largest cross-section or the largest opening. This simplifies the material filling of the vias 1V and ensures that the vias 1V can be completely filled with electrical materials such as aluminum, copper, silver, etc.

[0054] FIG. 4 The component 1 or power semiconductor device 10 shown is with FIG. 1A The component 1 or power semiconductor device 10 shown is substantially the same, except that the substrate 5 is disposed on the body 1M. The substrate 5 and the body 1M may have the same geometry, such as the same length, width, and thickness. The substrate 5 may also have a vertical thickness 5T that is smaller or larger than that of the body 1M. The substrate 5 may be formed of SiC. For example, the substrate 5 may be formed of the same material as the first layer 11 of the body 1M.

[0055] like FIG. 4 As shown, the second layer 12 is disposed between the SiC substrate 5 and the first layer 11. The substrate 5 has a vertical thickness of 5T, wherein the ratio 5T / 12T of the substrate 5 to the second thickness 12T can be from 1.5 to 250, for example from 5 to 250, from 5 to 200, from 5 to 100, from 5 to 50, from 5 to 25, or from 5 to 25. For example, the ratio 5T / 12T is greater than or equal to 5, 10, 30, 50, or 100. For example, the ratio 5T / 12T is greater than or equal to 1.5 and 5, but can be less than or equal to 10, 15, 20, 30, 50, or 100.

[0056] The ratio 5T / 11T of the substrate 5 to the first thickness 11T can be from 0.3 to 3, for example from 0.5 to 3, from 1 to 3, from 0.5 to 2, from 0.5 to 1.5, from 0.75 to 1.25, from 0.8 to 1.2, or from 0.9 to 1.1. However, compared to the body 1M or the first layer 11, the substrate 5 does not have any vias formed of conductive material.

[0057] The substrate 5 can act as a top side cooler. The substrate 5 and the body 1M can be separated by a metal layer, e.g. an aluminum or copper layer, which can constitute an electrode, e.g. a cathode of the component 1 or the power semiconductor device 10. The substrate 5 acting as a top side cooler is not electrically active. For this reason, no via, hole or trench is needed to reduce the resistive voltage drop. A thermal boundary electrode can be present at the bottom side of the component 1 or the power semiconductor device 10, e.g. at the bottom side 1 IB of the first layer 11 of the body 1M.

[0058] FIG. 5 The component 1 or the power semiconductor device 10 shown in FIG. 1A The component 1 or the power semiconductor device 10 shown in

[0059] Here, the heat sink 3 acts as a main heat sink or main cooler of the component 1 or the power semiconductor device 10. The presence of the heat sink 3 results in a reduction of self-heating and an improvement of the current density. If the heat sink 3 is used in combination with the via 1V formed in the first layer 11, these effects are enhanced. As FIG. 5 As shown in

[0060] FIG. 6 The component 1 or the power semiconductor device 10 shown in FIG. 5 The component 1 or the power semiconductor device 10 shown in FIG. 5 The heat sink 3 shown in FIG. 6 The heat sink shown in FIG. 5 Compared to the heat sink 3 shown in FIG. 6 The use of the heat sink 3 shown in

[0061] FIG. 7 The component 1 or the power semiconductor device 10 shown in FIG. 4 The component 1 or the power semiconductor device 10 shown in FIG. 7 The component 1 or the power semiconductor device 10 shown in FIG. 6 The component 1 or the power semiconductor device 10 shown in The component 1 or the power semiconductor device 10 shown in

[0062] In combination FIG. 8A , FIG. 8B , FIG. 8C and FIG. 8D some simulation results are shown.

[0063] The procedure to manufacture a SiC power device can start with a first layer 11 being a thick and highly doped SiC layer. For example, in the case of SiC unipolar power devices for 600 V and 1.2 kV applications, a second layer 12 being a thin, lowly doped voltage- withstanding SiC drift layer can be epitaxially grown on top of the first layer 11. For the voltage classes mentioned above, the thickness of the drift layer can range from a few μm up to about 10 μm, which is very thin compared to a thick first layer 11 having a vertical thickness 11T of 100 μm, 200 μm, 300 μm or more.

[0064] Since the resistive contribution of the first layer 11 is not negligible (for example, in such low voltage class devices), the thickness of the first layer 11 will so far be thinned in order to allow reaching a minimum on-state voltage drop.

[0065] For the self-heating simulation, the assembly 1 or the power semiconductor device 10 (for example, a resistor) has two electrical contacts for energizing the arrangement. Since aluminum is widely used for metal contacts in power semiconductor devices, the simulation contacts are chosen to be formed of aluminum. On the bottom side 1 IB of the first layer 11, there is a metallization as a hot electrode, with a thermal boundary condition implied on the metallization. In this example, the initial temperature is set to 300 K, and the hot electrode is characterized by a surface thermal resistance of 10 cm 2 K / W. This value of surface thermal resistance is an example of mounting the power semiconductor device on a small heat sink without forced cooling.

[0066] In the simulations discussed here, a hot boundary surface temperature of 300 K is used. In the self-heating simulation, a current pulse of 3 seconds length is imposed on the assembly 1 or power semiconductor device 10 comprising the first layer 11 and the second layer 12. The height of the current density pulse is variable, and thus different maximum device temperatures will be generated at the end of the current pulse.

[0067] For comparison purposes, in the 2D numerical simulation, a typical conventional thickness of the first SiC layer 11 is chosen to be 100 μm, and a typical conventional thickness of the second SiC layer 12 on top of the first layer 11 as a drift layer is chosen to be 8 μm, which has a specific on-state resistance of 1.4 mΩcm 2typical for a 1.2 kV SiC JFET. The width of the first layer 11 and the second layer is chosen to be 5120 pm, and a variable height current is impressed through the second layer 12 and the first layer 11, thus flowing from top to bottom of the component 1. The top surface and the bottom surface are electrical contacts, where at the bottom surface also a thermal contact exists with a thermal boundary condition T = 300 K.

[0068] The results for such a conventional component 1 or power semiconductor device 10 are shown by the curve Al in FIG. 8A , where dT denotes the average temperature rise (in Kelvin) and dl the pulsed current density (in A / cm 2 Here, the first layer 11 does not have any vias 1V.

[0069] The curve A2 corresponds to a configuration of the component 1 or power semiconductor device 10 identical to the configuration for curve Al, but with a first layer 11 having a thickness 11T of 600 pm without any vias 1V.

[0070] The curve A3 corresponds to a configuration of the component 1 or power semiconductor device 10 identical to the configuration for curve A2, but with four vias 1V as shown in FIG. 2 Here, each of the four vias 1V is in the form of a trench having a lateral width of 40 pm and a vertical height of 590 pm and is assumed to be filled with copper. They provide an electrical bypass from the second layer 12 as drift layer at the top to the electrical contacts at the bottom side 1 IB of the first layer 11. The thermal boundary / electrode is also located at the bottom side 1 IB of the first layer 11.

[0071] The curve A4 corresponds to a configuration of the component 1 or power semiconductor device 10 identical to the configuration for curve A2, but with eight vias 1V as shown in FIG. 1A Here, each of the eight vias 1V is in the form of a trench having a lateral width of 20 pm and a vertical height of 590 pm and is assumed to be filled with copper. They provide an electrical bypass from the second layer 12 as drift layer at the top to the electrical contacts at the bottom side 1 IB of the first layer 11. The thermal boundary / electrode is also located at the bottom side 1 IB of the first layer 11.

[0072] As shown in FIG. 8AAs shown in Fig. 1 1, due to the good thermal properties of silicon carbide, a thicker first layer 1 1 increases the thermal capacity by a considerable amount. This will result in a more slow temperature rise of the component when a current pulse is applied. However, it is also observed that a second, opposite effect occurs, namely: when the thickness 1 1 T of the first layer increases, the total electrical resistance of the component 1 or power semiconductor device 10 will become higher. This means that, in the second case, the amount of heat generated by a completely identical current pulse will be higher. Therefore, the first layer 1 1 will exist a maximum thickness 1 1 T, where the final maximum temperature reached after a current pulse will no longer decrease, but instead it will increase again.

[0073] However, in the presence of vias 1 V, even for a relatively thick first layer 1 1, a reduction of self-heating and an improvement of the current density can be ensured. The top of the vias 1 V can stop not far in front of the second layer 12, for example in the range of 1 μιη to 50 μιη, here 10 μιη in the case of curves A3 and A4, thereby contributing to a maximum path to bypass the electrical resistance of the first layer 1 1. The width of the four vias 1 V in the case of curve A3 and the width of the eight vias 1 V in the case of curve A4 are intentionally chosen to be different: it is shown that the width of the vias 1 V and the lateral spacing between the vias 1 V are parameters that are suitable for optimization. The curves A1 to A4 provide the results of self-heating simulations for various configurations. Although the density of the vias 1 V is still at a low level (here only 4 or 8 vias 1 V on an assembly width of 5120 μιη), the results provided by curves A3 and A4 have proven the potential that the peak temperature limit exceeds 100 K when measured against the basic case provided by curve A1, especially at higher current densities. The peak temperature can be further limited by increasing the number and / or size of the vias 1 V in the first layer 1 1.

[0074] Therefore, by using two-dimensional simulations, it has been proven that the approach is valid in the case of the configurations shown in FIG. 1A and FIG. 2 It has been shown that a thick first layer 1 1 with multiple vias 1 V can significantly delay thermal runaway. To enhance this effect, the density of vias 1 V per area can be much higher than the density used in the numerical examples presented here.

[0075] FIG. 8B Further curves B1, B2 and B3 are shown as a function of the temperature rise after a 3 second current pulse, depending on the current density.

[0076] Curve B1 corresponds to the same configuration of component 1 or power semiconductor device 10 (including a first SiC layer 11 with a thickness of 11T and a thickness of 600μm without any vias 1V, and a second SiC layer 12 with a thickness of 8μm as a drift layer) and a different configuration of component 1 or power semiconductor device 10 according to curve A2. Additionally, component 1 or power semiconductor device 10 is disposed on a heat sink 3, which is a copper plate with a thickness of 3T and a thickness of 4180μm. FIG. 5 Such a component 1 or power semiconductor device 10 is shown, but there are no vias 1V in the first layer 11.

[0077] Curve B2 corresponds to the same configuration of component 1 or power semiconductor device 10 as that for curve B1, but has a first SiC layer 11 with a thickness 11T of 600 μm and four vias 1V, as shown. FIG. 2 As shown in the image. FIG. 5 The diagram shows such a component 1 or power semiconductor device 10, but the first layer 11 has four vias 1V, each of the four vias 1V being in the form of a trench with a lateral width of 40 μm and a vertical height of 590 μm and filled with copper.

[0078] Curve B3 corresponds to the same configuration of component 1 or power semiconductor device 10 as that for curve B1, but with eight through-holes 1V. FIG. 5 The diagram illustrates such a component 1 or power semiconductor device 10, wherein eight vias 1V are present in a first layer 11, each of the eight vias 1V being in the form of a trench having a lateral width of 20 μm and a vertical height of 590 μm and being filled with copper.

[0079] like FIG. 8B As shown, using thick-film first SiC with the highest density of 1V vias can delay thermal runaway in the most efficient way. This effect is enhanced in the presence of heat sink 3. FIG. 8B Under a given current density, the maximum temperature is reached after a 3-second current pulse. FIG. 8A In comparison, such as FIG. 8B As shown, it is evident that the presence of heatsink 3 significantly limits the final temperature reached at the end of the current pulse. Here, for a given, permissible temperature rise, the maximum current density can be roughly doubled when a thick copper heatsink 3, as used in the numerical example, is added. This can be seen in... FIG. 8A Curve A4 and FIG. 8B When comparing curve B3, it can be seen, for example, when the temperature increase is 150K.

[0080] FIG. 8B It was also shown that even at higher current densities, such as 300 A / cm²,2 The benefits of a thick SiC first layer 11, characterized by copper-filled vias 1V, also remain significant. At lower current densities, for example at 150 A / cm², the advantages are further enhanced. 2 Under these conditions, the maximum tolerable current density increases by 10% or more.

[0081] FIG. 8C It shows FIG. 8B The curves B1, B2 and B3 already shown, as well as the additional curves C4 and C5, are shown in the figure.

[0082] Curve C4 corresponds to the same configuration of component 1 or power semiconductor device 10 as that for curve B3, but with a heat sink 3 having a width or cross-section exceeding that of the main body 1M, such as FIG. 6 As shown in the figure. Here, the dimensions of heat sink 3 have changed from 5120μm x 4180μm to 10240μm x 2090μm, while the volume of heat sink 3 remains unchanged.

[0083] and FIG. 5 Compared to the heat sink 3 shown, FIG. 6 The radiator 3 in the middle has a larger width or a larger cross-section, but a smaller thickness of 3T. Therefore, FIG. 5 The volume of the heat sink 3 shown is... FIG. 6 The volume of the heat sink 3 shown can be the same, which is the case for the configuration of component 1 or power semiconductor device 10 according to curves B3 and C4. In other words, curve B3 corresponds to FIG. 5 The component 1 or power semiconductor device 10 shown, and curve C4 corresponds to FIG. 5 The component 1 or power semiconductor device 10 shown is illustrated. To quantitatively assess the additional effect of the size of the heat sink 3, it can be seen from curves B3 and C4 that at 300 A / cm²... 2 At the same current density, a wider heatsink 3 of the same volume provides a reduction of approximately 50K.

[0084] Curve C5 corresponds to the same configuration of component 1 or power semiconductor device 10 as that for curve C4, except that component 1 or power semiconductor device 10 includes, for example, FIG. 7 Apart from the SiC substrate 5 shown (i.e., the top-side cooler), the SiC substrate 5 may have approximately the same dimensions as the first layer 11 or the body 1M. However, the substrate 5 does not have vias 1V. For simulation purposes, the SiC substrate and the first SiC layer 11 have the same thickness of 600 μm.

[0085] FIG. 8D and FIG. 8A Basically the same, among which, in FIG. 8DAn additional curve D5 is shown in Fig. 6. Curve D5 corresponds to the same configuration of the assembly 1 or power semiconductor device 10 as for curve A4, except that the assembly 1 comprises an additional SiC substrate 5 with a thickness 5T (as shown in Fig. 7) instead of the heat sink 3. For the numerical simulation, the thickness 5T was chosen to be 600 pm. Curve D5 shows that the additional substrate 5 can further delay thermal runaway, resulting in a further reduction of the self-heating and further improvement of the current density. FIG. 1A FIG. 4

[0086] In case the additional SiC substrate 5 is a SiC top side cooler acting as an additional heat sink, the final maximum temperature after a current pulse with a pulse width of 3 seconds can be further reduced. The investigated configuration (using a 1.2 kV JFET with an on-resistance of 1.4 mWcm 2 would sustain a current pulse at 150 to 160 A / cm 2 resulting in a final temperature rise of 150 K. This temperature rise would be reached after a current pulse at 70 to 80 A / cm 2 for the initial configuration of curve Al. Obviously, the configuration as shown in Fig. 6 can be extended for top and / or bottom cooling, i.e. for the additional substrate 5 and / or the heat sink 3. In this case, it is possible that the additional substrate 5 receives a second thermal boundary / electrode. FIG. 4

[0087] In FIG. 8A to FIG. 8D , some main ideas of the present disclosure have been illustrated for a 1200 V device. This can be extended to other voltage classes to achieve similar benefits in terms of reduced device temperature, thereby increasing the operating current density. Such benefits can be more pronounced in low voltage classes typically used in event switching applications (e.g. 600 V devices), since the thick first layer 11 contributes more to the total device resistance at such voltage ranges. An illustration has been made using a thick first SiC layer 11 of 600 pm. This can be applied to a standard SiC first layer 11 acting as a substrate with a thickness 11T of about 350 pm, where similar benefit trends would be observed by using metal filled trenches or vias IV in the first layer 11 and / or in combination with the heat sink 3 and the additional substrate 5.

[0088] FIG. 9A , FIG. 9B and FIG. 9C show some exemplary method steps for a method of manufacturing at least one assembly 1 for a power semiconductor device 10.

[0089] According to FIG. 9A ​​​, a wafer 100 is provided, the wafer comprising at least one body 1M based on SiC, wherein the body 1M comprises a first layer 11 having a first thickness 11T and a second layer 12 having a second thickness 12T. The second thickness 12T is smaller than the first thickness 11T, wherein the first layer 11 and the second layer 12 are formed of SiC. The first layer 11 has a higher n-type doping concentration than the second layer 12. For example, the first layer 11 is formed as a substrate and the second layer 12 is formed as a drift layer of a component 1 or a power semiconductor device 10.

[0090] According to FIG. 9B , a plurality of trenches 1H extends partially into the first layer 11 along a vertical direction from a bottom side 11B of the first layer 11 towards the second layer 12, wherein the trenches 1H do not extend into the second layer 12. In combination FIG. 10A to FIG. 13 Some possible arrangements of the trenches 1H are described. The trenches 1H can be formed by a drilling and / or etching process.

[0091] According to FIG. 9C , the trenches 1H are filled with an electrically conductive material for forming a plurality of vias 1V, wherein the vias 1V extend partially into the first layer 11 along a vertical direction from a bottom side 11B of the first layer 11 towards the second layer 12 and do not extend into the second layer 12. Thus, the vias 1V do not provide a connection between the bottom side 11B and a top side of the first layer 11. In other words, the trenches 1H are not formed as vias extending through the first layer 11 along a vertical direction. Thus, the vias 1V are not formed as through vias.

[0092] The trenches 1H can be completely filled with an electrically conductive material, as shown in FIG. 9C However, it is possible that the trenches 1H are partially filled with an electrically conductive material. For example, only the inner walls of the trenches 1H are covered with an electrically conductive material. In this case, the trenches 1H can comprise regions filled with a gaseous medium, e.g. air.

[0093] FIG. 10A Possible arrangements of the trenches 1H or vias 1V with respect to an edge 100E of the wafer 100 and with respect to a plurality of components 1 or power semiconductor devices 10 to be manufactured are shown. The trenches 1H or vias 1V extend orthogonal to the edge 100E. In a top view to the bottom side of the wafer, some of the trenches 1H or vias 1V overlap with the plurality of components 1 or power semiconductor devices 10 to be manufactured. The trenches 1H or vias 1V are parallel to each other. The trenches 1H or vias 1V can also be formed in regions between the components 1 or power semiconductor devices 10 to be manufactured. The trenches 1H or vias 1V can extend across the entire lateral extension of the wafer 100.

[0094] When singulating the wafer 100 along the singulation lines 1S into a plurality of bodies 1M, assemblies 1 or power semiconductor devices 10, at least some of the singulation lines 1S cut through the via 1V, so that at least some of the singulated bodies 1M, assemblies 1 or power semiconductor devices 10 comprise side surfaces comprising side surfaces of the via 1V.

[0095] FIG. 10B A cross-sectional view of the wafer 100 as shown in FIG. 10A is shown along the line AB. In contrast to FIG. 10A and FIG. 10B other lateral directions of the trench 1H or the via 1V are possible. For example, the trench 1H or the via 1V is parallel to the edge 100E of the wafer or can form an acute angle with the edge 100E.

[0096] FIG. 11A The wafer 100 as shown in FIG. 10A is essentially the same as the wafer 100 with the trench 1H or the via 1V as shown in FIG. 11B except that there is no trench 1H or via 1V in the area between the assemblies 1 or power semiconductor devices 10 to be manufactured. Thus, it can be ensured that none of the singulation lines cuts through the trench 1H or the via 1V. FIG. 11A A cross-sectional view of the wafer 100 as shown in is shown along the line AB.

[0097] FIG. 12 The wafer 100 as shown in FIG. 10A is essentially the same as the wafer 100 with the trench 1H or the via 1V as shown in

[0098] FIG. 13 The wafer 100 as shown in FIG. 10A is essentially the same as the wafer 100 with the trench 1H or the via 1V as shown in

[0099] According to FIG. 13 , when singulating the wafer 100 along the singulation lines 1S into a plurality of bodies 1M, assemblies 1 or power semiconductor devices 10, none of the singulation lines 1S cuts through the via 1V, so that none of the side surfaces of all singulated bodies 1M, assemblies 1 or power semiconductor devices 10 comprises the via 1V.

[0100] In contrast to FIG. 13The phase offset can be that the via 1V is rotated by an angle of 90° or another angle, for example by an angle of 45° ± 10°, 45° ± 15°, 45° ± 20° or 45° ± 30°. As FIG. 13 As shown in Fig. 1 1 B, in a top view onto the bottom side of the first layer 1 1, the via 1V can extend over the entire lateral width or lateral length of the power semiconductor device 10 to be manufactured. The via 1V can also have a lateral expansion which is smaller than the lateral width and smaller than the lateral length of the power semiconductor device 10 to be manufactured. As FIG. 13 As shown in Fig. 1 1 B, in a top view onto the bottom side of the first layer 1 1, the via 1V can extend over the entire lateral width or lateral length of the power semiconductor device 10 to be manufactured. The via 1V can also have a lateral expansion which is smaller than the lateral width and smaller than the lateral length of the power semiconductor device 10 to be manufactured. As

[0101] The embodiments as shown in the drawings represent exemplary embodiments of assemblies, power semiconductor devices and methods for manufacturing assemblies for power semiconductor devices; therefore, they do not constitute a complete list of all embodiments of arrangements according to the assemblies, power semiconductor devices and methods that are improved. The actual arrangements of the assemblies, power semiconductor devices and methods can differ from the exemplary embodiments described above.

[0102] This application claims priority from European patent application 23160696.3, the disclosure of which is hereby incorporated by reference.

[0103] Reference signs

[0104] 100 wafer

[0105] 10 power semiconductor device

[0106] 1 assembly

[0107] 1M body of the assembly

[0108] 1V via

[0109] 1H trench / hole

[0110] 1S singulation line

[0111] 11 first layer of the body

[0112] 1 1 B bottom side of the first layer

[0113] 1 1 F first side surface of the first layer

[0114] 1 1 S second side surface of the first layer

[0115] 1 1 T first thickness

[0116] 12 second layer of the body

[0117] 12T second thickness

[0118] 3 heat spreader

[0119] 3T thickness of heat spreader

[0120] 5 substrate

[0121] 5T thickness of substrate

[0122] 100E edge of wafer

Claims

1. A component (1) for a power semiconductor device (10), wherein, - The component (1) includes a SiC-based body (1M) and multiple through-holes (1V) based on a conductive material. The main body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T), wherein the second thickness (12T) is less than the first thickness (11T). - The first layer (11) and the second layer (12) are formed of SiC, and the first layer (11) has a higher n-type doping concentration than the second layer (12). - The through-hole (1V) extends vertically from the bottom side (11B) of the first layer (11) toward the second layer (12) into the first layer (11), but the through-hole (1V) does not extend into the second layer (12), and -The component further includes a SiC substrate (5), wherein, - The second layer (12) is disposed between the SiC substrate (5) and the first layer (11). The SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is from 1.5 to 250. -The SiC substrate (5) has no through holes formed by conductive material.

2. The component (1) according to claim 1, wherein, - The ratio (11T / 12T) of the first thickness (11T) to the second thickness (12T) ranges from 1.5 to 250. - The first thickness (11T) ranges from 100 μm to 1000 μm, and - The second thickness (12T) ranges from 2μm to 200μm.

3. The component (1) according to any one of the preceding claims, wherein, - The first thickness (11T) is greater than or equal to 300μm. - The second thickness (12T) is less than or equal to 55μm, and - The maximum vertical distance between the second layer (12) and the through hole (1V) is from 0.6 μm to 250 μm.

4. The component (1) according to any one of the preceding claims, wherein, - The ratio of the average vertical height of the through-hole (1V) to the first thickness (11T) of the first layer (11) is at least 0.5, and - The via (1V) has a lateral average width between 10μm and 150μm.

5. Component (1) according to any one of claims 1 to 4, wherein, Along the lateral direction, the through hole (1V) is completely surrounded by the first layer (11).

6. Component (1) according to any one of claims 1 to 4, wherein, The first layer (11) has a first side surface (11F) and a second side surface (11S), wherein, along the lateral direction, at least one of the through holes (1V) extends from the first side surface (11F) to the second side surface (11S).

7. The component (1) according to any one of the preceding claims, further comprising a heat sink (3) formed of metal, wherein, The main body (1M) is arranged on the heat sink (3), and the heat sink (3) has a vertical thickness (3T) greater than the sum of the first thickness (11T) and the second thickness (12T).

8. The component (1) according to claim 7, wherein, The radiator (3) has a larger cross-section than the body (1M) such that, in the plan view of the radiator (3), the body (1M) and the radiator (3) completely overlap.

9. The component (1) according to any one of the preceding claims, wherein, - The SiC substrate (5) and the body (1M) are separated by a metal layer, which forms the electrode of the component (1), and - The SiC substrate (5) acts as a top-side cooler and is not electrically active.

10. The component (1) according to any one of the preceding claims, wherein, The dimensions of the cross-section of the through hole (1V) vary along the vertical direction, and the dimensions of the cross-section of each of the through holes (1V) increase as the distance from the bottom side (11B) of the first layer (11) decreases.

11. A power semiconductor device (10) comprising a component (1), wherein, - The component (1) includes a SiC-based body (1M) and multiple through-holes (1V) based on a conductive material. The main body (1M) includes a first layer (11) having a first thickness (11T) and a second layer (12), the second thickness (12T) being less than the first thickness (11T). - The first layer (11) and the second layer (12) are formed of SiC, and the first layer (11) has a higher n-type doping concentration than the second layer (12). - The through-hole (1V) extends vertically from the bottom side (11B) of the first layer (11) toward the second layer (12) into the first layer (11), but the through-hole (1V) does not extend into the second layer (12). - The second layer (12) includes functional regions configured to implement the functions of the power semiconductor device (10), and -The component further includes a SiC substrate (5), wherein, - The second layer (12) is disposed between the SiC substrate (5) and the first layer (11). The SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is from 1.5 to 250. -The SiC substrate (5) has no through holes formed by conductive material.

12. The power semiconductor device (10) according to claim 11 is a MOSFET, JFET, IGBT, Schottky diode, junction barrier Schottky diode or SiC power device for event switching.

13. A method for manufacturing a component (1) for a power semiconductor device (10), the method comprising: - A wafer (100) is provided, the wafer comprising at least one body (1M) based on SiC, wherein the body (1M) comprises a first layer (11) having a first thickness (11T) and a second layer (12) having a second thickness (12T) less than the first thickness (11T), the first layer (11) and the second layer (12) being formed of SiC, and the first layer (11) having a higher n-type doping concentration than the second layer (12). - Forming a plurality of trenches (1H) extending vertically from the bottom side (11B) of the first layer (11) toward the second layer (12) and partially extending into the first layer (11), wherein the trenches (1H) do not extend into the second layer (12), and - A trench (1H) is filled with a conductive material to form a plurality of through holes (1V), wherein the through holes (1V) extend partially into the first layer (11) and not into the second layer (12) along the vertical direction from the bottom side (11B) of the first layer (11). The component includes a SiC substrate (5), wherein, - The second layer (12) is disposed between the SiC substrate (5) and the first layer (11). The SiC substrate (5) has a vertical thickness (5T), and the ratio (5T / 12T) of the SiC substrate (5) to the second thickness (12T) is from 1.5 to 250. -The SiC substrate (5) has no through holes formed by conductive material.

14. The method according to claim 13, wherein, -The wafer (100) is monomerized into multiple bodies (1M) along the monomerization line (1S), and - At least some of the monomerization lines (1S) cut through the through-hole (1V) such that at least some of the monomerized bodies (1M) include side surfaces, the side surfaces including the side surfaces of the through-hole (1V).

15. The method according to claim 13, wherein, -The wafer (100) is monomerized into multiple bodies (1M) along the monomerization line (1S), and - At least some of the monomerization lines (1S) do not cut through the through hole (1V), such that at least some of the monomerized bodies (1M) include all side surfaces without the side surface of the through hole (1V).

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