Memory computing chip and method of manufacturing the same

Abstract

The application provides a storage computing chip and a manufacturing method thereof, which vertically stacks a logic chip with a computing processor, a buffer chip and a DRAM chip (or a DRAM chip stack) by a through silicon via, and the chips can directly communicate through the through silicon via, so that the chip area is saved, the integration degree is high, the wafer processing difficulty is reduced, the logic chip can access a low-speed DRAM chip in a large amount of parallel mode through the buffer chip, high bandwidth and large capacity cache are provided, and a physical layer interface is not needed between the buffer chip and the logic chip to complete the inter-chip communication, so that the hardware resource cost is greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a storage computing chip and its manufacturing method. Background Technology

[0002] Please refer to Figure 1 As shown, common storage computing chips typically involve vertically stacking multilayer DRAM chips (DRAM die) 40 and basic chips (basic die) 50, and then placing them side-by-side with logic chips (logic die) 70, which have computing processors 10, on an interposer 90, and bonding them to the interposer 90 respectively through micro bumps (micro bumps) 80. The logic chip 70 typically includes a physical layer (PHY) interface 60, a memory controller (DRAM controller) 30, and a computing processor 10. The computing processor 10 can be an AI processor, a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), or other high-end processors. That is, the physical layer interface 60, the memory controller 30, and the computing processor 10 are implemented on the same wafer. The base chip 50 has a physical layer interface (PHY) 500a. The physical layer interfaces 60 and 500a are connected through microbumps 80 and wiring in the interposer 90. Therefore, the memory controller 30 and the base chip 50 need to communicate with each other through the physical interface 60, 500a, and microbumps 80.

[0003] Physical interfaces 60 and 500a serve as the physical connection layer between the memory control layer 60 of logic chip 70 and the DRAM chip 40, responsible for high-speed data transmission and signal processing. They mainly consist of the following parts: a data interface, a clock interface, a control interface, and a power interface. The data interface transmits data and address information; the clock interface provides a clock signal to synchronize data transmission; the control interface controls data reading, writing, and other operations; and the power interface provides power to ensure normal operation.

[0004] The above solution has the following problems:

[0005] 1. The memory controller 30 of logic chip 70 and the basic chip 50 need to introduce parallel high-speed physical interfaces 60 and 500a to realize inter-chip communication, which consumes a lot of hardware resources.

[0006] 2. As the bandwidth and capacity of DRAM chip 40 increase, the logic of memory controller 30 becomes increasingly complex. In addition, there are differences between the process technology of DRAM chip and logic chip 70. This solution of implementing memory controller 30 and computing processor 10 on the same wafer layer will increase the area and cost of storage computing chip, waste resources, and make it difficult to meet the needs of higher performance products. Summary of the Invention

[0007] The purpose of this invention is to provide a storage computing chip and its manufacturing method, which can save chip area and hardware resources and meet the needs of higher performance products.

[0008] To achieve the above objectives, the present invention provides a storage computing chip, which includes a logic chip, a buffer chip, and at least one layer of DRAM chip stacked vertically in sequence, wherein the logic chip and the buffer chip, and the buffer chip and the DRAM chip are directly connected through through-silicon vias and a hybrid bonding layer.

[0009] The logic chip includes a computing processor, and the buffer chip internally houses a memory controller and multiple parallel inter-chip communication bus interfaces that communicate with the memory controller. Each inter-chip communication bus interface is connected to the computing processor through several through-silicon vias and a hybrid bonding layer. The memory controller is connected to the DRAM chip through several through-silicon vias.

[0010] The inter-chip communication bus interface operates at a frequency higher than that of the DRAM chip.

[0011] Optionally, each of the inter-chip communication bus interfaces is connected to the computing processor via a plurality of through-silicon vias passing through a first side of the buffer chip, a multilayer hybrid bonding layer, and a plurality of through-silicon vias passing through a first or second side of the logic chip; and / or,

[0012] The memory controller is connected to the DRAM chip through several through-silicon vias passing through the second side of the buffer chip, a multilayer hybrid bonding layer, and several through-silicon vias passing through the second side of the DRAM chip.

[0013] Optionally, the memory controller includes a built-in self-test circuit for performing a first built-in self-test on the first stacked structure after the buffer chip and the DRAM chip are stacked, and / or for performing a second built-in self-test on the second stacked structure after the logic chip, the buffer chip and the DRAM chip are stacked.

[0014] Wherein, the content of the first built-in self-test is the same as the content of the second built-in self-test, or the content of the second built-in self-test is less than the content of the first built-in self-test.

[0015] Optionally, the memory controller further includes at least one of the following (1) to (7):

[0016] (1) An address mapping circuit, used to map the address range received by the inter-chip communication bus interface to the DRAM chip;

[0017] (2) Command arbitration circuit, used to perform priority arbitration on multiple commands sent by the computing processor through the inter-chip communication bus interface.

[0018] (3) Timing control circuit, used to insert appropriate delays between commands according to the specifications of various timing parameters;

[0019] (4) A refresh management circuit, used to refresh the DRAM chip according to the refresh command transmitted by the computing processor through the inter-chip communication bus interface;

[0020] (5) Error detection and correction circuit, used to perform error detection and correction on the data read from the DRAM chip when the computing processor reads data through the inter-chip communication bus interface, and / or to perform error detection and correction on the data written to the DRAM chip when the computing processor writes data through the inter-chip communication bus interface;

[0021] (6) Temperature detection circuit, used to detect the temperature change of the inter-chip communication bus interface and / or the DRAM chip, and adjust the corresponding parameters according to the temperature change;

[0022] (7) Power management circuit, used to control the DRAM chip to enter or exit at least one low power state.

[0023] Optionally, each of the inter-chip communication bus interfaces is connected to the computing processor through several through-silicon vias (TSVs), and multiple signal channels are provided between the memory controller and the computing processor. Each of the signal channels uses the same handshake mechanism to realize the information transmission between the computing processor and the memory controller.

[0024] Optionally, the handshake mechanism uses handshake signals to perform a communication handshake between the computing processor and the memory controller; the plurality of signal channels include:

[0025] A write data channel for transmitting the multi-bit data signal from the computing processor to the memory controller after completing the handshake of the handshake signal pairs in its channel;

[0026] A read data channel is used to transmit the multi-bit data signal from the memory controller to the computing processor after completing the handshake of the handshake signal pairs within its channel;

[0027] A write address channel is used to transfer a write address from the computing processor to the memory controller after the handshake of the handshake signal pair within the channel is completed;

[0028] A write response channel is used to transmit a write response signal from the memory controller to the computing processor after completing the handshake of the handshake signal pair within its channel;

[0029] A read address channel is used to transfer a read address from the computing processor to the memory controller after the handshake of the handshake signal pair in its channel is completed.

[0030] Optionally, at least one of the write data channel and the read data channel is provided with a cascaded first register slice and a second register slice. The first register slice is coupled to the computing processor. Both the first register slice and the second register slice are provided with at least one level of data register circuit. Each level of the data register circuit is used to transmit multiple bits of data signal in parallel after completing the handshake of the handshake signal pair in the data channel.

[0031] Optionally, the first-level data register circuit in the first register slice with the shortest signal path to the computing processor is removed from the driving force of the handshake signal sent by the computing processor to the first register slice, and the remaining level data register circuits in the second register slice and / or the first register slice are all driven by the handshake signal pair.

[0032] Optionally, each stage of the data register circuit includes multiple parallel data register branches, each data register branch is configured to correspond one-to-one with each bit of the data signal, and is driven by the handshake signal pair or one of the handshake signals in the handshake signal pair.

[0033] Optionally, each handshake signal in the handshake signal pair is a single-bit signal, and the handshake signal pair synchronously drives the multiple parallel data register branches corresponding to the same level of the data register circuit.

[0034] Optionally, each of the data register branches includes combinational logic and a one-bit data register coupled to the combinational logic, and the handshake signal synchronously drives the combinational logic in the multiple parallel data register branches corresponding to the same level of the data register circuit.

[0035] Optionally, the first register slice is a forward register slice, a backward register slice, or a bidirectional register slice, and the second register slice is a forward register slice, a backward register slice, or a bidirectional register slice; wherein, the forward register slice has a forward register circuit, the backward register slice has a backward register circuit, and the bidirectional register slice is composed of a combination of a forward register circuit and a backward register circuit.

[0036] Optionally, in the first register slice of the write data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the forward register circuit of the first register slice and is removed from the drive of the handshake signal sent by the computing processor, so as to be driven only by the handshake signal received by the computing processor.

[0037] In the first register slice of the read data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the backward register circuit of the first register slice and is de-driven by the handshake signal sent by the computing processor.

[0038] Optionally, the handshake signal pair includes a valid signal and a ready signal.

[0039] Based on the same inventive concept, the present invention also provides a method for manufacturing a storage computing chip as described herein, comprising the following steps:

[0040] At least one DRAM wafer and a buffer wafer having a memory controller and an inter-chip communication interface are provided. The buffer wafer and the DRAM wafer are vertically stacked and mixed-bonded in sequence to form a first stacked structure, and the DRAM wafer and the buffer wafer are directly connected through through-silicon vias.

[0041] Perform a first built-in self-test on the first stacked structure;

[0042] A logic wafer with a computing processor is provided, and the logic wafer is vertically stacked and hybrid-bonded with a tested first stacking structure to form a second stacking structure.

[0043] The second stacked structure is cut to form a storage computing chip.

[0044] Optionally, the method for manufacturing the storage computing chip further includes, before cutting the second stacked structure, performing a second built-in self-test on the second stacked structure;

[0045] Wherein, the content of the first built-in self-test is the same as the content of the second built-in self-test, or the content of the second built-in self-test is less than the content of the first built-in self-test.

[0046] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0047] 1. By using corresponding through-silicon vias (TSVs) and hybrid bonding layers, a logic chip with a computing processor, a buffer die, and at least one DRAM die are vertically stacked together, and the three chips can communicate directly with each other through the TSVs. Since the TSV spacing can be smaller than that of micro bumps, chip area can be saved, integration is high, and large-capacity cache can be achieved.

[0048] 2. The memory controller and multiple high-speed parallel inter-chip communication bus interfaces are set in the buffer chip. As a result, the logic chip can access the low-speed DRAM chip in a large number of parallel requests through the buffer chip. This not only provides high bandwidth and large capacity cache, but also allows the buffer chip and the logic chip to communicate directly through multiple inter-chip communication bus interfaces (providing multiple I / O) without the need for a physical layer interface to complete inter-chip communication, which greatly reduces the overhead of hardware resources.

[0049] 3. By placing the memory controller in the buffer chip, functions such as self-test, address mapping, temperature detection, error detection and correction are built in, eliminating the need to squeeze it onto the same wafer as the logic chip's computing processor, thus reducing chip area and simplifying wafer manufacturing.

[0050] 4. After vertically stacking buffer chips and DRAM chips at the wafer level to form a first stacked structure, a built-in self-test can be performed on the first stacked structure before vertically stacking the first stacked structure that has passed the test with the logic chips at the wafer level. This can avoid the problem of logic chips being wasted due to defective chips in the buffer chips and DRAM chips when performing the built-in self-test after vertically stacking the logic chips, thereby saving logic chip resources and costs. Attached Figure Description

[0051] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0052] Figure 1 This is a schematic diagram of existing storage and computing chip stacking.

[0053] Figure 2 This is a schematic diagram of a storage computing chip stack according to an embodiment of the present invention.

[0054] Figure 3 This is a schematic diagram of the internal circuit of the memory controller in a storage computing chip according to an embodiment of the present invention.

[0055] Figure 4 This is a schematic diagram of the signal channel of the inter-chip communication bus interface in a storage computing chip according to an embodiment of the present invention.

[0056] Figure 5 This is a schematic diagram of the data channel structure of the inter-chip communication bus interface in a storage computing chip according to an embodiment of the present invention.

[0057] Figure 6 This is a schematic diagram of an example structure of the inter-chip communication bus interface inside a storage computing chip when writing data, according to an embodiment of the present invention.

[0058] Figure 7 yes Figure 6 The diagram shows the timing of the inter-chip communication bus interface of the storage computing chip when it writes data.

[0059] Figure 8 yes Figure 6 The diagram shows the timing of the internal registers in the inter-chip communication bus interface of the storage computing chip when writing data.

[0060] Figure 9 This is a schematic diagram of an example structure of the inter-chip communication bus interface inside a storage computing chip when reading data, according to an embodiment of the present invention.

[0061] Figure 10 yes Figure 8 The diagram shows the timing of the internal registers in the inter-chip communication bus interface of the storage computing chip when it reads data.

[0062] Figure 11 This is another example structural diagram of the inter-chip communication bus interface inside the storage computing chip when writing data according to an embodiment of the present invention.

[0063] Figure 12 This is another example structural diagram of the inter-chip communication bus interface inside the storage computing chip when reading data according to an embodiment of the present invention. Detailed Implementation

[0064] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0065] Please refer to Figure 2 One embodiment of the present invention provides a storage computing chip, which includes a logic chip 70, a buffer chip 100, and at least one layer of DRAM chip 40 stacked vertically in sequence. The logic chip 70 and the buffer chip 100, as well as the buffer chip 100 and the DRAM chip 40, are directly connected through through-silicon vias (TSVs) and a hybrid bonding layer (HB). In other embodiments, the DRAM chip 40 comprises multiple layers, and the multiple layers of DRAM chips 40 are vertically stacked to form a DRAM chip 40 stack. The DRAM chips 40 in this DRAM chip 40 stack are also directly connected through through-silicon vias (TSVs) and a hybrid bonding layer (HB).

[0066] Among them, the logic chip 70, the buffer chip 100 and the DRAM chip 40 can be unpackaged bare dies (or "grids"), packaged chips, or wafer-level chip structures (uncut).

[0067] The logic chip 70 contains a computing processor 10, which may have at least one processor core. The computing processor 10 can be any type of processor with computing capabilities, such as a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), network processor, application processor (AP), field-programmable gate array (FPGA), or dedicated processor. The computing processor 10 can be configured to execute instructions or software (including code, operating system, or application programs), firmware, or combinations thereof, that can be executed by one or more computers. The logic chip 70 can be any suitable chip with computing capabilities, such as a traditional CPU chip, a GPU chip, or an emerging AI chip.

[0068] The buffer chip 100 internally includes a memory controller (DRAM controller) 30 and multiple parallel inter-chip communication bus interfaces 20 that communicate with the memory controller 30. Each inter-chip communication bus interface 20 is connected to the computing processor 10 through several through-silicon vias (TSVs) and a hybrid bonding layer (HB) (or, the memory controller 30 is directly connected to the computing processor 10 through TSVs), enabling the transmission of addresses, data, commands, etc. between the computing processor 10 and the memory controller (i.e., the memory controller 30). The memory controller 30 is connected to the DRAM chip 40 (or the DRAM chip 40 stack) through several through-silicon vias and a hybrid bonding layer HB. For example, the memory controller 30 can convert read, write, and refresh instructions issued by the computing processor 10 to the DRAM chip 40 (or the DRAM chip 40 stack) into signals that the DRAM chip 40 (or the DRAM chip 40 stack) can recognize. It can also decode the write address or read address between the computing processor 10 and the DRAM chip 40 (or the DRAM chip 40 stack), convert the data format (such as the data bit width), and transmit operation commands. This enables the necessary control of refresh operations, read and write operations, and other access to the DRAM chip 40 (or the DRAM chip 40 stack) (including the control of address signals, data signals, and various command signals).

[0069] In this embodiment, the operating frequency of the inter-chip communication bus interface 20 is higher than that of the DRAM chip 40. In one embodiment, the high-speed circuitry of the logic chip 70 and the buffer chip 100 (e.g., the inter-chip communication bus interface 20) both operate at frequencies higher than the DRAM chip 40, for example, multiple times the operating frequency of each layer of DRAM chips 40. Correspondingly, the data width of the inter-chip communication bus interface 20 is multiple times (e.g., 4 times) the data width of the IO interface (not shown) of the DRAM chip 40, and the data width of the computing processor 10 is multiple times (e.g., 4 times) the data width of each inter-chip communication bus interface 20.

[0070] For example, the data width of the I / O interface of a DRAM chip 40 is 256 bits, and the DRAM chip 40 can support a relatively low operating frequency (e.g., 50MHz to 400MHz). Figure 1 In the architecture shown, the maximum bandwidth of communication between the DRAM chip 40 and the logic chip 70 is only 256*400M. However, in this embodiment, since the memory controller 30 and the DRAM chip 40 can be bonded over a large area and purely through through-silicon vias (TSVs) and a hybrid bonding layer (HB), and the memory controller 30 and the inter-chip communication bus interface 20 are integrated in the buffer chip 100 and vertically stacked with the logic chip 70 having the computing processor 10, and communicate directly through TSVs, in this embodiment, the memory controller 30 can perform a large-scale, parallel processing of... The DRAM chip 40's I / O interface is invoked to meet the high-speed communication requirements of the inter-chip communication bus interface 20 (e.g., an AXI interface) between the memory controller 30 and the computing processor 10. When the buffer chip 100 supports an operating frequency of 800MHz, the maximum bandwidth of communication between the buffer chip 100 and the logic chip 70 (e.g., including four AXI subsystems, each AXI subsystem including four AXI interfaces, each AXI interface supporting a maximum data width of 1024 bits) can reach 1024*4*4*800MHz. Clearly, the architecture of this embodiment is relatively... Figure 1 The architecture shown significantly improves the bandwidth for communication between DRAM chip 40 and logic chip 70.

[0071] In other words, the storage computing chip in this embodiment, compared to Figure 1The storage computing chip shown has two advantages. First, by moving the memory controller 30 out of the logic chip 70 with computing functions and making it a separate buffer chip 100, the pressure on the logic chip 70 can be reduced, the area of ​​the logic chip 70 can be saved, and the manufacturing difficulty and cost of the logic chip 70 can be reduced. It also makes it easier for the memory controller 30 to realize the storage management functions of more layers of DRAM chips 40. Second, by using through-silicon vias (TSVs) and multiple inter-chip communication bus interfaces 20 with multiple I / O parallelism in the buffer chip 100 to replace the traditional physical layer interface PHY and microbumps and interposers, high-speed inter-chip communication can be directly realized while greatly reducing the overhead of hardware resources. Moreover, the smaller pitch of TSVs compared to microbumps can be used to place more inter-chip communication bus interfaces 20, realize more I / O, and thus achieve higher bandwidth.

[0072] In one example, each inter-chip communication bus interface 20 is connected to the computing processor 10 via several through-silicon vias (TSVs) passing through the first side of the buffer chip 100, a multilayer hybrid bonding layer (HB), and several through-silicon vias (TSVs) passing through the first side of the logic chip 70. The first side of the buffer chip 100 is its back side, while the memory controller 30 and other structures within the buffer chip 100 are fabricated on its front side. The first side of the logic chip 70 is its back side, while the computing processor and other structures within the logic chip 70 are fabricated on its front side. In this configuration, the buffer chip 100 and the logic chip 70 are bonded back-to-back (B2B) vias (TSVs) and hybrid bonding layers.

[0073] The through-silicon vias (TSVs) in the buffer chip 100 may include through-through TSVs and / or semi-insertion TSVs. The through-through TSV extends from the back side of the buffer chip 100 to the front side of the buffer chip 100, and both the front and back sides of the through-through TSV are exposed by the buffer chip 100 for electrical contact with the corresponding hybrid bonding layer HB between the buffer chip 100 and the logic chip 70. The semi-insertion TSV extends from the front side of the buffer chip 100 to a certain depth in the buffer chip 100 and is electrically connected to the inter-chip communication bus interface 20 and other electrical structures on the front side of the buffer chip 100. The back side of the semi-insertion TSV is exposed by the back side of the buffer chip 100 for electrical contact with the corresponding hybrid bonding layer HB between the buffer chip 100 and the logic chip 70.

[0074] The through-silicon vias (TSVs) in the logic chip 70 may include through-through TSVs and / or semi-insertion TSVs. The through-through TSV extends from the back side of the logic chip 70 to the front side of the logic chip 70, and both the front and back sides of the through-through TSV are exposed by the logic chip 70 for electrical contact with the corresponding hybrid bonding layer HB between the buffer chip 100 and the logic chip 70. The semi-insertion TSV extends from the front side of the buffer chip 100 to a certain depth in the logic chip 70 and is electrically connected to the electrical structure such as the computing processor 10 on the front side of the logic chip 70. The back side of the semi-insertion TSV is exposed by the back side of the logic chip 70 for electrical contact with the corresponding hybrid bonding layer HB between the buffer chip 100 and the logic chip 70.

[0075] Optionally, at least a portion of the through-silicon vias (TSVs) in the buffer chip 100 are vertically aligned with at least a portion of the through-silicon vias (TSVs) in the logic chip 70.

[0076] In one embodiment, the multilayer hybrid bonding layer HB further includes a multilayer metal layer, a hybrid via layer, and a hybrid pad layer.

[0077] In another example, each inter-chip communication bus interface 20 is connected to the computing processor 10 via a plurality of through-silicon vias (TSVs) passing through a first side of the buffer chip 100, a multilayer hybrid bonding layer HB, and a plurality of through-silicon vias (TSVs) passing through a second side of the logic chip 70. The first side of the buffer chip 100 is its back side, while structures such as the memory controller 30 within the buffer chip 100 are fabricated on its front side. The second side of the logic chip 70 is its front side, and structures such as the computing processor within the logic chip 70 are fabricated on its front side. In this case, the buffer chip 100 and the logic chip 70 are back-to-front bonded (B2F) vias (TSVs) and the hybrid bonding layer. In one embodiment, the multilayer hybrid bonding layer HB further includes multiple metal layers, a hybrid via layer, and a hybrid pad layer.

[0078] In one example, the memory controller 30 is connected to the DRAM chip 40 via several through-silicon vias (TSVs) passing through the second side of the buffer chip 100, a multilayer hybrid bonding layer (HB), and several through-silicon vias (TSVs) passing through the second side of the DRAM chip 40. The second side of the buffer chip 100 is its front face, and structures such as the memory controller 30 within the buffer chip 100 are fabricated on its front face. The second side of the DRAM chip 40 is its front face, and structures such as the memory array within the DRAM chip 40 are fabricated on its front face. In this configuration, the buffer chip 100 and the DRAM chip 40 are directly bonded (F2F) vias (TSVs) and the hybrid bonding layer. The reason for choosing the F2F bonding method between the buffer chip 100 and the DRAM chip 40 is that the number of through-silicon vias (TSVs) required between the buffer chip 100 and the DRAM chip 40 is relatively large. By using the F2F bonding method, most of the TSVs on the front side of the buffer chip 100 can be semi-inserted TSVs. These semi-inserted TSVs extend from the front side of the buffer chip 100 to a certain depth and are electrically connected to the internal electrical structures such as the memory controller 30 of the buffer chip 100. The front side of these semi-inserted TSVs is exposed by the front side of the buffer chip 100 to make electrical contact with the corresponding hybrid bonding layer HB between the buffer chip 100 and the DRAM chip 40. This helps to reduce the manufacturing difficulty of the TSVs on the front side of the buffer chip 100 and ensures the reliability of the buffer chip 100.

[0079] Optionally, a portion of the through-silicon via (TSV) passing through the second side of the buffer chip 100 may further penetrate vertically through the buffer chip 100 until it is exposed on the first side of the buffer chip 100, for bonding with a corresponding TSV in the logic chip 70 via a hybrid bonding layer HB.

[0080] Optionally, at least a portion of the through-silicon via (TSV) passing through the second side of the DRAM chip 40 may further penetrate vertically through the DRAM chip 40 until it is exposed by the first side of the DRAM chip 40, for bonding with a corresponding TSV of the second side of another DRAM chip via a hybrid bonding layer HB.

[0081] Further optionally, at least a portion of the through-silicon vias (TSVs) on the second side of the buffer chip 100 are vertically aligned with the corresponding through-silicon vias (TSVs) on the second side of the DRAM chip 40.

[0082] In one example, when DRAM chips 40 are vertically stacked in multiple layers, and structures such as memory arrays in the DRAM chips 40 are fabricated on the front (face) of the DRAM chips 40, Figure 2 Taking the structure in the example, the front side of the upper DRAM chip 40 and the back side of the lower DRAM chip 40 are bonded together by through silicon vias (TSV) and a hybrid bonding layer (HB). In other words, the two adjacent DRAM chips are bonded face-to-back (F2B).

[0083] Alternatively, when the DRAM chips 40 are stacked vertically in multiple layers, the aforementioned through-silicon vias (TSVs) in these DRAM chips 40 are vertically aligned with each other.

[0084] Optionally, the memory controller 30 is not only used to manage and plan the data storage and transmission between the computing processor 10 (as the master device) and the DRAM chip 40 or the DRAM chip 40 stack (as the slave device), and to convert the read, write, refresh commands issued by the computing processor 10 into signals that the DRAM chip 40 (or the DRAM chip 40 stack) can recognize, but also to realize various functions such as address decoding and data bit width conversion between the computing processor 10 and the DRAM chip 40 (or the DRAM chip 40 stack), built-in self-test, temperature detection, error detection and correction (ECC).

[0085] In one example, the memory controller 30 may include any one or more required logic circuits such as an address mapping circuit 300, a built-in self-test (BIST) circuit 301, a command arbitration circuit 302, a timing control circuit 303, a refresh management circuit 304, an error detection and correction (ECC) circuit 305, a temperature detection circuit 306, and a power management circuit 307.

[0086] In this regard, please combine Figure 2 and Figure 3 The address mapping circuit 300 is used to map the address range sent by the computing processor 10 to the inter-chip communication bus interface 20 (i.e. the address range received by the inter-chip communication bus interface 20) to the DRAM chips 40 (or the stack of DRAM chips 40) vertically stacked on the buffer chip 100.

[0087] Please combine Figure 2 and Figure 3The built-in self-test circuit 301 is used to perform a first built-in self-test on the first stacked structure after the buffer chip 100 and DRAM chip 40 are vertically stacked at the wafer level to form a first stacked structure, and / or to perform a second built-in self-test on the second stacked structure after the logic chip 70, buffer chip 100, and DRAM chip 40 are vertically stacked at the wafer level (which can be either the logic chip 70 vertically stacked with the first stacked structure, or the logic chip 70, buffer chip 100, and DRAM chip 40 directly vertically stacked) to form a second stacked structure. The content of the first built-in self-test and the content of the second built-in self-test can be the same or different.

[0088] In one example, since the logic chip 70 is a large chip manufactured using an advanced process, with high process requirements and high cost, the wafer-level buffer chip 100 (i.e., it is a buffer wafer at this stage) and the wafer-level DRAM chip 40 (i.e., it is a DRAM wafer at this stage) can be vertically stacked together at the wafer level using a WOW (wafer on wafer) process to form a first wafer-level stacked structure. The inter-chips of this first stacked structure are bonded via TSV hybrid bonding (HB). After forming the first wafer-level stacked structure, a first built-in self-test is performed at the wafer level using the built-in self-test circuit 301 in the memory controller 30 (during this test, the first stacked structure can be stimulated by the computing processor 10 or other test host). After the first built-in self-test passes, the first wafer-level stacked structure and the wafer-level logic chip 70 (i.e., it is a logic wafer at this stage) are then connected via a WOW (wafer on wafer) process. The buffer chip 100 and the logic chip 70 are vertically stacked together using a wafer-level process. The buffer chip 100 and the logic chip 70 are bonded together by a through-silicon via (TSV) hybrid bonding (HB), thereby forming a second wafer-level stacked structure (also known as a wafer-level memory computing chip). A second built-in self-test can then be performed on the second stacked structure. This avoids the problem of discovering defective chips and wasting logic chips after the logic chip 70, buffer chip 100 and DRAM chip 40 (or a stack of DRAM chips 40) are directly stacked at the wafer level.

[0089] Optionally, the second built-in self-test may contain fewer components than the first built-in self-test, thereby improving testing efficiency and reducing testing costs after stacking the logic chips 70. For example, the first built-in self-test may include a comprehensive test of the DRAM chip 40 or a comprehensive test of the DRAM chip 40 and a self-test of the buffer chip 100; the second built-in self-test may include testing the communication function between the logic chip 70 and the buffer chip 100, and / or, performing spot checks on the performance parameters of the DRAM chip 40.

[0090] Furthermore, after completing the second built-in self-test, the wafer-level second stacked structure is diced to obtain several discrete memory computing chips. In other embodiments, the memory computing chips obtained after dicing and packaging can be further subjected to other tests (e.g., FT tests).

[0091] Please combine Figure 2 and Figure 3 The command arbitration circuit 302 is used to perform priority arbitration and scheduling on multiple commands (or "requests") sent by the computing processor 10 through the inter-chip communication bus interface 20, so that each command is executed sequentially.

[0092] Please combine Figure 2 and Figure 3 The timing control circuit 303 is used to insert appropriate delays between commands according to the specifications of various timing parameters.

[0093] Please combine Figure 2 and Figure 3 The refresh management circuit 304 is used to refresh the DRAM chip 40 (or the stack of DRAM chips 40) according to the refresh command transmitted by the computing processor 10 through the inter-chip communication bus interface 20. The refresh management circuit 304 can be configured to interleave the refresh operation of the DRAM chip 40 with normal requests (such as read and write requests) and avoid the problem of high latency caused by the refresh operation.

[0094] Please combine Figure 2 and Figure 3 The error detection and correction circuit 305 is used to perform error detection and correction (ECC) on the data read from the DRAM chip 40 (or the DRAM chip 40 stack) when the computing processor 10 reads data through the inter-chip communication bus interface 20, and / or to perform error detection and correction on the data written to the DRAM chip 40 (or the DRAM chip 40 stack) when the computing processor 10 writes data through the inter-chip communication bus interface 20.

[0095] Please combine Figure 2 and Figure 3 The temperature detection circuit 306 is used to detect the temperature change of the inter-chip communication bus interface 20 and / or DRAM chip 40 (or DRAM chip 40 stack), and adjust the corresponding parameters according to the detected temperature change, such as adjusting the self-refresh frequency (or refresh cycle) and adjusting the working mode.

[0096] Please combine Figure 2 and Figure 3 The power management circuit 307 is used to control the DRAM chip 40 (or the DRAM chip 40 stack) to enter or exit at least one low power state.

[0097] Please refer to Figure 2 and Figure 4 The inter-chip communication bus interface 20 can provide multiple signal channels (e.g., between the computing processor 10 and the memory controller 30) Figure 4 As shown in 20a-20e, each signal channel uses the same handshake mechanism to realize the information transfer between the computing processor 10 and the memory controller 30. This handshake mechanism uses a handshake signal pair (which consists of a handshake signal sent by the computing processor 10 to the memory controller 30 and another handshake signal sent by the memory controller 30 to the computing processor 10, such as a valid signal and a ready signal) to perform the communication handshake between the computing processor 10 and the memory controller 30.

[0098] Optionally, each inter-chip communication bus interface 20 includes at least one of a write address channel 20a, a write data channel 20b, a write response channel 20c, a read address channel 20d, and a read data channel 20e. Each signal channel contains a set of information signals and a handshake signal pair, and each signal channel uses the handshake signal pair within the signal channel to perform a handshake. For example, the handshake signal pair can be a valid signal and a ready signal.

[0099] Please refer to Figure 4 The write address channel 20a is used to transmit the write address (i.e., the starting address of the data to be written) waddr from the computing processor 10 to the memory controller 30 after completing the handshake between the write address valid signal awvalid and the write address ready signal awready in this channel. The write address valid signal awvalid is sent by the computing processor 10 to the memory controller 30; awvalid = 1 indicates that the write address and control information in the write address channel 20a are valid, and awvalid = 0 indicates that the write address and control information in the write address channel 20a are invalid. The write address ready signal awready is sent by the memory controller 30 to the computing processor 10; awready = 1 indicates that the memory controller 30 is ready to receive the write address and control information in the write address channel 20a, and awready = 0 indicates that the memory controller 30 is not yet ready to receive the write address and control information in the write address channel 20a. The transmission of the write address waddr in the write address channel 20a only actually occurs when awready = 1 and awvalid = 1.

[0100] Please refer to Figure 4The write data channel 20b is used to transmit multiple bits (e.g., n bits, where n is an integer greater than 1) of write data signals (i.e., the data to be written) wdata from the computing processor 10 to the memory controller 30 after completing the handshake between the write data valid signal wvalid and the write data ready signal wready in the channel. The write data channel 20b can include a data bus with a data width of 8 to 1024 bits (i.e., n = 8 to 1024), such as 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, 512-bit, or 1024-bit. The write data channel 20b can support burst data transmission to continuously transmit multiple blocks of data in a single transaction. The write data channel 20b can identify the last data transmission cycle of a burst transmission using the write end signal wlast. During a burst transmission, each byte channel consists of eight bits of data. The write data channel 20b can specify the byte channel containing valid information in its data bus using the write byte enable signal wstrb (Write strobes). The write data valid signal wvalid is sent by the processor 10 to the memory controller 30. wvalid = 1 indicates that the write data signal wdata (which is n bits) and control information in the write data channel 20b are valid, and wvalid = 0 indicates that the write data signal wdata (which is n bits) and control information in the write data channel 20b are invalid. The write data ready signal wready is sent by the memory controller 30 to the processor 10. wready = 1 indicates that the memory controller 30 is ready to receive the write data signal wdata (which is n bits) and control information in the write data channel 20b, and wready = 0 indicates that the memory controller 30 is not yet ready to receive the write data signal wdata (which is n bits) and control information in the write data channel 20b. Only when wready = 1 and wvalid = 1 does the transmission of the write data signal wdata (which is n bits) in the write data channel 20b actually occur.

[0101] Please refer to Figure 4The write response channel 20c is used to transmit the write response status signal wresp from the memory controller 30 to the computing processor 10 after completing the handshake between the write response valid signal bvalid and the write response ready signal bready within the channel, indicating that the write data operation is complete. Specifically, the write response valid signal bvalid is sent by the memory controller 30 to the computing processor; bvalid = 1 indicates that the write response status signal wresp and control information in the write response channel 20c are valid, and bvalid = 0 indicates that the write response status signal wresp and control information in the write response channel 20c are invalid. The write response ready signal bready is sent by the computing processor 10 to the memory controller 30; bready = 1 indicates that the computing processor is ready to receive the write response status signal wresp and control information in the write response channel 20c, and bready = 0 indicates that the computing processor 10 is not yet ready to receive the write response status signal wresp and control information in the write response channel 20c. The transmission of the write response status signal wresp in the write response channel 20c only actually occurs when bready = 1 and bvalid = 1. wresp = 1 indicates that the write data signal wdata (which is n bits) was successfully written, and wresp = 0 indicates that the write data signal wdata (which is n bits) failed to be written.

[0102] Please refer to Figure 4 The read address channel 20d is used to transmit the read address (i.e., the starting address of the data to be read) raddr from the computing processor 10 to the memory controller 30 after completing the handshake between the read address valid signal arvalid and the read address ready signal arready in this channel. The read address valid signal arvalid is sent by the computing processor 10 to the memory controller 30. arvalid = 1 indicates that the read address and control information in the read address channel 20d are valid, and arvalid = 0 indicates that the read address and control information in the read address channel 20d are invalid. The read address ready signal arready is sent by the memory controller 30 to the computing processor 10. arready = 1 indicates that the memory controller 30 is ready to receive the read address and control information in the read address channel 20d, and arready = 0 indicates that the memory controller 30 is not yet ready to receive the read address and control information in the read address channel 20d. The transmission of the read address raddr in the read address channel 20d only actually occurs when arready = 1 and arvalid = 1.

[0103] Please refer to Figure 4The read data channel 20e is used to transmit multiple bits (e.g., n bits) of read data signals (i.e., the data to be read) rdata from the memory controller 30 to the computing processor 10 after completing the handshake between the read data valid signal rvalid and the read data ready signal rready in the channel. The read data channel 20e may include a data bus with a data width of 8 to 1024 bits (i.e., n = 8 to 1024), such as 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, 512-bit, or 1024-bit. The read data channel 20e can support burst data transmission to continuously transmit multiple blocks of data in a single transaction. The read data channel 20e can use the read end signal rlast to identify the last data transmission cycle of a burst transmission. The read data valid signal `rvalid` is sent from the memory controller 30 to the computing processor 10. `rvalid = 1` indicates that the read data signal `rdata` (which is n bits) and control information in the read data channel 20b are valid; `rvalid = 0` indicates that the read data signal `rdata` (which is n bits) and control information in the read data channel 20b are invalid. The read data ready signal `rready` is sent from the memory controller 10 to the computing processor 30. `rready = 1` indicates that the computing processor 10 is ready to receive the read data signal `rdata` (which is n bits) and control information in the read data channel 20b; `rready = 0` indicates that the computing processor 10 is not yet ready to receive the read data signal `rdata` (which is n bits) and control information in the read data channel 20b. Only when `rready = 1` and `rvalid = 1` does the transmission of the read data signal `rdata` in the read data channel 20b actually occur.

[0104] The data width of the inter-chip communication bus interface 20 is relatively large (e.g., 1024 bits). Each data bit needs to form a through-silicon via (TSV) path between the buffer chip 100 and the logic chip 70. These TSV paths are arranged horizontally, and the corresponding TSV positions of the data channels in the layout are relatively far apart, which will introduce additional delay. In addition, the buffer chip 100 and the logic chip 70 may operate under different process corners. At the same time, the buffer chip 100 operates under a high-frequency clock and the DRAM chip 40 operates under a low-frequency clock, which will cause some circuits (such as voltage converter level shifters) to cause corresponding delays. As a result, when the inter-chip communication bus interface 20 adopts a conventional handshake mechanism, under the condition of high-speed TSV communication, the timing of each data channel of the inter-chip communication bus interface 20 is difficult to converge.

[0105] Based on this, in one example, please refer to Figure 2 and Figure 4 In at least one data channel (which can be a write data channel, a read data channel, or both) of the inter-chip communication bus interface 20, a cascaded first register slice 201 and a second register slice 202 are configured. The first register slice 201 is also coupled to the computing processor 10, and the second register slice 202 is also coupled to the memory controller 30. Each of the first register slice 201 and the second register slice 202 is provided with at least one stage of data register circuit 200a. Each stage of the data register circuit 200a is used to transmit the multi-bit data signal "data" in parallel after completing the handshake signal pair (e.g., valid signal and ready signal) in the data channel.

[0106] In this case, the first-level data register circuit 200a in the first register slice 201 with the shortest signal path to the computing processor 10 is de-driven by the handshake signal sent by the computing processor 10 to the first register slice 201 (i.e., the handshake signal sent by the computing processor 10 to the memory controller 30), while the remaining level data register circuits 200a in the second register slice 202 and / or the first register slice 201 are all driven by the handshake signal pair.

[0107] Therefore, by reducing the load of handshake signals sent by the computing processor 10 in the data channel (i.e., reducing the number of TSV paths driven by the handshake signals sent by the computing processor 10 in the data channel), the inter-chip timing converges as quickly as possible when the buffer chip 100 and the logic chip 70 are vertically stacked.

[0108] In one example, please refer to Figure 5When the data signal is an n-bit signal, in the first register slice 201 and the second register slice 202 set in the corresponding data channels of each inter-chip communication bus interface 20, each level of data register circuit 200a includes n parallel data register branches. Each data register branch is configured one-to-one with each bit of data signal data and is driven by a handshake signal pair or one of the handshake signals in the handshake signal pair. Each handshake signal in the handshake signal pair is a 1-bit signal, and the handshake signal pair can synchronously drive the n parallel data register branches corresponding to the same level of data register circuit 200a. In a further embodiment, each data register branch includes combinational logic comb and a one-bit data register data reg coupled to the combinational logic comb. The handshake signal (e.g., a valid signal and a ready signal) synchronously drives the combinational logic comb in the n parallel data register branches corresponding to the same level of data register circuit 200a. For example, when n = 1024 and the handshake signal pair is valid and ready, each level data register circuit 200a can transmit 1024 bits of data signal data in parallel under the drive of 1 bit of valid signal and / or 1 bit of ready signal.

[0109] Alternatively, please refer to Figure 5 Each stage of data register circuit 200a in the first register slice 201 and the second register slice 202 further includes a first handshake signal transmission circuit 200b and a second handshake signal transmission circuit 200c. The first handshake signal transmission circuit 200b is used to transmit one handshake signal in the handshake signal pair, and the second handshake signal transmission circuit 200c is used to transmit the other handshake signal in the handshake signal pair.

[0110] In this embodiment, a two-level register slice design is inserted into the corresponding data channel of the inter-chip communication bus interface 20, and the driving of the same handshake signal is reduced for each data register branch in the first-level data register circuit 200a with the shortest signal path to the computing processor 10. Although this method increases the number of toggle operations on the data register circuit 200a at this stage, it does not affect the handshake of the handshake signal pairs (e.g., valid and ready signals) in the data channel. Moreover, since the data register circuit 200a at this stage reduces the number of handshake signals sent by the computing processor 10 (valid signal when writing data, ready signal when reading data), it can reduce the load of the handshake signal (i.e., reduce the number of TSV paths it drives, each TSV path includes a TSV and a data register branch), thereby reducing the timing pressure of communication handshake in the data channel. This is conducive to completing the timing convergence of communication handshake in the data channel as soon as possible, and can support large data bit width and high-speed synchronous transmission between the logic chip 70 and the buffer chip 100, ensuring the accuracy and stability of the data. In addition, the remaining data register circuits are still driven by the handshake signal pairs (e.g., valid and ready signals) in the data channel, which can prevent the additional power consumption caused by frequent data toggle.

[0111] Please refer to Figure 6 , Figure 9 and Figures 11 to 12 The first register slice 201 can be a forward register slice (FR), a backward register slice (BR), or a full register slice, and the present invention does not specifically limit it.

[0112] Here, "forward" refers to the direction in which the data sender (source) transmits data to the data receiver (destination). Please refer to [reference needed]. Figure 5 and Figure 11 The forward register slice has a forward register circuit FR, which includes a first-level data register circuit 200a, a first handshake signal transmission circuit 200b, and a second handshake signal transmission circuit 200c. The data register circuit 200a has n data register branches, each consisting of combinational logic comb0 and a 1-bit data register wdata reg0 (wherein, for clarity, ...). Figure 11Only one data register branch of this data register circuit is shown in the diagram. Each data register branch can stamp its transmitted 1-bit data signal (data). The first handshake signal transmission circuit 200b consists of combinational logic comb2 and a first handshake signal register valid reg0. This first handshake signal transmission circuit 200b is used to transmit one handshake signal (e.g., the valid signal) in the handshake signal pair and stamps the handshake signal during transmission. The second handshake signal transmission circuit 200c consists of combinational logic comb4, which is used to transmit the other handshake signal (e.g., the ready signal) in the handshake signal pair. The forward register slice FR will stamp both the n-bit data signal (data) in the data channel and one handshake signal (e.g., the valid signal) in the handshake signal pair simultaneously.

[0113] Backward refers to the direction in which the data receiver sends a handshake signal (e.g., a ready signal) to the data sender. The backward register slice contains backward register circuitry; please refer to [the relevant documentation / reference]. Figure 5 and Figure 12 The backward register circuit BR includes a first-stage data register circuit 200a, a first handshake signal transmission circuit 200b, and a second handshake signal transmission circuit 200c. The data register circuit 200a has n data register branches, each consisting of combinational logic comb1 and a 1-bit data register rdata reg1 (for clarity, ...). Figure 9 Only one data register branch of this data register circuit is shown in the diagram. Each data register branch can stamp the 1-bit data signal 'data' it transmits. The first handshake signal transmission circuit 200b consists of combinational logic comb3 and a first handshake signal register valid reg1. This first handshake signal transmission circuit 200b is used to transmit one handshake signal (e.g., the valid signal) in the handshake signal pair and stamps the handshake signal during transmission. The second handshake signal transmission circuit 200c consists of combinational logic comb5 and a second handshake signal register ready reg0. It is used to transmit the other handshake signal (e.g., the ready signal) in the handshake signal pair and stamps the handshake signal during transmission. The backward register slice BR can stamp both the handshake signal pair and the n-bit data signal 'data' in the data channel to prevent data omissions or duplicate sampling.

[0114] Please combine Figure 5 , Figure 6 and Figure 9The bidirectional register slice is composed of a forward register circuit FR and a backward register circuit BR, including a first handshake signal transmission circuit 200b, a second handshake signal transmission circuit 200c, and two cascaded data register circuits 200a. The first handshake signal transmission circuit 200b in this bidirectional register slice can be formed by sequentially coupling combinational logic comb2, the first handshake signal register valid reg0, combinational logic comb3, and the first handshake signal register validreg1, enabling it to time the first handshake signal (e.g., the valid signal). The second handshake signal transmission circuit 200c in this bidirectional register slice can be formed by sequentially coupling combinational logic comb4, the second handshake signal register readyreg0, and combinational logic comb5, enabling it to time the second handshake signal (e.g., the ready signal). Each stage of the data register circuit 200a in this bidirectional register slice has n data register branches (for clarity of illustration). Figure 6 and Figure 9 Each data register branch in the first-level data register circuit 200a consists of a corresponding combinational logic comb0 and a data register wdata reg0. Similarly, each data register branch in the second-level data register circuit 200a consists of a corresponding combinational logic comb1 and a data register wdatareg1. The data register branches in both levels of the data register circuit 200a are configured and connected in a one-to-one correspondence, thereby slicing the data for that bit. Thus, this bidirectional register slice can slice both the handshake signal pairs and the n-bit data signal data in the data channel.

[0115] Similarly, please refer to Figure 5 , Figure 6 , Figure 9 and Figures 11 to 12 The second register slice 202 can be a forward register slice (FR), a backward register slice (BR), or a full register slice; this invention does not specifically limit this. The second register slice 202 can use the same circuit design as the first register slice 201, or it can use a different circuit design. For example, in... Figure 6 and Figure 9 In the example shown, both the second register slice 202 and the first register slice 201 employ the same bidirectional register slice circuit design; Figure 11 In the example shown, both the second register slice 202 and the first register slice 201 employ the same forward register slice circuit design; Figure 12 In the example shown, both the second register slice 202 and the first register slice 201 employ the same backward register slice circuit design. In other examples, the first register slice 201 employs a forward register slice circuit design, and the second register slice 202 employs a bidirectional register slice circuit design, or the first register slice 201 employs a bidirectional register slice circuit design, and the second register slice 202 employs a backward register slice circuit design, and so on.

[0116] In this embodiment, please refer to Figures 2 to 8 and Figure 11 The inter-chip communication bus interface 20 has a write data channel 20b, into which two levels of register slices, a first register slice 201 and a second register slice 202, are inserted. The first register slice 201 is coupled between the computing processor 10 and the second register slice 202, and the second register slice 202 is coupled between the first register slice 201 and the memory controller 30. The first-level data register circuit 200a in the first register slice 201 with the shortest signal path to the computing processor 10 is de-driven by the write data valid signal wvalid sent by the computing processor 10. The remaining levels of data register circuits 200a are all driven by the corresponding write data valid signal wvalid and write data ready signal wready. Compared with the remaining levels of data register circuits 200a, the first-level data register circuit 200a with the shortest signal path to the computing processor 10 in the first register slice 201 reduces the drive of the write data valid signal wvalid (i.e., the load of the write data valid signal wvalid).

[0117] In one example, please combine Figures 2 to 6Both the first register slice 201 and the second register slice 202 adopt a bidirectional register slice circuit design. The first-level data register circuit with the shortest signal path between the first register slice 201 and the computing processor 10 is the data register circuit 200a in the forward register circuit FR of the first register slice 201. It has n data register branches. Each data register branch is composed of the corresponding combinational logic comb0 and write data register wdata reg0 in the first register slice 201. Each data register branch is driven only by the write data ready signal wready. The remaining data register circuits include: (1) a data register circuit 200a in the backward register circuit BR of the first register slice 201, which has n data register branches (furthermore, each data register branch is composed of combinational logic comb1 and write data register wdata reg1 in the first register slice 201), and each data register branch is driven by the write data valid signal wvalid and the write data ready signal wready; (2) a data register circuit 200a in the forward register circuit FR of the second register slice 202, which has n data register branches (furthermore, each data register branch is composed of combinational logic comb0 and write data register wdata in the second register slice 202). (3) The data register circuit 200a in the backward register circuit BR of the second register slice 202 has n data register branches (furthermore, each data register branch is composed of combinational logic comb1 and write data register wdata reg1 in the second register slice 202), and each data register branch is driven by the write data valid signal wvalid and write data ready signal wready. Compared with the first-level data register circuit 200a in the first register slice 201 and the second register slice 202 (furthermore, it has n combinational logic comb0 and n write data register wdata reg0, one comb0 and one wdata (reg0 forms a data register branch). It can be observed that the data register circuit 200a in the first register slice 201 is not driven by the write data valid signal wvalid, but only by the write data ready signal wready. In contrast, the data register circuit 200a in the second register slice 201 is driven by the write data valid signal wvalid (see... Figure 6 (As shown by the red line in the image) and the write data ready signal wready work together to drive it.

[0118] When the computing processor 10 writes data to the DRAM chip 40 (or the stack of DRAM chips 40) through the inter-chip communication bus interface 20 and the memory controller 30, the write timing in the inter-chip communication bus interface 20 is as follows: Figure 7 As shown, the signal timing of the first register slice 201 in the write response channel 20c and write data channel 20b of the inter-chip communication bus interface 20 is as follows: Figure 5 As shown. Please refer to... Figures 6 to 8 (especially) Figure 8 As shown in the red box, when wvalid is 0, the switching of wdata provided by the computing processor 10 will also cause the data cached in the data register wdata_reg0 inside the first register slice 201 (i.e., the data register in the data register circuit 200 with the shortest signal path between the computing processor 10 and the data register) to switch (toggle). This will bring a certain increase in power consumption, but it will not affect the handshake between wvalid and wready in the write data channel. Moreover, since the combinational logic comb0 coupled to the data register wdata_reg0 eliminates the wvalid driver, the number of loads of the wvalid driver in the write data channel (i.e., the number of TSV paths between the buffer chip 100 and the logic chip 70) is reduced. This can reduce the timing pressure of the handshake in the write data channel 20b, and make the timing convergence of the write data channel 20b more convenient. In this way, it can support the large data bit width and high-speed synchronous transmission of data between the buffer chip 100 and the logic chip 70, and ensure the accuracy and stability of the computing processor 10 writing data to the memory controller 30 and the DRAM chip 40 (or the DRAM chip 40 stack). In addition, the data register circuit in the second register slice 202 is still driven by the wvalid and wready signals, which can prevent the additional power consumption caused by frequent data switching (toggle).

[0119] In another example, please combine Figure 5 and Figure 11Both the first register slice 201 and the second register slice 202 adopt a forward register slice circuit design. Specifically, the data register circuit 200a in the first register slice 201 has the shortest signal path to the computing processor 10, and it has n data register branches (furthermore, each data register branch consists of a corresponding combinational logic comb0 and a write data register wdata reg0 in the first register slice 201), and each data register branch is driven by the write data ready signal wready. The data register circuit 200a in the second register slice 202 also has n data register branches (furthermore, each data register branch consists of a corresponding combinational logic comb0 and a write data register wdata reg0 in the second register slice 202), and each data register branch is jointly driven by the write data valid signal wvalid and the write data ready signal wready. This example not only enables the wvalid and wready handshake in the write data channel, reducing the timing pressure of the handshake, but also facilitates the timing convergence of the write data channel. This, in turn, supports large data bit width and high-speed synchronous transmission between buffer chip 100 and logic chip 70, ensuring data accuracy and stability. Furthermore, it is relatively... Figure 6 The example shown has a simpler circuit and lower circuit cost.

[0120] In this embodiment, please refer to Figure 5 , Figure 9 and Figure 12 The inter-chip communication bus interface 20 has a read data channel 20e, into which two levels of register slices, a first register slice 201 and a second register slice 202, are inserted. The first register slice 201 is coupled between the computing processor 10 and the second register slice 202, and the second register slice 202 is coupled between the first register slice 201 and the memory controller 30. The first-level data register circuit 200a in the first register slice 201 with the shortest signal path to the computing processor 10 has had the drive of the read data ready signal rready sent by the computing processor 10 removed from the handshake signal pair (e.g., rvalid / rready). The remaining levels of data register circuits 200a are all driven by the corresponding read data valid signal rvalid and read data ready signal rready.

[0121] In one example, please refer to Figure 9Both the first register slice 201 and the second register slice 202 adopt a bidirectional register slice circuit design. The first-level data register circuit with the shortest signal path between the first register slice 201 and the computing processor 10 is the data register circuit 200a in the backward register circuit BR of the first register slice 201, which has n data register branches (furthermore, each data register branch is composed of the corresponding combinational logic comb1 and read data register rdata reg1 in the first register slice 201). The remaining data register circuits include: (1) a data register circuit 200a in the forward register circuit FR of the first register slice 201, which has n data register branches (furthermore, each data register branch is composed of the corresponding combinational logic comb0 and read data register rdata reg0 in the first register slice 201), and each data register branch is driven by the read data valid signal rvalid and the read data ready signal rready; (2) a data register circuit 200a in the backward register circuit BR of the second register slice 202, which has n data register branches (furthermore, each data register branch is composed of the corresponding combinational logic comb1 and read data register rdata in the second register slice 202). (3) The data register circuit 200a in the forward register circuit FR of the second register slice 202 has n data register branches, (furthermore, each data register branch is composed of combinational logic comb0 and read data register rdata reg0 in the second register slice 202), and each data register branch is driven by read data valid signal rvalid and read data ready signal rready. Comparing the data register circuits 200a closest to the computing processor 10 in the first register slice 201 and the second register slice 202 (each data register branch consists of a corresponding combinational logic comb1 and a read data register rdata reg1), it can be found that the data register circuit 200a in the first register slice 201 is not driven by the read data ready signal rready provided by the computing processor 10, while the data register circuit 200a in the second register slice 201 is driven by the read data ready signal rready provided by the first register slice 201 (see...). Figure 9 (As shown by the red line in the image) and the read data valid signal rvalid work together to drive the system.

[0122] When the computing processor 10 reads data from the DRAM chip 40 (or the DRAM chip 40 stack) through the inter-chip communication bus interface 20 and the memory controller 30, the signal timing of the first register slice 201 in the read data channel 20e of the inter-chip communication bus interface 20 is as follows: Figure 10 As shown. Please refer to... Figure 9 and Figure 10 As shown in the red box, when ready_reg0 is 0, the switching of the n-bit read data rdata provided by the memory controller 30 will also cause the data cached in the data register rdata_reg1 inside the first register slice 201 (i.e., the data register in the first-level data register circuit 200a with the shortest signal path between it and the computing processor 10) to switch (toggle). This will lead to a certain increase in power consumption, but it will not affect the handshake signal for rvalid and rready in this read data channel. Moreover, because each data register branch in this level of data register circuit 200 (furthermore, this data register branch is the read data register...) The combinational logic comb1 coupled to register rdata_reg1 eliminates the need for the rready signal driven by the computing processor 10 during the handshake signal pair. This reduces the load on the rready driver (i.e., reduces the number of TSV paths between the buffer chip 100 and the logic chip 70), thereby reducing the timing pressure of the handshake in the read data channel and facilitating timing convergence. This enables high-volume, high-speed synchronous transmission of data between the buffer chip 100 and the logic chip 70, ensuring the accuracy and stability of the computing processor 10 in reading data from the DRAM chip 40 (or the DRAM chip 40 stack). Furthermore, the data register circuit 200a in the second register slice 202 is still driven by the rvalid and rready signals, preventing further power consumption caused by frequent data toggle switching.

[0123] In another example, please refer to Figure 12Both the first register slice 201 and the second register slice 202 adopt a backward register slice circuit design. Specifically, the data register circuit 200a in the first register slice 201, which has the shortest signal path to the computing processor 10, has n data register branches. Optionally, each data register branch consists of a corresponding combinational logic comb1 and a read data register rdata reg1 in the first register slice 201, reducing the driving force of the read data ready signal rready provided by the computing processor 10. The data register circuit 200a in the second register slice 202 also has n data register branches. Optionally, each data register branch consists of a corresponding combinational logic comb1 and a read data register rdata reg1 in the second register slice 202. Each data register branch in the second register slice 202 is driven by both the read data valid signal rvalid and the read data ready signal rready.

[0124] In this embodiment, a cascaded two-level register slice is set in the corresponding data channel of the inter-chip communication bus interface. The first-level data register circuit with the shortest signal path between the two-level register slice and the computing processor reduces the driving of the handshake signal sent by the computing processor. Although this method increases the number of toggle operations of the multi-bit data signals buffered by the data register circuit, it does not affect the handshake of the handshake signal pairs in the data channel. Moreover, since the first-level data register circuit with the shortest signal path between the first register slice and the computing processor is freed from the driving of the handshake signal sent by the computing processor, the number of data registers driven by the handshake signal (i.e., the number of loads) is reduced, thereby reducing the timing pressure of communication handshake in the data channel. This is conducive to completing the timing convergence of the data channel as soon as possible, and can support large data bit width, high-speed synchronous inter-chip data transmission, ensuring the accuracy and stability of the data. The remaining data register circuits are still driven by the handshake signal pairs, which can prevent the additional power consumption caused by frequent toggle operations of the buffered data.

[0125] Please refer to Figure 2 This embodiment also provides a method for manufacturing a storage computing chip as described in this invention, which includes the following steps:

[0126] First, at least one DRAM wafer (i.e., a wafer-level DRAM chip 40) and a buffer wafer (i.e., a wafer-level buffer chip 100) are provided. The buffer wafer and the DRAM wafer are vertically stacked and hybrid-bonded in sequence to form a first wafer-level stacked structure. In the first stacked structure, the DRAM wafer (i.e., the wafer-level DRAM chip 100) and the buffer wafer (i.e., the wafer-level buffer chip 100) are directly connected through through-silicon vias (TSVs) and hybrid bonding layers (HBs). Each DRAM wafer includes multiple DRAM chips 40, and the buffer wafer includes multiple buffer chips 100. Each buffer chip 100 has a memory controller 30 and an inter-chip communication interface 20.

[0127] Next, a first built-in self-test is performed on the first stacked structure at the wafer level. This first built-in self-test generates specific test vectors through the built-in self-test circuit embedded in the memory controller 30 to perform a comprehensive test on the DRAM chip 40. Further optionally, the first built-in self-test can also generate random vectors and responses through the built-in self-test circuit embedded in the memory controller 30 to perform self-tests on the memory controller 30 and other related logic circuits in the buffer chip 100.

[0128] Then, a logic wafer (i.e., a wafer-level logic chip 70) is provided and vertically stacked with the first built-in self-test passed first stacking structure described above, and hybrid bonded by through-silicon vias (TSVs) to form a wafer-level second stacking structure (which may be referred to as a wafer-level memory computing chip), wherein the logic wafer includes a plurality of logic chips 70 (furthermore, each logic chip 70 has a computing processor 10).

[0129] The logic chip 70 is generally a large chip with advanced process technology, which has high process requirements and high cost. In the manufacturing method of this embodiment, a first built-in self-test is first performed on the first stacked structure formed by vertically stacking and bonding at least one layer of DRAM chip 40 and buffer chip 100 using a wafer-level buffer chip 100. Only after the test is passed can the logic chip 70 be further vertically stacked and bonded. This can avoid the problem in the prior art of directly bonding DRAM chip 40, buffer chip 100 and logic chip 70 and then performing built-in self-test, which would discover defective chips and lead to the waste of logic chips.

[0130] Optionally, the method for manufacturing the storage computing chip in this embodiment, after bonding the logic chip 70 to form a wafer-level second stacked structure, further includes performing a second built-in self-test on the second stacked structure (i.e., the wafer-level storage computing chip). This second built-in self-test can be implemented using a built-in self-test circuit embedded in the memory controller 30, and the content of the second built-in self-test can be the same as or different from the content of the first built-in self-test.

[0131] Preferably, the content of the second built-in self-test differs from and is less than that of the first built-in self-test, thereby improving testing efficiency and reducing testing costs. For example, the content of the first built-in self-test may include a comprehensive test of the DRAM chip 40 or a comprehensive test of the DRAM chip 40 and a self-test of the buffer chip 100; the content of the second built-in self-test may include testing the communication function between the logic chip 70 and the buffer chip 100, and / or, performing spot checks on the performance parameters of the DRAM chip 40.

[0132] Furthermore, after completing the second built-in self-test, the wafer-level second stacked structure is then diced to obtain several grain-level storage and computing chips.

[0133] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A storage computing chip, characterized in that, It includes logic chips, buffer chips, and at least one layer of DRAM chips stacked vertically in sequence. The logic chips and the buffer chips, as well as the buffer chips and the DRAM chips, are directly connected through through-silicon vias and a hybrid bonding layer. The logic chip includes a computing processor, and the buffer chip internally houses a memory controller and multiple parallel inter-chip communication bus interfaces that communicate with the memory controller. Each inter-chip communication bus interface is connected to the computing processor through several through-silicon vias (TSVs), and the memory controller is connected to the DRAM chip through several TSVs and a hybrid bonding layer. The inter-chip communication bus interface operates at a frequency many times that of the DRAM chip, and its data width is many times that of the DRAM chip's I / O interface. The computing processor's data width is also many times that of the inter-chip communication bus interface. The logic chip directly communicates in parallel with multiple inter-chip communication bus interfaces through the memory controller to call the DRAM chip's I / O interface in parallel, thereby achieving the required bandwidth for communication between the DRAM chip and the logic chip.

2. The storage computing chip as described in claim 1, characterized in that, Each of the inter-chip communication bus interfaces is connected to the computing processor via a plurality of through-silicon vias passing through the first side of the buffer chip, a multilayer hybrid bonding layer, and a plurality of through-silicon vias passing through the first or second side of the logic chip; and / or, The memory controller is connected to the DRAM chip through several through-silicon vias passing through the second side of the buffer chip, a multilayer hybrid bonding layer, and several through-silicon vias passing through the second side of the DRAM chip.

3. The storage computing chip as described in claim 1, characterized in that, The memory controller includes a built-in self-test circuit, used to perform a first built-in self-test on the first stacked structure after the buffer chip and the DRAM chip are stacked, and / or to perform a second built-in self-test on the second stacked structure after the logic chip, the buffer chip and the DRAM chip are stacked. Wherein, the content of the first built-in self-test is the same as the content of the second built-in self-test, or the content of the second built-in self-test is less than the content of the first built-in self-test.

4. The storage computing chip as described in any one of claims 1-3, characterized in that, The memory controller further includes at least one of the following (1) to (7): (1) An address mapping circuit, used to map the address range received by the inter-chip communication bus interface to the DRAM chip; (2) A command arbitration circuit, used to perform priority arbitration on multiple commands sent by the computing processor through the inter-chip communication bus interface; (3) Timing control circuit, used to insert appropriate delays between commands according to the specifications of various timing parameters; (4) A refresh management circuit, used to refresh the DRAM chip according to the refresh command transmitted by the computing processor through the inter-chip communication bus interface; (5) Error detection and correction circuit, used to perform error detection and correction on the data read from the DRAM chip when the computing processor reads data through the inter-chip communication bus interface, and / or to perform error detection and correction on the data written to the DRAM chip when the computing processor writes data through the inter-chip communication bus interface; (6) Temperature detection circuit, used to detect the temperature change of the inter-chip communication bus interface and / or the DRAM chip, and adjust the corresponding parameters according to the temperature change; (7) Power management circuit, used to control the DRAM chip to enter and exit at least one low power mode.

5. The storage computing chip as described in any one of claims 1-3, characterized in that, Each of the inter-chip communication bus interfaces is connected to the computing processor through several through-silicon vias (TSVs) and provides multiple signal channels between the memory controller and the computing processor. Each of the signal channels uses the same handshake mechanism to realize the information transmission between the computing processor and the memory controller.

6. The storage computing chip as described in claim 5, characterized in that, The handshake mechanism uses handshake signals to perform a communication handshake between the computing processor and the memory controller. The plurality of signal channels include: A write data channel is used to transmit multiple bits of data signals from the computing processor to the memory controller after completing the handshake of the handshake signal pairs in its channel; A read data channel is used to transmit the multi-bit data signal from the memory controller to the computing processor after completing the handshake of the handshake signal pairs within its channel; A write address channel is used to transfer a write address from the computing processor to the memory controller after the handshake of the handshake signal pair within the channel is completed; A write response channel is used to transmit a write response signal from the memory controller to the computing processor after completing the handshake of the handshake signal pair within its channel; A read address channel is used to transfer a read address from the computing processor to the memory controller after the handshake of the handshake signal pair in its channel is completed.

7. The storage computing chip as described in claim 6, characterized in that, At least one of the write data channel and the read data channel has a cascaded first register slice and a second register slice. The first register slice is coupled to the computing processor. Both the first register slice and the second register slice have at least one level of data register circuit. Each level of the data register circuit is used to transmit multiple bits of data signal in parallel after completing the handshake of the handshake signal pair in the data channel.

8. The storage computing chip as described in claim 7, characterized in that, The first-level data register circuit in the first register slice with the shortest signal path to the computing processor is removed from the handshake signal pair sent by the computing processor to the first register slice. The remaining data register circuits in the second register slice and / or the first register slice are all driven by the handshake signal pair.

9. The storage computing chip as described in claim 7 or 8, characterized in that, Each stage of the data register circuit includes multiple parallel data register branches, each data register branch is configured to correspond one-to-one with each bit of the data signal, and is driven by the handshake signal pair or one of the handshake signals in the handshake signal pair.

10. The storage computing chip as described in claim 9, characterized in that, Each handshake signal in the handshake signal pair is a one-bit signal, and the handshake signal pair synchronously drives the multiple parallel data register branches corresponding to the same level of the data register circuit.

11. The storage computing chip as described in claim 9, characterized in that, Each of the data register branches includes combinational logic and a one-bit data register coupled to the combinational logic. The handshake signal synchronously drives the combinational logic in the multiple parallel data register branches corresponding to the same level of the data register circuit.

12. The storage computing chip as described in any one of claims 7, 8, and 10-11, characterized in that, The first register slice is a forward register slice, a backward register slice, or a bidirectional register slice, and the second register slice is a forward register slice, a backward register slice, or a bidirectional register slice; wherein, the forward register slice has a forward register circuit, the backward register slice has a backward register circuit, and the bidirectional register slice is composed of a combination of a forward register circuit and a backward register circuit.

13. The storage computing chip as described in claim 12, characterized in that, In the first register slice of the write data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the forward register circuit of the first register slice and is de-driven by the handshake signal sent by the computing processor, so as to be driven only by the handshake signal received by the computing processor. In the first register slice of the read data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the backward register circuit of the first register slice and is de-driven by the handshake signal sent by the computing processor.

14. The storage computing chip as described in any one of claims 6-8, 10-11, and 13, characterized in that, The handshake signal pair includes a valid signal and a ready signal.

15. A method for manufacturing a storage computing chip, characterized in that, Includes the following steps: At least one DRAM wafer and one buffer wafer are provided. The buffer wafer and the DRAM wafer are stacked vertically and hybrid-bonded in sequence to form a first stacked structure. The DRAM wafer and the buffer wafer are directly connected through through-silicon vias and a hybrid bonding layer. Each DRAM wafer includes multiple DRAM chips, and each buffer wafer includes multiple buffer chips. Each buffer chip has a memory controller and an inter-chip communication interface. Perform a first built-in self-test on the first stacked structure; A logic wafer is provided, and the logic wafer is vertically stacked and hybrid-bonded with a first stacked structure that has passed testing to form a second stacked structure, wherein the logic wafer and the buffer wafer are directly connected through through-silicon vias and a hybrid bonding layer, wherein the logic wafer includes multiple logic chips; The second stacked structure is cut to form a storage computing chip.

16. The method for manufacturing a storage computing chip as described in claim 15, characterized in that, Before cutting the second stacked structure, the method further includes: performing a second built-in self-test on the second stacked structure; Wherein, the content of the first built-in self-test is the same as the content of the second built-in self-test, or the content of the second built-in self-test is less than the content of the first built-in self-test.

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