Method and device for reducing error bit digits, storage control chip and storage medium

Abstract

The invention provides a method and device for reducing error bit digits, a storage control chip and a storage medium. The method comprises the following steps: reading a preset offset voltage of the Flash, and obtaining an error bit numerical value matched with the preset offset voltage; performing right offset adjustment on the preset offset voltage according to a first adjustment method to obtain a first offset voltage of which the error bit digit change value exceeds a change threshold; performing left offset adjustment on the preset offset voltage according to a second adjustment method to obtain a second offset voltage of which the error bit digit change value exceeds the change threshold; and obtaining a target offset voltage based on the first offset voltage and the second offset voltage by using a quadratic function characteristic. According to the method, the target offset voltage is obtained according to the obtained first offset voltage and the second offset voltage by utilizing the characteristics of the analogy quadratic function curve, and the target offset voltage can effectively reduce the error bit number of the Flash and ensure the accuracy of Flash read data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Flash, in particular to a method and device for reducing the number of error bits, a storage control chip and a storage medium. BACKGROUND

[0002] NAND Flash (hereinafter referred to as Flash) is a kind of Flash memory, which has the advantages of large capacity and fast rewriting speed, and is suitable for storing a large amount of data, so it has been widely used in the industry.

[0003] Flash is composed of a plurality of storage units. The Flash storing 1 Bit data is called SLC (Single Level Cell); the Flash storing 2 Bit data is called MLC (Multiple Level Cell); the Flash storing 3 Bit data is called TLC (Triple Level Cell); and the Flash storing 4 Bit data is called QLC (Quad Level Cell).

[0004] With the passage of time, the electrons stored in the storage unit will be lost, causing the threshold voltage of the storage unit to change, i.e. to shift. The data stored in the Flash is read by threshold voltage, and if the data is read by the pre-configured threshold voltage, the read data will be incorrect. If the number of storage units with bit flips is too large, the Flash cannot use the ECC error correction performance of the storage control chip to correct the error bits, resulting in data errors. SUMMARY

[0005] The present application aims to overcome the shortcomings of the prior art, and provides a method and device for reducing the number of error bits, a storage control chip and a storage medium, which can obtain a good threshold voltage and ensure the accuracy of Flash data reading.

[0006] The first aspect of the present application provides a method for reducing the number of error bits of Flash, comprising: reading a preset offset voltage of the Flash, and obtaining an error bit value matched with the preset offset voltage; adjusting the preset offset voltage to the right according to a first adjustment method to obtain a first offset voltage whose error bit number change value exceeds a change threshold; adjusting the preset offset voltage to the left according to a second adjustment method to obtain a second offset voltage whose error bit number change value exceeds the change threshold; obtaining a target offset voltage based on the first offset voltage and the second offset voltage using the quadratic function characteristic.

[0007] Further, in one of the preferred embodiments, the right bias adjustment of the preset offset voltage according to the first adjustment method to obtain the first offset voltage with the error bit number change value exceeding the change threshold value comprises: configuring a right bias step size; gradually increasing the preset offset voltage according to the right bias step size, and obtaining an error bit number value matched with the adjusted preset offset voltage; calculating the difference between the error bit number value matched with the adjusted preset offset voltage and the error bit number value matched with the preset offset voltage before adjustment, to obtain a plurality of first difference values; if the absolute value of the first difference value is greater than or equal to the change threshold value, determining that the adjusted preset offset voltage is the first offset voltage.

[0008] Further, in one of the preferred embodiments, the left bias adjustment of the preset offset voltage according to the second adjustment method to obtain the second offset voltage with the error bit number change value exceeding the change threshold value comprises: configuring a left bias step size; gradually decreasing the preset offset voltage according to the left bias step size, and obtaining an error bit number value matched with the adjusted preset offset voltage; calculating the difference between the error bit number value matched with the adjusted preset offset voltage and the error bit number value matched with the preset offset voltage before adjustment, to obtain a plurality of second difference values; if the absolute value of the second difference value is greater than or equal to the change threshold value, determining that the adjusted preset offset voltage is the second offset voltage.

[0009] Further, in one of the preferred embodiments, if the absolute value of the second difference value is greater than or equal to the change threshold value, determining that the adjusted preset offset voltage is the second offset voltage comprises: if the absolute value of the second difference value is greater than or equal to the change threshold value, determining a first objective function with the preset offset voltage before and after adjustment as the base point; determining a second objective function with the error bit number value matched with the first offset voltage; calculating the intersection point of the first objective function and the second objective function; locating the intersection point as a vertical line point on the error bit number curve according to the intersection point as the base point; taking the vertical line point as the second offset voltage.

[0010] The second aspect of the present application provides a device for reducing the error bit number of Flash, comprising: a reading module, configured to read a preset offset voltage of a flash memory and obtain a number of error bits matched with the preset offset voltage; a right offsetting module, configured to right offset the preset offset voltage according to a first adjusting method to obtain a first offset voltage with a number of error bits changing beyond a change threshold; a left offsetting module, configured to left offset the preset offset voltage according to a second adjusting method to obtain a second offset voltage with the number of error bits changing beyond the change threshold; a target module, configured to obtain a target offset voltage based on the first offset voltage and the second offset voltage by using a quadratic function characteristic.

[0011] Further, in one of the preferred embodiments, the right offsetting module comprises: a first step length unit, configured to configure a right offset step length; a right adjusting unit, configured to gradually increase the preset offset voltage according to the right offset step length and obtain a number of error bits matched with the adjusted preset offset voltage; a first calculating unit, configured to calculate a difference between the number of error bits matched with the adjusted preset offset voltage and the number of error bits matched with the preset offset voltage before adjustment to obtain a plurality of first difference values; a first target unit, configured to determine that the adjusted preset offset voltage is the first offset voltage if an absolute value of the first difference value is greater than or equal to a change threshold.

[0012] Further, in one of the preferred embodiments, the left offsetting module comprises: a second step length unit, configured to configure a left offset step length; a left adjusting unit, configured to gradually decrease the preset offset voltage according to the left offset step length and obtain a number of error bits matched with the adjusted preset offset voltage; a second calculating unit, configured to calculate a difference between the number of error bits matched with the adjusted preset offset voltage and the number of error bits matched with the preset offset voltage before adjustment to obtain a plurality of second difference values; a second target unit, configured to determine that the adjusted preset offset voltage is the second offset voltage if an absolute value of the second difference value is greater than or equal to a change threshold.

[0013] Further, in one of the preferred embodiments, the second target unit a first function subunit, configured to determine a first target function by taking the preset offset voltage before and after adjustment as a base point if the absolute value of the second difference value is greater than or equal to the change threshold. a second function sub-unit configured to determine a second target function according to the error bit number value matched with the first offset voltage; an intersection calculating sub-unit configured to calculate an intersection point of the first target function and the second target function; a projecting sub-unit configured to locate a perpendicular point of the intersection point on the error bit number curve according to the intersection point as a base point; a confirming sub-unit configured to confirm the perpendicular point as a second offset voltage.

[0014] A third aspect of the present application provides a storage control chip, comprising the error bit number reducing device as described above.

[0015] A fourth aspect of the present application provides a computer readable storage medium, which stores executable codes, when the executable codes are executed by a processor of an electronic device, the processor executes the error bit number reducing method as described above.

[0016] The technical solution of the present application comprises: reading a preset offset voltage of a Flash, and obtaining an error bit number value matched with the preset offset voltage; adjusting the preset offset voltage to the right according to a first adjustment method, and obtaining a first offset voltage with an error bit number change value exceeding a change threshold; adjusting the preset offset voltage to the left according to a second adjustment method, and obtaining a second offset voltage with an error bit number change value exceeding the change threshold; and obtaining a target offset voltage based on the first offset voltage and the second offset voltage by using the quadratic function characteristic. According to the first offset voltage and the second offset voltage, the target offset voltage is obtained by using the relationship between the Flash error bit number and the offset voltage point, which is similar to the characteristics of the quadratic function curve, and the target offset voltage can effectively reduce the Flash error bit number and ensure the accuracy of Flash data reading. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0018] Figure 1 is a flowchart of the error bit number reducing method according to an embodiment of the present application; Figure 2 is a structural diagram of the error bit number reducing device according to an embodiment of the present application; Figure 3Fig. 1 shows a structural diagram of a storage control chip according to an embodiment of the present application; Figure 4 Fig. 2 shows a structural diagram of an electronic device according to an embodiment of the present application; Figure 5 Fig. 3 shows a curve diagram of the relationship between the offset voltage and the number of error bits. DETAILED DESCRIPTION

[0019] For the purpose of clarity, the present application will be described in more detail with reference to the accompanying drawings in which the preferred embodiments of the present application are shown. The present application may, however, be carried out in many different ways and the embodiments described below are merely illustrative of the principles of the present application.

[0020] It should be noted that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present. The terms "vertical", "horizontal", "left", "right", and the like as used herein are used for illustration only and are not intended to limit the present application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0022] In the related art, over time, the electrons stored in the storage unit will flow out, causing the threshold voltage of the storage unit to change, i.e., to be offset. The data stored in the flash memory particles is read by using the threshold voltage, and if the data is read by using the pre-configured threshold voltage, the read data will be incorrect. If the number of storage units that have bit flips is too large, the flash cannot use the ECC error correction performance of the storage control chip to correct the error bits, causing data errors.

[0023] Therefore, in order to solve the above technical problems, the present application provides a method for reducing the number of error bits, which can obtain a good threshold voltage and ensure the accuracy of the flash data reading.

[0024] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1The diagram shown is a flowchart illustrating a method for reducing the number of error bits in one embodiment of this application.

[0026] Please see Figure 1 A method for reducing the number of error bits includes the following steps: Step S110: Read the preset offset voltage of Flash and obtain the error bit value that matches the preset offset voltage.

[0027] Threshold voltage is a key parameter that determines the state of a Flash memory cell. When the memory controller chip sends a read command to the Flash, the Flash needs to perform a read operation based on the pre-configured threshold voltage. Different threshold voltages will result in different data being read from the memory cell.

[0028] The offset voltage is used to adjust the threshold voltage. Adjustments to the threshold voltage are made by configuring the offset voltage. It's understood that the offset voltage can be positive or negative. A positive offset voltage indicates an increase in the threshold voltage for data reading; a negative offset voltage indicates a decrease in the threshold voltage for data reading. The relationship between the threshold voltage and the offset voltage is shown in Equation 1).

[0029] Adjusted threshold voltage V th =Threshold voltage V before adjustment th +Offset voltage V off 1) like Figure 5 The diagram shows the relationship between offset voltage and the number of error bits in Flash memory. Figure 5 The horizontal axis represents different offset voltages, and the vertical axis represents the number of error bits. According to... Figure 5 As can be seen, the relationship curve between the two is analogous to a quadratic function curve, with the lowest point of the curve representing the lowest number of error bits, and the curve exhibits symmetry. It should be noted that this symmetry refers to the overall similarity in the changing trends on both sides of the curve. When the threshold voltage is continuously increased during data reading, the change in the number of error bits gradually flattens out; similarly, when the threshold voltage is continuously decreased during data reading, the change in the number of error bits also gradually flattens out. More importantly, there is a voltage point on each side of the curve where the change in the number of error bits is most pronounced (i.e., the point with the steepest slope; these two points exhibit symmetry). These curve characteristics are maintained even after the Flash memory undergoes high-temperature aging treatment. Figure 5The curve shown is the curve after high-temperature aging treatment (the curve has shifted to the left). The difference lies in the fact that the shift means the originally configured threshold voltage may no longer be the optimal voltage reading point. The technical problem to be solved by the technical solution of this embodiment is to obtain this voltage reading point. Combining the relationship curve between offset voltage and number of error bits with the characteristics of a quadratic function curve, in this embodiment, we can first find the points on both sides of the curve where the change in the number of error bits is most significant, and then use these two points on both sides where the change in the number of error bits is most significant to obtain the lowest point of the curve, that is: X T = (X R +X L ) / twenty two) It should be noted that, as Figure 5 Point T shown is the target point, "X" T "X" represents the x-coordinate of the target point, i.e., the offset voltage value; R That is, the point on the right side of the curve where the change in the number of error bits is most obvious; X L That is, the point on the left side of the curve where the change in the number of error bits is most obvious.

[0030] In this embodiment, the preset offset voltage of the Flash memory is read. The preset offset voltage is pre-configured, and for most Flash memory, the voltage value at this point is usually 0V (e.g., ...). Figure 5 Point A shown is the lowest point of the curve when there is no offset, meaning that the threshold voltage was not adjusted and the Flash data read operation was completed using the factory-configured threshold voltage. It is also important to note that both the threshold voltage and the offset voltage are expressed in hexadecimal notation internally in the Flash memory. The corresponding error bit value can be obtained based on the preset offset voltage.

[0031] Step S120: Adjust the preset offset voltage to the right according to the first adjustment method to obtain a first offset voltage where the change in the number of error bits exceeds the change threshold.

[0032] It should be noted that in this embodiment, the following steps are used to obtain the first offset voltage: 1) Configure the right offset step size; 2) Gradually increase the preset offset voltage according to the right offset step size, and obtain the error bit value that matches the adjusted preset offset voltage; 3) Calculate the difference between the error bit value that matches the adjusted preset offset voltage and the error bit value that matches the original preset offset voltage, and obtain several first differences; 4) If the absolute value of the first difference is greater than or equal to the change threshold, then the adjusted preset offset voltage is determined to be the first offset voltage.

[0033] A right bias step, i.e. a voltage value of each adjustment of the preset offset voltage (the value of the right bias step is configured according to specific conditions, which is not specifically limited here). In this embodiment, the threshold voltage is adjusted by continuously increasing the preset offset voltage, and the number of error bits matched with the adjusted preset offset voltage (which is equivalent to the number of error bits matched with the adjusted threshold voltage) is obtained.

[0034] In order to better understand the technical principle of the first adjustment method of the present embodiment, the following specific cases listed in Table 1 are described.

[0035] Right bias frequency Right bias step Pre-set offset voltage Threshold voltage before adjustment Threshold voltage after adjustment Error bit number 0 0.1V 0V 2.0V 2.0V 20 Bit 1 0.1V 0.1V 2.0V 2.1V 22 Bit 2 0.1V 0.2V 2.1V 2.2V 28 Bit 3 0.1V 0.3V 2.2V 2.3V 32 Bit 4 0.1V 0.4V 2.3V 2.4V 40 Bit 5 0.1V 0.5V 2.4V 2.5V 70 Bit Table 1 According to the cases in Table 1, the threshold voltage is adjusted a total of 5 times, each time increasing the threshold voltage by 0.1V, and each threshold voltage has a number of error bits matched therewith. Subsequently, the difference between the number of error bits matched with the adjusted preset offset voltage and the number of error bits matched with the preset offset voltage before adjustment is calculated, and a plurality of first differences are obtained, as shown in Table 2.

[0036] Right bias frequency First difference value 1 2 Bit 2 6 Bit 3 4 Bit 4 8 Bit 5 30 Bit Table 2 It can be understood that the number of error bits of the Flash changes each time the threshold voltage is adjusted. It is determined whether the absolute value of the first difference is greater than or equal to the change threshold value. If yes, it is determined that the adjusted preset offset voltage is the first offset voltage; if no, the right bias step is reconfigured, and the first offset voltage is located using steps 1) ~ 4). It should be noted that in this embodiment, the change threshold value is configured to be 20 Bit, and the value of the change threshold value can be set according to the specific conditions of the Flash. In addition, due to the limited hardware computing power, it is impossible to adjust the threshold voltage to the right without cost, and in this embodiment, when the right bias number reaches 200 times without locating the first offset voltage, it is determined that the right bias step is misconfigured, and the right bias step needs to be reconfigured. The maximum right bias number is configured to prevent falling into a dead loop and to prevent the best threshold voltage from being obtained.

[0037] After judgment, when the fifth right bias adjustment is performed, the first difference (30 Bit) is greater than the change threshold value (20 Bit), which meets the condition, and the preset offset voltage (0.5V) after the fifth right bias adjustment is locked as the first offset voltage. According to the first offset voltage, the threshold voltage (2.5V) is obtained, which is the right side point at which the number of error bits of the Flash changes most obviously during right bias adjustment (such as point B shown in Figure 5

[0038] ​Step S130, adjusting the preset offset voltage left according to the second adjustment method to obtain the second offset voltage whose error bit number change value exceeds the change threshold.

[0039] It should be noted that, by the same reason, the second adjustment method with the same principle as the first adjustment method is used to obtain the second offset voltage, and the steps are as follows: 5) configuring the left bias step; 6) gradually reducing the preset offset voltage according to the left bias step, and obtaining the error bit number value matched with the adjusted preset offset voltage; 7) calculating the difference between the error bit number value matched with the adjusted preset offset voltage and the error bit number value matched with the preset offset voltage before adjustment, to obtain a plurality of second difference values; 8) if the absolute value of the second difference value is greater than or equal to the change threshold, it is determined that the adjusted preset offset voltage is the second offset voltage.

[0040] The left bias step, that is, the voltage value of the preset offset voltage adjusted each time (the value of the left bias step is configured according to specific circumstances, which is not limited here). In this embodiment, the threshold voltage is adjusted by continuously reducing the preset offset voltage, and the error bit number value matched with the adjusted preset offset voltage (which is equivalent to the error bit number value matched with the adjusted threshold voltage) is obtained.

[0041] Please explain in combination with the specific cases listed in Table 3.

[0042] Left bias frequency Left bias step Pre-set offset voltage Threshold voltage before adjustment Threshold voltage after adjustment Error bit number 0 0.2V 0V 2.0V 2.0V 22 Bit 1 0.2V -0.2V 2.0V 1.8V 25 Bit 2 0.2V -0.4V 1.8V 1.6V 28 Bit 3 0.2V -0.6V 1.6V 1.4V 34 Bit 4 0.2V -0.8V 1.4V 1.2V 39 Bit 5 0.2V -1.0V 1.2V 1.0V 71 Bit Table 3 According to the cases in Table 3, the threshold voltage is adjusted a total of 5 times, each time reducing the threshold voltage by 0.1V, and each threshold voltage has a matched error bit number. Then, the difference between the error bit number value matched with the adjusted preset offset voltage and the error bit number value matched with the preset offset voltage before adjustment is calculated, to obtain a plurality of second difference values, as shown in Table 4.

[0043] Left bias frequency Second difference value 1 3 Bit 2 3 Bit 3 6 Bit 4 5 Bit 5 31 Bit Table 4 It can be understood that, as with the right bias adjustment, the number of error bits of the Flash changes each time the threshold voltage is adjusted. If it is determined that the absolute value of the second difference is greater than or equal to the change threshold, it is determined that the adjusted preset offset voltage is the second offset voltage; if not, the right bias step is reconfigured, and steps 5) to 8) are continued to locate the second offset voltage. In addition, the number of left bias adjustments should be the same as the number of right bias adjustments, and the left bias adjustment cannot be unlimited. In the embodiment, when the number of left bias adjustments reaches 200 times and the second offset voltage is not located, it is determined that the left bias step is misconfigured, the left bias step is reconfigured, and steps 5) to 8) are re-executed according to the newly configured left bias step. The purpose of configuring the maximum number of left bias adjustments is also to prevent falling into a dead loop and ultimately failing to obtain the optimal threshold voltage.

[0044] It is determined that when the fifth left bias adjustment is performed, the second difference (31Bit) is greater than the change threshold (20Bit), which meets the condition, and the preset offset voltage (0.5V) after the fifth left bias adjustment is locked as the second offset voltage. According to the second offset voltage, the threshold voltage (1.5V) is obtained, which is the leftmost point at which the number of error bits of the Flash changes most obviously during left bias adjustment (for example, the D point shown in Figure 5 ).

[0045] In step S140, the target offset voltage is obtained based on the first offset voltage and the second offset voltage by using the quadratic function characteristic.

[0046] It should be noted that the first target offset voltage is obtained by the first adjustment method, and the second target offset voltage is obtained by the second adjustment method. By using the quadratic function characteristic, that is, formula 2), the target offset voltage (for example, the K point shown in Figure 5 ) can be obtained.

[0047] X T = (0.5+-1.0) / 2 =-0.25V X T is substituted into formula 1), the adjusted threshold voltage V th = 2.0-0.25 = 1.75V, which can ensure the accuracy of the Flash data reading operation.

[0048] According to the first offset voltage and the second offset voltage, the target offset voltage is obtained by using the relationship between the number of error bits of the Flash and the offset voltage point, which is similar to the characteristics of the quadratic function curve, the target offset voltage can effectively reduce the number of error bits of the Flash, and ensure the accuracy of the Flash data reading operation.

[0049] Further, as a preferred embodiment, the second target offset voltage is obtained by using the second adjusting method, which comprises the following steps: 9) configuring a left offset step; 10) gradually reducing the preset offset voltage according to the left offset step, and obtaining the error bit number matched with the adjusted preset offset voltage; 11) calculating the difference between the error bit number matched with the adjusted preset offset voltage and the error bit number matched with the unadjusted preset offset voltage, and obtaining a plurality of second differences; 12) if the absolute value of the second difference is greater than or equal to a change threshold, taking the preset offset voltage before and after the adjustment as the base point to determine the first target function; 13) taking the error bit number matched with the first offset voltage to determine the second target function; 14) calculating the intersection point of the first target function and the second target function; 15) locating the vertical point of the intersection point on the error bit number curve according to the intersection point as the base point; and 16) taking the vertical point as the second offset voltage.

[0050] It should be noted that in the present embodiment, the principles of steps 9) to 11) are the same as those of steps 5) to 7), and the principles will not be described herein. The difference lies in steps 12) to 16). As can be seen from the relationship curve between the offset voltage and the error bit number, the curve has symmetry. When the first offset voltage is obtained by using the first adjusting method, according to the symmetry characteristics of the curve, the second offset voltage should have high symmetry with the first offset voltage. However, the right offset step and the left offset step can be different, and the second offset voltage can deviate from the symmetric point of the first offset voltage by a certain distance, that is, the obtained second offset voltage can not have high symmetry with the first target offset voltage.

[0051] Therefore, in order to eliminate this error, when it is determined that the absolute value of the second difference is greater than or equal to the change threshold, the preset offset voltage before and after the adjustment is taken as the base point to determine the first target function, that is, the threshold voltages before and after the adjustment of the 5th left offset number shown in Table 3 are two points (1.2, 39) and (1.0, 71), and the first target function Y=KX+b can be determined according to the two points, as shown in FIG. 4. The first target function is a linear function, and the corresponding image is a straight line. Figure 5 As shown in FIG. 5, the second target function is a constant function, and the corresponding image is also a straight line perpendicular to the Y axis. The intersection point of the two target functions is calculated, and the intersection point is taken as the base point to locate the vertical point of the intersection point on the error bit number curve (such as point E shown in FIG. 6), and the vertical point is taken as the second offset voltage. Figure 5 As shown in FIG. 5, the second target function is a constant function, and the corresponding image is also a straight line perpendicular to the Y axis. The intersection point of the two target functions is calculated, and the intersection point is taken as the base point to locate the vertical point of the intersection point on the error bit number curve (such as point E shown in FIG. 6), and the vertical point is taken as the second offset voltage. Figure 5

[0052] ​The embodiment first determines a target interval range in which the second offset voltage is located, and finds the second offset voltage in the target interval range according to the symmetry of the curve, taking the first offset voltage as a symmetric reference point. Compared with directly taking the preset offset voltage after adjustment as the second offset voltage, the second offset voltage obtained by the embodiment has high symmetry with the first offset voltage, and can infinitely approach the symmetric reference point of the first offset voltage. Finally, the target offset voltage is obtained according to the first offset voltage (point B) and the second offset voltage (point E).

[0053] It should be noted that, as Figure 5 shown, the T point and the K point, the T point relative to the K point, the corresponding error bit number is less, is closer to the lowest point of the curve, which is derived from the T point is obtained by B point and E point, and E point is obtained based on B point as a symmetric reference point, the two points have high symmetry on the curve, which can eliminate the result error caused by the different right and left step lengths or the different right and left times, which proves that the error can be eliminated by steps 9) ~ 16), and the target offset voltage closer to the lowest point of the curve can be obtained.

[0054] Corresponding to the foregoing method embodiment, the application also provides a device for reducing error bit number and corresponding embodiments.

[0055] Figure 2 The structure of the device for reducing error bit number in the embodiment of the application is shown.

[0056] Please refer to Figure 2 , a device for reducing error bit number 200, comprising: a reading module 210, a right biasing module 220, a left biasing module 230 and a target module 240. Wherein: The reading module 210 is used for reading the preset offset voltage of the Flash, and obtaining the error bit number value matched with the preset offset voltage.

[0057] The right biasing module 220 is used for right bias adjustment of the preset offset voltage according to the first adjustment method, to obtain the first offset voltage whose error bit number change value exceeds the change threshold.

[0058] The left biasing module 230 is used for left bias adjustment of the preset offset voltage according to the second adjustment method, to obtain the second offset voltage whose error bit number change value exceeds the change threshold.

[0059] The target module 240 is used for obtaining the target offset voltage based on the first offset voltage and the second offset voltage by using the quadratic function characteristic.

[0060] Further, please refer to Figure 2In one preferred embodiment, the right biasing module 220 comprises a first step unit 221, a right adjusting unit 222, a first calculating unit 223 and a first target unit 224. In which: The first step unit 221 is configured to configure a right bias step.

[0061] The right adjusting unit 222 is configured to gradually increase the preset offset voltage according to the right bias step, and obtain the error bit value matched with the adjusted preset offset voltage.

[0062] The first calculating unit 223 is configured to calculate the difference between the error bit value matched with the adjusted preset offset voltage and the error bit value matched with the unadjusted preset offset voltage, and obtain a plurality of first difference values.

[0063] The first target unit 224 is configured to determine that the adjusted preset offset voltage is the first offset voltage if the absolute value of the first difference value is greater than or equal to a change threshold.

[0064] Further, please refer to Figure 2 In one preferred embodiment, the left biasing module 230 comprises a second step unit 231, a left adjusting unit 232, a second calculating unit 233 and a second target unit 234. In which: The second step unit 231 is configured to configure a left bias step.

[0065] The left adjusting unit 232 is configured to gradually decrease the preset offset voltage according to the left bias step, and obtain the error bit value matched with the adjusted preset offset voltage.

[0066] The second calculating unit 233 is configured to calculate the difference between the error bit value matched with the adjusted preset offset voltage and the error bit value matched with the unadjusted preset offset voltage, and obtain a plurality of second difference values.

[0067] The second target unit 234 is configured to determine that the adjusted preset offset voltage is the second offset voltage if the absolute value of the second difference value is greater than or equal to a change threshold.

[0068] Further, please refer to Figure 2 In one preferred embodiment, the second target unit 234 comprises a first function sub-unit 2341, a second function sub-unit 2342, an intersection calculating sub-unit 2343, a projection sub-unit 2344 and a confirmation sub-unit 2345. In which: The first function sub-unit 2341 is configured to determine the first target function by taking the preset offset voltage before and after adjustment as the base point if the absolute value of the second difference value is greater than or equal to a change threshold.

[0069] The second function sub-unit 2342 is configured to determine the second target function according to the error bit number matching the first offset voltage.

[0070] The intersection calculation sub-unit 2343 is configured to calculate the intersection of the first target function and the second target function.

[0071] The projection sub-unit 2344 is configured to locate the vertical point of the error bit number curve according to the intersection as the base point.

[0072] The confirmation sub-unit 2345 is configured to take the vertical point as the second offset voltage.

[0073] As shown in Figure 3 Fig. 1 shows a structure diagram of a storage control chip according to an embodiment of the present application.

[0074] Referring to Fig. 3, a storage control chip 300 includes the error bit number reducing device 200.

[0075] According to the first offset voltage and the second offset voltage, the present application uses the relationship between the Flash error bit number and the offset voltage point to analog the characteristics of the quadratic function curve, and obtains the target offset voltage. The target offset voltage can effectively reduce the Flash error bit number and ensure the accuracy of the Flash data reading.

[0076] Referring to Figure 4 Fig. 4 shows a computing electronic device 400 according to another embodiment of the present application, which includes a processor 410 and a memory 420.

[0077] The processor 410 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0078] The general-purpose processor can be a microprocessor or any conventional processor. The memory 410 can include various types of storage units, such as system memory, read-only memory (ROM) and permanent storage device.

[0079] The ROM can store static data and instructions that are needed by the processor 420 or other modules of the computer. The permanent storage device can be a read-only memory, a flash memory or a hard disk. In some embodiments, the permanent storage device can be a non-volatile memory, which can retain stored instructions and data even when the computer is powered off.

[0080] In some other embodiments, the permanent storage device can be a removable storage device (e.g., a floppy disk, a compact disk, an optical disk, etc.). The system memory can be a read-and-write memory device or a volatile read-and-write memory device, such as a dynamic random access memory. The system memory can store some or all of the instructions and data that the processor needs at runtime.

[0081] In addition, the memory 420 can include a combination of any or all of the above, including various types of semiconductor-based memory chips (e.g., DRAM, SRAM, SDRAM, flash, programmable read-only memory), magnetic disks and / or optical disks.

[0082] In some embodiments, the memory 420 can include a removable storage device, such as a compact disk (CD), a read-only digital versatile disk (e.g., DVD-ROM, dual-layer DVD-ROM), a read-only Blu-ray disk, an ultra-density disk, a flash memory card (e.g., SD card, min SD card, and Micro-SD card, etc.), a magnetic floppy disk, etc. The computer readable storage media does not include carrier waves and transitory electronic signals propagating wirelessly or over wired connections. The memory 420 stores executable code that, when executed by the processor 410, can cause the processor 410 to perform some or all of the steps described above.

[0083] In addition, the method according to the present application can also be implemented as a computer program or a computer program product, which includes computer program code instructions for performing some or all of the steps of the above-mentioned method according to the present application.

[0084] Alternatively, the present application can also be implemented as a computer readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium) having stored thereon executable code (or computer program or computer instruction code), which, when executed by an electronic device (or a server, etc.), can cause the processor to perform some or all of the steps of the above-mentioned method according to the present application.

[0085] Having described various embodiments of the application, it is to be understood that the above description is meant to be illustrative only, and that many modifications and variations of the embodiments described herein are possible. It is therefore to be understood that within the scope of the appended claims, and their equivalents, many alternatives to the embodiments described herein are possible. The selection of terms to be used in the description is not intended to limit the scope of the embodiments described herein, but rather to best explain the principles of the embodiments, practical application, or improvement over the technology in the art, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method of reducing the number of error bits, comprising: The method comprises the following steps: reading a preset offset voltage of a flash memory and obtaining an error bit value matched with the preset offset voltage; adjusting the preset offset voltage to the right according to a first adjustment method to obtain a first offset voltage with an error bit value change value exceeding a change threshold value; adjusting the preset offset voltage to the left according to a second adjustment method to obtain a second offset voltage with an error bit value change value exceeding the change threshold value; obtaining a target offset voltage based on the first offset voltage and the second offset voltage by using a quadratic function characteristic.

2. The method for reducing the number of error bits according to claim 1, wherein, The step of adjusting the preset offset voltage to the right according to the first adjustment method to obtain the first offset voltage with the error bit value change value exceeding the change threshold value comprises the following steps: configuring a right offset step; gradually increasing the preset offset voltage according to the right offset step and obtaining an error bit value matched with the adjusted preset offset voltage; calculating a difference value between the error bit value matched with the adjusted preset offset voltage and the error bit value matched with the unadjusted preset offset voltage to obtain a plurality of first difference values; if the absolute value of the first difference value is greater than or equal to the change threshold value, determining that the adjusted preset offset voltage is the first offset voltage.

3. The method of claim 2, wherein, The step of adjusting the preset offset voltage to the left according to the second adjustment method to obtain the second offset voltage with the error bit value change value exceeding the change threshold value comprises the following steps: configuring a left offset step; gradually decreasing the preset offset voltage according to the left offset step and obtaining an error bit value matched with the adjusted preset offset voltage; calculating a difference value between the error bit value matched with the adjusted preset offset voltage and the error bit value matched with the unadjusted preset offset voltage to obtain a plurality of second difference values; if the absolute value of the second difference value is greater than or equal to the change threshold value, determining that the adjusted preset offset voltage is the second offset voltage.

4. The method for reducing the number of error bits according to claim 3, wherein, The step of determining that the adjusted preset offset voltage is the second offset voltage if the absolute value of the second difference value is greater than or equal to the change threshold value comprises the following steps: if the absolute value of the second difference value is greater than or equal to the change threshold value, taking the preset offset voltage before and after the adjustment as a base point to determine a first target function; determining a second target function based on the error bit value matched with the first offset voltage; calculating an intersection point of the first target function and the second target function; positioning the intersection point as a perpendicular point of the error bit value on a curve based on the intersection point as a base point; taking the perpendicular point as the second offset voltage.

5. An apparatus for reducing the number of error bits, comprising: The method comprises the following steps: a reading module, configured to read a preset offset voltage of a flash memory and obtain an error bit value matched with the preset offset voltage; a right offset module, configured to adjust the preset offset voltage to the right according to a first adjustment method to obtain a first offset voltage with an error bit value change value exceeding a change threshold value; a left offset module, configured to adjust the preset offset voltage to the left according to a second adjustment method to obtain a second offset voltage with an error bit value change value exceeding the change threshold value; and a target offset voltage obtaining module, configured to obtain a target offset voltage based on the first offset voltage and the second offset voltage by using a quadratic function characteristic. The target module is configured to obtain a target offset voltage based on the first offset voltage and the second offset voltage by using a quadratic function characteristic.

6. The apparatus of claim 5, wherein, The right offsetting module comprises: The first step length unit is configured to configure a right offset step length. The right adjusting unit is configured to gradually increase the preset offset voltage according to the right offset step length, and obtain an error bit number value matched with the adjusted preset offset voltage. The first calculating unit is configured to calculate a difference between the error bit number value matched with the adjusted preset offset voltage and the error bit number value matched with the unadjusted preset offset voltage, and obtain a plurality of first difference values. The first target unit is configured to determine that the adjusted preset offset voltage is the first offset voltage if an absolute value of the first difference value is greater than or equal to a change threshold.

7. The apparatus of claim 6, wherein, The left offsetting module comprises: The second step length unit is configured to configure a left offset step length. The left adjusting unit is configured to gradually decrease the preset offset voltage according to the left offset step length, and obtain an error bit number value matched with the adjusted preset offset voltage. The second calculating unit is configured to calculate a difference between the error bit number value matched with the adjusted preset offset voltage and the error bit number value matched with the unadjusted preset offset voltage, and obtain a plurality of second difference values. The second target unit is configured to determine that the adjusted preset offset voltage is the second offset voltage if an absolute value of the second difference value is greater than or equal to a change threshold.

8. The apparatus of claim 7, wherein, The second target unit comprises: The first function subunit is configured to determine a first target function by taking the preset offset voltage before and after adjustment as a base point if the absolute value of the second difference value is greater than or equal to the change threshold. The second function subunit is configured to determine a second target function by taking the error bit number value matched with the first offset voltage. The intersection calculating subunit is configured to calculate an intersection point of the first target function and the second target function. The projection subunit is configured to locate the intersection point as a perpendicular point of the error bit number curve according to the intersection point as a base point. The confirmation subunit is configured to take the perpendicular point as the second offset voltage.

9. A memory control chip, comprising: The error bit number reduction device of any one of claims 5-8.

10. A computer-readable storage medium, characterized in that, The error bit number reduction device of any one of claims 5-8. The error bit number reduction device of any one of claims 5-8.

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