Method, device and equipment for determining diffusion coefficient of reaction gas

Abstract

The invention discloses a reaction gas diffusion coefficient determination method, device and equipment, relates to the field of integrated circuit manufacturing, and is used for solving the problem of low accuracy of a transverse deposition process simulation model of a GAA inner side wall cavity structure in the prior art. Comprising the following steps: extracting a target contour corresponding to a laminated structure of a to-be-deposited gate-all-around transistor; calculating geometric data of a target contour based on a target function in the image processing library; in combination with the geometric data of the target contour and a reaction gas diffusion coefficient calculation formula, the reaction gas diffusion coefficient of the gate-all-around transistor under the current deposition time is calculated; and iteratively updating the structure information of the to-be-deposited gate-all-around transistor according to the deposition time, and iteratively calculating a reaction gas diffusion coefficient to obtain a target reaction gas diffusion coefficient of the reaction gas in the cavity structure of the gate-all-around transistor at different deposition time.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing, and in particular to a reaction gas diffusion coefficient determination method, device and equipment. BACKGROUND

[0002] When the technology node of integrated circuit manufacturing process steps into 7nm and below, the device structure of advanced technology node of logic device gradually develops to Gate-all-around (GAA) structure, and the etching and deposition processes of GAA inner spacer cavity structure have obvious influence on device performance, and the experiment difficulty and cost are extremely high, so it is urgent to simulate the etching and deposition processes of GAA inner spacer cavity structure to assist its development. The model of GAA inner spacer cavity structure lateral deposition modeling mainly includes: diffusion-reaction model, Monte Carlo model and ballistic transport model. The diffusion-reaction model has the advantages of calculation efficiency and simulation accuracy, however, when the diffusion-reaction model is used to model the lateral deposition process of GAA inner spacer cavity structure, the diffusion of reaction gas in GAA structure is an important part of model establishment. When analyzing the diffusion distribution of reaction gas in GAA inner spacer cavity structure, the accurate solution of diffusion coefficient of reaction gas molecules in cavity is the key. In the GAA inner spacer cavity structure, the diffusion coefficient of reaction gas molecules is not only affected by the process conditions, but also closely related to the structure parameters of GAA stack (SiGe layer thickness, cavity depth). When modeling the lateral deposition of GAA inner spacer cavity structure, how to calculate the diffusion coefficient of reaction gas under different process conditions and different GAA transistor parameters is one of the main problems faced in deposition simulation modeling.

[0003] Therefore, it is urgent to provide a more reliable reaction gas diffusion coefficient determination scheme suitable for deposition modeling of GAA transistor structure. SUMMARY

[0004] The purpose of the present application is to provide a reaction gas diffusion coefficient determination method, device and equipment, which solves the problem of low accuracy of the lateral deposition process simulation model of GAA inner spacer cavity structure in the prior art.

[0005] In order to achieve the above-mentioned purpose, the present application provides the following technical scheme: In a first aspect, the present application provides a reaction gas diffusion coefficient determination method, which comprises: extracting a target contour corresponding to a stack structure of a to-be-deposited GAA transistor; calculating the geometric data of the target contour based on a target function in an image processing library; combined with the geometric data of the target contour and a reaction gas diffusion coefficient calculation formula, a reaction gas diffusion coefficient of the ring gate transistor at the current deposition time is calculated; According to the deposition time, the structure information of the ring gate transistor to be deposited is iteratively updated, the reaction gas diffusion coefficient is iteratively calculated, and the target reaction gas diffusion coefficient of the reaction gas in the cavity structure of the ring gate transistor at different deposition times is obtained.

[0006] Optionally, the target contour of the stacked structure of the ring gate transistor to be deposited is extracted, including: In an advanced process node, the stacked structure of the ring gate transistor to be deposited is input, and the substrate structure format at least includes an electron microscope picture, a layout, and a custom structure; Based on the image processing library, the input ring gate transistor to be deposited is subjected to grayscale and binary processing to obtain processed data; The target contour of the ring gate transistor to be deposited after processing is extracted from the processed data.

[0007] Optionally, the geometric data of the target contour is calculated based on a target function in the image processing library, including: The target function is selected from the image processing library; the target function at least includes a contour perimeter calculation function and a contour area calculation function; The contour perimeter calculation function and the contour area calculation function are used to calculate the perimeter of the target contour and the area surrounded by the target contour.

[0008] Optionally, combined with the geometric data of the target contour and a reaction gas diffusion coefficient calculation formula, a reaction gas diffusion coefficient of the ring gate transistor at the current deposition time is calculated, including: If the reaction gas under the current substrate structure is a monatomic gas, based on the perimeter and the area of the target contour, the formula is: The first diffusion coefficient of the first reaction gas under the current substrate structure is calculated; wherein, Kn represents the Knudsen diffusion coefficient of the first reaction gas, D represents the molecular diffusion coefficient of the first reaction gas, D represents the first diffusion coefficient, A represents the area of the target contour, L represents the perimeter of the target contour, B represents the Boltzmann constant, N represents the Avogadro constant, P represents the process pressure, and T represents the process temperature. represents the molar mass of the first reaction gas molecule, represents the molecular diameter of the first reaction gas.

[0009] Optionally, the reaction gas diffusion coefficient of the ring gate transistor at the current deposition time is calculated by combining the geometric data of the target profile and the reaction gas diffusion coefficient calculation formula, including: If the reaction gas under the current substrate structure is a binary gas mixture, then based on the circumference and the area of the target profile, the formula is used: calculating the second diffusion coefficient of the reaction gas under the current substrate structure; the binary gas mixture includes a first reaction gas and a second reaction gas; wherein, represents the molecular diffusion coefficient of the first reaction gas in the binary gas mixture, represents the second diffusion coefficient, represents the molar mass of the second reaction gas molecule, represents the molecular diameter of the second reaction gas.

[0010] Optionally, the structure information of the ring gate transistor to be deposited is iteratively updated according to the deposition time, and the reaction gas diffusion coefficient is iteratively calculated to obtain the target reaction gas diffusion coefficient of the ring gate transistor in the cavity structure of the ring gate transistor under different deposition times, including: In each time step, the profile of the deposited ring gate transistor is extracted; the surface topography of the ring gate transistor structure changes as the lateral deposition of the cavity structure of the ring gate transistor progresses; The profile circumference and area are recalculated, and the diffusion coefficient is calculated according to the process conditions to obtain the diffusion coefficient of the reaction gas in the cavity structure of the ring gate transistor under the current deposition time under the corresponding process conditions; Based on the diffusion coefficient, the gas flow spatial distribution and the deposition rate are updated to realize the iterative evolution of thin film growth.

[0011] Optionally, based on the diffusion coefficient, the gas flow spatial distribution and the deposition rate are updated to realize the iterative evolution of thin film growth, including: The flux values of the reaction gas at different deposition times in the cavity structure of the ring gate transistor at each reaction site are calculated; Based on the flux values, the deposition rates at the corresponding positions are calculated in turn.

[0012] Compared with the prior art, the reaction gas diffusion coefficient determination method provided by the application extracts the target contour corresponding to the stacked structure of the ring gate transistor to be deposited; geometric data of the target contour is calculated based on a target function in an image processing library; the reaction gas diffusion coefficient of the ring gate transistor at the current deposition time is calculated by combining the geometric data of the target contour and a reaction gas diffusion coefficient calculation formula; the structure information of the ring gate transistor to be deposited is iteratively updated according to the deposition time, the reaction gas diffusion coefficient is iteratively calculated, and the target reaction gas diffusion coefficient of the reaction gas in the cavity structure of the ring gate transistor at different deposition times is obtained. The method improves the accuracy of the lateral deposition process simulation model of the GAA inner wall cavity structure to a certain extent. Moreover, the method has a wide range of applications and can be used for the calculation of the gas diffusion part in the deposition simulation of different GAA substrate structures, so as to improve the accuracy of the corresponding simulation model.

[0013] In a second aspect, the application provides a reaction gas diffusion coefficient determination device. The device is applied to the reaction gas diffusion coefficient determination method provided in the first aspect, and the device comprises: a target contour extraction module configured to extract a target contour corresponding to a stacked structure of a ring gate transistor to be deposited; a geometric data calculation module of the target contour configured to calculate geometric data of the target contour based on a target function in an image processing library; a reaction gas diffusion coefficient calculation module configured to calculate a reaction gas diffusion coefficient of a ring gate transistor at a current deposition time by combining the geometric data of the target contour and a reaction gas diffusion coefficient calculation formula; a target reaction gas diffusion coefficient determination module configured to iteratively update structure information of the ring gate transistor to be deposited according to the deposition time, iteratively calculate the reaction gas diffusion coefficient, and obtain a target reaction gas diffusion coefficient of the reaction gas in a cavity structure of the ring gate transistor at different deposition times.

[0014] In a third aspect, the application provides a reaction gas diffusion coefficient determination device, which comprises: a memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program executable by the processor; and the processor executes the computer program to perform the reaction gas diffusion coefficient determination.

[0015] In a fourth aspect, the application provides a computer storage medium, which stores instructions, and the instructions are executed to implement the reaction gas diffusion coefficient determination.

[0016] The technical effects achieved by the device scheme provided in the second aspect, the equipment scheme provided in the third aspect and the computer storage medium scheme provided in the fourth aspect are the same as those of the method scheme provided in the first aspect, and details are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. In the drawings: Figure 1 A flow chart of a reaction gas diffusion coefficient determination method provided by the present application is shown in the figure; Figure 2 A GAA structure target profile provided by the present application is shown in the figure; Figure 3 A reaction gas diffusion coefficient determination device structure provided by the present application is shown in the figure; Figure 4 A reaction gas diffusion coefficient determination device structure provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0018] In order to clearly describe the technical scheme of the embodiments of the present application, in the embodiments of the present application, the terms "first", "second", etc. are used to distinguish the same or similar items with basically the same function and effect. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit the order. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the number and execution order, and the terms "first", "second", etc. also do not necessarily mean different.

[0019] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or having more advantages than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are used in the specific manner to present the relevant concept.

[0020] In the present application, “at least one” means one or more, and “multiple” means two or more. “And / or” describes the association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the associated objects before and after it. “At least one of the following” or similar expressions means any combination of these items, including single or multiple items in any combination. For example, at least one of a, b or c can represent a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be singular or plural.

[0021] The device structure of a logic device gradually develops towards a gate-all-around (GAA) transistor structure as the advanced technology node of the device. The etching and deposition processes of the GAA structure cavity have a significant impact on the performance of the device, and the experiment is extremely difficult and costly. Therefore, it is urgent to simulate the etching and deposition processes of the GAA structure cavity to assist the development. The models for modeling the lateral deposition of the GAA structure cavity mainly include a diffusion-reaction model, a Monte Carlo model and a ballistic transport model. The diffusion-reaction model has the advantages of calculation efficiency and simulation accuracy. However, when the diffusion-reaction model is used to model the lateral deposition process of the GAA structure cavity, the diffusion of the reaction gas in the GAA structure is an important part of the model establishment. When analyzing the diffusion distribution of the reaction gas in the GAA structure cavity, the accurate solution of the diffusion coefficient of the reaction gas molecules in the cavity is the key. In the GAA structure cavity, the diffusion coefficient of the reaction gas molecules is not only affected by the process conditions, but also closely related to the structure parameters (SiGe layer thickness, cavity depth) of the GAA stack. When modeling the lateral deposition of the GAA cavity, how to calculate the diffusion coefficient of the reaction gas under different process conditions and different GAA stack structure parameters is one of the main problems faced in the deposition simulation modeling.

[0022] The calculation of the diffusion coefficient in the prior art is only based on the initial substrate structure. However, in the deposition process, the substrate structure is constantly changing with the reaction time, so the diffusion coefficient of the gas is also changing iteratively. Therefore, the calculation method in the scheme is not accurate. Moreover, the calculation given is in a regular structure, and the scope of application is narrow.

[0023] Based on the above problems, the present application provides a reaction gas diffusion coefficient determination method suitable for Gate-all-around (GAA) structure deposition modeling. The method mainly consists of three parts: GAA substrate structure contour extraction module, contour perimeter and area calculation, and diffusion coefficient solving. First, based on the image processing library (such as OpenCV, Scikit-image, Pillow, etc.), the input GAA structure is grayed and binarized, and then the contour of the processed GAA structure is extracted; second, as the GAA cavity lateral deposition is carried out, the evolving GAA structure contour is extracted according to the deposition time, and the contour perimeter and area calculation function in the image processing library is used to calculate the perimeter and area of the target contour; finally, the calculated contour perimeter and area are brought into the diffusion coefficient solving formula, and the diffusion coefficient of the GAA structure at the current deposition time is obtained.

[0024] The method of the present application can be applied to the lateral deposition simulation modeling of GAA inner sidewall cavity structure to calculate the diffusion coefficient of the reaction gas in the cavity, so as to improve the accuracy of the simulation model.

[0025] Next, the scheme provided by the embodiments of the present application will be described in combination with the drawings: As Figure 1 shown, the flow can include the following steps: Step 110: Extract the target contour corresponding to the stacked structure of the ring gate transistor to be deposited.

[0026] The stacked structure of the GAA transistor is an advanced design that enhances the performance of the transistor by vertically stacking multiple nanosheets (or nanowires). The innovation of this structure lies in significantly increasing the effective channel width by stacking multiple horizontal nanosheets, thereby improving the drive current density while maintaining a small chip area. The nanosheet (or nanowire) layer is the core part of the GAA transistor and can usually be composed of semiconductor materials such as silicon, germanium silicon or III-V compound semiconductors, etc. Multiple nanosheets are vertically stacked to form the channel region of the transistor. Each nanosheet serves as an independent conduction path, which helps to increase the total drive current. The gate material (such as metal) of the gate layer surrounds each nanosheet on all sides. The inner sidewall and the isolation layer are between the nanosheet and the gate, the inner sidewall can regulate the parasitic capacitance and parasitic resistance between the gate and the source / drain, reduce the parasitic effect, at the same time, it serves as an etching stop layer for channel release, which helps to control the effective gate length and improve the control ability of the gate to the channel. The source and drain are usually composed of doped semiconductor materials, which are connected to both ends of the nanosheet to form the entrance and exit of the current.

[0027] Step 120: Calculate the geometric data of the target contour based on the objective function in the image processing library.

[0028] The geometric data can include the perimeter, area, aspect ratio, center point coordinates, direction angle, etc. of the target contour. These data can be calculated from the target contour, for example: when using OpenCV image processing library to calculate the geometric data of the target contour, findContours function can be used to extract the target contour in the image, then arcLength function is used to calculate the perimeter of the contour, contourArea function is used to calculate the area surrounded by the contour, etc. These functions are based on the corresponding objective function and mathematical principles to calculate the geometric data.

[0029] Step 130: Calculate the reaction gas diffusion coefficient of the ring gate transistor at the current deposition time based on the geometric data of the target contour and the reaction gas diffusion coefficient calculation formula.

[0030] In the manufacturing process of the ring gate transistor (GAA transistor), the diffusion of the reaction gas is crucial for the film deposition and other process steps. The geometric data of the target contour (such as perimeter, surface area, aspect ratio, cross-sectional shape, etc.) will affect the diffusion path and diffusion rate of the reaction gas in the transistor structure. Therefore, it is necessary to combine the geometric data of the target contour and the reaction gas diffusion coefficient calculation formula to calculate the reaction gas diffusion coefficient of the ring gate transistor at different deposition times.

[0031] Step 140: According to the deposition time, iteratively update the structure information of the ring gate transistor to be deposited, iteratively calculate the reaction gas diffusion coefficient, and obtain the target reaction gas diffusion coefficient of the reaction gas in the cavity structure of the ring gate transistor at different deposition times.

[0032] In specific implementation, based on the design specifications of the ring gate transistor to be deposited, its three-dimensional geometric model can be constructed, focusing on the cavity structure part, and the initial shape, size and geometric parameters related to the diffusion of the reaction gas, such as the length, width, height, cross-sectional area, surface area, etc. of the cavity are determined. The initial concentration of the reaction gas, the estimated value of the diffusion coefficient, the initial time step of the deposition process, etc. are determined. Provide a basis for subsequent iterative calculation.

[0033] When simulating the cavity (cavity) lateral deposition process of the GAA device inner wall module, we mainly based on the two-dimensional reaction-diffusion model, the model building process chart is as Figure 1 shown, the main calculation formula is as follows: (1) where J_i(t,x,y) is the particle flux value of the reactant in the GAA structure, is the diffusion coefficient, is the adsorption loss term. When simulating the lateral deposition process of the cavity in the GAA structure using this model, the calculation of the deposition rate at different positions in the GAA structure is the key to the simulation, and the calculation of the deposition rate is closely related to the flux distribution of the reaction gas in the cavity. In the reaction-diffusion model, the calculation of the diffusion coefficient of the reaction gas in the cavity in the GAA device structure is the key to the calculation of the flux distribution of the reaction gas in the cavity in the GAA device structure. Therefore, by using the technical scheme of the present application, the interaction between the change of the ring gate transistor structure with the deposition time and the diffusion of the reaction gas can be considered comprehensively, and the target reaction gas diffusion coefficient in the cavity structure at different deposition times can be accurately calculated, thereby providing strong support for the optimization of the semiconductor manufacturing process.

[0034] Figure 1 The method in the method, the target profile corresponding to the stacked structure of the ring gate transistor to be deposited is extracted; geometric data of the target profile is calculated based on a target function in an image processing library; the reaction gas diffusion coefficient of the ring gate transistor at the current deposition time is calculated in combination with the geometric data of the target profile and a reaction gas diffusion coefficient calculation formula; the structure information of the ring gate transistor to be deposited is iteratively updated according to the deposition time, and the reaction gas diffusion coefficient is iteratively calculated to obtain the target reaction gas diffusion coefficient of the reaction gas in the cavity structure of the ring gate transistor at different deposition times. The method improves the accuracy of the lateral deposition process simulation model of the GAA inner spacer cavity structure to a certain extent. Moreover, the method has a wide range of applications and can be used for the calculation of the gas diffusion part in the deposition simulation of different GAA substrate structures, thereby improving the accuracy of the corresponding simulation model.

[0035] Based on the method, Figure 1 The embodiments of the present specification also provide some specific implementations of the method, which are described below.

[0036] For step 110, in specific implementation, can include: In advanced process nodes, the stacked structure of the ring gate transistor to be deposited is input, and the substrate structure format at least includes an electron microscope picture (such as: SEM / TEM picture), a layout and a custom structure; The input ring gate transistor to be deposited is subjected to grayscale and binarization processing based on an image processing library (such as: OpenCV, Scikit-image, Pillow, etc.), to obtain processed data; The target profile of the ring gate transistor to be deposited after processing is extracted from the processed data. As shown in Figure 2 Figure 2 ​The red part in the figure is the outline of the GAA structure after processing.

[0037] Step 120 can specifically include: selecting a target function from the image processing library; the target function at least includes a contour perimeter calculation function and a contour area calculation function; calculating the perimeter and the enclosed area of the target contour based on the contour perimeter calculation function and the contour area calculation function.

[0038] Step 130 can specifically include: if the reaction gas under the current substrate structure is a monatomic gas, based on the perimeter and the area of the target contour, using the formula: (2) (3) (4) calculating the first diffusion coefficient of the first reaction gas under the current substrate structure; In formula (2), the hydraulic diameter is used to calculate the Knudsen diffusion coefficient, and the calculation of the hydraulic diameter is closely related to the shape of the substrate. As the deposition time increases, the morphology of the substrate is also constantly changing. According to the definition of the hydraulic diameter, the edge contour of the substrate structure is selected as the target contour after each iteration of the substrate morphology update with the deposition time, and then the perimeter L and the area S enclosed by the edge contour of the substrate structure are calculated according to the contour perimeter and area calculation functions in the image processing library (such as OpenCV, Scikit-image, Pillow, etc.), and the corresponding diffusion coefficient is calculated.

[0039] wherein, Knudsen diffusion coefficient of the first reaction gas, molecular diffusion coefficient of the first reaction gas, the first diffusion coefficient, the area of the target contour, the perimeter of the target contour, Boltzmann constant, Avogadro constant, P represents process pressure, and T represents process temperature, molecular molar mass of the first reaction gas, molecular diameter of the first reaction gas.

[0040] if the reaction gas under the current substrate structure is a binary gas mixture, based on the perimeter and the area of the target contour, using the formula: (2) (5) (6) calculating a second diffusion coefficient of the reaction gas under the current substrate structure; the binary gas mixture comprises a first reaction gas and a second reaction gas; wherein, represents a molecular diffusion coefficient of the first reaction gas in the binary gas mixture, represents the second diffusion coefficient, represents a molecular molar mass of the second reaction gas, represents a molecular diameter of the second reaction gas.

[0041] The method is to bring the geometric data obtained in step 120 into formulas (2)-(6) to calculate the diffusion coefficient, further, the first reaction gas is represented by reaction gas A, and the second reaction gas is represented by reaction gas B. The circumference L and the area S are brought into the gas diffusion coefficient calculation formula. If it is a unary gas, the diffusion coefficient D1 of the reaction gas A under the current substrate structure is obtained according to formulas (2)(3)(4); if it is a binary gas mixture, the diffusion coefficient D2 of the reaction gas A under the current substrate structure is obtained according to formulas (2)(5)(6).

[0042] Step 140, when specifically implemented, iteratively updates the structure information of the ring gate transistor to be deposited according to the deposition time, iteratively calculates the reaction gas diffusion coefficient, and obtains the target reaction gas diffusion coefficient of the ring gate transistor in the cavity structure of the ring gate transistor under different deposition times of the reaction gas. It can include: In each time step, the profile of the deposited ring gate transistor is extracted; the surface topography of the ring gate transistor structure changes as the lateral deposition of the cavity structure of the ring gate transistor proceeds; The profile circumference and area are recalculated, and the diffusion coefficient is calculated according to the process conditions to obtain the diffusion coefficient of the reaction gas under the current deposition time of the cavity structure of the ring gate transistor under the corresponding process conditions; Based on the diffusion coefficient, the gas flow spatial distribution and the deposition rate are updated and solved to realize the iterative evolution of thin film growth.

[0043] Specifically, as the lateral deposition of the cavity structure inside the GAA proceeds, the surface morphology of the GAA structure also changes. By extracting the contour of the deposited GAA structure at each time step, recalculating the contour perimeter and area, and then substituting them into formulas (1)-(5) according to the process conditions, the diffusion coefficient of the reactive gas under the cavity of the GAA structure at the current deposition time can be obtained. Based on the diffusion coefficient, the spatial distribution of gas flow rate and deposition rate are updated to achieve the iterative evolution of film growth. The iteration ends with the deposition time.

[0044] The method provided in the above embodiments of the present invention is a method for determining the diffusion coefficient of reactive gases in deposition modeling of gate-annular (GAA) transistor structures. It mainly relies on the changes in the surface morphology of the GAA structure during lateral deposition of the inner wall cavity structure. It adaptively calculates the change in the diffusion coefficient of reactive gases in the inner wall cavity structure of the GAA with deposition time, thereby accurately calculating the flux value of reactive gases at each reaction site in the inner wall cavity structure of the GAA at different deposition times, and then sequentially calculates the deposition rate at the corresponding locations. This method improves the accuracy of the lateral deposition process simulation model of the inner wall cavity structure of the GAA to a certain extent.

[0045] Furthermore, this invention first performs grayscale and binarization processing on the input GAA structure using image processing libraries (such as OpenCV, Scikit-image, Pillow, etc.), and then extracts the contour of the processed GAA structure. Secondly, as the lateral deposition of the GAA cavity proceeds, the evolving GAA structure contour is extracted based on the deposition time, and the perimeter and area of ​​the target contour are calculated using contour perimeter and area calculation functions from the image processing library. Finally, the calculated contour perimeter and area are substituted into the diffusion coefficient calculation formula to obtain the diffusion coefficient of the GAA structure at the current deposition time. This algorithm has a wide range of applications and can be used to calculate the gas diffusion portion in deposition simulations of different GAA substrate structures, thereby improving the accuracy of the corresponding simulation models.

[0046] Based on the same idea, the present invention also provides a device for determining the diffusion coefficient of a reactant gas, which is applied to a method for determining the diffusion coefficient of a reactant gas provided in the preceding embodiments. Figure 3 As shown, the device may include: The target contour extraction module 310 is used to extract the target contour corresponding to the stacked structure of the gate ring transistor to be deposited; The geometric data calculation module 320 for the target contour is used to calculate the geometric data of the target contour based on the target function in the image processing library; The reactive gas diffusion coefficient calculation module 330 is used to calculate the reactive gas diffusion coefficient of the gate ring transistor at the current deposition time by combining the geometric data of the target contour and the reactive gas diffusion coefficient calculation formula. The target reactive gas diffusion coefficient determination module 340 is used to iteratively update the structural information of the gate ring transistor to be deposited based on the deposition time, iteratively calculate the reactive gas diffusion coefficient, and obtain the target reactive gas diffusion coefficient in the cavity structure of the gate ring transistor at different deposition times.

[0047] based on Figure 3 The device may also include specific implementation units: Optionally, the target contour extraction module 310 may include: The stacked structure input unit for the gate ring transistor to be deposited is used to input the stacked structure of the gate ring transistor to be deposited in advanced process nodes. The substrate structure format includes at least electron microscope images, layouts, and custom structures. The data processing unit is used to perform grayscale and binarization processing on the input gate ring transistor to be deposited based on the image processing library to obtain the processed data; The target contour extraction unit is used to extract the processed target contour of the gate ring transistor to be deposited from the processed data.

[0048] Optionally, the geometric data calculation module 320 for the target contour may include: The objective function selection unit is used to select an objective function from the image processing library; the objective function includes at least a contour perimeter calculation function and a contour area calculation function. The perimeter and area determination unit is used to calculate the perimeter of the target contour and the area it encloses based on the contour perimeter calculation function and the contour area calculation function.

[0049] Optionally, the reactant gas diffusion coefficient calculation module 330 may include: The first diffusion coefficient calculation unit is used to calculate the diffusion coefficient based on the perimeter and area of ​​the target profile, using the following formula, if the reactant gas under the current substrate structure is a monolithic gas: Calculate the first diffusion coefficient of the first reactant gas under the current substrate structure; in, This represents the Knudsen diffusion coefficient of the first reacting gas. This represents the molecular diffusion coefficient of the first reacting gas. Represents the first diffusion coefficient. denotes an area of the target profile, denotes a perimeter of the target profile, denotes a Boltzmann constant, denotes an Avogadro constant, P denotes a process pressure, and T denotes a process temperature, denotes a molar mass of a first reaction gas molecule, denotes a molecular diameter of the first reaction gas; a second diffusion coefficient calculation unit, configured to, if the reaction gas under the current substrate structure is a binary gas mixture, calculate a second diffusion coefficient of the reaction gas under the current substrate structure based on the perimeter and the area of the target profile, by using a formula: a second diffusion coefficient calculation unit, configured to, if the reaction gas under the current substrate structure is a binary gas mixture, calculate a second diffusion coefficient of the reaction gas under the current substrate structure based on the perimeter and the area of the target profile, by using a formula: wherein, denotes a molecular diffusion coefficient of the first reaction gas in the binary gas mixture, denotes the second diffusion coefficient, denotes a molar mass of a second reaction gas molecule, denotes a molecular diameter of the second reaction gas.

[0050] Optionally, the target reaction gas diffusion coefficient determination module 340 can be configured to: extract a profile of the deposited ring-gate transistor at each time step; the surface topography of the ring-gate transistor structure changes as the lateral deposition of the cavity structure of the ring-gate transistor proceeds; re-calculate the perimeter and the area of the profile, and calculate the diffusion coefficient according to the process conditions, to obtain the diffusion coefficient of the reaction gas under the cavity structure of the ring-gate transistor at the current deposition time under the corresponding process conditions; update the gas flow spatial distribution and the deposition rate based on the diffusion coefficient, to realize the iterative evolution of the thin film growth.

[0051] Further, the iterative evolution of the thin film growth based on the diffusion coefficient update to solve the gas flow spatial distribution and the deposition rate can include: calculate the flux values of the reaction gas at different reaction sites in the cavity structure of the ring-gate transistor at different deposition times; calculate the deposition rates at the corresponding positions based on the flux values.

[0052] Based on the same idea, the present specification also provides a reaction gas diffusion coefficient determination device. As shown in Figure 4As shown in the figure, the device comprises: a memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program executable by the processor; and the processor executes the computer program to implement the reaction gas diffusion coefficient determination method.

[0053] As shown in the figure, Figure 4 the processor can be a general central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs of the present application. The communication interface can be one or more. The communication interface can use any transceiver device to communicate with other devices or communication networks.

[0054] As shown in the figure, Figure 4 the terminal device can further include a communication line. The communication line can include a path for transmitting information between the components.

[0055] Optionally, as shown in the figure, Figure 4 the terminal device can further include a memory. The memory stores a computer program executable by the processor; and the processor executes the computer program to implement the method provided by the embodiment of the present application.

[0056] As shown in the figure, Figure 4 the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but not limited to. The memory can exist independently and be connected to the processor through the communication line. The memory can also be integrated with the processor.

[0057] Optionally, the computer-executable instructions in the embodiments of the present application can also be referred to as application codes, which are not specifically limited in the embodiments of the present application.

[0058] In a specific implementation, as an embodiment, as shown in Figure 4 , the processor can include one or more CPUs, such as CPU0 and CPU1 in Figure 4 .

[0059] In a specific implementation, as an embodiment, as shown in Figure 4 , the terminal device can include a plurality of processors, such as the processors in Figure 4 . Each of the processors can be a single-core processor or a multi-core processor.

[0060] Based on the same idea, the embodiments of the present specification also provide a computer storage medium corresponding to the above-mentioned embodiments, and the computer storage medium stores instructions, and when the instructions are executed, the method in the above-mentioned embodiments is implemented.

[0061] The above mainly introduces the scheme provided by the embodiments of the present application from the perspective of the interaction between the modules. It can be understood that each module includes a hardware structure and / or a software unit for executing the corresponding functions in order to achieve the above functions. Those skilled in the art should easily realize that the units and method steps of the examples described in combination with the embodiments disclosed in the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0062] The embodiments of the present application can divide the functional modules according to the above-mentioned method examples, for example, each functional module can be divided according to each function, or two or more functions can be integrated in one processing module. The above-mentioned integrated module can be realized in the form of hardware or software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical functional division. There can be another division method when actually implemented.

[0063] The processor in the present specification can also have the function of a memory. The memory is used to store computer-executable instructions for executing the scheme of the present application, and is controlled by the processor to execute. The processor is used to execute the computer-executable instructions stored in the memory, so as to realize the method provided by the embodiments of the present application.

[0064] The memory can be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), Blu-ray discs, etc.), magnetic disk storage or other magnetic storage devices, or any other media that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a communication line. The memory can also be integrated with the processor.

[0065] Optionally, the computer-executed instructions in the embodiments of the present application can also be referred to as application program codes, and the embodiments of the present application do not make specific limitations thereto.

[0066] The method disclosed in the embodiments of the present application can be applied to a processor or implemented by the processor. The processor can be an integrated circuit chip with a signal processing capability. In the implementation process, each step of the above method can be completed by an integrated logic circuit or an instruction in the form of software in the processor. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.

[0067] Although the application is described herein with reference to the embodiments, those skilled in the art will understand that various modifications and changes in form and detail can be made thereto without departing from the spirit and scope of the application. Accordingly, the description and drawings are to be regarded as illustrative in nature and are not intended as limiting the scope of the application as defined by the appended claims. The word "comprising" does not exclude other elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. A single processor or other unit can fulfil the functions of several items recited in a claim. A combination of claims does not require that each element recited in the combination be present in every embodiment.

[0068] Although the application is described herein with reference to the specific features thereof and embodiments thereof, it is evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive. It is to be understood that the application is not limited to the details of the above-described embodiments but includes all modifications within the scope and spirit of the application as expressed by the appended claims.

Claims

1. A method for determining the diffusion coefficient of a reactive gas, characterized in that the method... The method comprises the steps of: extracting a target contour corresponding to a stacked structure of a ring gate transistor to be deposited; calculating geometric data of the target contour based on a target function in an image processing library; calculating a reaction gas diffusion coefficient of the ring gate transistor at a current deposition time based on the geometric data of the target contour and a reaction gas diffusion coefficient calculation formula; iteratively updating structure information of the ring gate transistor to be deposited according to deposition time, iteratively calculating the reaction gas diffusion coefficient, and obtaining a target reaction gas diffusion coefficient of the reaction gas in a cavity structure of the ring gate transistor at different deposition times.

2. The reaction gas diffusion coefficient determination method according to claim 1, characterized by, The method comprises the steps of: in an advanced process node, inputting a stacked structure of a ring gate transistor to be deposited, and a substrate structure format at least including an electron microscope picture, a layout, and a self-defined structure; performing grayscale and binarization processing on the input ring gate transistor to be deposited based on an image processing library to obtain processed data; extracting a target contour of the ring gate transistor to be deposited from the processed data.

3. The reaction gas diffusion coefficient determination method according to claim 1, characterized by, The method comprises the steps of: selecting a target function from the image processing library; the target function at least includes a contour perimeter calculation function and a contour area calculation function; calculating a perimeter and an enclosed area of the target contour based on the contour perimeter calculation function and the contour area calculation function.

4. The reaction gas diffusion coefficient determining method according to claim 3, characterized by, The method comprises the steps of: if the reaction gas under the current substrate structure is a monatomic gas, then based on the perimeter and the area of the target contour, a formula is used to calculate a first diffusion coefficient of the first reaction gas under the current substrate structure; The method comprises the steps of: where D KnA represents the Knudsen diffusion coefficient of the first reaction gas, D A represents the molecular diffusion coefficient of the first reaction gas, D1 represents the first diffusion coefficient, S represents the area of the target profile, L represents the perimeter of the target profile, k B represents the Boltzmann constant, N0 represents the Avogadro constant, P represents the process pressure, T represents the process temperature, M A represents the molar mass of the first reaction gas molecule, d A represents the molecular diameter of the first reaction gas.

5. The reaction gas diffusion coefficient determining method according to claim 4, characterized by, if the reaction gas under the current substrate structure is a binary gas mixture, then based on the perimeter and the area of the target contour, a formula is used to calculate a second diffusion coefficient of the reaction gas under the current substrate structure; the binary gas mixture includes a first reaction gas and a second reaction gas. The method comprises the steps of: in each time step, extracting a contour of the deposited ring gate transistor; the surface topography of the ring gate transistor changes as the cavity structure of the ring gate transistor is laterally deposited; Among them, D AB D1 represents the molecular diffusion coefficient of the first reacting gas in the binary gas mixture, D2 represents the second diffusion coefficient, and M2 represents the molecular diffusion coefficient. B d represents the molar mass of the second reactant gas molecules. B This indicates the molecular diameter of the second reacting gas.

6. The reaction gas diffusion coefficient determination method according to claim 1, characterized by, recalculating the contour perimeter and the area, and calculating the diffusion coefficient according to the process conditions to obtain the diffusion coefficient of the reaction gas in the cavity structure of the ring gate transistor at the current deposition time under the corresponding process conditions; based on the diffusion coefficient, updating the gas flow spatial distribution and the deposition rate to realize the iterative evolution of thin film growth. ​ ​ 7. The reaction gas diffusion coefficient determining method according to claim 6, characterized by, Based on the diffusion coefficient update solving gas flow spatial distribution and deposition rate, the iterative evolution of thin film growth is realized, including: The flux values of the reaction gas at each reaction site in the cavity structure of the ring gate transistor under different deposition times are calculated; Based on the flux values, the deposition rates at the corresponding positions are calculated in turn.

8. A reaction gas diffusion coefficient determining apparatus characterized by comprising: The device is applied to the reaction gas diffusion coefficient determination method in any one of claims 1-7, and the device comprises: A target contour extraction module is configured to extract a target contour corresponding to a stacked structure of a ring gate transistor to be deposited; A geometric data calculation module of the target contour is configured to calculate geometric data of the target contour based on a target function in an image processing library; A reaction gas diffusion coefficient calculation module is configured to calculate the reaction gas diffusion coefficient of the ring gate transistor under the current deposition time by combining the geometric data of the target contour and a reaction gas diffusion coefficient calculation formula; A target reaction gas diffusion coefficient determination module is configured to iteratively update the structure information of the ring gate transistor to be deposited according to the deposition time, iteratively calculate the reaction gas diffusion coefficient, and obtain the target reaction gas diffusion coefficient of the reaction gas in the cavity structure of the ring gate transistor under different deposition times.

9. A device for determining the diffusion coefficient of a reactive gas, characterized in that the device... It comprises: A memory, a processor, and a communication interface coupled with the processor; The memory stores a computer program executable by the processor; When the processor runs the computer program, it executes the reaction gas diffusion coefficient determination method in any one of claims 1-7.

10. A computer storage medium, characterized in that, The computer storage medium stores instructions, which, when executed by the processor, implement the reaction gas diffusion coefficient determination method in any one of claims 1-7.

Images