Passive up-conversion mixer

Abstract

The invention relates to a passive up-conversion mixer. In one embodiment, an apparatus includes a complementary metal oxide semiconductor (CMOS) up-conversion passive mixer to receive a baseband signal and to up-convert the baseband signal to a radio frequency (RF) signal; and a class AB amplifier circuit module coupled to the CMOS up-conversion passive mixer to receive and amplify the RF signal.

Description

BACKGROUND

[0001] Wireless transmitters are used to transmit radio frequency (RF) signals of different modulation schemes, including non-constant envelope modulation schemes like Orthogonal Frequency Division Multiplexing (OFDM) (used in Wi-Fi). To process these OFDM signals, the transmitter typically includes a voltage-to-current (V-to-I) converter followed by a Gilbert cell mixer that upconverts lower frequency signals to RF signals and drives a power amplifier (PA).

[0002] At high carrier frequencies like those used in the 5 / 6 / 7 GHz Wi-Fi bands, a class-A Gilbert cell mixer consumes high current to drive a high output power PA. This is because the impedance presented by the input capacitance of a high output power PA is lower at higher frequencies and thus consumes more current. Moreover, by definition, a Gilbert cell mixer operates in class-A mode, meaning it requires high DC current to achieve a given swing at its output. According to one estimate, the current consumed by a Gilbert cell mixer at these high carrier frequencies can be a significant fraction of the current consumed by the PA itself (e.g., the mixer consumes 80 milliamps (mA) and the PA consumes 185 mA), and thus has an adverse impact on transmitter efficiency.

[0003] Moreover, since a Gilbert cell mixer operates in current mode, linear V-to-I conversion is required. However, typical V-to-I converters suffer from high mismatch, high noise, and require higher power supply. These issues are raised in the context of Wi-Fi 6, 6E, and 7 higher order modulation schemes like 256 Quadrature Amplitude Modulation (QAM) and 1024 QAM that require high dynamic range. SUMMARY

[0004] In one aspect, an apparatus includes a complementary metal-oxide-semiconductor (CMOS) upconversion passive mixer to receive a baseband signal and upconvert the baseband signal to a radio frequency (RF) signal, and an AB class amplifier circuit module coupled to the CMOS upconversion passive mixer to receive and amplify the RF signal.

[0005] In one implementation, the CMOS up-conversion passive mixer includes a double balanced mixer. The CMOS up-conversion passive mixer includes a plurality of switching circuits, each of the plurality of switching circuits to receive at least a portion of the baseband signal and output at least a portion of the RF signal. Each of the plurality of switching circuits can include a first metal oxide semiconductor field effect transistor (MOSFET) of a first polarity to receive at least the portion of the baseband signal and output at least the portion of the RF signal, and a second MOSFET of a second polarity to receive at least the portion of the baseband signal and output at least the portion of the RF signal. The first MOSFET of the first polarity is to be driven by a first local oscillator (LO) signal of a pair of a plurality of complementary LO signals, and the second MOSFET of the second polarity is to be driven by a second LO signal of the pair of the plurality of complementary LO signals.

[0006] In one implementation, the device further includes a buffer circuit module to provide the plurality of complementary LO signals to the CMOS up-conversion passive mixer. The buffer circuit module can include a plurality of circuits each having an inverter to receive at least one LO signal and generate therefrom the first LO signal of the pair of the plurality of complementary LO signals, the first LO signal having a first polarity, and a buffer coupled to the inverter to generate the second LO signal of the pair of the plurality of complementary LO signals. The buffer circuit module is to provide the plurality of complementary LO signals each having a duty cycle, wherein a sum of the duty cycles of each of the pair of the plurality of complementary LO signals is equal to 100%.

[0007] In one implementation, the apparatus further includes a biasing circuit coupled to the CMOS up-conversion passive mixer, the biasing circuit to generate a first bias signal and a second bias signal, wherein each of the plurality of switching circuits is to receive the first bias signal and the second bias signal. The biasing circuit can include a first diode-connected MOSFET to provide the first bias signal, the first diode-connected MOSFET including a replica of the first MOSFET of the first polarity, and a second diode-connected MOSFET to provide the second bias signal, the second diode-connected MOSFET including a replica of the second MOSFET of the second polarity. The biasing circuit can further include a first degeneration resistor coupled to the first diode-connected MOSFET, and a second degeneration resistor coupled to the second diode-connected MOSFET. The first bias signal is to prevent the first MOSFET of the first polarity from operating in reverse. Each of the plurality of switching circuits can further have a filter capacitor coupled to a common node, the common node coupled to a first terminal of the first MOSFET of the first polarity and a first terminal of the second MOSFET of the second polarity.

[0008] In another aspect, an integrated circuit includes a digital-to-analog converter (DAC) to convert a digital baseband signal to an analog baseband signal, a passive up-conversion mixer coupled to the DAC to up-convert the analog baseband signal to an RF signal, an AB class pre-driver coupled to the passive up-conversion mixer to pre-drive the RF signal, and an AB class amplifier coupled to the AB class pre-driver to amplify the pre-driven RF signal and output the amplified RF signal.

[0009] In one implementation, the passive up-conversion mixer includes a voltage-mode up-conversion mixer to receive a first voltage signal including the analog baseband signal and output a second voltage signal including the RF signal. The passive up-conversion mixer can include a plurality of switching circuits, each of the plurality of switching circuits to receive at least a portion of the analog baseband signal and output at least a portion of the RF signal. Each of the plurality of switching circuits can include a first MOSFET of a first polarity to receive at least the portion of the analog baseband signal and output at least the portion of the RF signal, and a second MOSFET of a second polarity to receive at least the portion of the analog baseband signal and output at least the portion of the RF signal, wherein the first MOSFET of the first polarity is to be driven by a first LO signal of a pair of complementary LO signals and the second MOSFET of the second polarity is to be driven by a second LO signal of the pair of complementary LO signals.

[0010] In one implementation, the integrated circuit further includes a first transformer to couple the passive up-conversion mixer to the class-AB pre-driver, and a second transformer to couple the class-AB pre-driver to the class-AB amplifier.

[0011] In yet another aspect, a wireless device includes an integrated circuit, a matching circuit coupled to the integrated circuit, and an antenna coupled to the matching circuit to radiate an RF signal.

[0012] In one implementation, the integrated circuit includes a DAC to convert a digital signal to an analog signal, and a CMOS passive upconversion mixer coupled to the DAC to upconvert the analog signal to an RF signal. The CMOS passive upconversion mixer can include a plurality of switch circuits, each of the plurality of switch circuits including a CMOS device to be driven by a complementary clock signal to receive at least a portion of the analog signal and output at least a portion of the RF signal, a buffer circuit module coupled to the CMOS passive upconversion mixer to receive and use a first clock signal to provide the complementary clock signal having a duty cycle to the CMOS passive upconversion mixer, a bias circuit module coupled to the CMOS passive upconversion mixer to generate a bias signal for the plurality of switch circuits to prevent reverse operation of the CMOS device, and the integrated circuit can further include an AB class predriver coupled to the CMOS passive upconversion mixer to pre-drive the RF signal, and an AB class amplifier coupled to the AB class predriver to amplify the pre-driven RF signal and output an amplified RF signal.

[0013] In one implementation, each of the plurality of switch circuits includes a PMOS device to receive at least the portion of the analog signal and output at least the portion of the RF signal, and an NMOS device to receive at least the portion of the analog signal and output at least the portion of the RF signal, wherein the PMOS is to be driven by a first complementary clock signal and the NMOS is to be driven by a second complementary clock signal. The integrated circuit can further include a transformer coupled between the CMOS passive upconversion mixer and the AB class predriver. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram of a transmitter according to an embodiment.

[0015] Figure 2 is a schematic diagram of a passive mixer according to an embodiment.

[0016] Figure 3A is another schematic diagram of a passive mixer according to an embodiment.

[0017] Figure 3B is a timing diagram showing a local oscillator duty cycle signal according to an embodiment.

[0018] Figure 4This is a schematic diagram of a mixer switch according to an embodiment.

[0019] Figure 5 This is a schematic diagram of the bias circuit according to an embodiment.

[0020] Figure 6 This is a schematic diagram of a buffer circuit according to an embodiment.

[0021] Figure 7 This is a block diagram of a representative integrated circuit including a passive upconversion mixer according to an embodiment.

[0022] Figure 8 This is a high-level view of the network according to an embodiment. Detailed Implementation

[0023] In various embodiments, the wireless transmitter is equipped with a complementary metal-oxide-semiconductor (CMOS) passive up-conversion mixer. In this way, reduced power consumption can be achieved compared to typical implementations that include active mixers. Furthermore, by providing a passive mixer that operates in voltage mode, the transmitter's amplifier circuitry (including a pre-driver and power amplifier (PA)) can be implemented as a Class AB device, thereby providing higher power efficiency.

[0024] Now for reference Figure 1 The diagram shown is a schematic representation of a transmitter according to an embodiment. Figure 1 As shown, transmitter 100 is a wireless transmitter that can be included in any type of wireless device, such as a smartphone, tablet computer, personal computer, Internet of Things (IoT) device, etc. While in a typical implementation, transmitter 100 may be part of a transceiver that further includes a receiver circuitry module, embodiments are not limited thereto, and in some cases, transmitter 100 may be a standalone transmitter. Figure 1 In the high-level view, it should be understood that only certain components of the radio frequency (RF) signal processing path are shown; additional components such as additional filtering and / or gain circuit modules may exist. Furthermore, although in Figure 1 Some illustrative representations are shown, but it should be understood that a particular implementation may include a much larger number of circuit modules, as will be described further herein.

[0025] In one or more embodiments, Figure 1 Most of the circuit modules shown are implemented on a single semiconductor die, which can then be implemented within an integrated circuit (IC). As shown, transmitter 100 is configured to receive incoming baseband digital signals, such as incoming in-phase (I) and quadrature-phase (Q) signals, which are first received via digitizer 110. I,Q Converted to analog signal, as shown in the figure, digitizer 110I,Q The resulting analog signal can also be converted to differential form, so that there are I-channel positive (p) and negative (n) signals and Q-channel p and n signals. These signals are provided to corresponding filters 115 I,Q .

[0026] In embodiments, the filters 115 can be implemented as Chebyshev filters, for example, second order 1 dB ripple filters. In one embodiment, the filters 115 can be implemented as second order Chebyshev filters with a 1 dB crossover frequency of approximately 54 megahertz (MHz). Note that the filters 115 can be implemented with operational amplifiers (opamps). In one or more embodiments, the mixers 130 can be directly driven by these opamps without the need for any V / I converters. The resulting filtered analog signals output by the filters 115 are provided to CMOS passive mixers 130. Note that passive mixers differ from active mixers, such as Gibert cell type mixers, in that there is no current consumption within the mixer operating in voltage mode, as compared to potentially significant current consumption that can occur in active mixers operating in current mode.

[0027] In the high-level view shown in Figure 1 , the CMOS mixers 130 are shown as including a set of switches S1-S8. In Figure 1 , each switch Sn is shown as a single metal oxide semiconductor field effect transistor (MOSFET), namely, an N-channel MOSFET (NMOS). However, as will be described herein, in actual implementations, each such represented switch Sn can be implemented in a CMOS configuration having both NMOS and P-channel MOSFETs (PMOS).

[0028] As shown, the switches of the CMOS mixers 130 are controlled via a clock signal received from a buffer 120, namely, a 25% duty cycle local oscillator (LO) signal. The buffer 120, in turn, receives a differential quadrature LO signal, for example, from an on-chip LO or other clock generator. The mixers 130 operate to up-convert the analog baseband signals to a given RF frequency. The resulting RF signal is coupled through a first transformer T1 having a capacitor CI coupled in parallel with a primary winding. The transformer T1 is configured to present a tuning load to the mixers 130 and help achieve higher conversion gain. In turn, a secondary winding of the transformer T1 is coupled to a predriver 140 implemented as an AB class predriver. As Figure 1As shown in the high level view, the predriver 140 can be implemented with multiple cells or slices to provide programmable control over the desired number of slices to be enabled. Although embodiments are not limited in this regard, in one implementation the predriver 140 can include eight slices.

[0029] Still referring to Figure 1 , note that the RF signal input to the predriver 140 is also provided to a buffer 135, which in turn can be coupled to a feedback circuit. This feedback circuit can perform image rejection calibration (IRCAL) and / or DC offset calibration. By providing a slice predriver 140 under programmable control, the DC offset and IRCAL algorithms can be simplified.

[0030] Following amplification in the predriver 140, the resulting RF signal is output and coupled through another transformer T2 having a capacitor C2 coupled in parallel with its primary winding. The secondary winding of the transformer T2 is coupled to a PA 150, which is implemented as an AB class power amplifier. The PA 150 can also be a slice amplifier. In one implementation, the PA 150 can include 127 slices, which can be controlled individually and / or in groups. The resulting amplified RF signal is output from the semiconductor die through another transformer T3 and via output pads 160, 162, which can output at a saturation power level up to approximately 27 decibel-milliwatts (dBm). In turn, the RF signal is provided to a matching circuit 170. In embodiments, the matching circuit 170 can be a separate component, e.g., implemented on a common circuit board with the IC including the semiconductor die. Of course, in other implementations, this matching circuit module can be included within the IC.

[0031] The matching circuit 170 outputs the RF signal to a transmit / receive switch 180, which is coupled to an output node 185, which is coupled to an antenna (not shown for ease of illustration in Figure 1 ) for transmission. Further note that the PA output can also be coupled through a buffer 155 to another feedback circuit, e.g., a loopback circuit. Although shown at this high level in embodiments, it should be understood that many variations and alternatives are possible. Figure 1

[0032] Now referring to Figure 2 , shown is a further illustration of a passive mixer according to embodiments. As shown in Figure 2 , the passive mixer 130 is shown at the same high level as shown in Figure 1 . In this illustration, the incoming differential quadrature signal is shown, along with the resulting upconverted RF signal following mixing with the provided 25% duty cycle LO signal.​

[0033] Reference is now made to Figure 3A , which shows a schematic diagram of a CMOS passive up-conversion mixer in accordance with an embodiment. More specifically, in Figure 3A , the mixer 300 is implemented as a double balanced CMOS passive up-conversion mixer. As shown, the mixer 300 includes a plurality of CMOS mixer switches 3101-3108, where each CMOS mixer switch 3101-3108 is implemented with CMOS devices, i.e., PMOS devices and NMOS devices. Each of these switches is configured to receive one of a pair of complementary LO input clock signals via its gate terminal (the polarity of these 25% LO duty cycle signals is shown in Figure 3A near the gate terminals of the NMOS / PMOS devices inside the mixer switch 310). That is, as shown, the NMOS devices receive a 25% active high duty cycle LO signal at their gate terminals, while the PMOS devices receive a 25% active low duty cycle LO signal at their gate terminals. Note that these 25% LO duty cycle signals are as shown in Figure 3B . These LO signals are provided from a local oscillator, and can be coupled through a buffer circuit module (not shown in the illustration of Figure 3A .

[0034] With reference to Figure 3Acomplementary design in the input signal swings over a large voltage range. That is, the NMOS and PMOS devices of the mixer switches have similar but complementary characteristics such that even when the input signal swings over a high range, the complementary devices cancel out any degradation. In other words, when the input voltage at the baseband port is high, the on-resistance of the NMOS switch increases while the on-resistance of the PMOS switch decreases. When the input voltage at the baseband port is low, the opposite occurs. This behavior results in an average lower total on-resistance as the input voltage at the baseband port moves from high to low and back. It should be noted that if the same low on-resistance average were to be achieved through only NMOS switches, a much larger device size would be required. The increased capacitance of this larger device size would consume much higher current in the LO path. Further, it should be noted that for typical high-K metal gate semiconductor process technologies, such as in the 22 nanometer (nm) process node, the PMOS devices are not much slower than their NMOS counterparts, as is also true for older process technologies. In the 22 nm process, the PMOS devices are only about 1.25 times slower than their NMOS counterparts, while in older process technology nodes, they are 2.5-3.0 times slower. This means that by using PMOS devices, there is no significant loss of increased gate capacitance, and thus no loss of increased power consumption in the LO buffer. And the complementary nature of the PMOS devices (versus the NMOS devices) provides a significant improvement in the average on-resistance of the complementary LO switches. This results in a significant improvement in the linearity of the passive mixer. In one embodiment, the CMOS passive mixer can achieve an error vector magnitude (EVM) of over 50 dB while processing a 5.5 GHz IEEE 802.11ax MCS9 signal at -7 dBm power at its output, while consuming less than about 2 mA in the LO path.

[0035] As shown, each mixer switch 310 receives an incoming baseband input signal, i.e., one of the baseband I or Q signals (and positive or negative signals BBI_P, N and BBQ_P, N; collectively referred to as BBIN) coupled to the source terminals of the NMOS and PMOS devices. In turn, the drain terminals of the NMOS and PMOS devices are coupled together and provide a corresponding RF output signal (collectively referred to as RFOUT). As shown, the resulting outputs of the positive and negative switch sets 310 are coupled together to provide a differential RF output signal (RFOUTP, RFOUTN). Although not shown in the high level, it should be understood that each NMOS / PMOS device of the mixer switch 310 is also configured to receive an incoming bias signal, as will be further described below. Figure 3A

[0036] Reference is now made to FIG. 3, which illustrates a high level schematic diagram of a CMOS passive mixer 300, in accordance with one embodiment. As shown, the CMOS passive mixer 300 includes a differential input port 302 for receiving a differential baseband input signal (BBIN) and a differential output port 304 for providing a differential RF output signal (RFOUT). The CMOS passive mixer 300 also includes a local oscillator (LO) input port 306 for receiving an LO signal (LO) and a LO buffer 308 for buffering the LO signal. As shown, the LO buffer 308 includes a differential pair of complementary LO switches 310, each of which includes a PMOS device 312 and an NMOS device 314. As will be further described below, the LO buffer 308 is configured to provide a differential LO signal (LO) to the differential input port 302. Figure 4 ​A schematic diagram of an example CMOS mixer switch according to an embodiment is shown. Figure 4 The diagram shows a single CMOS mixer switch 310 in detail. At higher levels, the CMOS mixer switch 310 includes a pair of MOSFETs of opposite polarities, namely an NMOS device M1 and a PMOS device M2. As shown, these CMOS devices have a common coupled source terminal to receive the incoming baseband signal (bbin, via baseband input node 405) and a common coupled drain terminal to output the corresponding RF signal (rfout, via RF output node 410).

[0037] As further illustrated, each CMOS device in the CMOS device has a gate terminal coupled to receive an incoming LO signal. Specifically, NMOS device M1 receives a first LO signal (LO_n), and consequently PMOS device M2 receives a second complementary LO signal (LO_p). Note that these complementary LO signals (e.g., one of the four pairs of complementary LO signals provided to the dual-balanced CMOS passive mixer) are AC coupled to the gate terminals of NMOS device M1 and PMOS device M2 via DC blocking capacitors C1 and C4 (respectively).

[0038] As further shown, each gate terminal is also coupled to receive a bias voltage. Specifically, the NMOS device M1 has a gate terminal to receive a first bias signal (LO bias_nmos), which is received through resistor R1. Furthermore, the PMOS device M2 has a gate terminal to receive a second bias signal (LO bias_pmos), which is received through resistor R2. As further shown, a capacitor network is coupled to the gate terminals of the CMOS device. Specifically, a first capacitor C1 is coupled in series with the gate terminal of the NMOS device M1. The first capacitor C1 is coupled between parallel capacitors C2 and C3. Furthermore, capacitor C4 is coupled in series with the gate terminal of the PMOS device M2. Capacitor C4 is coupled between parallel capacitors C5 and C6.

[0039] like Figure 4 As further shown, the filter capacitor CF is coupled between the baseband input terminal 405 and the common coupling source terminal of the NMOS device M1 and the PMOS device M2. Figure 4 As shown, capacitor CF is a capacitor network formed by capacitors CF1 and CF2 coupled in parallel. Although in Figure 4 The embodiment is shown with this particular arrangement, but it should be understood that the filter capacitor can be implemented with a single capacitor rather than separate capacitors.

[0040] In this embodiment, the filter capacitor CF is coupled to the mixer switch ( Figure 4The baseband side of M1 and M2 in the mixer is used to reduce unwanted signal coupling. This is because passive mixers typically suffer from signal coupling through parasitic capacitance from the LO port (the gate terminal of the mixer switch) to the baseband port (the source terminal of the mixer switch). The filter capacitor CF reduces the effects of this spurious coupling by acting as a 2LO filter capacitor. Note that the value of the capacitor is not important as long as it is greater than a certain value. However, using a very large capacitor will increase the power dissipation in the baseband circuitry driving the passive mixer. In a particular implementation, CF can be implemented as a 1 picofarad capacitor, which can sufficiently reduce the 2LO ripple on the baseband side of the mixer switch while causing a tolerable increase in baseband current consumption. Although in Figure 4 The embodiments are shown at this high level, but it should be understood that variations and alternatives are possible.

[0041] As mentioned above, the mixer switches can be provided with bias signaling. Such bias voltages can be provided to prevent the PMOS / NMOS device from operating in reverse. In other words, these bias voltages prevent the mixer switches from turning on in the opposite direction. Now refer to... Figure 5 The diagram shown is a schematic of a bias circuit according to an embodiment. More specifically, as... Figure 5 As shown, the bias circuit 500 is configured to bias the mixer switches (such as in...) Figure 4 The diagram shows the bias voltage provided for LObias_nmos,pmos. Figure 5 As shown, the bias circuit 500 includes a diode-connected PMOS device M11 with a common-coupled gate and drain terminal to provide a first bias voltage (LObias_pmos). As shown, the source terminal of the PMOS device M11 is coupled to the power supply voltage node 505 via a resistor R11. A second bias voltage (corresponding to the N-polarity LO bias signal (LObias_nmos)) is output from a diode-connected NMOS device M12, which has a common-coupled drain and source terminal to provide this bias voltage. Furthermore, the source terminal of the NMOS device M12 is coupled to the reference voltage node 530 via a resistor R12.

[0042] like Figure 5As further shown, the drain / gate terminal of NMOS device M12 is also coupled to output device M14 of current mirror 510 formed by MOSFETs M13-M14. Similarly, the drain / gate terminal of PMOS device M11 is coupled to NMOS device M16 of current mirror 520 formed by MOSFETs M15-M17. As shown, NMOS devices M15-M17 have a common coupled gate terminal and source terminal coupled to a reference voltage node 530. The drain (and gate) terminal of NMOS device M15 is coupled to current source 110. The drain terminal of NMOS device M17 is coupled to a common coupled drain terminal and gate terminal of PMOS device M13. Although shown in this high level in the embodiment of Figure 5 Many variations and alternatives are possible, although shown in this high level in the embodiment. Note that MOSFETs M11 and M12 of bias circuit 500 can be sized to be a replica of the MOSFETs of the CMOS switches of the CMOS mixer, and thus provide a bias voltage to the CMOS switches that is independent of process, temperature, and voltage.

[0043] In implementations, there is a buffer circuit module to provide the LO signals to the CMOS mixer. Referring now to Figure 6 , shown is a schematic diagram of a buffer circuit according to an embodiment. More specifically, as shown in Figure 6 , buffer circuit 600 is configured as a transmission gate, which can be implemented as a balanced delay to generate a drive signal, i.e., a complementary 25% duty cycle LO signal for the CMOS mixer. It should be understood that, Figure 6 buffer circuit 600 shown in is configured to provide a pair of complementary LO signals; provide additional buffer circuits similarly configured to generate additional LO signals (i.e., a set of 8 individual LO signals).

[0044] As shown, buffer circuit 600 is implemented with an inverter 610 and a buffer 620. Inverter 610 includes a plurality of inverter stages 611-613, each of which includes a corresponding CMOS pair (formed by a respective PMOS device (M21, M23, and M25) and a respective NMOS device (M22, M24, and M26)). As shown, each stage 611-613 is coupled between a supply voltage node (VDD) and a ground node (VSS). Stage 611 includes a CMOS pair having a common coupled gate terminal to receive an input signal (i.e., one of the four LO signal pairs provided from the LO, shown here as ILOP PMOS and ILOP NMOS) and provide an output signal at a common coupled drain terminal. This intermediate output signal is in turn provided to the common coupled gate terminal of the CMOS pair of stage 612 via an inverter internal node 615 (which in turn provides the intermediate output signal at the common coupled drain terminal of the CMOS pair to the common coupled gate terminal of the CMOS pair of stage 613). Finally, the common coupled drain terminal of the CMOS pair of stage 613 provides the non-inverted LO signal ILOP PMOS.

[0045] Still referring to buffer circuit 600, the output of stage 611 is further coupled at node 615 to the common coupled source terminal of NMOS devices M27, M28 of a CMOS pass gate 624, which has a common coupled drain terminal that provides an intermediate signal to the common coupled gate terminal of a CMOS pair 626, which provides the inverted LO signal (ILOP NMOS). Although shown in this particular implementation in the embodiment of FIG. 6, many variations and alternatives are possible. Figure 6

[0046] Referring now to Figure 7 , shown is a block diagram of a representative integrated circuit 700 including a passive upconversion mixer as described herein. In Figure 7 the embodiment shown in FIG. 7, integrated circuit 700 can be, for example, a dual-mode wireless transceiver that can operate according to one or more wireless protocols (e.g., WLAN and Bluetooth, etc.), or other devices that can be used in various use cases. In one or more embodiments, Figure 7 The circuit modules of integrated circuit 700 shown in FIG. 7 can be implemented on a single semiconductor die.

[0047] Integrated circuit 700 can be included in a range of devices including smart phones, wearable devices, smart home devices, IoT devices, other consumer devices, or industrial, scientific and medical (ISM) devices, etc., including various stations.

[0048] ​In the illustrated embodiment, integrated circuit 700 includes a memory system 710, which in embodiments can include volatile storage such as RAM and non-volatile memory such as flash memory. Flash memory is a non-transitory storage medium that can store instructions and data. As further shown, integrated circuit 700 can also include a memory controller 790.

[0049] Memory system 710 is coupled to one or more digital cores 720 via bus 750, which can include one or more cores and / or microcontrollers that act as processing units of the integrated circuit. In turn, digital cores 720 can be coupled to a clock generator 730, which can provide one or more phase-locked loops or other clock generator circuitry to generate various clocks for use by circuitry of the IC, including a complementary 25% duty cycle LO clock signal provided to a passive upconversion mixer.

[0050] As further shown, IC 700 further includes power circuitry 740. Depending on the particular implementation, there can be additional circuitry to provide various functionality and interaction with external devices. Such circuitry can include an interface circuitry 760 that provides a digital communication interface to additional circuitry, such as memory, to be coupled to IC 700 via link 795. IC 700 can also include security circuitry 770 to perform wireless security techniques.

[0051] Additionally, as Figure 7 shown in the middle, a transceiver circuitry 780 can be provided to enable transmission and reception of wireless signals, for example according to one or more of local or wide area wireless communication schemes such as Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, cellular communication, etc. As shown, transceiver circuitry 780 includes multiple transceiver circuits 785 1-n to communicate according to multiple wireless communication protocols. One or more of transceiver circuits 785 include a CMOS passive upconversion mixer as described herein to enable upconversion of lower frequency signals to RF signals in a low power manner while maintaining high linearity. It will be appreciated that while shown in this high level view, many variations and alternatives are possible.

[0052] An IC such as described herein can be implemented in a variety of different devices such as a wireless station, IoT device, etc. Referring now to Figure 8 , a high level view of a network according to an embodiment is shown. As Figure 8As shown in FIG. 8, network 800 includes various devices, including wireless stations (which include smart devices such as IoT devices), access points, and remote service providers, which can utilize embodiments for reducing power consumption while maintaining high linearity of CMOS passive upconversion mixers as described herein.

[0053] In Figure 8 embodiments, wireless network 805 exists, for example, in a building with multiple wireless devices 810 0-n coupled to access points 830, which in turn communicate with remote service providers 860 via a wide area network 850 (e.g., the Internet). It should be appreciated that while shown in this high-level overview in Figure 8 embodiments, many variations and alternatives are possible.

[0054] With passive mixers according to embodiments, a high dynamic range transmitter baseband chain is implemented, which can achieve better EVM performance specified for 256QAM and 1024QAM. Embodiments can also achieve excellent LO feedthrough performance and better spectral emission mask. Additionally, embodiments can save overall power in the transmitter by enabling an AB class predriver to drive an AB class PA.

[0055] While this disclosure has been described relative to a limited number of implementations, it will be appreciated that many modifications and variations of the implementations described herein are possible. It is intended, therefore, to cover all such modifications and variations that fall within the scope of the disclosure.

Claims

1. An apparatus comprising: a complementary metal-oxide-semiconductor (CMOS) up-conversion passive mixer to receive a baseband signal and up-convert the baseband signal to a radio frequency (RF) signal; and an AB class amplifier circuit module coupled to the CMOS up-conversion passive mixer to receive and amplify the RF signal. The CMOS up-conversion passive mixer includes a double balanced mixer.

2. The apparatus of claim 1, wherein, The CMOS up-conversion passive mixer includes a plurality of switch circuits, each of the plurality of switch circuits to receive at least a portion of the baseband signal and output at least a portion of the RF signal.

3. The apparatus of claim 1, wherein, Each of the plurality of switch circuits includes:

4. The apparatus of claim 3, wherein, a first metal-oxide-semiconductor field effect transistor (MOSFET) of a first polarity to receive at least the portion of the baseband signal and output at least the portion of the RF signal; and a second MOSFET of a second polarity to receive at least the portion of the baseband signal and output at least the portion of the RF signal, wherein the first MOSFET of the first polarity is to be driven by a first local oscillator (LO) signal of a pair of a plurality of complementary LO signals and the second MOSFET of the second polarity is to be driven by a second LO signal of the pair of the plurality of complementary LO signals.

5. The apparatus of claim 4, further comprising a buffer circuit module to provide the plurality of complementary LO signals to the CMOS up-conversion passive mixer. The buffer circuit module includes a plurality of circuits, each of the plurality of circuits including:

6. The apparatus of claim 5, wherein, an inverter to receive at least one LO signal and generate therefrom the first LO signal of the pair of the plurality of complementary LO signals, the first LO signal having a first polarity; and a buffer coupled to the inverter to generate the second LO signal of the pair of the plurality of complementary LO signals. The buffer circuit module is to provide the plurality of complementary LO signals each having a duty cycle, wherein a sum of the duty cycles of each of the pair of the plurality of complementary LO signals comprises 100%.

7. The apparatus of claim 5, wherein, Each of the plurality of switch circuits is to receive the first bias signal and the second bias signal.

8. The apparatus of claim 4, further comprising a biasing circuit coupled to the CMOS up-conversion passive mixer, the biasing circuit to generate a first bias signal and a second bias signal, wherein, The bias circuit includes:

9. The apparatus of claim 8, wherein, a first diode-connected MOSFET to provide the first bias signal, the first diode-connected MOSFET including a replication of the first MOSFET of the first polarity; and a second diode-connected MOSFET to provide the second bias signal, the second diode-connected MOSFET including a replication of the second MOSFET of the second polarity. ​ 10. The apparatus of claim 9, wherein, The biasing circuit further includes: a first degeneration resistor coupled to the first diode-connected MOSFET; and a second degeneration resistor coupled to the second diode-connected MOSFET.

11. The apparatus of claim 8, wherein, The first biasing signal will prevent the first MOSFET of the first polarity from operating in reverse.

12. The apparatus of claim 4, wherein, Each of the plurality of switching circuits further includes a filter capacitor coupled to a common node, the common node coupled to a first terminal of the first MOSFET of the first polarity and a first terminal of the second MOSFET of the second polarity.

13. An integrated circuit comprising: a digital-to-analog converter (DAC) to convert a digital baseband signal to an analog baseband signal; a passive up-conversion mixer coupled to the DAC to up-convert the analog baseband signal to a radio frequency (RF) signal; an AB class pre-driver coupled to the passive up-conversion mixer to pre-drive the RF signal; and an AB class amplifier coupled to the AB class pre-driver to amplify the pre-driven RF signal and output an amplified RF signal. The passive up-conversion mixer includes a voltage-mode up-conversion mixer to receive a first voltage signal including the analog baseband signal and output a second voltage signal including the RF signal.

14. The integrated circuit of claim 13, wherein, The passive up-conversion mixer includes a plurality of switching circuits, each of the plurality of switching circuits to receive at least a portion of the analog baseband signal and output at least a portion of the RF signal.

15. The integrated circuit of claim 13, wherein, Each of the plurality of switching circuits includes:

16. The integrated circuit of claim 15, wherein, a first metal oxide semiconductor field effect transistor (MOSFET) of a first polarity to receive at least the portion of the analog baseband signal and output at least the portion of the RF signal; and a second MOSFET of a second polarity to receive at least the portion of the analog baseband signal and output at least the portion of the RF signal, wherein the first MOSFET of the first polarity is to be driven by a first local oscillator (LO) signal of a pair of complementary LO signals and the second MOSFET of the second polarity is to be driven by a second LO signal of the pair of complementary LO signals.

17. The integrated circuit of claim 13, further comprising: a first transformer to couple the passive up-conversion mixer to the AB class pre-driver; and a second transformer to couple the AB class pre-driver to the AB class amplifier.

18. A wireless device comprising: an integrated circuit comprising: a digital-to-analog converter (DAC) to convert a digital signal to an analog signal; ​ ​ a complementary metal-oxide-semiconductor (CMOS) passive up-conversion mixer coupled to the DAC to up-convert the analog signal to a radio frequency (RF) signal, the CMOS passive up-conversion mixer including: a plurality of switching circuits, each switching circuit of the plurality of switching circuits including a CMOS device to be driven by a complementary clock signal, the CMOS device to receive at least a portion of the analog signal and output at least a portion of the RF signal; a buffer circuit module coupled to the CMOS passive up-conversion mixer to receive and use a first clock signal to provide the complementary clock signal having a duty cycle to the CMOS passive up-conversion mixer; a bias circuit module coupled to the CMOS passive up-conversion mixer to generate a bias signal for the plurality of switching circuits, the bias signal to prevent reverse operation of the CMOS device; an AB class pre-driver coupled to the CMOS passive up-conversion mixer to pre-drive the RF signal; and an AB class amplifier coupled to the AB class pre-driver to amplify the pre-driven RF signal and output an amplified RF signal; a matching circuit coupled to the integrated circuit; and an antenna coupled to the matching circuit, the antenna to radiate the amplified RF signal.

19. The wireless device of claim 18, wherein, each switching circuit of the plurality of switching circuits includes: a P-channel metal-oxide-semiconductor (PMOS) device to receive at least the portion of the analog signal and output at least the portion of the RF signal; and an N-channel metal-oxide-semiconductor (NMOS) device to receive at least the portion of the analog signal and output at least the portion of the RF signal, wherein the PMOS is to be driven by a first complementary clock signal and the NMOS is to be driven by a second complementary clock signal.

20. The wireless device of claim 18, wherein, the integrated circuit includes a transformer coupled between the CMOS passive up-conversion mixer and the AB class pre-driver.

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