Array substrate, preparation method thereof and display panel
By employing passivation layers and interlayer insulating layers with different materials and hydrogen contents in the array substrate, the problem of large photo-generated leakage current in display devices was solved, resulting in cost reduction and process simplification, while also improving the reliability of thin-film transistors.
Patent Information
- Application Number
- CN202511006693.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-21
- Publication Date
- 2025-11-07
AI Technical Summary
Existing display devices generate large leakage currents without a light-shielding layer, resulting in poor display quality. Furthermore, adding a light-shielding layer increases cost and process complexity.
By using different materials for the passivation layer and the interlayer insulating layer in the array substrate, and making the hydrogen content in the passivation layer greater than that in the interlayer insulating layer, the silicon nitride layer in the interlayer insulating layer is removed, the number of masks is reduced, photogenerated carriers are prevented from recombinating with dangling bonds, and the photogenerated leakage current is reduced.
This technology reduces photo-induced leakage current without the need for a light-shielding layer, thereby lowering costs, simplifying process steps, and improving the reliability and display effect of thin-film transistors.
Smart Images
Figure CN120916484A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel. BACKGROUND
[0002] With the development of display devices, the requirements of existing display devices on thin film transistors are higher and higher. Low-temperature polysilicon thin film transistors are widely used due to their fast switching speed and low power consumption. However, it is found that the leakage current of the low-temperature polysilicon thin film transistor is large after being irradiated by light. In order to reduce the photo-generated leakage current, a light shielding layer needs to be arranged under the active layer for light shielding. However, the arrangement of the light shielding layer needs to increase a mask plate, and each film layer of the thin film transistor needs to be patterned or a via hole is formed by using a mask plate, which leads to high cost and large process complexity. If the light shielding layer is not arranged, the photo-generated leakage current will be caused, the on-off current ratio of the device will be reduced, the contrast ratio and color accuracy of the display device will be affected, and the display will be poor.
[0003] Therefore, the existing display device has the technical problem that the photo-generated leakage current is large if the light shielding layer is not arranged. SUMMARY
[0004] Embodiments of the present application provide an array substrate, a preparation method thereof and a display panel, to solve the technical problem that the photo-generated leakage current is large if the light shielding layer is not arranged in the existing display device.
[0005] In order to achieve the above-mentioned purpose, according to a first aspect of the present application, an array substrate is provided, which comprises:
[0006] a substrate;
[0007] an active layer arranged on one side of the substrate;
[0008] a gate layer arranged on a side of the active layer away from the substrate;
[0009] an interlayer insulating layer arranged on a side of the gate layer away from the active layer;
[0010] a source-drain electrode layer arranged on a side of the interlayer insulating layer away from the gate layer;
[0011] a passivation layer arranged on a side of the source-drain electrode layer away from the interlayer insulating layer;
[0012] wherein the material of the passivation layer is different from that of the interlayer insulating layer, and the hydrogen content in the passivation layer is greater than that in the interlayer insulating layer.
[0013] According to a second aspect of the present application, a preparation method of an array substrate is provided, which prepares the array substrate according to any one of the above embodiments, and the preparation method comprises:
[0014] A substrate is provided, and a buffer layer, an active layer, a gate insulating layer and a gate layer, an interlayer insulating layer and a source-drain layer are sequentially formed on the substrate;
[0015] A passivation layer is formed on the source-drain layer, and the active layer is hydrogen-activated.
[0016] According to a third aspect of the present application, a display panel is also provided, which comprises the array substrate according to any one of the above embodiments.
[0017] The embodiments of the present application provide an array substrate and a preparation method thereof, and a display panel. By making the material of the passivation layer different from that of the interlayer insulating layer, and the hydrogen content in the passivation layer greater than that in the interlayer insulating layer, the silicon nitride layer in the interlayer insulating layer can be removed, so that the dangling bonds in the active layer will not be combined with the hydrogen in the silicon nitride layer in the interlayer insulating layer, and the density of the dangling bonds in the active layer is greater. When the photo-generated carriers are generated in the active layer, the photo-generated carriers will be combined with the dangling bonds, thereby reducing the photo-generated leakage current. Therefore, the effect of removing the light shielding layer and reducing the photo-generated leakage current can be achieved.
[0018] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.
[0020] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.
[0021] Figure 1 is a perspective view of a comparative display device.
[0022] Figure 2 is Figure 1 are the A-A sectional view and the B-B sectional view of the comparative display device in
[0023] Figure 3 is Figure 2 are the structure schematic diagrams of the comparative display device corresponding to some steps of the preparation method of the comparative display device in
[0024] Figure 4 For Figure 2 Another step of the preparation method of the array substrate in the comparative display device corresponds to the structural schematic diagram of the comparative display device.
[0025] Figure 5 The first perspective view of the array substrate provided by the embodiment of the present application.
[0026] Figure 6 For Figure 5 The cross-sectional schematic diagram of the array substrate in the comparative display device.
[0027] Figure 7 The second perspective view of the array substrate provided by the embodiment of the present application.
[0028] Figure 8 For Figure 7 The cross-sectional schematic diagram of the array substrate in the comparative display device.
[0029] Figure 9 The flow chart of the preparation method of the array substrate provided by the embodiment of the present application.
[0030] Figure 10 The structural schematic diagram of the array substrate corresponding to some steps of the preparation method of the array substrate provided by the embodiment of the present application.
[0031] Figure 11 The structural schematic diagram of the array substrate corresponding to some steps of another preparation method of the array substrate provided by the embodiment of the present application.
[0032] Figure 12 The curve diagram of the gate voltage and the drain current of the array substrate in the comparative display device and the embodiment of the present application. DETAILED DESCRIPTION
[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.
[0034] In order to explain the principle of the technical problem in the embodiments of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be used as the prior art in the embodiments of the present application. Figure 1 The perspective view of a comparative display device; Figure 2 The cross-sectional view of the comparative display device in Figure 1 The A-A cross-sectional view and the B-B cross-sectional view of the comparative display device in Figure 2 (a) in Figure 1A-A sectional view of the contrast display device in FIG. 1, Figure 2 (b) in FIG. 1 is Figure 1 B-B sectional view of the contrast display device in FIG. 1; Figure 3 is Figure 2 Structure schematic diagram of the contrast display device corresponding to some steps of the preparation method of the contrast display device in FIG. 1; Figure 4 is Figure 2 Structure schematic diagram of the contrast display device corresponding to some steps of the preparation method of the contrast display device in FIG. 1. As Figure 1 , Figure 2 As shown in FIG. 1, in order to shield light for the active layer, the contrast display device is provided with a light shielding film 12, so that the contrast display device comprises a substrate 11, the light shielding film 12, a first insulating film 13, an active film 14, a second insulating film 15, a gate film 16, a third insulating film, a source-drain film 18, a planarization film 191, a bottom electrode film 192, a passivation film 193 and a top electrode film 194, the active film 14 comprises a channel region 143, a light doped region 142 and a heavy doped region 141, the third insulating film comprises a silicon nitride film 171 and a silicon oxide film 172, the material of the silicon nitride film 171 is silicon nitride, and the material of the silicon oxide film 172 is silicon oxide.
[0035] Meanwhile, in the preparation of the contrast display device, the substrate is provided first, and the light shielding film is formed on the substrate, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 3 (a); the first insulating film and the active film are formed on the light shielding film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 3 (b); the second insulating film and the gate film are formed on the active film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 3 (c); the third insulating film is formed on the gate film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 3 (d); the source-drain film is formed on the third insulating film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 3 (e); the planarization film is formed on the source-drain film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 4 (a); the bottom electrode film is formed on the planarization film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 4 (b); the passivation film is formed on the bottom electrode film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 4 (c); the top electrode film is formed on the passivation film, the structure of the contrast display device corresponding to this step is shown in FIG. 1, Figure 2 (a).
[0036] From the preparation method of the contrast display device, it can be seen that 9 mask plates are required when forming the contrast display device, which are one mask plate for forming the light shielding film 12, one mask plate for forming the first insulating film 13 and the active film 14, one mask plate for forming the gate electrode film 16, one mask plate for forming the via hole of the third insulating film 17, one mask plate for forming the source-drain electrode film 18, one mask plate for forming the via hole of the planarization film 191, one mask plate for forming the bottom electrode film 192, one mask plate for forming the via hole of the passivation film 193, and one mask plate for forming the top electrode film 194. It can be seen that the number of mask plates required in the formation process of the contrast display device is large, and the process steps are more, which leads to a complex process for forming the contrast display device, high cost, and low preparation efficiency. However, not setting the light shielding film will cause the active layer to be exposed to light, resulting in photo-generated leakage current. Therefore, the existing display device has the technical problem that not setting the light shielding layer will cause large photo-generated leakage current.
[0037] The embodiment of the present application aims at the above technical problems, and provides an array substrate and a preparation method thereof, and a display panel, to solve the above technical problems.
[0038] Figure 5 The first perspective view of the array substrate provided by the embodiment of the present application. Figure 6 The cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2B. Figure 5 The cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2B. Figure 6 The A-A cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2C. Figure 5 The A-A cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2C.
[0039] Figure 6 The B-B cross-sectional schematic view of the array substrate in (b) is as shown in FIG. 2D. Figure 5 The B-B cross-sectional schematic view of the array substrate in (b) is as shown in FIG. 2D. Figure 7 The second perspective view of the array substrate provided by the embodiment of the present application. Figure 8 The cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2B. Figure 7 The cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2B. Figure 8 The A-A cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2C. Figure 7 The A-A cross-sectional schematic view of the array substrate in (a) is as shown in FIG. 2C. Figure 8 The B-B cross-sectional schematic view of the array substrate in (b) is as shown in FIG. 2D. Figure 7 The B-B cross-sectional schematic view of the array substrate in (b) is as shown in FIG. 2D. Figure 9 The flow chart of the preparation method of the array substrate provided by the embodiment of the present application. Figure 10 The structure schematic view of the array substrate corresponding to some steps of the preparation method of the array substrate provided by the embodiment of the present application. Figure 11 The structure schematic view of the array substrate corresponding to some steps of the preparation method of the array substrate provided by the embodiment of the present application. Figure 12 The curve graph of the gate voltage and the leakage current of the array substrate in the contrast display device and the embodiment of the present application.
[0040] As Figure 5 to Figure 8 shown, the embodiment of the present application provides an array substrate, which comprises a substrate 21, an active layer 23, a gate layer 25, an interlayer insulating layer 26, a source-drain layer 27, a passivation layer 28 and a transparent electrode layer 29. The active layer 23 is arranged on one side of the substrate 21. The gate layer 25 is arranged on a side of the active layer 23 away from the substrate 21. The interlayer insulating layer 26 is arranged on a side of the gate layer 25 away from the active layer 23. The source-drain layer 27 is arranged on a side of the interlayer insulating layer 26 away from the gate layer 25. The passivation layer 28 is arranged on a side of the source-drain layer 27 away from the interlayer insulating layer 26. The material of the passivation layer 28 is different from that of the interlayer insulating layer 26, and the hydrogen content in the passivation layer 28 is greater than that in the interlayer insulating layer 26.
[0041] The embodiment of the present application provides an array substrate 2. By making the material of the passivation layer 28 different from that of the interlayer insulating layer 26, and the hydrogen content in the passivation layer 28 greater than that in the interlayer insulating layer 26, the silicon nitride layer in the interlayer insulating layer can be removed, so that the dangling bonds in the active layer 23 will not be combined with the hydrogen in the silicon nitride layer in the interlayer insulating layer, and the density of the dangling bonds in the active layer 23 is greater. When the photo-generated carriers are generated in the active layer, the photo-generated carriers will be combined with the dangling bonds, so that the photo-generated leakage current is reduced, and the effect of removing the light shielding layer and reducing the photo-generated leakage current can be achieved. Figure 5 to Figure 8 As
[0042] As Figure 5 to Figure 8As shown, the embodiment of the present application provides an array substrate, the array substrate comprises a substrate 21, an active layer 23, a gate layer 25, an interlayer insulating layer 26, a source-drain layer 27, a passivation layer 28 and a transparent electrode layer 29, the active layer 23 is arranged on one side of the substrate 21, the gate layer 25 is arranged on the side of the active layer 23 away from the substrate 21, the interlayer insulating layer 26 is arranged on the side of the gate layer 25 away from the active layer 23, the source-drain layer 27 is arranged on the side of the interlayer insulating layer 26 away from the gate layer 25, the passivation layer 28 is arranged on the side of the source-drain layer 27 away from the interlayer insulating layer 26, and the transparent electrode layer 29 is arranged on the side of the passivation layer 28 away from the source-drain layer 27, the transparent electrode layer 29 comprises a pixel electrode 291 and a common electrode 292; wherein the material of the passivation layer 28 is different from that of the interlayer insulating layer 26, and the hydrogen content in the passivation layer 28 is greater than that in the interlayer insulating layer 26.
[0043] The embodiment of the present application provides an array substrate, the array substrate 2 by making the transparent electrode layer 29 include the pixel electrode 291 and the common electrode 292, so that the pixel electrode and the common electrode do not need to be arranged separately, the number of required mask plates is reduced, and the planarization layer does not need to be arranged, the number of required mask plates is reduced, the film layer thickness of the array substrate is reduced, and by making the material of the passivation layer 28 different from that of the interlayer insulating layer 26, and the hydrogen content in the passivation layer 28 greater than that in the interlayer insulating layer, the light shielding layer can be removed, and the silicon nitride layer in the interlayer insulating layer can be removed, so that the density of dangling bonds in the active layer is greater, and the excessive large leakage current caused by the small density of dangling bonds in the active layer when the light shielding layer is removed is avoided, and the leakage current is reduced; the effect of reducing the leakage current and the number of mask plates is achieved.
[0044] Specifically, it can be understood that in the contrast display device, the third insulating film includes a silicon nitride film 171 and a silicon oxide film 172, and the hydrogen content in the silicon nitride film 171 is high, so that the hydrogen in the silicon nitride film 171 diffuses to the silicon dangling bonds on the surface of the active film to form Si-H bonds, so that the density of silicon dangling bonds on the surface of the active film is small. When the light shielding film is arranged in the contrast display device, the light shielding film can shield light, so that even if the density of silicon dangling bonds on the surface of the active film is small, the light cannot reach the surface of the active film or the light reaching the surface of the active film is small, so that the photo-induced leakage current of the thin film transistor is small. In the contrast display device in which the light shielding film is removed, since there is no shielding of the light shielding film, light will irradiate to the active film, and the hydrogen in the silicon nitride film 171 will diffuse to the silicon dangling bonds on the surface of the active film to form Si-H bonds, so that the density of silicon dangling bonds on the surface of the active film is small, so that the photo-induced carrier density is large, resulting in large photo-induced leakage current of the thin film transistor.
[0045] The embodiment of the present application can remove the silicon nitride layer in the interlayer insulating layer by making the passivation layer and the material of the interlayer insulating layer different, and the hydrogen content in the passivation layer is greater than the hydrogen content in the interlayer insulating layer, so that the density of the silicon dangling bond on the surface of the active layer is greater. When the light irradiates the active layer, the photo-generated carriers will recombine at the defects on the surface of the active layer, reducing the photo-generated carriers, reducing the photo-generated leakage current, and because the photo-generated leakage current is small, the light shielding film can not be arranged, thereby reducing the number of required mask plates, achieving the effect of reducing the leakage current and reducing the number of mask plates. And removing the silicon nitride layer in the interlayer insulating layer can reduce the thickness of the array substrate and reduce the cost.
[0046] And in the embodiment of the present application, the transparent electrode layer includes a pixel electrode and a common electrode, without the need to arrange a planarization layer and an electrode layer, reducing the number of film layers of the display panel and reducing the number of required mask plates.
[0047] In some embodiments, the material of the passivation layer 28 is silicon nitride, and the material of the interlayer insulating layer 26 is silicon oxide. By making the material of the interlayer insulating layer 26 silicon oxide and removing the silicon nitride layer in the interlayer insulating layer 26, the density of the silicon dangling bond on the surface of the active layer can be increased, the deep level defects can be increased, the photo-induced electron-hole pairs can be effectively captured and recombined, the number of free carriers can be reduced, the photo-generated leakage current can be reduced, and the stability of the thin film transistor can be improved. And the material of the passivation layer 28 is silicon nitride, which can reduce the density of the silicon dangling bond on the surface of the active layer to a certain extent, and improve the reliability of the thin film transistor.
[0048] Specifically, in the comparative display device, even if the passivation film is made of silicon nitride, the hydrogen content of the silicon nitride film in the third insulating film will be greater than the hydrogen content in the passivation film, so that the density of the silicon dangling bond on the surface of the active film is small, and the photo-generated leakage current is large. However, in the embodiment of the present application, the material of the interlayer insulating layer is silicon oxide, and the silicon nitride in the interlayer insulating layer is removed, so that the hydrogen content in the interlayer insulating layer is small or even no hydrogen in the interlayer insulating layer, so that the density of the silicon dangling bond on the surface of the active layer is large, and the defect state density is large. When the light irradiates the active layer, the photo-generated carriers will recombine at the defect states, reducing the number of free carriers, thereby reducing the photo-generated leakage current. In order to avoid the density of the silicon dangling bond being too large and the defect state density being too large to reduce the reliability of the thin film transistor, the material of the passivation layer can be made of silicon nitride, and the hydrogen in the silicon nitride in the passivation layer can be combined with some silicon dangling bonds to reduce the density of the silicon dangling bond and improve the reliability of the thin film transistor.
[0049] Specifically, the array substrate includes a thin film transistor.
[0050] In some embodiments, the atomic percentage hydrogen content in the passivation layer 28 is 5% to 13%; that is, the hydrogen content in the passivation layer 28 ranges from 5 at% (atomic percentage) to 13 at% (atomic percentage), so that the density of silicon dangling bonds on the active layer surface is neither too large nor too small, thereby reducing the photo-generated leakage current and improving the reliability of the thin film transistor.
[0051] Specifically, in the comparative display device, the atomic percentage hydrogen content in the nitrogen-silicon film in the third insulating film is much greater than 13%, so that the hydrogen in the nitrogen-silicon film diffuses to the active film surface and forms Si-H bonds with the silicon dangling bonds, which results in that the density of silicon dangling bonds on the active film surface is too small, and in the absence of the light shielding film, the number of photo-generated free carriers that can recombine on the active film surface is too small, resulting in that the photo-generated leakage current is too large; and in some comparative display devices, after the nitrogen-silicon film in the third insulating film is removed, even if the passivation layer is formed of silicon nitride, the atomic percentage hydrogen content in the passivation layer is less than or equal to 4%, so that the number of hydrogen elements that can recombine with the silicon dangling bonds on the active film surface is too small, and the density of silicon dangling bonds on the active film surface is too large, so that although the photo-generated leakage current can be reduced, the density of silicon dangling bonds on the active film surface is too large, resulting in that the acceptor defect state on the active film surface is too large, the number of carriers is too small, and the mobility of the device is reduced, and the thin film transistor is prone to avalanche breakdown, device parameter drift and other problems, resulting in that the reliability of the thin film transistor is reduced.
[0052] Based on the above technical problems, in the embodiments of the present application, the silicon nitride layer in the interlayer insulating layer is removed, so that the atomic percentage hydrogen content in the passivation layer is 5% to 13%, so that the density of silicon dangling bonds in the active layer is controllable, and the density of silicon dangling bonds in the active layer is neither too large nor too small, thereby reducing the photo-generated leakage current and improving the reliability of the thin film transistor.
[0053] Specifically, it can be understood that, in the comparative display device, because the planarization film exists, the passivation layer cannot be subjected to high-temperature process treatment to control the hydrogen content, and in the embodiments of the present application, the transparent electrode layer includes the pixel electrode and the common electrode, so that the planarization layer is not required, and the passivation layer can be subjected to high-temperature process treatment to control the hydrogen content, so that the atomic percentage hydrogen content in the passivation layer is 5% to 13%, thereby reducing the photo-generated leakage current and improving the reliability of the thin film transistor.
[0054] Specifically, it can be seen that the atomic percentage hydrogen content of the passivation layer in the comparative display device is low when the passivation layer is formed by using silicon nitride, the atomic percentage hydrogen content of the passivation layer before hydrogenation is 5%, and the atomic percentage hydrogen content of the passivation layer after hydrogenation is 2% to 4%; and in the embodiment of the present application, the planarization layer can be removed, the high-temperature silicon nitride film can be used, the flow of SiH4(silane) and NH3(ammonia) can be increased, and the power can be increased to increase the hydrogen content in the passivation layer, so that the atomic percentage hydrogen content of the passivation layer before hydrogenation is 8% to 15%, and the atomic percentage hydrogen content of the passivation layer after hydrogenation is 5% to 13%. The hydrogen in the passivation layer can diffuse to the surface of the active layer and combine with a part of the silicon dangling bonds, so as to reduce the density of the silicon dangling bonds and improve the reliability of the thin film transistor.
[0055] Specifically, it can be understood that when the atomic percentage hydrogen content of the passivation layer is 5% to 13%, the third insulating film in the comparative display device includes a silicon nitride film, the density of the dangling bonds on the surface of the active layer in the embodiment of the present application is greater than the density of the dangling bonds on the surface of the active layer in the comparative display device; and when the atomic percentage hydrogen content of the passivation layer is 5% to 13%, the third insulating film in the comparative display device only includes a silicon oxide film, and the material of the passivation layer is silicon oxide or the material of the passivation layer is silicon nitride, but the atomic percentage hydrogen content of the passivation layer is less than or equal to 4%, the density of the dangling bonds on the surface of the active layer in the embodiment of the present application is less than the density of the dangling bonds on the surface of the active layer in the comparative display device. The photogenerated leakage current of the thin film transistor in the embodiment of the present application is small, and the reliability of the thin film transistor is good.
[0056] Specifically, it can be understood that when the passivation layer is treated to diffuse hydrogen elements to the active layer, the hydrogen elements in the part of the passivation layer corresponding to the active layer can be diffused, or the hydrogen elements in each region of the passivation layer can be diffused. It can be understood that after the hydrogen elements in the part of the passivation layer corresponding to the active layer diffuse to the active layer, the hydrogen elements will combine with the silicon dangling bonds, and after the hydrogen elements in other regions diffuse, the hydrogen elements may not combine with other ions or the hydrogen elements that combine are less, so that the hydrogen elements will remain in other regions and other film layers, for example, will remain in the interlayer insulating layer, the gate insulating layer and the buffer layer. The embodiment of the present application does not limit this, and the hydrogen elements in other regions may also combine with the ions of other film layers after diffusion.
[0057] In some embodiments, the material of the active layer 23 is polysilicon, and the density of the dangling bonds of the silicon in the active layer 23 ranges from 1*10 20 / per square centimeter to 5*10 20 / per square centimeter; by making the density of the dangling bonds of the silicon in the active layer range from 1*10 20 / per square centimeter to 5*10 20 / per square centimeter, so that the density of the dangling bonds of the silicon in the active layer is not too small, so that the photo-induced leakage current of the thin film transistor is small; and the density of the dangling bonds of the silicon in the active layer is not too large, to avoid problems such as avalanche breakdown and device parameter drift of the thin film transistor, improve the reliability of the thin film transistor, and improve the service life of the thin film transistor.
[0058] In some embodiments, as shown in Figure 5 、 Figure 6 The array substrate 2 further includes a buffer layer 22, which is arranged between the substrate 21 and the active layer 23, and each part of the substrate 21 is in direct contact with the buffer layer 22. By making each part of the substrate in direct contact with the buffer layer, the light shielding layer does not need to be arranged when the array substrate is formed, and accordingly, the mask plate for forming the light shielding layer is not needed, thereby reducing the number of mask plates required by the array substrate.
[0059] Specifically, compared with the display device in which the light shielding layer needs to be arranged for light shielding to avoid the photo-induced leakage current of the thin film transistor being too large, the embodiment of the present application removes the silicon nitride layer in the interlayer insulating layer, increases the density of the dangling bonds on the surface of the active layer, and reduces the photo-induced leakage current, so that the light shielding layer does not need to be arranged, and the number of mask plates required by the array substrate can be reduced; and the density of the dangling bonds on the surface of the active layer can be reduced to a certain extent by processing the passivation layer, and the reliability of the thin film transistor is improved, thereby achieving the reduction of the number of mask plates required by the array substrate, the reduction of the photo-induced leakage current, and the improvement of the reliability of the thin film transistor.
[0060] Specifically, the material of the buffer layer can be silicon oxide.
[0061] Specifically, as shown in Figure 5 、 Figure 6 It can be seen that the array substrate 2 further includes a gate insulating layer 24, which is arranged between the active layer 23 and the gate layer 25.
[0062] Specifically, the material of the gate insulating layer 24 can be silicon oxide.
[0063] Specifically, as shown in Figure 5 、 Figure 6 It can be seen that the substrate 21, the buffer layer 22, the active layer 23, the gate insulating layer 24, the gate layer 25, the interlayer insulating layer 26, the source-drain layer 27, the passivation layer 28, and the transparent electrode layer 29 are sequentially arranged.
[0064] Specifically, as shown in Figure 5 、 Figure 6As shown, the active layer 23 includes an active pattern 231, which includes a channel portion 231a and doped portions disposed on both sides of the channel portion 231a. The doped portions include a lightly doped portion 231b and a heavily doped portion 231c. The lightly doped portion 231b is disposed between the heavily doped portion 231c and the channel portion 231a. The doping concentration of the lightly doped portion 231b is greater than the doping concentration of the channel portion 231a and less than the doping concentration of the heavily doped portion 231c.
[0065] Specifically, Figure 6 The example described uses a doped portion including a lightly doped portion 231b and a heavily doped portion 231c, but the embodiments of this application are not limited to this, and the doped portion may only include the heavily doped portion.
[0066] In some embodiments, the thickness of the passivation layer 28 ranges from 600 angstroms to 2000 angstroms. By making the thickness of the passivation layer 28 from 600 angstroms to 2000 angstroms, the photo-generated leakage current of the thin-film transistor is reduced, and the liquid crystal capacitance of the thin-film transistor is increased, enabling the array substrate to operate normally.
[0067] In some embodiments, such as Figure 7 , Figure 8 As shown, the array substrate 2 further includes a buffer layer 22 and a light-shielding layer 31. The light-shielding layer 31 is disposed between the substrate 21 and the buffer layer 22, and the buffer layer 22 is disposed between the light-shielding layer 31 and the active layer 23. The light-shielding layer 31 includes a light-shielding pattern 311, and the active layer 23 includes an active pattern 231. The light-shielding pattern 311 corresponds to the active pattern 231. By including the light-shielding layer 31 in the array substrate, the photogenerated leakage current can be further reduced, and the silicon nitride layer in the interlayer insulating layer can be removed, reducing costs. At the same time, the reliability of the thin-film transistor is improved by the recombination of hydrogen elements in the passivation layer with silicon dangling bonds in the active layer to form Si-H bonds.
[0068] Specifically, such as Figure 7 , Figure 8 As shown, the array substrate 2 also includes a gate insulating layer 24, which is disposed between the active layer 23 and the gate layer 25.
[0069] Specifically, the material of the gate insulating layer 24 can be silicon oxide.
[0070] Specifically, such as Figure 7 , Figure 8 As shown, the substrate 21, light-shielding layer 31, buffer layer 22, active layer 23, gate insulating layer 24, gate layer 25, interlayer insulating layer 26, source-drain layer 27, passivation layer 28 and transparent electrode layer 29 are arranged sequentially.
[0071] Specifically, such as Figure 7 ,Figure 8 As shown, the active layer 23 includes an active pattern 231, which includes a channel portion 231a and doped portions disposed on both sides of the channel portion 231a. The doped portions include a lightly doped portion 231b and a heavily doped portion 231c. The lightly doped portion 231b is disposed between the heavily doped portion 231c and the channel portion 231a. The doping concentration of the lightly doped portion 231b is greater than the doping concentration of the channel portion 231a and less than the doping concentration of the heavily doped portion 231c.
[0072] Specifically, Figure 8 The example described uses a doped portion including a lightly doped portion 231b and a heavily doped portion 231c, but the embodiments of this application are not limited to this, and the doped portion may only include the heavily doped portion.
[0073] In some embodiments, such as Figure 7 , Figure 8 As shown, the thickness of the passivation layer ranges from 600 angstroms to 4000 angstroms.
[0074] In some embodiments, such as Figure 5 to Figure 8 As shown, the passivation layer 28 is in direct contact with the transparent electrode layer 29, and the passivation layer 28 is in direct contact with the source / drain layer 27. By making the passivation layer 28 in direct contact with the transparent electrode layer 29 and the source / drain layer 27, there is no need to set a planarization layer, and correspondingly, there is no need for a mask to form the vias of the planarization layer, reducing the number of masks on the array substrate. Furthermore, without a planarization layer, the passivation layer can be processed using a high-temperature process, increasing the hydrogen content in the passivation layer. This ensures that the density of dangling bonds in the active layer is neither too high nor too low, reducing the leakage current of the thin-film transistor and improving the reliability of the array substrate.
[0075] Specifically, the substrate material includes glass.
[0076] Specifically, the active layer material includes polycrystalline silicon.
[0077] Specifically, the material of the light-shielding layer includes molybdenum.
[0078] Specifically, the material of the transparent electrode layer includes indium tin oxide.
[0079] Specifically, the above embodiments have provided a detailed description of the array substrate from the aspects of film layer design, structure of each film layer, and material design. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the active layer is made of polysilicon and the transparent electrode layer is made of indium tin oxide.
[0080] Specifically, the FTIR spectrum of the passivation layer can be measured by FTIR (Fourier Transform Infrared Spectroscopy) method, and the hydrogen concentration can be calculated by integrating the Si-H and N-H absorption peak area. The hydrogen concentration of the passivation layer can also be measured by SIMS (Secondary Ion Mass Spectrometry) method. Specifically, the surface of the passivation film can be sputtered by ion beam, and the secondary ion signal can be collected and analyzed. The quantitative curve can be established by comparing the standard sample, and the hydrogen concentration can be calculated.
[0081] As shown in Figure 12 , taking the array substrate in which the atomic percentage hydrogen content of the passivation layer is 5% to 13% in the comparative display device and the array substrate in the embodiment of the present application as an example for comparison, Figure 12 , the abscissa in Figure 12 is the gate voltage, and the unit is volt, Figure 12 , the ordinate in Figure 12 is the leakage current, and the unit is ampere. Curve 1 is the curve of the gate voltage and the leakage current of the comparative display device, and curve 2 is the curve of the gate voltage and the leakage current of the array substrate in the embodiment of the present application. As can be seen from , when the gate voltage is less than or equal to 0, it means that the thin film transistor is in the off state, and as can be seen from
[0082] , the leakage current in the embodiment of the present application is smaller than that of the comparative display device, and the leakage current is reduced.
[0083] Meanwhile, the embodiment of the present application provides a preparation method of an array substrate, which prepares the array substrate as described in any one of the above embodiments. Figure 9 In some embodiments, as shown in
[0084] , the preparation method of the array substrate comprises: Figure 10 Figure 10 , (d) in Figure 11 , (a) to Figure 11 , (e) in
[0085] S2, forming a passivation layer on the source-drain layer, and hydrogen activating the active layer; the structure of the array substrate corresponding to this step is shown in (e), Figure 10 , (f) in Figure 11 .
[0086] The embodiment of the present application provides a preparation method of an array substrate, the array substrate prepared by the preparation method of the array substrate removes a silicon nitride layer in an interlayer insulating layer, performs hydrogen activation on an active layer after forming a passivation layer, so that the density of dangling bonds in the active layer is not too small, the too small density of the dangling bonds in the active layer avoids too large leakage current when removing a light shielding layer, the leakage current is reduced, and the density of the dangling bonds in the active layer is not too large, and the reliability of the array substrate is improved.
[0087] In some embodiments, after the step of forming the passivation layer on the source-drain layer and performing hydrogen activation on the active layer, the method further comprises: forming a transparent electrode layer on the passivation layer and patterning the transparent electrode layer, and the structure of the array substrate corresponding to the step is as shown in Figure 5 、 Figure 7 .
[0088] In some embodiments, the step of providing a substrate and sequentially forming a buffer layer, an active layer, a gate insulating layer and a gate layer, an interlayer insulating layer and a source-drain layer on the substrate comprises:
[0089] providing a substrate and forming a buffer layer and an active layer on the substrate and patterning the active layer; the structure of the array substrate corresponding to the step is as shown in (a) of Figure 10 ;
[0090] forming a gate insulating layer and a gate layer on the active layer and patterning the gate layer; the structure of the array substrate corresponding to the step is as shown in (b) of Figure 10 ;
[0091] forming an interlayer insulating layer on the gate layer and etching the interlayer insulating layer to form a via; the structure of the array substrate corresponding to the step is as shown in (c) of Figure 10 ;
[0092] forming a source-drain layer on the interlayer insulating layer and patterning the source-drain layer; the structure of the array substrate corresponding to the step is as shown in (d) of Figure 10 .
[0093] Specifically, the pattern of the active layer is formed by one mask plate, the pattern of the gate layer is formed by one mask plate, the via of the interlayer insulating layer and the gate insulating layer is formed by one mask plate, the pattern of the source-drain layer is formed by one mask plate, the via of the passivation layer is formed by one mask plate, and the pattern of the transparent electrode layer is formed by one mask plate, so it can be seen that only six mask plates are needed to form the array substrate, and the number of required mask plates is reduced.
[0094] In some embodiments, the step of providing a substrate and sequentially forming a buffer layer, an active layer, a gate insulating layer and a gate layer, an interlayer insulating layer and a source-drain layer on the substrate comprises:
[0095] A substrate is provided, and a light shielding layer is formed on the substrate and is patterned; the structure of the array substrate corresponding to this step is shown as (a) in FIG. 1; Figure 11
[0096] A buffer layer and an active layer are formed on the light shielding layer, and the active layer is patterned; the structure of the array substrate corresponding to this step is shown as (b) in FIG. 1; Figure 11
[0097] A gate insulating layer and a gate layer are formed on the active layer, and the gate layer is patterned; the structure of the array substrate corresponding to this step is shown as (c) in FIG. 1; Figure 11
[0098] An interlayer insulating layer is formed on the gate layer, and the interlayer insulating layer is etched to form a via hole; the structure of the array substrate corresponding to this step is shown as (d) in FIG. 1; Figure 11
[0099] A source-drain layer is formed on the interlayer insulating layer, and the source-drain layer is patterned; the structure of the array substrate corresponding to this step is shown as (e) in FIG. 1. Figure 11
[0100] Specifically, the pattern of the light shielding layer is formed by one mask plate, the pattern of the active layer is formed by one mask plate, the pattern of the gate layer is formed by one mask plate, the via hole of the interlayer insulating layer and the gate insulating layer is formed by one mask plate, the pattern of the source-drain layer is formed by one mask plate, the via hole of the passivation layer is formed by one mask plate, and the pattern of the transparent electrode layer is formed by one mask plate. It can be seen that only seven mask plates are needed to form the array substrate, thereby reducing the number of mask plates required.
[0101] Meanwhile, the display panel provided in the embodiments of the present application comprises the array substrate according to any one of the above embodiments.
[0102] Specifically, the display panel can comprise an array substrate, a color film substrate and a liquid crystal layer; but the embodiments of the present application are not limited thereto, and the display panel can be other display panels.
[0103] Specifically, the display device provided in the embodiments of the present application comprises the display panel according to any one of the above embodiments.
[0104] Specifically, the display device can comprise a backlight module.
[0105] In the description of the application, the terms "first", "second", "third" and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0106] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.
[0107] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.
[0108] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment in accordance with the technical essence of the present application without departing from the technical solution content of the present application still falls within the scope of the technical solution of the present application.
Claims
1. An array substrate, characterized by, The array substrate comprises: a substrate; an active layer disposed on one side of the substrate; a gate layer disposed on a side of the active layer away from the substrate; an interlayer insulating layer disposed on a side of the gate layer away from the active layer; a source-drain layer disposed on a side of the interlayer insulating layer away from the gate layer; a passivation layer disposed on a side of the source-drain layer away from the interlayer insulating layer; wherein the passivation layer and the interlayer insulating layer are made of different materials, and the hydrogen content in the passivation layer is greater than that in the interlayer insulating layer.
2. The array substrate of claim 1, wherein, The passivation layer is made of silicon nitride, and the interlayer insulating layer is made of silicon oxide.
3. The array substrate of claim 2, wherein, The atomic percentage hydrogen content in the passivation layer is 5% to 13%.
4. The array substrate of claim 3, wherein, The material of the active layer is polysilicon, the density of the dangling bond of the silicon in the active layer ranges from 1*10 20 / per square centimeter to 5*10 20 / per square centimeter.
5. The array substrate of claim 3, wherein, The array substrate further comprises a buffer layer disposed between the substrate and the active layer, and each part of the substrate is in direct contact with the buffer layer.
6. The array substrate of claim 3, wherein, The array substrate further comprises a buffer layer and a light-shielding layer, the light-shielding layer is disposed between the substrate and the buffer layer, and the buffer layer is disposed between the light-shielding layer and the active layer. The light-shielding layer comprises a light-shielding pattern, and the active layer comprises an active pattern, the light-shielding pattern is disposed corresponding to the active pattern.
7. The array substrate according to any one of claims 1 to 6, wherein, The array substrate further comprises a transparent electrode layer disposed on a side of the passivation layer away from the source-drain layer, the transparent electrode layer comprises a pixel electrode and a common electrode.
8. The array substrate of claim 7, wherein, The passivation layer is in direct contact with the transparent electrode layer, and the passivation layer is in direct contact with the source-drain layer.
9. A method for fabricating an array substrate, characterized in that, The array substrate as claimed in any one of claims 1 to 8 is prepared by a method comprising: providing a substrate, and sequentially forming a buffer layer, an active layer, a gate insulating layer and a gate layer, an interlayer insulating layer and a source-drain layer on the substrate; forming a passivation layer on the source-drain layer, and performing hydrogen activation on the active layer.
10. A display panel, characterized by, The array substrate as claimed in any one of claims 1 to 8.