Cooling structure of electronic device

Abstract

A cooling structure having a first side and a second side opposite the first side may be formed by a method including: forming an inlet and an outlet in a first substrate; forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and the outlet; forming a plurality of nozzles on the first side of the second substrate; and forming a plurality of channels on the second side of the second substrate opposite to the first side of the second substrate. The plurality of channels are aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Description

[0001] Reference to Related Applications

[0002] This application claims priority to U.S. Application No. 18 / 398,984, entitled “ELECTRONIC DEVICE COOLING STRUCTURES,” filed on December 28, 2023, and U.S. Provisional Application No. 63 / 483,944, entitled “SEMICONDUCTOR DEVICE COOLING STRUCTURES,” filed on February 8, 2023, the disclosures of which are incorporated herein by reference in their entirety for all purposes TECHNICAL FIELD

[0003] The present disclosure is directed to electronic device cooling structures. Some specific examples are directed to direct bonding structures. BACKGROUND

[0004] Cooling structures can be disposed over and bonded to semiconductor elements, such as integrated device dies, and utilize a liquid or coolant to be flowed through cavities or channels within the cooling structure. The cooling structure can be bonded to the semiconductor elements or integrated device dies to be cooled. A pump can be used to help facilitate the flow of the liquid through the cooling structure. BRIEF DESCRIPTION OF DRAWINGS

[0005] These and other features, aspects, and advantages of the present disclosure will be described in connection with certain specific examples, with reference to the following drawings, which are intended to illustrate but not to limit the disclosure. It will be understood that the attached drawings are intended to be illustrative and not limiting of the concepts disclosed herein. The following drawings set forth illustrative examples of the presently disclosed technology and are not intended to limit the scope of what is described herein.

[0006] Figures 1A-1B is a schematic cross-section to illustrate a direct bonding process according to some examples.

[0007] Figure 2A is a schematic plan view to show channels in a liquid cooling structure.

[0008] Figure 2B is a schematic cross-section taken along line 2B-2B of FIG. 2B along the length of parallel channels in the upper and lower blocks of the cooling structure. Figure 2A

[0009] Figure 2C is a schematic cross-section taken along line 2C-2C of FIG. 2C across the width of two parallel channels in the upper and lower blocks of the cooling structure. Figure 2A

[0010] Figure 3A ​​A schematic plan view showing the horizontal positions of non-parallel channels intersecting in a cooling structure, according to another specific example.

[0011] Figure 3B A schematic cross-section taken along line 3A-3A of FIG. 3A showing the horizontal positions of non-parallel channels intersecting in a cooling structure, according to some specific examples. Figure 3A

[0012] Figure 3C A schematic cross-section taken along line 3B-3B of FIG. 3B showing the horizontal positions of non-parallel channels intersecting in a cooling structure, according to some specific examples. Figure 3A

[0013] Figures 4A-4E A schematic cross-section showing an exemplary process for forming a cooling structure, according to some specific examples.

[0014] Figure 5 A schematic cross-section showing an exemplary specific example of a package structure.

[0015] Figure 6 A schematic cross-section showing an exemplary specific example of a package structure connected to an inlet pump and an outlet pump.

[0016] Throughout the specification and drawings like reference numerals are used to refer to like elements throughout the specification and drawings. DETAILED DESCRIPTION

[0017] While several specific examples, examples, and drawings are disclosed herein, it is understood that the application described herein extends beyond the specifically disclosed examples, examples, and drawings, and includes other uses of the application and obvious modifications and equivalents thereof. The examples described herein are presented by way of example to provide an adequate description of the methodologies and procedures disclosed herein. The terminology used herein is for the purpose of describing the specific examples and is not intended to be limiting. Additionally, the specific examples of the application can include numerous novel features, and no single feature is solely responsible for its desirable attributes or is essential to practicing the application described herein.

[0018] As feature sizes shrink, density increases, and more functionality is brought into a single semiconductor chip, the need for efficient heat removal increases. Liquid cooling has been one option for cooling semiconductor chips. However, there are serious limitations to current technology. For example, liquid cooling solutions are often deployed relatively far away from the chip itself. For example, a liquid cooling solution can be placed on top of a heat spreader or heat sink. It is possible to bring liquid cooling closer to the semiconductor chip itself, but there are a number of complications.

[0019] ​​Inadequate cooling of semiconductor devices can result in reduced performance, increased errors, reduced lifespan, and the like. Providing adequate cooling can be particularly challenging for semiconductor devices fabricated using advanced processing nodes, where features can be densely packed together, generating a large amount of heat in a relatively small area. Accordingly, improved cooling solutions are needed.

[0020] According to some embodiments herein, heat transport away from a semiconductor chip can be improved via spraying liquid onto the backside of the chip. According to some embodiments, multiple spray nozzles, multiple channels, or both can be used to facilitate liquid flow (also referred to herein as a spray stream). In some embodiments, multiple spray streams can be provided. In some embodiments, the spray streams can be arranged in a regular pattern. In some embodiments, the spray streams can be distributed non-uniformly. For example, there can be an increased density of spray streams over regions of the semiconductor chip that can generate the most heat.

[0021] In some embodiments, the cooling structure can include one or more layers. In some embodiments, each layer can be formed on a different substrate. In some embodiments, the substrates can be directly bonded to each other. In some embodiments, the channel structure can be directly bonded to the semiconductor chip. In some embodiments, wafer-to-wafer bonding can be used. In some embodiments, die-to-wafer bonding can be used. In some embodiments, die-to-die bonding can be used. In some embodiments, a combination of wafer-to-wafer bonding, die-to-wafer bonding, and / or die-to-die bonding can be used.

[0022] The channel structure can provide a number of advantages. If a large open chamber is used, structural integrity can be compromised. For example, if subjected to high pressure, cracking or breaking can occur, which can result in reduced cooling efficiency, or in some cases, render the device inoperable. By maintaining a relatively low flow rate and pressure, this problem can be mitigated to some extent, but since the flow rate is relatively slow and the liquid is in contact with the semiconductor chip for a longer period of time, cooling capacity can be limited. The channels can provide structural reinforcement, enabling higher pressure. In some embodiments, the layers defining the channels can be directly bonded to the semiconductor die without adhesive. In addition to providing structural support, the channels can provide some degree of thermal isolation, which can reduce heat transport from one region of the semiconductor chip to another via the cooling liquid.

[0023] In some embodiments, a pump can be used to flow liquid into the cooling structure. In some embodiments, a pump can be used to remove liquid from the cooling structure. As described in more detail below Figure 6As shown in the middle, in some embodiments, the use of an extraction pump can cause a pressure differential that creates an air gap in the lower chamber. The formation of an air gap can improve performance. The nozzle can taper to cause the pressure to increase as the cooling liquid flows through the nozzle, causing the spray to enter the lower chamber. If the lower chamber is filled with liquid, the liquid can slow the spray. If there is an air gap, the liquid can impact the semiconductor chip at a relatively high velocity, which can increase cooling performance.

[0024] Various embodiments disclosed herein are directed to direct bonding structures in which two or more elements can be directly bonded to one another without intervening adhesive. These processes and structures are referred to herein as "direct bonding" processes or "direct bonding" structures. Direct bonding can involve bonding a material on one element and a material on another element (also referred to herein as "uniform" direct bonding), where the materials on different elements need not be the same, without a traditional adhesive material. Direct bonding can also involve bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0025] In some embodiments (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material on each element is directly bonded. Exemplary uniform direct bonding processes include the Technologies available from Adeia Corporation of San Jose, CA. The materials of the opposing bonding layers on different elements can be the same or different, and can include elemental or compound materials. For example, in some embodiments, a non-conductive bonding layer can be blanket deposited over a portion of a base substrate without patterning of conductive features (e.g., without a liner). In other embodiments, the bonding layers can be patterned on one or both elements, and can be the same or different from one another, but one material from each element directly bonds across the surface of the element (or across the surface of the smaller element in the case of different sizes of elements) without adhesive. In another embodiment of uniform direct bonding, one or both of the non-conductive bonding layers can include one or more conductive features, but the conductive features do not participate in the bonding. For example, in some embodiments, opposing non-conductive bonding layers can be uniformly directly bonded to one another, and through substrate vias (TSVs) can be subsequently formed through one element after bonding to provide electrical communication to the other element.

[0026] In various embodiments, the bonding layer 108a and / or 108b can include a non- conductive material, such as a dielectric material or an undoped semiconductor material, such as undoped silicon, which can include a native oxide. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon carbon oxynitride, low-K dielectric materials, SICOH dielectrics, silicon carbonitride, or diamond-like carbon or materials including a diamond surface. Such carbon-containing ceramic materials can be considered inorganic, despite including carbon. In some embodiments, the dielectric material at the bonding surface does not include a polymeric material, such as an epoxy (e.g., an epoxy adhesive, cured epoxy, or an epoxy composite, such as an FR-4 material), a resin, or a molding material.

[0027] In other embodiments, the bonding layer can include a conductive material, such as a deposited conductive oxide material, for example, indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed June 30, 2023, the entirety of which is incorporated herein by reference, for examples of providing a conductive bonding layer without shorting through the interface.

[0028] In direct bonding, the first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process and results in a structurally different interface than that produced by deposition. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonded structure is different than the width of the second element. The width or area of the larger element in the bonded structure can be at least 10% greater than the width or area of the smaller element. Additionally, unlike the interface under a deposited layer, the interface between the directly bonded structures can include a defect region with nanoscale voids (nanovoids) present. The nanovoids can be formed due to activation (e.g., exposure to a plasma, explained below) of one or both of the bonding surfaces.

[0029] In contrast to most bonding layers, the bonding interface between the non-conductive bonding surfaces can include a higher concentration of material from the activation and / or final chemical treatment processes. For example, in the particular example of activation with a nitrogen plasma, a nitrogen concentration peak can form at the bonding interface. In some examples, the nitrogen concentration peak can be detected using secondary ion mass spectroscopy (SIMS) techniques. In various examples, for example, a nitrogen termination process (e.g., exposing the bonding surfaces to a nitrogen-containing plasma) can replace the OH groups of a hydroxylated (OH-terminated) surface with NH2molecules, resulting in a nitrogen-terminated surface. In the particular example of activation with an oxygen plasma, an oxygen concentration peak can form at the bonding interface between the non-conductive bonding surfaces. In some examples, the bonding interface can include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. The direct bond can include a covalent bond, which is stronger than a van der Waals bond. The bonding layer can also include a polished surface that is planarized to a high degree of smoothness.

[0030] In direct bonding processes such as uniform direct bonding and hybrid bonding, two elements are bonded together without intervening adhesive. In non-direct bonding processes that utilize adhesive, an intervening material is typically applied to one or both elements to achieve a physical connection between the elements. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive such as an epoxy) can include a conductive filler material, can be applied to one or both elements, and cured to form a physical (rather than chemical or covalent) connection between the elements. Typical organic adhesives lack strong chemical or covalent bonding to either element. In these processes, the connection between the elements is weak and / or susceptible to reversal, such as by reheating or de-soldering.

[0031] In contrast, direct bonding processes join two elements by forming strong chemical bonds (e.g., covalent bonds) between the relatively non-conductive materials. For example, in a direct bonding process between non-conductive materials, one or both non-conductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and / or terminated) such that when the elements come into contact, strong chemical bonds (e.g., covalent bonds) form that are stronger than van der Waals or hydrogen bonds. In some implementations (e.g., between opposing dielectric surfaces, such as between opposing silicon oxide surfaces), the chemical bonds can spontaneously occur at room temperature upon contact. In some implementations, the chemical bonds between the relatively non-conductive materials can be strengthened after annealing the elements.

[0032] As mentioned above, hybrid bonding is a kind of direct bonding in which two non-conductive features are directly bonded to non-conductive features and a conductive feature is directly bonded to a conductive feature of the bonded elements. The non-conductive bonding material and interface can be as described above, while the conductive bonding can be formed, for example, as a direct intermetallic connection. In a conventional metal bonding process, a fusible metal alloy (e.g., solder) can be disposed between the conductors of two elements, heated to melt the alloy, and cooled to form a connection between the two elements. The resulting bond typically exhibits a sharp interface with the conductors of the two elements and is subject to reversal by reheating. In contrast, the direct metal bonding employed in hybrid bonding does not require a molten or intermediate fusible metal alloy and can produce a strong mechanical and electrical connection, often manifesting interdiffusion of the bonded conductive features with grain growth across the bonding interface between the elements, even without the much higher temperatures and pressures of thermocompression bonding.

[0033] Figure 1A and Figure 1B schematically depict cross-sectional side views of a first element 102 and a second element 104 before and after a method for forming a direct bonding structure, and more particularly a hybrid bonding structure, according to some embodiments. In Figure 1B The bonding structure 100 includes the first element 102 and the second element 104 directly bonded to each other at a bonding interface 118 without intervening adhesive. The conductive feature 106a of the first element 102 can be electrically connected to a corresponding conductive feature 106b of the second element 104. In the hybrid bonding structure 100 depicted, the conductive feature 106a is directly bonded to the corresponding conductive feature 106b without intervening solder or conductive adhesive.

[0034] The conductive features 106a and 106b of the depicted embodiments are embedded in a first bonding layer 108a of the first element 102 and a second bonding layer 108b of the second element 104, respectively, and can be considered part of the first and second bonding layers. The field regions of the bonding layers 108a, 108b extend between and partially or completely surround the conductive features 106a, 106b. The bonding layers 108a, 108b can include the non-conductive material layers described above suitable for direct bonding, and the field regions are directly bonded to each other without adhesive. The non-conductive bonding layers 108a, 108b can be disposed on respective front sides 114a, 114b of base substrate portions 110a, 110b.

[0035] The first and second elements 102, 104 can include microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some specific examples, the base substrate portions can include device portions, such as bulk semiconductor (e.g., silicon) portions of the elements 102, 104 and back-end-of-line (BEOL) interconnect layers over these semiconductor portions. The bonding layers 108a, 108b can be provided as part of these BEOL layers during device fabrication, as part of a redistribution layer (RDL), or as a particular bonding layer added to an existing device with a bonding pad extending from a bottom layer contact. Active devices and / or circuitry can be patterned and / or otherwise disposed in or on the base substrate portions 110a, 110b and can be in electrical communication with at least some of the conductive features 106a, 106b. The active devices and / or circuitry can be disposed at or near the front sides 114a, 114b of the base substrate portions 110a, 110b and / or at or near the opposing back sides 116a, 116b of the base substrate portions 110a, 110b. In other specific examples, the base substrate portions 110a, 110b can not include active circuitry, but can instead include dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. The bonding layers 108a, 108b are shown disposed on the front sides of the elements, but similar bonding layers can additionally or alternatively be disposed on the back sides of the elements.

[0036] In some specific examples, the base substrate portions 110a, 110b can have significantly different coefficients of thermal expansion (CTEs), and a bonded element including these different base substrate portions can form a non-uniform bonded structure. The CTE difference between the base substrate portions 110a and 110b, and especially between the bulk semiconductor (typically single-crystal) portions of the base substrate portions 110a, 110b, can be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between the base substrate portion 110a and the base substrate portion 110b can be in a range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0037] In some implementations, one of the base substrate portions 110a, 110b can include an optoelectronic single crystal material suitable for optical piezoelectric or pyroelectric applications, including a perovskite material, and the other of the base substrate portions 110a, 110b includes a more conventional substrate material. For example, one of the base substrate portions 110a, 110b includes lithium tantalate (LiTa03) or lithium niobate (LiNb03), and the other of the base substrate portions 110a, 110b includes silicon (Si), quartz, fused silica glass, sapphire, or glass. In other implementations, one of the base substrate portions 110a, 110b includes a III-V single semiconductor material such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the base substrate portions 110a, 110b can include a non-III-V semiconductor material such as silicon (Si), or can include other materials with similar CTEs such as quartz, fused silica glass, sapphire, or glass. In still other implementations, one of the base substrate portions 110a, 110b includes a semiconductor material, and the other of the base substrate portions 110a, 110b includes an encapsulation material such as a glass, organic, or ceramic substrate.

[0038] In some arrangements, the first element 102 can include a singulated element such as a singulated integrated device die. In other arrangements, the first element 102 can include a carrier or substrate (e.g., a semiconductor wafer) including a plurality (e.g., tens, hundreds, or more) of device regions that form a plurality of integrated device dies when singulated, although in other implementations such a carrier can be a package substrate or an active or passive interposer. Similarly, the second element 104 can include a singulated element such as a singulated integrated device die. In other arrangements, the second element 104 can include a carrier or substrate (e.g., a semiconductor wafer). The implementations disclosed herein can thus apply to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers can be bonded directly to one another (e.g., direct hybrid bonding) and singulated using a suitable singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) can be substantially flush (substantially aligned x-y dimensions) and / or the edges of the bonding interfaces for both the bonded and singulated elements can be coextensive, and can include a mark indicative of the common singulation process of the bonded structure (e.g., a saw cut mark if a saw cut singulation process is used).

[0039] While only two elements 102, 104 are shown, any suitable number of elements can be stacked in the bonded structure 100. For example, a third element (not shown) can be stacked on the second element 104, a fourth element (not shown) can be stacked on the third element, and so on. In these embodiments, through substrate vias (TSVs) can be formed to provide vertical electrical communication between and / or among the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be laterally stacked adjacent to each other along the first element 102. In some specific examples, the laterally stacked additional elements can be smaller than the second element. In some specific examples, the bonded structure can be encapsulated with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be disposed over the bonded structure. For example, in some embodiments, a first insulating layer can be conformally deposited over the bonded structure, and a second insulating layer (which can comprise the same material as the first insulating layer or a different material) can be disposed over the first insulating layer.

[0040] To enable direct bonding between the bonding layers 108a, 108b, the bonding layers 108a, 108b can be prepared for direct bonding. The non-conductive bonding surfaces 112a, 112b at the upper or outer surfaces of the bonding layers 108a, 108b can be prepared for direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 112a, 112b can be less than 1 nm, 0.5 nm, 0.1 nm, 0.05 nm, 0.01 nm, 0.005 nm, 0.001 nm, or 0.0005 nm. In some embodiments, the roughness of the polished bonding surfaces 112a, 112b can be less than 0.1 nm, 0.01 nm, or 0.001 nm. For example, the roughness of the bonding surfaces 112a and 112b can be in the range of about 0.1 nm to 0.01 nm, 0.01 nm to 0.001 nm, or 0.001 nm to 0.0001 nm. to 0.01 nm, 0.01 nm to 0.001 nm, or 0.001 nm to 0.0001 nm. to 0.01 nm, 0.01 nm to 0.001 nm, or 0.001 nm to 0.0001 nm. or to 0.01 nm, 0.01 nm to 0.001 nm, or 0.001 nm to 0.0001 nm. The polishing can also be tuned to recess the conductive features 106a, 106b relative to the field regions of the bonding layers 108a, 108b.

[0041] Preparation for direct bonding can also include cleaning one or both of bonding surfaces 112a, 112b and exposing them to a plasma and / or etchant to activate at least one of surfaces 112a, 112b. In some embodiments, one or both of surfaces 112a, 112b can be terminated with a species after activation or during activation (e.g., during a plasma and / or etching process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at bonding surfaces 112a, 112b, and a termination process can provide additional chemical species at bonding surfaces 112a, 112b that alter the chemical bonds and / or improve bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step, such as a plasma to activate and terminate surfaces 112a, 112b. In other embodiments, one or both of bonding surfaces 112a, 112b can be terminated in a separate process to provide additional species for direct bonding. In various embodiments, the termination species can include nitrogen. For example, in some embodiments, bonding surfaces 112a, 112b can be exposed to a nitrogen-containing plasma. Other termination species can be suitable to improve bonding energy depending on the material of bonding surfaces 112a, 112b. Also, in some embodiments, bonding surfaces 112a, 112b can be exposed to fluorine. For example, there can be one or more fluorine concentration peaks at or near bonding interface 118 between first element 102 and second element 104. Typically, fluorine concentration peaks occur at interfaces between layers of material. Additional examples of activation and / or termination processes can be found in U.S. Patent No. 9,391,143 at col. 5, line 55 to col. 7, line 3; col. 8, line 52 to col. 9, line 45; col. 10, lines 24-36; col. 11, lines 24-32, 42-47, 52-55, and 60-64; col. 12, lines 3-14, 31-33, and 55-67; col. 14, lines 38-40 and 44-50; and U.S. Patent No. 10,434,749 at col. 4, lines 41-50; col. 5, lines 7-22, 39, 55-61; col. 8, lines 25-31, 35-40, and 49-56; and col. 12, lines 46-61, the activation and termination teachings of which are incorporated herein by reference.

[0042] Accordingly, in the direct bond structure 100, the bond interface 118 between the two non-conductive materials (e.g., bond layers 108a, 108b) can include an extremely smooth interface having a higher nitrogen (or other termination species) content and / or a fluorine concentration peak at the bond interface 118. In some specific examples, various types of inspection techniques such as SIMS techniques can be used to detect the nitrogen and / or fluorine concentration peaks. The polished bond surfaces 112a and 112b can be slightly rougher (e.g., about 0.5-1 nm Ra) after the activation process. In some specific examples, the activation and / or termination can produce a slightly smoother surface prior to bonding, such as in the case where the plasma treatment preferentially etches the high points on the bond surface. To To or possibly rougher). In some specific examples, the activation and / or termination can produce a slightly smoother surface prior to bonding, such as in the case where the plasma treatment preferentially etches the high points on the bond surface.

[0043] The non-conductive bond layers 108a and 108b can be directly bonded to each other without an adhesive. In some specific examples, the elements 102, 104 are brought together at room temperature without the need to apply a voltage, and without the need to apply external pressure or force beyond that used to initiate contact between the two elements 102, 104. The mere contact can cause direct bonding (e.g., covalent dielectric bonding) between the non-conductive surfaces of the bond layers 108a, 108b. Subsequent annealing of the bond structure 100 can cause the conductive features 106a, 106b to be directly bonded.

[0044] In some specific examples, prior to direct bonding, the conductive features 106a, 106b are recessed relative to the surrounding field region, such that the total gap between the opposing contacts after dielectric bonding and prior to annealing is less than 15 nm, or less than 10 nm. Because the recess depth of the conductive features 106a and 106b can vary from element to element due to process variations, the gap referred to can represent the maximum or average gap between the corresponding conductive features 106a, 106b of the two joined elements (prior to annealing). After annealing, the conductive features 106a and 106b can immediately expand and contact each other to form an intermetallic direct bond.

[0045] During annealing, the conductive features 106a, 106b (e.g., metallic material) can expand, while the direct bond of the surrounding non-conductive material between the bond layers 108a, 108b separates, such that the thermal expansion increases the internal contact pressure between the opposing conductive features. The annealing can also cause metal grain growth across the bond interface, such that grains from one element at least partially migrate across the bond interface into the other element, and vice versa. Accordingly, in some hybrid bonding specific examples, the opposing conductive materials are joined without the need to be heated above the melting temperature of the conductive material, such that the bond can be formed at a lower annealing temperature compared to soldering or thermal compression bonding.

[0046] In various embodiments, the electrically conductive features 106a, 106b can include discrete pads, contacts, electrodes, or traces at least partially embedded in a non- conductive field region of the bonding layers 108a, 108b. In some embodiments, the electrically conductive features 106a, 106b can include exposed contact surfaces of TSVs (e.g., silicon vias).

[0047] As mentioned above, in some embodiments, prior to direct bonding, the Figure 1A In elements 102, 104 of FIG. 1, portions of respective electrically conductive features 106a and 106b can be recessed below the non-conductive bonding surfaces 112a and 112b, for example, by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in a range of 2 nm to 20 nm or in a range of 4 nm to 10 nm. Due to process variations, both dielectric thickness and conductor recess depth can vary across elements. Thus, the above recess depth ranges can apply to individual electrically conductive features 106a, 106b or to an average depth of the recess relative to the local non-conductive field region. Even for individual electrically conductive features 106a, 106b, the vertical recess can vary across the feature, and thus can be measured at or near a lateral middle or center of the cavity formed by the given electrically conductive feature 106a, 106b, or can be measured at the sides of the cavity.

[0048] Advantageously, high density connections between electrically conductive features 106a, 106b across the direct bonding interface 118 (e.g., for small or fine pitch of regular arrays) can be achieved using hybrid bonding techniques, such as direct bond interconnect, or the technology available from Adeia Corporation of San Jose, California ) can be used.

[0049] In some embodiments, the pitch p of the electrically conductive features 106a, 106b, such as electrically conductive traces embedded in a bonding surface of one of the bonded elements, can be less than 40 pm, less than 20 pm, less than 10 pm, less than 5 pm, less than 2 pm, or even less than 1 pm. For some applications, the ratio of one of the pitch of the electrically conductive features 106a and 106b to the lateral dimension (e.g., diameter) of the bonding pads is less than 20, or less than 10, or less than 5, or less than 3, and sometimes desirably less than 2. In various embodiments, the electrically conductive features 106a and 106b and / or traces can include copper or copper alloys, although other metals can be suitable, such as nickel, aluminum, or alloys thereof. The electrically conductive features disclosed herein, such as the electrically conductive features 106a and 106b, can include fine grain metal (e.g., fine grain copper). Furthermore, the major lateral dimension (e.g., pad diameter) can also be small, for example, in a range of about 0.25 pm to 30 pm, in a range of about 0.25 pm to 5 pm, or in a range of about 0.5 pm to 5 pm.

[0050] For hybrid bonding elements 102, 104, as illustrated, the orientation of the one or more electrically conductive features 106a, 106b from the opposing element can be opposite one another. As known in the art, electrically conductive features can generally be formed with near-vertical sidewalls, particularly where the conductor sidewalls are defined directly by etching the conductive material or indirectly by etching the surrounding insulator in a damascene process using directional reactive ion etching (RIE). However, there can be some slight tapering of the conductor sidewalls, where the conductor becomes narrower further from the surface that was initially exposed to the etching. The tapering can be even more pronounced when utilizing isotropic wet etching or dry etching to define the conductive sidewalls directly or indirectly. In the depicted example, at least one electrically conductive feature 106b (and / or at least one internal electrically conductive feature, such as a BEOL feature) in the bonding layer 108b of the upper element 104 can taper away from the bonding surface 112b or taper upward. In contrast, at least one electrically conductive feature 106a (and / or at least one internal electrically conductive feature, such as a BEOL feature) in the bonding layer 108a of the lower element 102 can taper away from the bonding surface 112a or taper downward. Similarly, any bonding layer (not shown) on the backside 116a, 116b of the elements 102, 104 can taper away from the backside in an opposite tapering orientation relative to the frontside electrically conductive features 106a, 106b of the same element.

[0051] As described above, in the annealing phase of hybrid bonding, the electrically conductive features 106a, 106b can expand and contact one another to form an intermetallic direct bond. In some examples, the materials of the electrically conductive features 106a, 106b of the opposing elements 102, 104 can interdiffuse during the annealing process. In some examples, metal grains grow into one another across the bonding interface 118. In some examples, the metal is or includes copper, which can have grains oriented along the 111 crystal plane for improved copper diffusion across the bonding interface 118. In some examples, the electrically conductive features 106a and 106b can include a nanotwinned copper grain structure, which can assist in merging the electrically conductive features during annealing. There is substantially no gap between the non-conductive bonding layers 108a and 108b at or near the bonded electrically conductive features 106a and 106b. In some examples, a barrier layer can be disposed under the electrically conductive features 106a and 106b and / or laterally surrounding the electrically conductive features (e.g., which can include copper). However, in other examples, there can be no barrier layer under the electrically conductive features 106a and 106b.

[0052] Figures 2A-2C One example of utilizing liquid cooling to extract heat is illustrated by introducing a cooling structure 230 on the back of the integrated device die 218. In some examples, the cooling structure 230 can be a heat spreader, heat sink, or other heat extraction structure.Figures 2A-6 In the description, for consistency and ease of description, orientation and surface are described such that the upper surface of the features in the cross section is regarded as on the first side, and the lower surface of the features in these views is regarded as on the second side.

[0053] Figure 2A A top view of the joining structure 200 is shown, while Figure 2B A cross-section of a bonding structure 200 is shown, the bonding structure including a cooling structure 230 attached to an integrated device die 218. The cooling structure 230 includes an inlet 202, an outlet 204, two or more cavities 246, 248 corresponding to two or more elements 210, 216, and a plurality of nozzles 208. In the specific example illustrated, cavities 246, 248 each include a plurality of channels. In the illustrated plan view, a liquid (e.g., water, dielectric fluid, etc.) may enter the cooling structure 230 through the inlet 202 (e.g., "enter"), propagate through a plurality of first channels 212, flow through the nozzles 208, flow through a plurality of second channels 214, and exit the cooling structure 230 through the outlet 204 (e.g., "exit"). Those skilled in the art will understand... Figure 2B and Figure 2C learn, Figure 2A This is for illustrative purposes only, and the same channel does not lead directly from inlet 202 to outlet 204; more precisely, the liquid is forced to flow from first channel 212 through nozzle 208 and through second channel 214.

[0054] Figures 2B-2C Cross-sectional views of the bonding structure 200 in the xz and yz planes are shown, respectively. The bonding structure 200 includes a cooling structure 230 having a first side 232 and a second side 242 bonded to the integrated device die 218 (such as a chip or integrated circuit) via a bonding interface 222 between the cooling structure 230 and the integrated device die 218. In some specific examples, the cooling structure 230 is a semiconductor structure comprising one or more semiconductor layers or blocks that can be bonded together. In some specific examples, the cooling structure 230 comprises a material whose coefficient of thermal expansion (CTE) closely matches the CTE of the cooled integrated device die 218.

[0055] In some specific examples, the cooling structure 230 is directly bonded to the back side 224 of the integrated device die 218 without the intervention of an adhesive. In other specific examples, the cooling structure 230 may be bonded to the front side 250 of the integrated device die 218. Directly bonding the cooling structure 230 to the back side 224 of the integrated device die 218 helps to achieve a fluid-tight seal while ensuring excellent thermal contact compared to an adhesive layer. The cooling structure 230 includes a first element 210 disposed above and bonded to the second element 216. In some specific examples, the second side 226 (bottom side in the figure) of the first element 210 is directly bonded to the first side 228 (top side in the figure) of the second element 216 without the intervention of an adhesive. Directly bonding the first element 210 to the second element 216 creates a fluid-tight seal between the two elements 210, 216 constituting the cooling structure 230 and also ensures excellent thermal contact. In some specific instances, the first element 210 has a CTE that matches the coefficient of thermal expansion (CTE) of the second element 216 of the cooling structure 230.

[0056] Although not shown, those skilled in the art will understand that direct bonding interfaces, such as bonding interface 222 between the second side 242 of cooling structure 230 and the back surface 224 of integrated device die 218, and bonding interface 222 between the second side 226 of first element 210 and the first side 228 of second element 216, may have the bonding layers described above. Direct bonding may be uniform direct bonding or hybrid bonding, and may also require metal connections (not shown) for electrical or thermal reasons. Bonding layers may form portions of pre-bonded elements and provide surfaces to be directly bonded, and each bonding layer may contain the inorganic dielectric described above. At least one of the bonding surfaces for each bonding interface may be prepared for the direct bonding described above.

[0057] Although an inlet 202 and an outlet 204 are shown, the cooling structure 230 may include multiple inlets and / or outlets.

[0058] exist Figure 2B In this embodiment, the second element 216 includes a second cavity 248 extending from the engagement interface 222. The second cavity 248 in the illustrated specific example includes a plurality of parallel channels 214, but in other specific examples, the second cavity 248 may take other forms, such as non-parallel channels, open chambers, etc. A plurality of nozzles 208 are disposed above and in fluid communication with the second cavity 248. Although in relation to one channel 214... Figure 2BIn the view of FIG. 2, four nozzles 208 are illustrated coupled to the first cavity 246, but some embodiments can include more than four nozzles. In some embodiments, two or more nozzles 208 can be formed. Additionally, the nozzles 208 can be arranged in a periodic array. In some embodiments, the nozzles 208 can be configured to be in a non-periodic arrangement. The customization of the number and arrangement of the nozzles 208 adds flexibility to configurations that can be suitable for cooling different types of chips or chips with hot spots. For example, in some embodiments, more nozzles 208 can be included over possible hot spots in the integrated device die 218. The first cavity 246 is joined with the plurality of nozzles 208 when the second side 226 of the first element 210 is disposed on the first side 228 of the second element 216. The plurality of nozzles 208 (or spray nozzles) are configured to eject a cooling liquid in a direction perpendicular to the backside 224 of the die 218 and represent a restriction in the flow path from the inlet 202 to the cooled integrated device die 218. In some embodiments, the liquid expelled by the plurality of nozzles 208 into the second cavity 248 can be collimated. In some embodiments, the liquid expelled by the plurality of nozzles 208 into the second cavity 248 can be tapered (e.g., pyramidal or conical). In some embodiments, the die 218 is exposed to the liquid (e.g., in some embodiments, the cooling liquid directly contacts or impacts the backside 224 of the die 218) to achieve optimal heat removal without the need for additional layers, such as a thermal interface layer.

[0059] As Figure 2CAs shown in the middle, the first cavity 246 includes a first plurality of channels 212 in the first element 210 and the second cavity 248 includes a second plurality of channels 214 in the second element 216. The cavities 246, 248 can also further include a plurality of support structures 220. While in the particular example depicted, the support structures 220 also act as walls between the channels 212, 214 of the cavities 246, 248, in other examples, the support structures can include struts within the cavities or channels. The support structures 220 included in the cavity 248 facing the integrated device die 218 provide structural support. The cavities can be subjected to pressure during assembly, and in operation, high pressure can be used to facilitate liquid to be ejected vertically onto the integrated device die 218. The support structures 220 can help reduce the risk of breakage. In some examples, the support structures 220 are directly bonded to the integrated device die or semiconductor element 218. The integrated device die 218 can be a semiconductor wafer that is cut or singulated later in assembly, or a semiconductor die. The first plurality of channels 212 join with the respective nozzles 208 in the second element 216 at the orifices 234 of the nozzles 208. In the depicted example, each orifice 234 is narrower than the corresponding cavity 246, 248. In some examples, the first element 210 includes the inlet 202, the outlet 204, and the first plurality of channels 212 in fluid communication with the plurality of nozzles 208, and the second element 216 includes the second plurality of channels 214 and the plurality of nozzles 208.

[0060] In Figures 2A-2C some examples, the first channels 212 are oriented parallel to the second channels 214. In this parallel configuration, the inlet 202 is positioned opposite the outlet 204, as can be seen in the top view in Figure 2A As shown in Figure 2B , liquid (e.g., water, dielectric fluid, etc.) can enter and flow through the inlet 202 of the first element 210 of the cooling structure 230. The liquid can then flow into the first channels 212 in the first element 210, and then flow through the plurality of nozzles 208 on the first side 228 of the second element 216. In some examples, the liquid enters the orifices 234 on the first side 236 of the nozzles 208 and exits the orifices 234 on the second side 238 of the nozzles 208.

[0061] As mentioned, the nozzles 208 represent a restriction in the flow path, and can represent a greater than 20% reduction in the flow path from the first channels 212 to the nozzles 208, which increases the flow rate through the nozzles and enhances the cooling effect. In other words, the ratio of the flow path surface area in the first channels 212 to the flow path surface area in the nozzles 208 can be greater than 1.2: 1, such as between 2: 1 and 50: 1.

[0062] In some embodiments, the nozzle 208 can have straight sidewalls. In the depicted embodiment, the orifice 234 on the first side 236 of the nozzle 208 is larger in size than the orifice 234 on the second side 238 of the nozzle 208. The orifice 234 on the second side 238 of the nozzle 208 includes a narrower opening. In some embodiments, the orifice 234 can be rectangular or circular in shape, viewed from the top. In some embodiments, the orifice 234 can have a width or diameter dimension of between about 25 pm and about 50 pm. In some embodiments, the nozzle 208 can be formed to include a side comprising an angle a, where a can be a value of about 55° and a value of about 90° or an angle therebetween. In some embodiments, the surface area of the orifice 234 from the first side 236 of the nozzle 208 to the second side 238 of the nozzle 208 can be reduced by 10% to 80%.

[0063] This narrower opening can create a high pressure, enhancing the cooling effect on the integrated device die 218. After exiting the nozzle 208, the liquid flows into the second channel 214 in the second element 216 of the cooling structure 230. The second channel 214 provides a defined flow path that can reduce or mitigate thermal crosstalk by a degree of thermal insulation, reducing the transport of heat from one area of the die 218 to another via the cooling liquid, and reducing the risk of dead zones in the coolant flow. As shown in Figure 2B The liquid flows into the second cavity 248 on the second side 240 of the second element 216, and then into the outlet 204 and out of the cooling structure 230. In some embodiments, and as depicted in Figure 2B The second side 240 is opposite the first side 228, as depicted in Figure 2B Although the embodiment of FIG. 1 shows the first element 210 including the inlet 202, the outlet 204, and the first cavity 246, while the nozzle is disposed in the second element 216, in other embodiments, the first element can alternatively include the nozzle. In yet other embodiments, the inlet and outlet need not be formed at the first side of the first element, e.g., the inlet can be disposed in the first element and the outlet can be disposed in the second element, and the inlet and / or outlet can be oriented horizontally at the edge of the cooling structure.

[0064] Figure 2C It is shown that in some embodiments, the width of the nozzle 208 can be smaller in size compared to the width of the channels 212, 214. Additionally, while the orifice 234 of the nozzle 208 is larger in size than the orifice 234 of the second element 216, in other embodiments, the orifice 234 of the nozzle 208 can be smaller in size than the orifice 234 of the second element 216. Figure 2AWhile shown as circular, the orifice 234 of nozzle 208 does not need to be circular and can be configured to have other geometries (e.g., square). In fact, as discussed in more detail below, the conical nozzle formed by wet etching of monocrystalline silicon can naturally be rectangular in a top-down view and pyramidal in three-dimensional shape.

[0065] Figures 3A-3C The joining structure 300 according to another specific example is illustrated. Unless otherwise indicated, Figures 3A-3C Components and Figures 2A-2C Components with the same number are identical or substantially similar. Figures 2A-2C In the first element 210, the first channel 212 in the first cavity 246 is configured parallel to the second channel 214 in the second cavity 248 of the second element 216, unlike the second channel 214 in the second cavity 248 of the second element 216. Figures 3A-3C In a specific example, the first channel 212 is configured perpendicular to the second channel 214. The inlet 202 and outlet 204 communicate with lateral channels that are not parallel to each other. For example, such as... Figure 3A As shown in the plan view, inlet 202 is located at the first lateral side 302, and outlet 204 is located at the second lateral side 304, such that the first side 302 is perpendicular to the second side 304. In this configuration, inlet 202 can... Figure 3B Viewed in the yz plane cross-section of the joint structure 300, and the outlet 204 is available in Figure 3C Viewed in the xz-plane cross-section of the joining structure 300. In some specific instances, the first channel 212 is configured not to be parallel to the second channel 214. This non-parallel configuration allows for customization and flexibility in manufacturing cooling structures suitable for the needs of a given cooling application.

[0066] Figures 4A-4E Drawing is used to form similar to Figures 2A-3C The manufacturing process of cooling structure 230 and cooling structure 400. Second substrate 426 is shown. Figure 4A In. Figure 4AIn this embodiment, multiple nozzles 208 may be formed or etched (e.g., wet or dry etching) on ​​a first side 406 of a second substrate 426. In one specific example, the second substrate 426 may comprise a crystalline structure, such as a single-crystal semiconductor (e.g., silicon) substrate or wafer. As known in the art, masking and etching such a substrate, for example with potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), can naturally produce the illustrated slanted vias to serve as nozzles 208, due to the longer exposure time of the etchant at the first side 406 and / or due to preferential etching along the crystal orientation. This anisotropic etching along the crystal structure can also naturally produce rectangular openings or pyramidal openings in three dimensions, even if the masked opening is circular. Although the nozzles 208 are shown as having tapered sides, in some specific examples, the nozzles may be formed with straight sides using techniques such as dry etching (e.g., reactive ion etching (RIE)).

[0067] A protective layer 404 may be formed or deposited on the first side 406 of the second substrate 426, and as follows: Figure 4B As shown in the image. The protective layer 404 can be formed of a material resistant to subsequent etching. Figure 4C For example, in order to wet etch a silicon substrate with KOH or TMAH, the protective layer 404 may contain silicon oxide or silicon nitride, which are resistant to these etchants and are etched much more slowly than silicon (e.g., >100:1 selectivity).

[0068] Figure 4C A second cavity 248 is illustrated formed or etched (e.g., wet or dry etching) on ​​a second side 408 of a second substrate 426 opposite to a first side 406 of the second substrate 426. This second cavity may include a second channel 214. For example, for a silicon substrate, the etching may involve KOH or TMAH impregnation, as mentioned above regarding the etching nozzle 208. A protective layer 404 prevents etching of the first side 406 during the formation of the channel 214. The channel 214 is aligned with the nozzle 208. Due to the choice of etching type, the channel 214 is also shown as angled, but like the nozzle 208, the walls can be made more vertical by using, for example, a RIE.

[0069] exist Figure 4D In the process, the protective layer 404 is removed (i.e., by selective wet etching or dry etching, etc.).

[0070] May include about Figures 2A-3C The first cavity 246 of the described first channel 212 may be formed or etched (e.g., wet or dry etching) on ​​the second side 410 of the first substrate 402, such as Figure 4E As shown in the image. Figure 4EFurther comprising forming or etching (e.g., wet or dry etching) the inlet 202 and outlet 204 on the first side 412 of the first substrate 402 Figure 4E Etching of both sides of the first substrate 402 can employ the protective layer described above, which can be omitted, especially in cases where a second etching is performed using reactive ion etching (RIE) instead of wet etching at locations requiring vertical walls, such as for the inlet and outlet.

[0071] Figure 4E Also shown is bonding the first side 406 of the second substrate 426 to the second side 410 of the first substrate 402. In some embodiments, the outlet 204 extends from the first side 412 of the first substrate 402 through the second side 406 of the first substrate 402, and the inlet 202 extends from the first side 412 of the first substrate 402 to a depth that is less than the thickness Tl of the first substrate 402. After bonding, the channel 214 of the second substrate 426 can be directly connected to the outlet 204. In some embodiments, the fabrication process includes directly bonding the first side 406 of the second substrate 426 to the second side 410 of the first substrate 402. In some embodiments, this direct bonding can be performed without intervening adhesive. In some embodiments, the direct bonding includes forming an inorganic dielectric bonding layer, such as silicon oxide, on the first side 406 of the second substrate 426 and / or on the second side 410 of the first substrate 402. The first substrate 402 and the second substrate 426 can include a semiconductor material having an inorganic bonding layer at the direct bonding surface. Additionally, the formation of the first cavity 246 (e.g., the first channel 212), the second cavity 248 (e.g., the second channel 214), and the nozzle 208 can be achieved entirely through a wet etching process that allows for relatively inexpensive batch processing of the cooling structure 400, and can result in the depicted angled sidewalls due to preferential etching along crystallographic facets.

[0072] Although the cooling structure 400 has been described as being formed by a method that utilizes two substrates 402, 426, in some embodiments, three substrates can be used. For example, a method of forming a cooling structure can include three layers such that a first plurality of channels is formed in a first substrate (first layer), a plurality of nozzles is formed in a second substrate (second layer), and a second plurality of channels is formed in a third substrate (third layer). The first layer can be directly bonded to the second layer, and the second layer can be directly bonded to the third layer. In this latter formation method, the problem of etching unintended sides is removed or mitigated by further separating the layers in which the channels and nozzles are etched, but requires an additional substrate, an additional alignment process, and an additional bonding process.

[0073] The manufacturing process for forming the cooling structure 400 can further include a step of bonding the cooling structure 400 to the integrated device die 218 at the wafer or die stage. For example, the second side 408 of the second substrate 426 of the cooling structure 400 can be bonded to a semiconductor element that is or includes the integrated device die 218. The second channels 214 of the second substrate 426 are exposed to the semiconductor element 218. In some embodiments, bonding the cooling structure 400 to the integrated device die 218 can include bonding the second side 408 of the second substrate 426 directly to the integrated device die 218 or a wafer from which the integrated device die is singulated. In some embodiments, the second substrate 426 and the first substrate 402 can have a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated device die 218.

[0074] Figure 5 One embodiment of a semiconductor device package 500 including a cooling structure 230 is illustrated. In the semiconductor device package 500, the bonded structure 200 includes the cooling structure 230, which includes a first cavity 246 over a second cavity 248 with intervening nozzles 208 of communicating fluid between the two cavities, and the cooling structure 230 is bonded directly to the integrated device die 218. The bonded structure 200 is embedded in an encapsulant 506. The encapsulant 506 at least encapsulates the outer side surfaces 508 of the first element 210 and the second element 216 of the cooling structure 230. The encapsulant 506 provides protection to the integrated device die 218 and the cooling structure 230 from the environment (e.g., protection from external heat). In some embodiments, the encapsulant 506 can be formed by a molding process and using existing epoxy or other polymer molding materials. A heat sink or heat spreader 502 is disposed on a top surface 510 of the encapsulant 506 and attached to the encapsulant 506 in which the bonded structure 200 is embedded. The heat sink / heat spreader 502 further aids in dissipating heat generated in the semiconductor device package 500. The top surface 510 of the encapsulant 506 can be disposed on an opposite side 512 of the first element 210 from the semiconductor element 218. The heat sink / heat spreader 502, the encapsulant 506, and the bonded structure 200 are disposed over a package substrate 504, as shown in Figure 5 In some embodiments, the heat sink / heat spreader 502 can include metal. In some embodiments, the heat sink / heat spreader can include ports or connections 514. In some embodiments, the presence of the ports or connections 514 allows the semiconductor device package 500 to be connected to coolant lines 610 (shown in Figure 6These coolant lines can be configured to pump in cooling liquid and pump out heated liquid (i.e., liquid heated by heat exchange between the integrated device die 218 and the cooling liquid sprayed into the second cavity 246), thereby facilitating efficient heat dissipation from the integrated device die 218.

[0075] Figure 6 One particular example of a semiconductor device package 600 including the bonded structure 230 and the inlet pump 602 and the outlet pump 604 is illustrated. Unless otherwise noted, the components of the semiconductor device package 600 can be the same as or substantially similar to the components of the semiconductor device package 200. In Figure 6 Figure 5 Figure 6 In particular examples, the inlet pump 602 can be used to flow liquid (e.g., coolant) into the cavity 246, and the outlet pump 604 can be used to remove liquid from the cavity 248. Although Figure 6 particular examples of the semiconductor device package 600 do not illustrate the heat sink / heat spreader 502, but rather show the encapsulation 506 extending over the cooling structure 230, in some particular examples, the heat sink / heat spreader 502 can be included and the connections 514 (shown in Figure 5 In some particular examples, the outlet pump 604 can be used to establish an air gap or pocket 606 in the second cavity 248 (e.g., the second channel 214) facing the integrated device die 218. The outlet pump 604 can be configured to reduce the pressure near the outlet 204 so that this pressure is less than the pressure in the second cavity 248 facing the integrated device die 218.

[0076] Creating the air gap 606 can increase the efficiency of the divergent spray and improve heat removal. In Figure 6 ​​In particular examples, the semiconductor device package 600 can be configured to generate a negative pressure on the outlet 204 to increase the pressure drop in the system between the inlet 202 and the outlet 204. Upon creation of the air gap 606, the cooling liquid can be expelled from the nozzle 208 as vapor in the air within the bottom cavity 248. The vapor can then form a liquid layer 608 in the bottom cavity 248, which can then be pumped out through the outlet 204. Expelling the liquid into the air gap 606 can improve the dispersion of the cooling liquid, as the cooling liquid exits the nozzle 208 as a vapor or mist (e.g., conical) rather than a jet (e.g., collimated). Further, including the air gap 606 can help maintain a high velocity near the surface to be cooled, which allows for an improved heat removal process. In some particular examples, the cooling liquid can be expelled from the nozzle 208 into the liquid-filled cavity 248. In some particular examples, the cooling liquid can be expelled from the nozzle 208 into the cavity 248 containing a vacuum. In some particular examples, the ejection of the cooling liquid can be continuous. In some particular examples, the ejection of the cooling liquid can be non-continuous or pulsed. In some particular examples, non-continuous or pulsed ejection of the cooling liquid can facilitate the creation of an air gap for evaporative cooling. In some particular examples, including a nozzle having a conical sidewall can reduce turbulence, thereby reducing flow resistance and velocity. Thus, in these particular examples, non-continuous or pulsed ejection of the cooling liquid can introduce turbulence and assist in eliminating dead spots, thereby improving heat transfer of heat generated by the integrated device die to the cooling liquid. For example, the pulsed ejection can have a duty cycle of at least 50%, such as a duty cycle of about 55% to about 90%.

[0077] In one aspect, the technology described herein is directed to a method of forming a cooling structure having a first side and a second side opposite the first side, the method comprising: forming an inlet and an outlet in a first substrate; forming at least one channel on a second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and the outlet; forming a plurality of nozzles on a first side of a second substrate; forming a plurality of channels on a second side of the second substrate opposite the first side of the second substrate, wherein the plurality of channels are aligned with the nozzles; and bonding the second side of the first substrate to the first side of the second substrate.

[0078] In some particular examples, the technology described herein is directed to a method wherein the outlet extends from a first side of a first substrate through a second side of the first substrate, and wherein the inlet extends from the first side of the first substrate to a depth less than a thickness of the first substrate.

[0079] In some particular examples, the technology described herein is directed to a method wherein the plurality of channels of the second substrate are directly connected to the outlet.

[0080] In some embodiments, the technology described herein is directed to a method, further comprising forming an inorganic dielectric layer on the second side of the second substrate.

[0081] In some embodiments, the technology described herein is directed to a method, wherein bonding the second side of the first substrate to the first side of the second substrate comprises directly bonding the second side of the first substrate to the first side of the second substrate without intervening adhesive.

[0082] In some embodiments, the technology described herein is directed to a method of forming a liquid-cooled package, the method comprising: a method of forming a cooling structure and bonding a second side of a second substrate to a semiconductor element.

[0083] In some embodiments, the technology described herein is directed to a method, wherein the plurality of channels of the second substrate are exposed to the semiconductor element.

[0084] In some embodiments, the technology described herein is directed to a method, wherein bonding the second side of the second substrate to the semiconductor element comprises directly bonding the second side of the second substrate to the semiconductor element without intervening adhesive.

[0085] In some embodiments, the technology described herein is directed to a method, wherein the semiconductor element comprises one of a wafer or a semiconductor die.

[0086] In some embodiments, the technology described herein is directed to a method, wherein the first substrate and the second substrate have a coefficient of thermal expansion that matches a coefficient of thermal expansion of the semiconductor element.

[0087] In some embodiments, the technology described herein is directed to a method, wherein directly bonding comprises forming an oxide bonding layer on the second side of the first substrate or on the first side of the second substrate.

[0088] In some embodiments, the technology described herein is directed to a method, wherein forming a plurality of nozzles comprises forming tapered openings.

[0089] In some embodiments, the technology described herein is directed to a method, wherein forming tapered openings comprises wet etching a single crystalline material of the second substrate.

[0090] In some embodiments, the technology described herein is directed to a method, wherein the tapered openings are rectangular in shape.

[0091] In another aspect, the technology described herein is directed to a cooling structure comprising: a semiconductor structure having a bonding surface for bonding to an integrated device die and a back surface opposite the bonding surface, the semiconductor structure comprising: a plurality of cavities extending into the semiconductor structure from the bonding surface; and a plurality of nozzles, each nozzle of the plurality of nozzles disposed over and in fluid communication with a corresponding cavity of the plurality of cavities.

[0092] In some embodiments, the technology described herein is directed to a cooling structure, wherein each nozzle of the plurality of nozzles is joined with a corresponding cavity at an orifice, the orifice being narrower than the corresponding cavity.

[0093] In some embodiments, the technology described herein is directed to a cooling structure, wherein the semiconductor structure comprises a first element and a second element bonded directly to the first element without intervening adhesive.

[0094] In some embodiments, the technology described herein is directed to a cooling structure, wherein the first element comprises an inlet, an outlet, and a first plurality of channels in fluid communication with the plurality of nozzles, and wherein the second element comprises a second plurality of channels and the plurality of nozzles.

[0095] In some embodiments, the technology described herein is directed to a cooling structure, wherein the plurality of nozzles taper to have wider openings on a first side and narrower openings on a second side, wherein the narrower openings are in fluid communication with the plurality of cavities.

[0096] In some embodiments, the technology described herein is directed to a bonded structure comprising a cooling structure and an integrated device die, the cooling structure bonded directly to a backside of the integrated device die without intervening adhesive.

[0097] In another aspect, the technology described herein is directed to a cooling structure comprising: an inlet; a first element; a second element; and an outlet, wherein the first element comprises an inlet and a first cavity, wherein the second element comprises a plurality of nozzles on a first side and a second cavity on a second side opposite the first side, wherein a bottom surface of the first element is disposed on a top surface of the second element, wherein the cooling structure is configured to allow liquid to flow from the inlet into the first cavity, from the first cavity into the plurality of nozzles, from the plurality of nozzles into the second cavity, and from the second cavity to the outlet.

[0098] In some embodiments, the technology described herein is directed to a cooling structure, wherein the first cavity comprises a first plurality of channels and at least one support structure, wherein the second cavity comprises a second plurality of channels and at least one support structure.

[0099] In some embodiments, the technology described herein is directed to a cooling structure, wherein the first plurality of channels is parallel to the second plurality of channels.

[0100] In some embodiments, the technology described herein is directed to a cooling structure, wherein the first plurality of channels is perpendicular to the second plurality of channels.

[0101] In some embodiments, the technology described herein is directed to a cooling structure, wherein the plurality of nozzles is exposed to a first cavity on a first side of the plurality of nozzles and a second cavity on a second side of the plurality of nozzles, wherein the first side of the plurality of nozzles has an opening size that is larger than an opening size of the second side of the plurality of nozzles.

[0102] In some embodiments, the technology described herein is directed to a cooling structure, wherein the plurality of nozzles includes one or more sidewalls formed with a wet etch.

[0103] In some embodiments, the technology described herein is directed to a cooling structure, wherein the plurality of nozzles includes a plurality of circular openings.

[0104] In some embodiments, the technology described herein is directed to a cooling structure, wherein the plurality of nozzles includes a plurality of rectangular openings.

[0105] In some embodiments, the technology described herein is directed to a cooling structure, wherein a bottom surface of the first element is directly bonded to a top surface of the second element.

[0106] In some embodiments, the technology described herein is directed to a cooling structure, wherein the cooling structure is directly bonded to a semiconductor element.

[0107] In some embodiments, the technology described herein is directed to a cooling structure, wherein at least one support structure of the second element is directly bonded to a semiconductor element.

[0108] In some embodiments, the technology described herein is directed to a cooling structure, wherein exposed outer surfaces of the first element and the second element are encapsulated by an encapsulant.

[0109] In some embodiments, the technology described herein is directed to a cooling structure, wherein a heat spreader is disposed on a top surface of an encapsulant, wherein the top surface of the encapsulant is disposed on a side of the first element opposite a semiconductor element.

[0110] In some embodiments, the technology described herein is directed to a cooling structure, wherein the heat spreader includes a metal.

[0111] In some embodiments, the technology described herein is directed to a cooling structure in which the coefficient of thermal expansion of the first and second elements matches the coefficient of thermal expansion of the semiconductor element.

[0112] In some embodiments, the technology described herein is directed to a cooling structure in which the semiconductor element comprises one of a semiconductor wafer or a semiconductor die.

[0113] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to". As used herein the terms "coupled" and "coupling" generally mean the joining of two or more elements together in a manner that permanently or temporarily interconnects the connected elements. Likewise, as used herein the terms "connected" and "connecting" generally mean the joining of two or more elements together in a manner that permanently or temporarily interconnects the connected elements. Additionally, as used herein when referring to a part of a structure, the phrases "on the" and "on a" and the like mean that the element is located in direct contact with the named element without any intervening elements. Further, as used herein, when a first element is described as being "on" or "above" a second element, the first element can be directly on or above the second element such that the first element and the second element are in direct contact, or the first element can be indirectly on or above the second element such that one or more elements are interposed between the first element and the second element. The use of singular or plural number of words in the above implementation is also meant to encompass the plural or singular number, respectively, unless the context above requires otherwise. The use of the word "or" in reference to a list of two or more items means that any of the items in the list can be used, all of the items in the list can be used, or any combination of the items in the list can be used.

[0114] Further, unless expressly stated to the contrary, or as otherwise inherently understood by the skilled reader, the use of conditional language, such as, for example, "can", "could", "might", "may", "e.g.", "for example", "such as", and the like, etc., throughout the present disclosure, mostly means that a certain specific embodiment includes, while other embodiments do not include, a certain feature, element, and / or state. Therefore, such conditional language is, generally, not intended to imply that a feature, element, and / or state is in any way required for one or more specific embodiments or that a feature, element, and / or state is in any way required generally for a specific embodiment.

[0115] While certain specific examples have been described, these specific examples are presented by way of example only, and are not intended to limit the scope of the application. Indeed, the novel apparatus, methods and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the application. For example, while blocks are presented in a given arrangement, alternative specific examples can perform similar functions by different components and / or circuit topologies, and some blocks can be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be implemented in a number of different ways. Any suitable combination of the elements and acts of the various described specific examples can be combined into other specific examples. This application, including the claims, and its equivalents, is intended to cover all of the forms or modifications of the application falling within the scope of the application.

Claims

1. A method of forming a cooling structure having a first side and a second side opposite the first side, the method comprising: forming an inlet and an outlet in a first substrate; forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and the outlet; forming a plurality of nozzles on the first side of a second substrate; forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate, wherein the plurality of channels are aligned with the plurality of nozzles; and bonding the second side of the first substrate to the first side of the second substrate.

2. The method of claim 1, wherein the outlet extends from the first side of the first substrate through the second side of the first substrate, and wherein the inlet extends from the first side of the first substrate to a depth less than a thickness of the first substrate.

3. The method of claim 1, wherein the plurality of channels of the second substrate are directly connected to the outlet.

4. The method of claim 1, further comprising forming an inorganic dielectric bonding layer on the second side of the second substrate.

5. The method of claim 1, wherein bonding the second side of the first substrate to the first side of the second substrate comprises directly bonding the second side of the first substrate to the first side of the second substrate without intervening adhesive.

6. A method of forming a liquid-cooled package, the method comprising: the method of claim 1 of forming a cooling structure; and bonding the second side of the second substrate to a semiconductor element.

7. The method of claim 6, wherein the plurality of channels of the second substrate are exposed to the semiconductor element.

8. The method of claim 6, wherein bonding the second side of the second substrate to the semiconductor element comprises directly bonding the second side of the second substrate to the semiconductor element without intervening adhesive.

9. The method of claim 6, wherein the semiconductor element comprises one of a wafer or a semiconductor die.

10. The method of claim 6, wherein the first substrate and the second substrate have a coefficient of thermal expansion that matches a coefficient of thermal expansion of the semiconductor element.

11. The method of claim 5, wherein the directly bonding comprises forming an oxide bonding layer on the second side of the first substrate or on the first side of the second substrate.

12. The method of claim 1, wherein forming the plurality of nozzles comprises forming tapered openings.

13. The method of claim 12, wherein forming the tapered openings comprises wet etching a single crystalline material of the second substrate.

14. The method of claim 12, wherein the tapered openings are rectangular in shape.

15. A cooling structure comprising: a semiconductor structure having a bonding surface for bonding to an integrated device die and a back surface opposite the bonding surface, the semiconductor structure comprising: a semiconductor structure having a bonding surface for bonding to an integrated device die and a back surface opposite the bonding surface, the semiconductor structure comprising: a plurality of cavities extending into the semiconductor structure from the bonding surface; and a plurality of nozzles, each nozzle of the plurality of nozzles disposed over and in fluid communication with a corresponding cavity of the plurality of cavities.

16. The cooling structure of claim 15, wherein each nozzle of the plurality of nozzles is joined with the corresponding cavity at an orifice, the orifice being narrower than the corresponding cavity.

17. The cooling structure of claim 15, wherein the semiconductor structure includes a first element and a second element, the second element directly bonded to the first element without intervening adhesive.

18. The cooling structure of claim 17, wherein the first element comprises an inlet, an outlet, and a first plurality of channels in fluid communication with the plurality of nozzles, and wherein the second element comprises a second plurality of channels and the plurality of nozzles.

19. The cooling structure of claim 18, wherein the plurality of nozzles taper to have a wider opening on a first side and a narrower opening on a second side, wherein the narrower opening is in fluid communication with the plurality of cavities.

20. A bonded structure comprising the cooling structure of claim 15 and the integrated device die, the cooling structure directly bonded to a backside of the integrated device die without intervening adhesive.

21. A cooling structure comprising: an inlet; a first element; a second element; and an outlet, wherein the first element comprises the inlet and a first cavity, wherein the second element comprises a plurality of nozzles on a first side and a second cavity on a second side opposite the first side, wherein a bottom surface of the first element is disposed on a top surface of the second element, wherein the cooling structure is configured to allow liquid to flow from the inlet into the first cavity, from the first cavity into the plurality of nozzles, from the plurality of nozzles into the second cavity, and from the second cavity to the outlet.

22. The cooling structure of claim 21, wherein the first cavity comprises a first plurality of channels and at least one support structure, wherein the second cavity comprises a second plurality of channels and at least one support structure.

23. The cooling structure of claim 22, wherein the first plurality of channels is parallel to the second plurality of channels.

24. The cooling structure of claim 22, wherein the first plurality of channels is perpendicular to the second plurality of channels.

25. The cooling structure of claim 21, wherein on a first side of the plurality of nozzles, the plurality of nozzles is exposed to the first cavity, and on a second side of the plurality of nozzles, the plurality of nozzles is exposed to the second cavity, wherein the first side of the plurality of nozzles has an opening size that is larger than an opening size of the second side of the plurality of nozzles.

26. The cooling structure of claim 25, wherein the plurality of nozzles comprises one or more sidewalls formed with wet etching.

27. The cooling structure of claim 21, wherein the plurality of nozzles comprises a plurality of circular openings.

28. The cooling structure of claim 21, wherein the plurality of nozzles comprise a plurality of rectangular openings.

29. The cooling structure of claim 21, wherein the bottom surface of the first element is directly bonded to the top surface of the second element.

30. The cooling structure of claim 22, wherein the cooling structure is directly bonded to a semiconductor element.

31. The cooling structure of claim 30, wherein the at least one support structure of the second element is directly bonded to the semiconductor element.

32. The cooling structure of claim 30, wherein exposed outer surfaces of the first element and the second element are encapsulated by an encapsulant.

33. The cooling structure of claim 32, wherein a heat sink is disposed on a top surface of the encapsulant, wherein the top surface of the encapsulant is disposed on an opposite side of the first element from the semiconductor element.

34. The cooling structure of claim 33, wherein the heat sink comprises a metal.

35. The cooling structure of claim 30, wherein coefficients of thermal expansion of the first element and the second element match a coefficient of thermal expansion of the semiconductor element.

36. The cooling structure of claim 30, wherein the semiconductor element comprises one of a semiconductor wafer or a semiconductor die.

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