Substrate for mounting semiconductor element

Abstract

This substrate for mounting a semiconductor element is provided with: a base material comprising a metal; an electrode connected to the semiconductor element; and a protective layer disposed between the base material and the electrode, the protective layer being formed of a material harder than the metal forming the base material.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor element mounting substrate. BACKGROUND

[0002] Conventionally, a semiconductor element mounting substrate for mounting a semiconductor element is known. For example, a semiconductor element mounting substrate is disclosed in Patent Literature 1, which has an insulating layer, a substrate composed of metal, and an intermediate layer disposed between the substrate and the insulating layer.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 7-240570 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, according to the prior art like Patent Literature 1, in the semiconductor element mounting substrate, there is room for improvement in the technology for suppressing generation of a failure caused by deformation of the substrate. In the semiconductor element mounting substrate described in Patent Literature 1, the substrate is formed of metal that is relatively easy to deform, and thus it is likely to be deformed by an external force due to handling in a manufacturing process, various inspections, and the like. If the substrate is deformed, a failure such as a crack is generated in the insulating layer, and thus a technology for suppressing deformation of the substrate is desired.

[0008] An object of the present application is to provide a technology for suppressing generation of a failure caused by deformation of a substrate in a semiconductor element mounting substrate.

[0009] SOLUTION TO PROBLEM

[0010] The present application is achieved in order to solve at least a part of the above problems, and can be implemented as the following technical solutions.

[0011] (1) According to one technical solution of the present application, a semiconductor element mounting substrate is provided. The semiconductor element mounting substrate has: a substrate composed of metal; an electrode connected to a semiconductor element; and a protective layer disposed between the substrate and the electrode, the protective layer being formed of a material harder than the metal forming the substrate.

[0012] According to this structure, the protective layer disposed between the electrode and the substrate composed of metal is formed of a material harder than the metal forming the substrate. Thus, even if a force that deforms the substrate acts on the semiconductor element mounting substrate, deformation of the substrate can be suppressed. Therefore, generation of a failure caused by deformation of the substrate can be suppressed.

[0013] (2) In the semiconductor element mounting substrate according to the above aspect, the protective layer can be formed of a metal. According to this structure, the protective layer is formed of a metal that is less likely to be broken compared to ceramic, for example. Thus, deformation of the base material can be further suppressed, and thus, occurrence of a defect caused by the deformation of the base material can be further suppressed.

[0014] (3) In the semiconductor element mounting substrate according to the above aspect, a material forming the protective layer can have a higher natural potential in salt water than a metal forming the base material. According to this structure, in a case where the semiconductor element mounting substrate on which the semiconductor element is actually mounted is used, for example, corrosion of the base material caused by contact with salt water can be suppressed by the protective layer.

[0015] (4) In the semiconductor element mounting substrate according to the above aspect, the protective layer can be formed of a material having corrosion resistance against sulfidation gas. According to this structure, in a case where the semiconductor element mounting substrate on which the semiconductor element is actually mounted is used, corrosion of the base material caused by sulfidation gas existing in the use environment can be suppressed by the protective layer.

[0016] (5) In the semiconductor element mounting substrate according to the above aspect, the semiconductor element mounting substrate can include an insulating layer disposed between the base material and the electrode, and the protective layer can be disposed between the base material and the insulating layer. According to this structure, in a manufacturing process of the semiconductor element mounting substrate, the protective layer is formed before the insulating layer is formed, and thus, deformation of the base material can be suppressed from before the insulating layer is formed. Thus, for example, generation of a crack in the insulating layer caused by deformation of the base material can be suppressed.

[0017] (6) In the semiconductor element mounting substrate according to the above aspect, the insulating layer can be formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SIC. According to this structure, the insulating layer is formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SIC. Thus, the insulating property of the insulating layer can be improved.

[0018] (7) In the semiconductor element mounting substrate according to the above aspect, the semiconductor element mounting substrate can include an insulating layer disposed between the base material and the electrode, and the protective layer can be disposed between the insulating layer and the electrode. According to this structure, for example, a force acting on the electrode can be suppressed from acting on the insulating layer by the protective layer. Thus, damage to the insulating layer can be suppressed.

[0019] (8) In the semiconductor element mounting substrate described in the above item, the insulating layer can be formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SiC. According to this structure, the insulating layer is formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SiC. Thus, the insulating property of the insulating layer can be improved.

[0020] (9) In the semiconductor element mounting substrate described in the above item, the base material can be formed in a flat plate shape, and the protective layer can be formed on each of a pair of main surfaces of the base material. According to this structure, even if a force that deforms the base material acts on the main surface on the side opposite to the side on which the electrode is formed with respect to the base material, the deformation of the base material can be suppressed by the protective layer.

[0021] (10) In the semiconductor element mounting substrate described in the above item, the thickness of the protective layer can be 0.5 μm or more and 10 μm or less. According to this structure, in a case where the semiconductor element mounting substrate is used as a heat dissipation substrate for releasing heat generated in a semiconductor element, the deformation of the base material can be suppressed without reducing the heat dissipation property due to the protective layer.

[0022] (11) In the semiconductor element mounting substrate described in the above item, the protective layer can contain any one of a nickel-cobalt alloy, a nickel-phosphorus alloy, and a nickel-boron alloy. According to this structure, the nickel-cobalt alloy, the nickel-phosphorus alloy, or the nickel-boron alloy contained in the protective layer can be formed by plating. Thus, the protective layer can be formed relatively easily in a manufacturing process of the semiconductor element mounting substrate.

[0023] (12) In the semiconductor element mounting substrate described in the above item, the base material can be formed of a material in which copper or aluminum is a main component. According to this structure, the base material is formed of a material in which copper or aluminum, which has a high heat dissipation property, is a main component. Thus, the heat dissipation property of the semiconductor element mounting substrate can be improved.

[0024] In addition, the present application can be implemented in various ways, for example, as a product including a semiconductor element mounting substrate, a manufacturing method of a semiconductor element mounting substrate, an inspection method of a semiconductor element mounting substrate, and the like. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a cross-sectional schematic view of a semiconductor element mounting substrate according to a first embodiment.

[0026] Figure 2 is a cross-sectional schematic view of a semiconductor package.

[0027] Figure 3is a cross-sectional view of a semiconductor element mounting substrate of Embodiment 2.

[0028] Figure 4 is a cross-sectional view of a semiconductor element mounting substrate of Embodiment 3. DETAILED DESCRIPTION

[0029] <Embodiment 1>

[0030] Figure 1 is a cross-sectional view of a semiconductor element mounting substrate 1 of Embodiment 1. Figure 2 is a cross-sectional view of a semiconductor package 5 provided with the semiconductor element mounting substrate 1 of Embodiment 1. The semiconductor element mounting substrate 1 of the present embodiment supports a light semiconductor such as a light emitting diode (LED) or a semiconductor laser (LD) as a semiconductor element 5a, and functions as a heat dissipation substrate that releases heat generated at the time of light emission to the outside. The semiconductor element mounting substrate 1 is provided with a base material 10, a protective layer 20, an adhesion layer 30, an insulating layer 40, an adhesion layer 50, a bonding layer 60, and an electrode 70. In addition, in order to facilitate explanation, Figure 1 and Figure 2 the relationship of the thicknesses of the base material 10, the protective layer 20, the adhesion layer 30, the insulating layer 40, the adhesion layer 50, the bonding layer 60, the electrode 70, and the semiconductor element 5a in each of the above-described drawings is different from the actual relationship of the thicknesses.

[0031] The base material 10 is a member having a flat plate shape, and becomes a base of the semiconductor element mounting substrate 1. In the present embodiment, the thickness of the base material 10 is 1 mm. The base material 10 is composed of a metal. In the present embodiment, the base material 10 is composed of copper (Cu). The base material 10 can also be formed of a material in which copper is a main component, aluminum (Al), or a material in which aluminum is a main component. Here, the "main component" means a component that is greater than 50% by mass in the target material. The base material 10 can also be composed of an alloy of copper and aluminum. By forming the base material 10 of these metals, heat generated in the semiconductor element 5a can be effectively released to the outside via the base material 10.

[0032] The protective layer 20 is provided between the substrate 10 and the electrode 70, more specifically, between the substrate 10 and the adhesion layer 30. In the present embodiment, the protective layer 20 is provided on one of the pair of main surfaces 11, 12 of the substrate 10. The protective layer 20 is formed of a material harder than the metal forming the substrate 10. Here, the "material harder than the metal forming the substrate 10" means, for example, a material having a Vickers hardness greater than the Vickers hardness of the metal forming the substrate 10. In the present embodiment, the protective layer 20 is formed of a metal less likely to be broken than ceramics and the like. Specifically, the protective layer 20 is formed of a metal containing nickel-cobalt alloy (Ni-Co). In the present embodiment, the thickness of the protective layer 20 is 0.5 μm or more and 10 μm or less. Thus, the protective layer 20 can transfer heat generated in the semiconductor element 5a to the substrate 10, and suppress deformation of the substrate 10. In addition, the protective layer 20 can be formed of a metal containing any one of nickel-phosphorus alloy (Ni-P) and nickel-boron alloy (Ni-B), or tungsten (W), molybdenum (Mo).

[0033] The material forming the protective layer 20 is a material having a natural potential in salt water higher than the natural potential in salt water of copper forming the substrate 10. Here, the "salt water" means water having a mass concentration of sodium chloride (NaCl) of 5% or less. Thus, the protective layer 20 is less likely to be corroded even when it contacts a metal material likely to be in electrical contact in the semiconductor element mounting substrate 1, such as copper, titanium (Ti), nickel, cobalt, and the like, in salt water.

[0034] The protective layer 20 is formed of a material having corrosion resistance to sulfidation gas (H2S) as compared with copper forming the substrate 10. Here, the "corrosion resistance to sulfidation gas" means a property that corrosion caused by sulfidation gas is less likely to proceed in an environment in which the volume concentration of the sulfidation gas is 15 ppm or less. Thus, the protective layer 20 can suppress corrosion of the substrate 10 by sulfidation gas in the environment in actual use.

[0035] The adhesion layer 30 is provided between the protective layer 20 and the insulating layer 40. In the present embodiment, the adhesion layer 30 is composed of titanium, and has a thickness of, for example, 0.5 μm. The adhesion layer 30 causes the protective layer 20 and the insulating layer 40 to adhere, and suppresses the formation of cracks in the insulating layer 40 due to a difference in thermal expansion coefficient.

[0036] The insulating layer 40 is provided between the substrate 10 and the electrode 70, more specifically, between the adhesion layer 30 and the adhesion layer 50. The insulating layer 40 is formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SIC. In the present embodiment, the insulating layer 40 is composed of Al2O3, and has a thickness of, for example, 5 μm. The insulating layer 40 insulates the electrode 70 and the substrate 10 composed of a metal.

[0037] The adhesion layer 50 is provided between the insulation layer 40 and the bonding layer 60. In the present embodiment, the adhesion layer 50 is composed of titanium, and has a thickness of, for example, 0.2 μm. The adhesion layer 50 causes the insulation layer 40 and the bonding layer 60 to adhere to each other, and suppresses the formation of cracks in the insulation layer 40 due to differences in thermal expansion coefficients.

[0038] The bonding layer 60 is provided between the adhesion layer 50 and the electrode 70. The bonding layer 60 is composed of palladium (Pd), and has a thickness of, for example, 0.07 μm. The bonding layer 60 increases the bonding strength between the adhesion layer 50 and the electrode 70.

[0039] The electrode 70 is connected to the semiconductor element 5a via the bump 6 (see FIG. 1). The electrode 70 is composed of gold (Au), and has a thickness of, for example, 3.0 μm. Figure 2

[0040] The semiconductor package 5 is provided with the semiconductor element mounting substrate 1, the semiconductor element 5a, the phosphor 5b, and the resin portion 5c (see FIG. 1). In the semiconductor package 5, the phosphor 5b is provided on the side opposite to the semiconductor element mounting substrate 1 with respect to the semiconductor element 5a connected to the semiconductor element mounting substrate 1 by the bump 6. The phosphor 5b converts the wavelength of light emitted from the semiconductor element 5a, which is a light semiconductor, and releases the converted light to the outside. The resin portion 5c seals the semiconductor element 5a and the phosphor 5b. Figure 2

[0041] Next, the manufacturing method of the semiconductor element mounting substrate 1 of the present embodiment will be described. First, a nickel-cobalt alloy is deposited on one surface of a flat plate member composed of copper, which becomes the base material 10, to form the protective layer 20. Thereafter, the adhesion layer 30, the insulation layer 40, the adhesion layer 50, the bonding layer 60, and the electrode 70 are sequentially deposited on the protective layer 20 to manufacture the semiconductor element mounting substrate 1.

[0042] Next, the features of the semiconductor element mounting substrate 1 of the present embodiment will be described while referring to problems of a semiconductor element mounting substrate not provided with the protective layer 20 as a comparative example. In the manufacturing process of the semiconductor element mounting substrate, a load is applied to the electrode of the semiconductor element mounting substrate in the probe inspection process, the chip mounting process, and the like, and thus the base material can be depressed at the portion to which the load is applied. In addition, with respect to the semiconductor element mounting substrate to be processed, a force from a tool used for the processing acts because the tool contacts the semiconductor element mounting substrate. Thus, in the semiconductor element mounting substrate of the comparative example, the base material can be deformed. If the base material is deformed, the insulation layer stacked on the base material is also deformed, and thus cracks can be formed in the insulation layer. The cracks in the insulation layer can cause insulation breakdown in the semiconductor element mounting substrate.

[0043] ​​The semiconductor element mounting substrate 1 of the present embodiment has the protective layer 20 formed of a material harder than the metal forming the base material 10 between the base material 10 and the electrode 70. Thus, even if a load is applied to the electrode 70 of the semiconductor element mounting substrate 1 in the manufacturing process of the semiconductor element mounting substrate 1, the protective layer 20 is less likely to deform, and thus the base material 10 is less likely to be dented. Also in contact with a tool at the time of processing, even if a force from the tool acts, the protective layer 20 is less likely to deform, and thus the base material 10 is less likely to deform. Thus, the insulating layer 40 is also less likely to deform, and thus in the insulating layer 40, an insulating breakdown due to deformation of the base material 10 is less likely to occur.

[0044] Further, in the case where the comparative example semiconductor element mounting substrate has a layer formed of chromium as the intermediate layer, since the natural potential of chromium in salt water is relatively low, electrons easily move between the interfaces of the metals contained in the comparative example semiconductor element mounting substrate. Thus, galvanic corrosion is likely to occur. Further, since it also excessively reacts with an etching solution at the time of etching of a counter electrode or the like, over-etching is likely to occur.

[0045] The protective layer 20 provided by the semiconductor element mounting substrate 1 of the present embodiment is formed of a nickel-cobalt alloy having a higher natural potential in salt water than the copper forming the base material 10. Thus, the potential difference between the base material 10 and the protective layer 20 is small, and thus corrosion due to salt water and etching due to an etching solution used in the manufacturing process are less likely to occur.

[0046] The semiconductor element mounting substrate 1 of the present embodiment described above is configured such that the protective layer 20 disposed between the electrode 70 and the base material 10 composed of copper is formed of a nickel-cobalt alloy, which is a material harder than the copper forming the base material 10. Thus, even if a force to deform the base material 10 acts on the semiconductor element mounting substrate 1 in the manufacturing process of the semiconductor element mounting substrate 1 or the like, deformation of the base material 10 can be suppressed. Thus, generation of a defect due to deformation of the base material 10 can be suppressed.

[0047] Further, according to the semiconductor element mounting substrate 1 of the present embodiment, the protective layer 20 is formed of a metal less likely to be broken than a ceramic, for example. Thus, deformation of the base material 10 can be further suppressed, and thus generation of a defect due to deformation of the base material 10 can be further suppressed.

[0048] Further, according to the semiconductor element mounting substrate 1 of the present embodiment, the protective layer 20 is formed of a nickel-cobalt alloy having a higher natural potential in salt water than the copper forming the base material 10. Thus, in actual use of the semiconductor element mounting substrate 1 on which the semiconductor element 5a is mounted, for example, corrosion of the base material 10 due to contact with salt water can be suppressed by the protective layer 20.

[0049] Further, according to the semiconductor element mounting substrate 1 of the present embodiment, the protective layer 20 is formed of a nickel-cobalt alloy having corrosion resistance against sulfurized gas. Thus, in actual use of the semiconductor element mounting substrate 1 on which the semiconductor element 5a is mounted, corrosion of the base material 10 caused by sulfurized gas existing in the use environment can be suppressed by the protective layer 20.

[0050] Further, according to the semiconductor element mounting substrate 1 of the present embodiment, the protective layer 20 is disposed between the base material 10 and the insulating layer 40, and the protective layer 20 is formed on the base material 10 before the insulating layer 40 is formed in the manufacturing process of the semiconductor element mounting substrate 1. Thus, deformation of the base material 10 can be suppressed from before the insulating layer 40 is formed, and thus, for example, generation of cracks in the insulating layer 40 caused by deformation of the base material 10 can be suppressed.

[0051] Further, according to the semiconductor element mounting substrate 1 of the present embodiment, the thickness of the protective layer 20 is 0.5 μm or more and 10 μm or less. In the present embodiment, the semiconductor element mounting substrate 1 functions as a heat dissipation substrate for the semiconductor element 5a, and thus, by setting the thickness of the protective layer 20 to 10 μm or less, the protective layer 20 can be suppressed from becoming a thermal resistance between the semiconductor element 5a and the base material 10. On the other hand, by setting the thickness of the protective layer 20 to 0.5 μm or more, the protective layer 20 can have a certain degree of strength, and thus, deformation of the base material 10 can be suppressed.

[0052] Further, according to the semiconductor element mounting substrate 1 of the present embodiment, the protective layer 20 is formed of a nickel-cobalt alloy that can be formed by plating. Thus, in the manufacturing process of the semiconductor element mounting substrate 1, the protective layer 20 can be formed relatively easily.

[0053] Further, according to the semiconductor element mounting substrate 1 of the present embodiment, since the base material 10 is formed of copper which has relatively high heat dissipation, the heat dissipation of the semiconductor element mounting substrate 1 can be improved.

[0054] <2nd Embodiment>

[0055] Figure 3 is a cross-sectional view of a semiconductor element mounting substrate 2 of a 2nd embodiment. The semiconductor element mounting substrate 2 of the 2nd embodiment is different from the semiconductor element mounting substrate 1 of the 1st embodiment in that a pair of protective layers are formed on a pair of main surfaces of the base material, respectively. Figure 1

[0056] ​The semiconductor element mounting substrate 2 of the second embodiment includes the base material 10, the protective layer 20, the adhesion layer 30, the insulating layer 40, the adhesion layer 50, the bonding layer 60, the electrode 70, and the protective layer 80. In addition, for convenience of explanation, Figure 3 The graph showing the relationship between the thicknesses of the base material 10, the protective layer 20, the adhesion layer 30, the insulating layer 40, the adhesion layer 50, the bonding layer 60, the electrode 70, and the protective layer 80 of the semiconductor element mounting substrate 2 of the second embodiment is different from the relationship of the actual thicknesses.

[0057] The protective layer 80 is provided on the main surface 12 on the side opposite to the side on which the electrode 70 is formed in the base material 10 having a flat plate shape. That is, in the semiconductor element mounting substrate 2, the protective layers 20, 80 formed of a material harder than the metal forming the base material 10 are respectively formed on the pair of main surfaces 11, 12 of the base material 10. The protective layer 80 is also formed of a metal containing nickel-cobalt alloy like the protective layer 20.

[0058] According to the semiconductor element mounting substrate 2 of the above-described embodiment, the protective layer 20 formed of a material harder than the copper forming the base material 10, i.e., a nickel-cobalt alloy, is disposed between the base material 10 and the electrode 70. Thus, in the manufacturing process of the semiconductor element mounting substrate 1 or the like, even if a load is applied to the electrode 70 in a chip mounting process or the like, it is possible to suppress the occurrence of a dent or deformation in the base material 10.

[0059] Further, according to the semiconductor element mounting substrate 2 of the embodiment, the protective layers 20, 80 are respectively formed on the pair of main surfaces 11, 12 of the base material 10. Thus, even if a force deforming the base material 10 is applied to the main surface 12 on the side opposite to the side on which the electrode 70 is formed with respect to the base material 10, it is possible to suppress the occurrence of a dent or deformation on the main surface 12 of the base material 10 by the protective layer 80.

[0060] Further, according to the semiconductor element mounting substrate 2 of the embodiment, the protective layers 20, 80 formed of the same material are respectively formed on the pair of main surfaces 11, 12 of the base material 10. Thus, compared to a case where the protective layer 20, the insulating layer 40, or the like is formed on only one side of the base material 10, the base material 10 is less likely to be warped. Therefore, it is possible to further suppress the deformation of the base material 10.

[0061] <3rd Embodiment>

[0062] Figure 4 is a cross-sectional view of a semiconductor element mounting substrate 3 of a 3rd embodiment. The semiconductor element mounting substrate 3 of the 3rd embodiment is different from the semiconductor element mounting substrate 1 of the 1st embodiment in that the protective layer is also disposed between the insulating layer and the electrode. Figure 1

[0063] ​The semiconductor element mounting substrate 3 of the third embodiment includes the base material 10, the protective layer 20, the adhesion layer 30, the insulating layer 40, the adhesion layer 50, the protective layer 90, the bonding layer 60, and the electrode 70. In addition, for convenience of explanation, Figure 4 The relationship between the thicknesses of the base material 10, the protective layer 20, the adhesion layer 30, the insulating layer 40, the adhesion layer 50, the protective layer 90, the bonding layer 60, and the electrode 70 is not necessarily the same as the actual relationship between the thicknesses.

[0064] The protective layer 90 is disposed between the insulating layer 40 and the electrode 70, and more specifically, between the adhesion layer 50 and the bonding layer 60. The protective layer 90 is formed of a material harder than the metal forming the base material 10, i.e., a nickel-cobalt alloy. Thus, the insulating layer 40 is also less likely to be deformed by a load applied to the electrode during the manufacturing process of the semiconductor element mounting substrate 3, a force acting during handling.

[0065] The semiconductor element mounting substrate 3 of the above-described embodiment is formed of a material harder than the copper forming the base material 10, i.e., a nickel-cobalt alloy. The protective layer 20 is disposed between the base material 10 and the electrode 70. Thus, even if a load is applied to the electrode 70 during the manufacturing process of the semiconductor element mounting substrate 1, or the like, a depression or deformation of the base material 10 can be suppressed.

[0066] Further, according to the semiconductor element mounting substrate 2 of the embodiment, the protective layer 90 is disposed between the insulating layer 40 and the electrode 70. Thus, a load applied to the electrode 70 can be suppressed from acting on the insulating layer 40 by the protective layer 90. Therefore, damage to the insulating layer 40 can be suppressed.

[0067] [Modified Example of the Embodiment]

[0068] The present application is not limited to the above-described embodiments, and can be implemented in various ways without departing from the gist thereof, for example, the following modified examples can be implemented.

[0069] [Modified Example 1]

[0070] In the above-described embodiments, the semiconductor element mounting substrate functions as a heat dissipation substrate that supports an optical semiconductor and releases heat generated during light emission to the outside. However, the semiconductor mounted on the semiconductor element mounting substrate is not limited to an optical semiconductor.

[0071] [Modified Example 2]

[0072] In the above-described embodiments, the protective layer 20, 80, 90 is formed of a metal including a nickel-cobalt alloy, but the material forming the protective layer is not limited thereto. The protective layer can be formed of a material harder than the metal forming the base material. Since the protective layer is formed of a metal, it is less likely to be broken, and thus the deformation of the substrate can be further suppressed. Further, by the protective layer including a nickel-cobalt alloy, the protective layer can be formed relatively easily in the manufacturing process.

[0073] [Modified Example 3]

[0074] In the above-described embodiments, the protective layer 20, 80, 90 is formed of a material having a higher natural potential in salt water than the copper forming the base material 10. By the protective layer being formed of a material having a higher natural potential in salt water than the material forming the base material, the corrosion of the base material 10 by salt water in actual use can be suppressed, but the material forming the protective layer is not limited thereto.

[0075] [Modified Example 4]

[0076] In the above-described embodiments, the protective layer 20, 80, 90 is formed of a material having corrosion resistance to sulfidation gas. By the protective layer being formed of a material having corrosion resistance to sulfidation gas, the corrosion of the base material by sulfidation gas in the environment in actual use can be suppressed, but the material forming the protective layer is not limited thereto.

[0077] [Modified Example 5]

[0078] In the above-described embodiments, the thickness of the protective layer is 0.5 μm or more and 10 μm or less. The thickness of the protective layer is not limited thereto. However, if the thickness of the protective layer is less than 0.5 μm, it is difficult to suppress the deformation of the base material 10. Further, if the thickness of the protective layer is more than 10 μm, it becomes a thermal resistance between the semiconductor element 5a and the base material 10, and thus the performance of releasing heat of the semiconductor element 5a is reduced, and thus it is desirable to be 0.5 μm or more and 10 μm or less.

[0079] [Modified Example 6]

[0080] In the above-described embodiments, the protective layer composed of a material including a nickel-cobalt alloy is formed by a plating process in the manufacturing process of the substrate for mounting a semiconductor element. The method of forming the protective layer is not limited thereto. It can be a film formation method such as a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, a PVD (Physical Vapor Deposition) method, a vacuum evaporation method, or the like.

[0081] [Modified Example 7]

[0082] In the first embodiment, the semiconductor element mounting substrate 1 has one protective layer 20 on the one main surface 11 side. In the third embodiment, the semiconductor element mounting substrate 3 has two protective layers 20, 90 on the one main surface 11 side. The number of protective layers provided to the semiconductor element mounting substrate is not limited to this.

[0083] [Modification 8]

[0084] In the first embodiment, the protective layer 20 is disposed between the base material 10 and the insulating layer 40. In the third embodiment, the protective layer 20 is disposed between the base material 10 and the insulating layer 40, and the protective layer 90 is disposed between the insulating layer 40 and the electrode 70. The protective layer can be disposed only between the insulating layer 40 and the electrode 70.

[0085] [Modification 9]

[0086] In the above-described embodiments, the insulating layer 40 is composed of Al2O3. The material forming the insulating layer is not limited to this. It is desirable to be formed of any one of SiO2, Y2O3, AlN, Si3N4, and SiC, but can not be these metal compounds.

[0087] The above-described embodiments of the present application have been described based on the embodiments and modifications, but the above-described embodiments of the present application are for easy understanding of the present application, and do not limit the present application. The present application can be changed, modified, and the like within the scope of the gist thereof and the claims, and the equivalents thereof are included in the present application. Furthermore, if the technical features thereof are not described as essential features in the present specification, they can be appropriately deleted.

[0088] (Application Example 1)

[0089] A semiconductor element mounting substrate characterized by comprising:

[0090] a base material composed of a metal;

[0091] an electrode connected to a semiconductor element; and

[0092] a protective layer disposed between the base material and the electrode, the protective layer being formed of a material harder than the metal forming the base material.

[0093] (Application Example 2)

[0094] The semiconductor element mounting substrate according to Application Example 1, characterized in that:

[0095] the protective layer is formed of a metal.

[0096]

[0097] ​(Application Example 3)

[0098] The semiconductor element mounting substrate according to any one of Application Examples 1 to 7, wherein

[0099] A material forming the protective layer has a higher natural potential in brine than a material forming the base material.

[0100] (Application Example 4)

[0101] The semiconductor element mounting substrate according to any one of Application Examples 1 to 3, wherein

[0102] The protective layer is formed of a material having corrosion resistance against sulfurized gas.

[0103] (Application Example 5)

[0104] The semiconductor element mounting substrate according to any one of Application Examples 1 to 4, wherein

[0105] The semiconductor element mounting substrate further includes an insulating layer disposed between the base material and the electrode,

[0106] The protective layer is disposed between the base material and the insulating layer.

[0107] (Application Example 6)

[0108] The semiconductor element mounting substrate according to any one of Application Examples 1 to 5, wherein

[0109] The insulating layer is formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SIC.

[0110] (Application Example 7)

[0111] The semiconductor element mounting substrate according to any one of Application Examples 1 to 6, wherein

[0112] The semiconductor element mounting substrate further includes an insulating layer disposed between the base material and the electrode,

[0113] The protective layer is disposed between the insulating layer and the electrode.

[0114] (Application Example 8)

[0115] The semiconductor element mounting substrate according to any one of Application Examples 1 to 7, wherein

[0116] The insulating layer is formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SIC.

[0117] (Application Example 9)

[0118] The semiconductor element mounting substrate according to any one of Application Examples 1 to 8, wherein

[0119] The substrate is formed in a flat plate shape,

[0120] The protective layer is formed on each of a pair of main surfaces of the substrate.

[0121] (Application Example 10)

[0122] The semiconductor element mounting substrate according to any one of Application Examples 1 to 9, wherein

[0123] The thickness of the protective layer is 0.5 μm or more and 10 μm or less.

[0124] (Application Example 11)

[0125] The semiconductor element mounting substrate according to any one of Application Examples 1 to 10, wherein

[0126] The protective layer contains any one of a nickel-cobalt alloy, a nickel-phosphorus alloy, and a nickel-boron alloy.

[0127] (Application Example 12)

[0128] The semiconductor element mounting substrate according to any one of Application Examples 1 to 11, wherein

[0129] The substrate is formed of a material containing copper or aluminum as a main component.

[0130] Explanation of Reference Numerals

[0131] 1, 2, 3, semiconductor element mounting substrate; 10, substrate; 11, 12, main surface; 20, 80, 90, protective layer; 40, insulating layer; 70, electrode.

Claims

1. A substrate for mounting a semiconductor element, characterized by comprising: a base material composed of a metal; an electrode connected to a semiconductor element; and a protective layer disposed between the base material and the electrode, the protective layer being formed of a material harder than the metal forming the base material.

2. The substrate for mounting a semiconductor element according to claim 1, characterized in that the protective layer is formed of a metal.

3. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized in that the material forming the protective layer has a higher natural potential in brine than the metal forming the base material.

4. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized in that the protective layer is formed of a material having corrosion resistance against sulfidation gas.

5. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized by further comprising an insulating layer disposed between the base material and the electrode, wherein the protective layer is disposed between the base material and the insulating layer.

6. The substrate for mounting a semiconductor element according to claim 5, characterized in that the insulating layer is formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SIC.

7. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized by further comprising an insulating layer disposed between the base material and the electrode, wherein the protective layer is disposed between the insulating layer and the electrode.

8. The substrate for mounting a semiconductor element according to claim 7, characterized in that the insulating layer is formed of any one of Al2O3, SiO2, Y2O3, AlN, Si3N4, and SIC.

9. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized in that the base material is formed in a flat plate shape, and the protective layer is formed on each of a pair of main surfaces of the base material.

10. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized in that the protective layer has a thickness of 0.5 μm or more and 10 μm or less.

11. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized in that the protective layer contains any one of a nickel-cobalt alloy, a nickel-phosphorus alloy, and a nickel-boron alloy.

12. The substrate for mounting a semiconductor element according to claim 1 or 2, characterized in that the base material is formed of a material having copper or aluminum as a main component. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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