Step-by-step decoding method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a step-by-step decoding method and device, a storage medium and electronic equipment, and relates to the technical field of computers, and the method comprises the steps: obtaining a code word and a target check matrix; determining a first SW value according to the code word and the target check matrix; and comparing the first SW value with a target threshold value, and executing a corresponding decoding operation according to a comparison result. Therefore, the decoding operation is dynamically selected according to the SW value, unnecessary iteration is avoided, the relationship between the number of iterations and the throughput is balanced, the decoding time delay and power consumption are reduced, and the decoding efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a step-by-step decoding method, apparatus, storage medium, and electronic device. Background Technology

[0002] The rapid development of fields such as the Internet of Things (IoT), 5G, and artificial intelligence (AI) has placed higher demands on computing power, which in turn has set new standards for storage capacity. Currently, the parameter scale of large-scale AI models has exceeded trillions, leading to exponential data growth. Enterprise-grade SSDs based on NAND flash memory serve as the foundation of computing infrastructure and a guarantee for the intelligence of AI edge devices. However, the physical characteristics of NAND flash memory chips make their threshold voltage distribution susceptible to programming interference and the cumulative effect of write / erase cycles. As storage cells undergo repeated write / erase operations, the charge trapping effect of the floating gate layer and the coupling effect between cells can cause threshold voltage shifts. This drift phenomenon not only exacerbates the risk of overlapping voltage distribution curves of adjacent storage cells but also increases the probability of level misjudgment during read operations, ultimately manifesting as a deterioration in the raw bit error rate (RBER) and a degradation in data persistence, becoming a core bottleneck restricting the long-term reliability of high-density flash memory.

[0003] Low-Density Parity Check (LDPC) codes have become the mainstream error correction scheme in NAND flash memory due to their theoretical performance approaching the Shannon limit. Their iterative decoding strategy based on belief propagation effectively ensures data reliability in current 3D NAND flash memory. The application of LDPC codes in NAND flash memory typically relies more on their hard decision performance. The difference between hard decision and soft decision lies in the fact that hard decision uses a 0 / 1 threshold for judgment, while soft decision utilizes statistical information about voltage distribution, providing richer reliability information and stronger decoding capabilities, but requiring more computation. Furthermore, the trade-off between the number of decoding iterations and high throughput during the decoding process not only leads to the encroachment of storage resources but also increases latency and power consumption.

[0004] Currently, the common process for decoding NAND flash memory media includes: codewords that have been scrambled by the channel after encoding are first subjected to hardware decoding. When hardware decoding fails, the main control chip may try to reread the data on different voltage axes, as incorrect voltage settings may lead to inaccurate data readings. Only after multiple voltage axis adjustments have failed will it switch to software decoding, using more complex methods to recover the data. This is because adjusting the voltage axis has relatively low latency and power consumption, while software decoding requires more computational resources and may affect overall performance. Therefore, before entering a software decoding stage, LDPC has already performed the maximum number of hard decoding iterations across multiple voltage axes. This increases the data latency during LDPC decoding and also increases the number of decoding iterations. Furthermore, some codewords with high RBER (Raw Bit Error Rate) cannot be corrected even after LDPC software decoding. The latency caused by these codewords not only increases power consumption during iterative calculations but also affects the final data throughput. Summary of the Invention

[0005] This application provides a step-by-step decoding method, apparatus, storage medium, and electronic device to at least solve the above-mentioned technical problems existing in the prior art.

[0006] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a step-by-step decoding method, the method comprising: Obtain the codeword and target verification matrix; The first SW value is determined based on the codeword and the target parity check matrix; The first SW value is compared with the target threshold, and the corresponding decoding operation is performed based on the comparison result.

[0007] Secondly, embodiments of this application provide a step-by-step decoding apparatus, the apparatus comprising: The acquisition module is used to acquire codewords and the target verification matrix; The first processing module is used to determine the first SW value based on the codeword and the target parity check matrix; The second processing module is used to compare the first SW value with the target threshold and perform the corresponding decoding operation based on the comparison result.

[0008] Thirdly, embodiments of this application provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the step-by-step decoding methods described above.

[0009] Fourthly, embodiments of this application provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the step-by-step decoding method according to any one of the claims.

[0010] The embodiments of this application have the following beneficial effects: The step-by-step decoding method, apparatus, storage medium, and electronic device provided in this application include: acquiring a codeword and a target parity-check matrix; determining a first SW value based on the codeword and the target parity-check matrix; comparing the first SW value with a target threshold, and performing a corresponding decoding operation based on the comparison result. In this way, decoding operations are dynamically selected based on the SW value, avoiding unnecessary iterations, balancing the relationship between the number of iterations and throughput, reducing decoding latency and power consumption, and improving decoding efficiency.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0012] Figure 1 A flowchart illustrating a step-by-step decoding method provided in an embodiment of this application; Figure 2 A schematic diagram of a verification matrix provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the relationship between error bits and SW values ​​in a code rate parity check matrix provided in this application embodiment; Figure 4 A schematic diagram illustrating the relationship between error bits and SW values ​​in a different code rate parity check matrix provided in this application embodiment; Figure 5 A schematic diagram illustrating the error correction capability of hardware and software decoding corresponding to matrix1, as provided in an embodiment of this application; Figure 6 A schematic diagram illustrating the error correction capability of hardware and software decoding corresponding to matrix2, as provided in an embodiment of this application; Figure 7 A schematic diagram illustrating the bit-flipping decoding performance of matrix1 and matrix2 provided for embodiments of this application; Figure 8 A schematic diagram of a step-by-step decoding device provided in an embodiment of this application; Figure 9 A schematic diagram of another step-by-step decoding device provided in the embodiments of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0017] Figure 1 This is a flowchart illustrating a step-by-step decoding method provided in an embodiment of this application; as shown below. Figure 1 As shown, the method includes: Step 101: Obtain the codeword and target parity matrix; Step 102: Determine the first SW (SyndromeWeight) value based on the codeword and the target parity check matrix; Step 103: Compare the first SW value with the target threshold, and perform the corresponding decoding operation based on the comparison result.

[0018] In coding theory, a codeword refers to a sequence of bits obtained after an encoding process. In error-correcting coding (such as LDPC (Low-Density Parity-Check Code) codes), a codeword is a fixed-length bit sequence formed by encoding information using specific coding rules (such as a parity check matrix). In other words, a codeword is the result of encoding information; it is a vector composed of 0s and 1s.

[0019] For example, in the decoding operation of LDPC codes, suppose the codeword after encoding by the parity check matrix H is c, c = [c(1) c(2) c(3) … c(m)], where c is a vector of bits, and each c(i) is a bit in the codeword, which can be 0 or 1. For c, the codeword is valid if and only if the vector satisfies that the product of the codeword c and the transpose of the parity check matrix H is 0 (i.e., it satisfies the parity check equation c·H). T When = 0 (T denotes transpose), it indicates that the codeword is a correct codeword. The decoding process involves continuously adjusting the values ​​of elements at different positions in c using various methods to ensure that they satisfy the above check equation. When the codeword is affected by the channel and contains erroneous bits, the check equation no longer holds true. The SW value represents the number of check equations that no longer hold true.

[0020] In LDPC codes, the parity-check matrix is ​​a tool used to describe how to check for errors in the transmitted code. As shown above, H is a parity-check matrix used to verify the correctness of the codeword. If the received codeword c contains an error, the parity-check equation will no longer hold. The parity-check matrix is ​​multiplied by the received codeword, and the result is called the synthesis value or synthesis vector, denoted as S.

[0021] The SW value, in LDPC code, is a vector obtained by operating on the received codeword c using the parity-check matrix H. If the received codeword is completely correct (error-free), the SW value is 0; if the received codeword contains erroneous bits, the SW value is the number of non-zero elements. In other words, the SW value represents the number of times the parity-check equation no longer holds true. That is, the larger the SW value, the more codeword errors there are, and the more severe the parity failure. If errors occur, the decoder needs to make more adjustments to correct them. After correction, the SW value will gradually decrease. If the SW value does not decrease significantly after multiple iterations of correction, it is considered to have reached the limit of its correction capability and cannot be corrected further.

[0022] The parity-check matrix H is a sparse matrix, with the number of 0s significantly exceeding the number of 1s. For each code rate, the number of error bits in the current codeword can be estimated based on the corresponding SW value. When the number of error bits is within a certain range, additional energy consumption and decoding delay can be avoided during the decoding process by selecting an appropriate decoding operation (or decoder).

[0023] In this embodiment, the number of error bits in the current codeword is inferred based on the SW value. When the number of error bits is within a certain range, the storage space of intermediate information can be saved by selecting an appropriate parity check matrix and corresponding decoding operation (or decoder), avoiding additional energy consumption and decoding latency during the decoding process. This achieves intelligent optimization and can effectively reduce power consumption, reduce latency, and improve throughput.

[0024] In some embodiments, obtaining the target verification matrix includes: The second SW value is obtained by calculating based on the codeword and the preset initial parity check matrix; If the second SW value is less than the first SW threshold, then the first verification matrix is ​​selected as the target verification matrix; If the second SW value is greater than or equal to the first SW threshold and less than the second SW value, then the second verification matrix is ​​selected as the target verification matrix; If the second SW value is greater than or equal to the second SW threshold, then the third verification matrix is ​​selected as the target verification matrix; The bitrate of the first parity check matrix is ​​greater than that of the second parity check matrix, and the bitrate of the second parity check matrix is ​​greater than that of the third parity check matrix.

[0025] Here, the magnitude of the SW value can be used to estimate the errors present in the codeword, and then the target parity check matrix can be dynamically selected. The subsequent decoding operation can be performed from multiple pre-configured parity check matrices for different error ranges or by selecting the most matching target parity check matrix.

[0026] Specifically, if the calculated second SW value is less than the first SW threshold, a parity check matrix (i.e., the first parity check matrix) with a higher code rate and simpler structure can be selected, sacrificing some error correction capability to obtain more information transmission bits, in exchange for speed and power consumption advantages.

[0027] If the second SW value is greater than or equal to the first SW threshold and less than the second SW value, select the set standard matrix (i.e., the second check matrix). If the second SW value is greater than or equal to the second SW threshold, then a parity check matrix with a lower code rate and more parity bits (i.e., the third parity check matrix) is selected to reduce the number of transmitted information bits in exchange for decoding accuracy.

[0028] Thus, by dynamically selecting based on the SW value, the parity check matrix can be dynamically switched to match the environment, avoiding the limitations of static matrices. This allows the system to more flexibly and intelligently select appropriate error correction schemes when facing different communication conditions, achieving a balance between ensuring data accuracy and effective transmission speed.

[0029] In some embodiments, before comparing the first SW value with the target threshold, the method further includes: The target threshold corresponding to the target verification matrix is ​​determined by querying a preset threshold table based on the target verification matrix. The preset threshold table includes at least one check matrix and a target threshold corresponding to each check matrix. The target threshold includes multiple thresholds used for comparison with the SW value.

[0030] Here, different code rates can correspond to different target thresholds; the target thresholds are multiple thresholds used for comparison with SW values, such as a first threshold, a second threshold, a third threshold, etc.

[0031] Here, the dimension of the parity check matrix H is determined by both the information bits and the parity bits, and the format of the parity check matrix is ​​as follows: Figure 2 As shown, nm represents the information bit length, m represents the parity bit length and number of rows, and n represents the complete codeword length and number of columns. The code rate is (nm) / n. A higher code rate results in fewer parity bits and a longer effective transmission of information. While a larger matrix dimension can improve decoding capability, it also often leads to higher storage resource consumption. Furthermore, more parity bits during decoding increases the delay of a complete iteration, further impacting the decoder's power consumption. Therefore, the SW value can be used to balance the relationship between error correction capability and matrix dimension. Further... Figure 3 and Figure 4 It can be seen that, within a certain error range, choosing a matrix with a higher bit rate can also bring good error correction capabilities.

[0032] For parity check matrices with different code rates, there is a certain relationship between the calculated SW value and the initial number of error bits. Based on this relationship, this application proposes to predetermine the target threshold corresponding to the parity check matrices with different code rates, compare the target threshold with the SW value, and select different decoding operations based on the comparison result.

[0033] In this way, by pre-determining the target thresholds corresponding to different code rates of the parity check matrix, it is possible to effectively compare the actual SW value with the target threshold, dynamically select different operations, thereby reducing unnecessary calculations, improving the overall performance of the system, reducing power consumption and latency, and selecting the most suitable decoding strategy according to the specific situation, ensuring that the best decoding effect can be achieved under different conditions, and improving decoding efficiency and accuracy.

[0034] Specifically, for parity check matrices with different code rates, the calculated SW value has a certain relationship with the initial number of error bits, and the relationship includes: When the number of errors is within a certain range, the SW value is basically linearly related to its initial number of error bits; that is, the more error bits there are, the faster the SW value increases. When the number of errors exceeds this range, the SW value will still continue to increase with the increase of the initial error, but its growth rate will slow down significantly; that is, as the number of error bits increases, the effect of the parity check matrix becomes less significant, resulting in a slower increase in the SW value. When the initial number of errors continues to grow beyond a certain range, the growth trend of the SW value will slow down further, and the SW value will remain basically unchanged as the number of errors increases; that is, after the number of errors is too large, the parity check matrix is ​​close to saturation and cannot effectively increase the error bit correction capability.

[0035] For parity check matrices with different bit rates, apart from the initial error bit range of the SW value trend changing according to the bit rate of the parity check matrix, the overall trend of the SW value as the number of errors increases is the same.

[0036] It should be noted that the above only illustrates how the decoder can be judged and dynamically selected based on the SW value. In practical applications, different target thresholds can be set for parity check matrices with different code rates. Here, the values ​​of the first, second, third, and fourth thresholds corresponding to each parity check matrix are not limited.

[0037] The target thresholds for parity check matrices (JCDs) at different code rates can be pre-determined through simulation testing, experimental data analysis, and data fitting. For example, to detect the target thresholds for JCDs at different code rates through experiments or simulations, different JCDs can be selected, and their n and m values ​​adjusted to obtain different code rates. The number of error bits and the SW value of the JCD during transmission can be simulated, and the results under each condition can be recorded. For each code rate, its bit error rate under different channel conditions can be tested, and the corresponding SW value measured. Through extensive simulation and experimental data, the relationship between the SW value and the number of error bits at each code rate can be obtained, and thus the target threshold for each code rate can be calculated.

[0038] Data on switch-check (SW) values ​​and number of error bits at different bit rates are collected, and statistical analysis methods (such as regression analysis and curve fitting) are used to model the relationship between SW values ​​and the number of error bits. Based on these fitting results, the corresponding target threshold can be determined for the parity check matrix at each bit rate.

[0039] In some embodiments, performing the corresponding decoding operation based on the comparison result includes: If the first SW value is less than the first threshold, the erroneous bits in the codeword are corrected using a bit-flipping decoder. If the first SW value is greater than or equal to the first threshold and less than the second threshold, a hard decoding operation is performed on the codeword using a belief propagation decoder. If the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is adjusted, the codeword is reread under the adjusted voltage axis and the third SW value is calculated, and either hard decoding or soft decoding is performed based on the third SW value. If the first SW value is greater than or equal to the third threshold and less than the fourth threshold, a soft decoding operation is performed on the codeword using a confidence propagation decoder. Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

[0040] This paper presents a method for dynamically selecting the corresponding decoding operation using the magnitude of the SW value. This method involves bit flip decoders, confidence propagation decoders, hard decoding operations, soft decoding operations, voltage axis adjustment, etc. In this way, the decision is made with the SW value as the core, realizing error prediction, resource adaptation (selecting the target parity matrix, selecting a suitable decoder, adjusting the voltage axis, etc.). Through the above intelligent selection, power consumption can be effectively reduced, latency can be reduced, and throughput can be improved.

[0041] In some embodiments, the step of correcting erroneous bits in the codeword using a bit-flipping decoder includes: The bit-flipping decoder is used to perform at least one round of first iteration operation until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails after the maximum number of iterations, the SW value corresponding to the last N first iteration operations is determined; N is greater than or equal to 2. The first average SW value is determined based on the N SW values; If the average value of the first SW is less than the first SW value, the confidence propagation decoder is used to perform a hard decoding operation on the codeword after the decoding failure. If the average value of the first SW is greater than or equal to the first SW value and less than the second threshold, the initial codeword is hard-decoded using a confidence propagation decoder. If the average value of the first SW is greater than or equal to the second threshold, a soft decoding operation is performed on the initial codeword using a confidence propagation decoder.

[0042] Here, the main operational logic of the bit-flipping decoder is a 1-bit AND and XOR operation (i.e., calculating c·H based on the parity check matrix). T The calculation steps of a bit-flipping decoder are simple, and it consumes very few hardware resources and power.

[0043] The following conditions must be met for a decoding decision to be satisfied: Decoding successful; or, If the decoding reaches a plateau, meaning there is no significant decrease in performance over multiple iterations, the current decoding can be terminated early, and the decoding is considered a failure.

[0044] In one example, the first iteration operation includes: The verification equations are calculated based on the verification matrix, and the positions in the verification matrix where the verification equations are not true are counted. Identify and flip the bits that involve the most false check equations; After flipping, continue calculating the verification equation and make a decoding decision based on the calculation result. If the calculation result is 0, the decoding is successful; if the calculation result is not 0, execute the next round of iteration.

[0045] Here, each row of the parity check matrix represents a constraint, that is, the relationship between information bits and parity bits in the encoding. For example, in error-correcting coding, each parity check equation usually involves some information bits and redundant bits, requiring that the linear combination of these bits satisfy a specific condition (such as the sum being 0).

[0046] The locations where the parity check equation fails refer to instances where, during the decoding process, the parity check equation is not valid (i.e., the constraints are not met) when calculated based on the current codeword. These locations indicate potential errors in the bits within the codeword. For the parity check matrix, if the result of any parity check equation is not 0 (i.e., the check fails), then the variable node (bit of the codeword) involved is at the location of the error.

[0047] That is, during the decoding process, if the result of the check equation is zero, it means that the current codeword has been successfully corrected and there are no errors or the error has been successfully fixed. If the result is not zero, it means that the decoding has failed and error correction needs to continue until the decoding decision is met or the maximum number of iterations is reached.

[0048] If decoding still fails after the maximum number of iterations, determine the SW value of the codeword after the last N iterations. Determine the target SW value based on the SW value of the last N iterations. If the target SW value exceeds a set threshold, perform a hard decoding operation.

[0049] Specifically, the first operation involves performing the following steps using a bit-flipping decoder: Step 11: Based on the check matrix and the codeword, find the positions where the check equation is not true, and count the number of check equations with errors (or failures) in all variable nodes of the check equation in turn (if the maximum column weight is 5, then each variable node has a maximum of 5 check equations). Step 12: Flip the point with the most incorrect check equations; Step 13: Continue to process the flipped codewords using c·H T The calculation is performed, and a decoding decision is made based on the calculation result. If the calculation result is 0, the reversed codeword is output. If the calculation result is not 0, the position where the check equation is not true is recorded, and the above steps 11 and 12 are repeated until the decoding decision is met or the set maximum number of iterations is reached.

[0050] The method further includes: Step 14: When decoding fails, determine the result based on the SW value after the last N-round iteration operation. Specifically, the average value of SW after the last N rounds of iteration is calculated to obtain the first average value of SW; If the average value of the first SW is less than the first SW value (i.e. the initial SW value, it is considered that the error has decreased compared to the initial codeword), the codeword after decoding failure is sent to the confidence propagation decoder, and the confidence propagation decoder is used to perform hard decoding operation on the codeword after decoding failure. If the average value of the first SW is greater than or equal to the first SW value and less than the second threshold, the initial codeword is sent to the confidence propagation decoder, and the confidence propagation decoder is used to perform a hard decoding operation on the initial codeword. If the average value of the first SW is greater than or equal to the second threshold, it indicates that the error correction effect is poor or the error is persistent. In this case, the hard decoding is skipped, and the confidence propagation decoder is used directly to perform a soft decoding operation on the initial codeword or to evaluate whether to give up.

[0051] In some embodiments, the hard decoding operation performed on the codeword using the belief propagation decoder includes: The confidence propagation decoder is used to perform at least one round of second iteration operation until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails until the maximum number of iterations, the SW value corresponding to the last M iteration operations is determined; M is greater than or equal to 2. The second average SW value is determined based on the SW values ​​of the M times; If the average value of the second SW is less than the fourth threshold, the initial codeword is soft-decoded using the confidence propagation decoder. If the average value of the second SW is greater than or equal to the fourth threshold, then the decoding operation is abandoned.

[0052] Here, each round of the second iteration operation includes: performing a hard decoding operation based on the codeword, the parity check matrix, and the selected voltage axis.

[0053] The main operational logic in the confidence propagation decoder is multiplication and addition based on LLR (Log-Likelihood Ratio) information. Since LLR information also requires bit quantization, it consumes more SRAM storage resources during the calculation process compared to the operation of the bit flip decoder. SRAM read and write operations also cause power consumption.

[0054] The following conditions must be met for a decoding decision to be satisfied: Decoding successful; or, If the decoding reaches a plateau, meaning there is no significant decrease in performance over multiple iterations, the current decoding can be terminated early, and the decoding is considered a failure.

[0055] In one example, a belief propagation decoder is used to perform a hard decoding operation based on the codeword, parity check matrix, and voltage axis, including: Step 21: Initialize the LLR information of each check node in the check matrix, the Lr information from the check node to the variable node, and the Lq information from the variable node to the check node; The codeword is generated jointly by the information from the variable nodes and the check nodes. Each variable node updates its state based on the received feedback, ultimately forming a codeword that conforms to the check matrix rules.

[0056] In a parity-check matrix, variable nodes are column nodes, and each variable node represents a data bit in the codeword. In LDPC codes, each column of the parity-check matrix corresponds to a variable node, indicating the participation of that data bit in certain parity-check equations.

[0057] A check node is a row node in a check matrix. Each check node corresponds to a check equation and is used to verify whether the variable nodes (data bits) connected to it meet certain check rules.

[0058] The LLR (Log-Likelihood Ratio) information for each check node indicates the check node's current confidence in the received bits.

[0059] The Lr information from the check node to the variable node represents the message that the check node passes to the variable node through the iterative process. Specifically, it is the information that the check node passes to the variable node after performing certain calculations based on the information of its neighboring variable nodes. The goal of the check node is to help the variable node adjust its bit estimation using the Lr information. For example, if the check node detects that the bits of some variable nodes have a certain relationship with other bits (such as satisfying a parity check equation), it will remind the variable node to adjust its current estimation by passing the Lr information.

[0060] The Lq information from the variable node to the check node: This represents the information that the variable node transmits to the check node after updating its bit estimate using the LLR of the received signal and information received from other check nodes during the decoding process. Lq represents the variable node's latest judgment on a particular bit, combining the LLR at signal reception and information from other nodes. The variable node uses this information to adjust its decisions and provide updated information for subsequent decoding processes.

[0061] The variable node and the verification node exchange Lq and Lr information to gradually update and correct their respective judgments until the final decoding result is reached.

[0062] Step 22: Quantize the LLR information corresponding to each variable node according to the currently selected voltage axis, and record the quantized LLR information as LQ; Here, bit quantization refers to converting the LLR (Log-Likelihood Ratio) value into a form more suitable for hardware processing (such as an integer or discrete value) based on the currently selected voltage axis. The quantized LLR value is denoted as LQ.

[0063] Step 23: Calculate the updated Lr information, specifically including: Lq update: Calculate Lq = LQ – Lr at the corresponding position in the first layer; Compare the absolute values ​​of Lq: Calculate and compare the minimum, second minimum, and column index of the absolute values ​​of Lq; at the same time, obtain the total sign of Lq for that row; Lr update: Calculate the Lr information corresponding to each variable node in the row. Lr = total symbol × current position symbol × (minimum value / second smallest value) × α, where α is the normalization factor, with a value between 0.5 and 1.

[0064] Step 24: Update LQ, specifically: calculate LQ = Lr + Lq; Step 25: Perform decoding decision. Specifically, make a decision based on the updated LQ value. When LQ is greater than 0, record the position as 1; when LQ is less than 0, record the position as 0.

[0065] Step 26, Decoding and Verification, specifically, by calculating H·c T If the calculation result is 0, the verification passes and the decoding is successful. If H·c T If the value is not equal to 0, the verification fails. In this case, the next layer of data is iterated, and steps 23 to 26 are repeated (i.e., a new second iteration operation is performed) until the decoding decision is met or the maximum number of iterations is reached.

[0066] The method further includes: Step 27: When decoding fails, make a judgment based on the SW value after the last M-marker iteration operation. Specifically, the average value of SW is calculated based on the set value of SW after the last M-round iteration operation to obtain the second average value of SW; If the average value of the second SW is lower than the fourth threshold, the initial codeword is sent to the confidence propagation decoder, and the confidence propagation decoder is used to perform a soft decoding operation on the initial codeword. If the average value of the second SW is greater than or equal to the fourth threshold, it indicates that hard decoding is almost ineffective, so the current codeword is abandoned and the operation ends.

[0067] In some embodiments, if the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is adjusted, the codeword is reread under the adjusted voltage axis and the third SW value is calculated, and a hard decoding operation or a soft decoding operation is selected according to the third SW value. The adjusted number of voltage axes is at least one; The step of selecting to perform a hard decoding operation or a soft decoding operation based on the third SW value includes: If there are multiple voltage axes in at least one voltage axis whose corresponding third SW values ​​are greater than or equal to the first threshold and less than the second threshold, then the voltage axis with the smallest third SW value is selected as the selected voltage axis, and the confidence propagation decoder performs a hard decoding operation based on the selected voltage axis.

[0068] Specifically, a certain range of voltage axes can be preset as selectable voltage axes. There is a certain offset between each voltage axis. When storing, they can be sorted in ascending order and the offset relationship is clearly defined.

[0069] If a voltage axis is reselected, the codeword is reread and the SW value is recalculated under the selected voltage axis. The calculated SW value is recorded as the third SW value. The decision to enter hardware decoding under the current voltage axis is determined based on the recalculated third SW value; if the SW range for hardware decoding is met, then hardware decoding operation under the current voltage axis is entered.

[0070] In some embodiments, the method further includes: If the third SW value corresponding to each voltage axis in at least one voltage axis is greater than the second threshold and less than the fourth threshold, the confidence propagation decoder is used to perform a soft decoding operation.

[0071] In some embodiments, rereading the codeword and calculating the third SW value under the adjusted voltage axis includes: If the first SW value is less than the third threshold and the difference between the first SW value and the third threshold is less than the first difference threshold, the codeword is reread using all preset voltage axes and the third SW value is calculated respectively. If the difference between the first SW value and the fifth threshold is less than the second difference threshold, the codeword is reread using the voltage axis in the first range with the offset from the default voltage axis, and the third SW value is calculated respectively; the fifth threshold is the intermediate value between the second threshold and the third threshold; If the first SW value is greater than the second threshold and the difference between the first SW value and the second threshold is less than the third difference threshold, the codeword is reread using the voltage axis with the smallest offset from the default voltage axis and the third SW value is calculated.

[0072] Here, the first difference threshold is configured based on the bitrate of the parity check matrix and the settings of each threshold; for example, it can be 3, 4, 5, etc. Similarly, the second and third difference thresholds can also be 3, 4, 5, etc.

[0073] Offset to the voltage axis in the first range refers to a smaller offset from the default voltage axis, such as the three voltage axes before and after it.

[0074] Specifically, under the default voltage axis (i.e., the voltage axis at the time of an initial reading), the calculated SW value is the first SW value mentioned above.

[0075] If the first SW value is greater than or equal to the second threshold and less than the third threshold, then a rapid reread of the voltage axis and a recalculation of the SW value are required.

[0076] When the first SW value is large (close to the third threshold, i.e. less than the third threshold, and the difference between the first SW value and the third threshold is less than the first difference threshold), then try all the set voltage axes, i.e. reread the codeword and calculate the third SW value using all the preset voltage axes respectively. When the first SW value is moderate (close to the middle value between the second and third thresholds, i.e., the difference between the first SW value and the fifth threshold is less than the second difference threshold), try to move away from the voltage axis that is less offset from the default voltage axis (i.e., the voltage axis that is offset from the default voltage axis in the first range). When the first SW value is low (close to the second threshold, i.e. greater than the second threshold, and the difference between the first SW value and the second threshold is less than the third difference threshold), try to find the voltage axis with the smallest offset from the default voltage axis.

[0077] During the rereading and selection of voltage axes, the SW value calculated after reading the codeword for each voltage axis is recorded. When the SW values ​​corresponding to multiple voltage axes meet the set hard decoding range (i.e., greater than or equal to the first threshold and less than the second threshold), the candidate voltage axis with the smallest SW value is selected to enter the confidence propagation decoder in hard decoding mode.

[0078] If all SW values ​​within the selected voltage axis range are greater than the second threshold and less than the fourth threshold, the codeword will not enter the hardware decoding mode, but will directly enter the software decoding stage.

[0079] It should be noted that the soft decoding operation is basically the same as the traditional soft decoding operation, except that the initial value of each LLR in the first iteration is changed from "hard information" determined by a single voltage axis to "soft information" obtained from multiple voltage axis reads. It can be seen that obtaining each piece of soft information requires multiple voltage axis reads, resulting in greater latency and power consumption.

[0080] In some embodiments, performing the corresponding decoding operation based on the comparison result includes: If the first SW value is greater than or equal to the fourth threshold, the decoding operation for the codeword is abandoned.

[0081] Here, when the calculated first SW value exceeds the fourth threshold, it indicates that the codeword will not be successfully decoded even after multiple iterations of soft decoding, and the decoding operation for this codeword is abandoned.

[0082] The method provided in this application embodiment allows the use of a bit-flipping decoder with lower power consumption and area when the first SW value is less than the first threshold. This avoids excessive use of power consumption and storage space caused by multiplication and addition operations during the interaction between the check node and the variable node when using a BP (Belief-Propagation) algorithm scheme in the early stages of NAND life when the number of errors is small.

[0083] When the first SW value is greater than or equal to the first threshold and less than the second threshold, the hard decoding mode in the confidence propagation decoder can be entered. In this mode, a single voltage axis reading is performed to determine the final data value.

[0084] When the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is reread and the SW value is reacquired. At the same time, the hardware decoding of the current voltage axis is determined based on the SW value corresponding to the codeword under different voltage axes.

[0085] Furthermore, if, after a set number of voltage axis readjustments, the SW value still exceeds the second threshold but is less than the fourth threshold under the corresponding parity check matrix, the codeword will not enter hard decoding mode. Instead, it will directly enter the soft decoding operation in the confidence propagation decoder, utilizing the soft information obtained from multiple voltage axis reads for soft decoding. When the SW value exceeds the fourth threshold, it indicates that the codeword will not succeed even after multiple iterations of soft decoding, and the decoding operation for that codeword will be abandoned.

[0086] In addition, the above also provides a hierarchical progressive decoding method. During the iterative operation at any level, the SW value is monitored in real time. If the SW value does not decrease significantly in multiple consecutive iterations, it indicates that the decoding of this segment has entered a plateau period. The decoding of the current level can be terminated in advance, and a decision can be made based on the current SW value level to either advance to the next level decoder or abandon it directly. When the SW value exceeds the preset fourth threshold (regardless of the decoding level or rereading stage), it is directly determined that the codeword is uncorrectable under the current conditions, all decoding attempts are terminated immediately, resources are released, and the next codeword is processed.

[0087] In this way, reducing unnecessary iterations and power consumption helps improve data throughput. At the same time, hierarchical decoding reduces the number of iterations while ensuring the accuracy of codeword decoding.

[0088] The following explains the principle of using the magnitude of the SW value to evaluate the number of errors in the initial codeword in the embodiments of this application, and further explaining the principle of selecting the corresponding decoding operation based on the estimated value.

[0089] like Figure 3 and Figure 4 The figure shows the relationship between the number of error bits and the average SW value of the parity-check matrix at two different code rates. The code rates for the two parity-check matrices are 0.8716 and 0.8989, respectively. Specifically, the code rate for matrix 1 is 0.8716, and the code rate for matrix 2 is 0.8989. The SW value is the average value calculated after performing 100,000 statistical analyses for each error bit.

[0090] Combination Figure 3 and Figure 4 It can be seen that for parity check matrices with different bit rates, there is a certain relationship between the calculated SW value and the initial number of error bits. Specifically, when the number of errors is within a certain range, the SW value is basically linearly related to its initial number of error bits. When the number of errors exceeds this range, the SW value will still continue to increase with the increase of the initial error, but its growth rate will slow down significantly. When the initial number of errors continues to increase beyond a certain range, the growth trend of the SW value will further slow down, and the SW value will remain basically unchanged as the number of errors increases. For matrices with different bit rates, except that the initial error bit range of the SW value trend changes according to the matrix's bit rate, the overall trend of the SW value changing with the increase of the number of errors is the same.

[0091] For a given parity check matrix H, its dimensions are determined by both the information bits and the parity bits. The format of the parity check matrix is ​​as follows: Figure 2As shown, nm represents the information bit length, m represents the parity bit length, and n represents the complete codeword length. The code rate is (nm) / n. A higher code rate results in fewer parity bits and a longer effective transmission of information. While a larger matrix dimension improves decoding capability, it also often leads to higher storage resource consumption. Furthermore, more parity bits during decoding increase the delay of a complete iteration, further impacting the decoder's power consumption. Therefore, the SW value can be used to balance error correction capability and matrix dimension. Further... Figure 3 and Figure 4 It can be seen that, within a certain error range, choosing a matrix with a higher bit rate can also bring good error correction capabilities.

[0092] Figure 5 The error correction performance of a parity-check matrix (mantrix1) at a given bitrate is presented in both software and hardware decoding modes. It can be seen that for the same bitrate parity-check matrix (such as...), the error correction performance is... Figure 5 In matrix 1), the threshold performance of soft decision and hard decision is also different. If the minimum decoding requirement is on the order of 1E-4, that is, at most one error is allowed in 10,000 decoding operations, the applicable range of hard decision is the initial error of less than 367 bits, while the applicable range of soft decision is the initial error of less than 820 bits.

[0093] When the initial error exceeds 900 bits, even if software decoding is initiated, there is a very high probability of decoding failure. This meaningless decoding not only increases iteration time and wastes power, but also affects the final data throughput. While the decoding processes of software and hardware decoding in LDPC are similar, they use different initial information, specifically different initial LLR values. The LLR value is a metric for evaluating bit information in the received signal; it measures the relative probability of a bit being "0" or "1".

[0094] When the number of error bits is small (e.g., less than 300 bits), starting software decoding to perform multiple voltage axis reads can greatly improve performance, but the multiple reads also increase latency and waste power.

[0095] Figure 6 The error correction performance of a different bitrate parity check matrix (matrix2) in software and hardware decoding modes is presented, and compared. Figure 5 and Figure 6 It can be seen that for parity check matrices with different bit rates (such as...) Figure 5 Matrix 1 and Figure 6Compared to matrix 2 in the previous example, the initial error ranges for both soft and hard solutions are different.

[0096] Based on this, the embodiments of this application propose to use the relationship between the above-mentioned SW value and the initial error bit to determine the target threshold corresponding to the SW value when starting soft decoding and hard decoding for each parity check matrix, and to pre-configure the value into the decoder during the decoding startup process, and select to enter different decoding modes according to the actual initial SW value of each codeword.

[0097] Furthermore, because NAND flash memory chips typically have very few error bits in the early stages of their lifespan, especially... Figure 4 The SW values ​​shown are within a linear range relative to the initial error bits, indicating that the errors are primarily distributed across different parity check equations. If hard decoding is used for error correction, it requires converting the initial codeword into corresponding prior probabilities, performing confidence multiplication and addition operations, and storing intermediate information. These steps not only increase storage space usage but also power consumption and latency during information reading and writing. Therefore, a fast bit-flipping decoding method is proposed at this stage. This method uses whether the SW value corresponding to each bit in each error check equation meets a set threshold to determine whether to flip the bit. It requires no additional information computation or storage, significantly reducing power consumption and improving decoding efficiency. The bit-flipping decoding performance of matrices 1 and 2 is as follows: Figure 7 As can be seen, when the number of errors is small, that is, when the corresponding SW value is in the linear region of the matrix, bit flipping also has good decoding performance.

[0098] Additionally, it should be noted that for some codewords, although their initial SW values ​​satisfy the corresponding decoders, there is still a certain probability of decoding failure within the set maximum number of iterations. Some failed codewords can be successfully decoded through further iterations in the next level decoder, while others cannot be decoded even after going through the next level decoder. In this case, the SW value of the last iteration or the average SW value of the last few iterations is evaluated. If the value meets the preset conditions, the initial codeword or the codeword after decoding failure is sent to the next level decoder for decoding. If the preset conditions are not met, the decoding attempt is terminated directly, and the decoding of the next codeword begins. For codewords in the iteration process, the SW value in each iteration can also be used to judge the errors in the iteration process. If the SW value does not decrease significantly in several consecutive iterations, or is in a fluctuating state, it is considered that the codeword has entered the "trap set", that is, it cannot be correctly decoded no matter how many iterations it takes. At this time, the decoding of the current level is terminated in advance, and the codeword is either sent to the next level decoder or abandoned based on the corresponding SW value.

[0099] Figure 8 A schematic diagram of a step-by-step decoder provided in an embodiment of this application is shown below. Figure 7 As shown, the step-by-step decoder includes a decoding control module and a decoding operation module.

[0100] The decoding control module is used to set the maximum number of iterations; calculate the SW value; configure the target threshold; and select the decoder in the decoding operation module.

[0101] Here, the selected decoder may include: a bit inversion decoder, a confidence propagation decoder, wherein the confidence propagation decoder may perform software decoding or hardware decoding.

[0102] The operation of bit-flipping decoders and belief propagation decoders has been described above. Figure 1 The method is explained in detail in the diagram, and will not be repeated here.

[0103] It should be noted that, Figure 8 The SW value calculation in the decoding control module is equivalent to calculating the first SW value mentioned above, while the SW value calculation in the decoding operation module includes: calculating the SW value after each iteration operation of the bit-flipping decoder, and calculating the average value of the SW value.

[0104] Figure 9 A schematic diagram of another step-by-step decoding device provided in the embodiments of this application; as shown Figure 9 As shown, the device includes: The acquisition module is used to acquire codewords and the target verification matrix; The first processing module is used to determine the first SW value based on the codeword and the target parity check matrix; The second processing module is used to compare the first SW value with the target threshold and perform the corresponding decoding operation based on the comparison result.

[0105] In some embodiments, the acquisition module is configured to determine a second SW value based on the codeword and a preset initial check matrix; If the second SW value is less than the first SW threshold, then the first verification matrix is ​​selected as the target verification matrix; If the second SW value is greater than or equal to the first SW threshold and less than the second SW threshold, then the second verification matrix is ​​selected as the target verification matrix. If the second SW value is greater than or equal to the second SW threshold, then the third parity check matrix is ​​selected as the target parity check matrix; wherein, the bitrate of the first parity check matrix is ​​greater than the bitrate of the second parity check matrix, and the bitrate of the second parity check matrix is ​​greater than the bitrate of the third parity check matrix.

[0106] In some embodiments, the second processing module is configured to correct erroneous bits in the codeword using a bit-flipping decoder if the first SW value is less than a first threshold. If the first SW value is greater than or equal to the first threshold and less than the second threshold, a hard decoding operation is performed on the codeword using a belief propagation decoder. If the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is adjusted, the codeword is reread under the adjusted voltage axis and the third SW value is calculated, and either hard decoding or soft decoding is performed based on the third SW value. Wherein, the second threshold is greater than the first threshold, and the third threshold is greater than the second threshold.

[0107] In some embodiments, the second processing module is used to perform at least one round of first iteration operation using the bit-flipping decoder until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails until the maximum number of iterations, the SW value corresponding to the last N first iteration operations is determined; N is greater than or equal to 2. The first average SW value is determined based on the N SW values; If the average value of the first SW is less than the first SW value, the confidence propagation decoder is used to perform a hard decoding operation on the codeword after the decoding failure. If the average value of the first SW is greater than or equal to the first SW value and less than the second threshold, the initial codeword is hard-decoded using a confidence propagation decoder. If the average value of the first SW is greater than or equal to the second threshold, a soft decoding operation is performed on the initial codeword using a confidence propagation decoder. If the first SW value is greater than or equal to the third threshold and less than the fourth threshold, a soft decoding operation is performed on the codeword using a confidence propagation decoder. Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

[0108] In some embodiments, the second processing module is configured to perform at least one round of second iteration operation using the confidence propagation decoder until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails until the maximum number of iterations, the SW value corresponding to the last M iteration operations is determined; M is greater than or equal to 2. The second average SW value is determined based on the SW values ​​of the M times; If the average value of the second SW is less than the fourth threshold, the initial codeword is soft-decoded using the confidence propagation decoder. If the average value of the second SW is greater than or equal to the fourth threshold, then the decoding operation is abandoned.

[0109] In some embodiments, the number of adjusted voltage axes is at least one; The second processing module is configured to, if there are multiple voltage axes in at least one voltage axis whose corresponding third SW values ​​are greater than or equal to a first threshold and less than a second threshold, select the voltage axis with the smallest third SW value as the selected voltage axis, and use the confidence propagation decoder to perform a hard decoding operation based on the selected voltage axis.

[0110] In some embodiments, the second processing module is configured to perform a soft decoding operation on the codeword using the confidence propagation decoder if the third SW value corresponding to each voltage axis in the at least one voltage axis is greater than the second threshold and less than the fourth threshold.

[0111] In some embodiments, the second processing module is configured to reread the codewords and calculate the third SW value using all preset voltage axes if the first SW value is less than a third threshold and the difference between the first SW value and the third threshold is less than a first difference threshold. If the difference between the first SW value and the fifth threshold is less than the second difference threshold, the codeword is reread using the voltage axis in the first range with the offset from the default voltage axis, and the third SW value is calculated respectively; the fifth threshold is the intermediate value between the second threshold and the third threshold; If the first SW value is greater than the second threshold and the difference between the first SW value and the second threshold is less than the third difference threshold, the codeword is reread using the voltage axis with the smallest offset from the default voltage axis and the third SW value is calculated.

[0112] In some embodiments, the second processing module is configured to abandon the decoding operation for the codeword if the first SW value is greater than or equal to a fourth threshold.

[0113] In some embodiments, before comparing the first SW value with the target threshold, the method further includes: The target threshold corresponding to the target verification matrix is ​​determined by querying a preset threshold table based on the target verification matrix. The preset threshold table includes at least one check matrix and a target threshold corresponding to each check matrix. The target threshold includes multiple thresholds used for comparison with the SW value.

[0114] It is understood that the step-by-step decoding apparatus provided in the above embodiments can, as needed, distribute the above processing to different program modules to complete all or part of the processing described above when implementing the corresponding step-by-step decoding method. Furthermore, the apparatus and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0115] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a step-by-step decoding method.

[0116] This application provides a computer-readable storage medium storing executable instructions. When the executable instructions are executed by a processor, the processor will execute the step-by-step decoding method provided in this application.

[0117] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0118] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0119] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0120] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0121] Figure 10This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; as shown below. Figure 10 As shown, the electronic device 100 includes a processor 1001 and a memory 1002 communicatively connected to the processor 1001; the memory 1002 stores instructions executable by the processor 1001. The instructions are executed by the processor 1001 to enable the processor 1001 to perform the aforementioned step-by-step decoding method.

[0122] The electronic devices provided in the above embodiments and the corresponding step-by-step decoding method embodiments belong to the same concept. For details of their specific implementation process, please refer to the method embodiments, which will not be repeated here.

[0123] In practical applications, the electronic device 100 may further include at least one network interface 1003. The various components in the electronic device 100 are coupled together via a bus system 1004. It is understood that the bus system 1004 is used to implement communication between these components. In addition to a data bus, the bus system 1004 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 10 All buses are labeled as bus system 1004. The number of processors 1001 can be at least one, and the number of memories 1002 can be at least one. Network interface 1003 is used for wired or wireless communication between electronic device 100 and other devices.

[0124] The memory 1002 in this embodiment is used to store various types of data to support the operation of the electronic device 100.

[0125] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in the memory 1002. The processor 1001 reads the information in the memory 1002 and, in conjunction with its hardware, completes the steps of the aforementioned step-by-step decoding method.

[0126] In some embodiments, the electronic device 100 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0127] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0128] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0129] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this application is for the purpose of describing embodiments of this application only and is not intended to be limiting of this application.

[0130] It should be understood that in the various embodiments of this application, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0131] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0132] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A step-by-step decoding method, characterized in that, The method includes: Obtain the codeword and target verification matrix; The first comprehensive weight SW value is determined based on the codeword and the target verification matrix; The first SW value is compared with the target threshold, and the corresponding decoding operation is performed based on the comparison result.

2. The method according to claim 1, characterized in that, Obtaining the target verification matrix includes: The second SW value is determined based on the codeword and the preset initial parity check matrix; If the second SW value is less than the first SW threshold, then the first verification matrix is ​​selected as the target verification matrix; If the second SW value is greater than or equal to the first SW threshold and less than the second SW threshold, then the second verification matrix is ​​selected as the target verification matrix. If the second SW value is greater than or equal to the second SW threshold, then the third parity check matrix is ​​selected as the target parity check matrix; wherein, the bitrate of the first parity check matrix is ​​greater than the bitrate of the second parity check matrix, and the bitrate of the second parity check matrix is ​​greater than the bitrate of the third parity check matrix.

3. The method according to claim 1, characterized in that, The step of performing the corresponding decoding operation based on the comparison result includes: If the first SW value is less than the first threshold, the erroneous bits in the codeword are corrected using a bit-flipping decoder. If the first SW value is greater than or equal to the first threshold and less than the second threshold, a hard decoding operation is performed on the codeword using a belief propagation decoder. If the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is adjusted, the codeword is reread under the adjusted voltage axis and the third SW value is calculated, and either hard decoding or soft decoding is performed based on the third SW value. If the first SW value is greater than or equal to the third threshold and less than the fourth threshold, a soft decoding operation is performed on the codeword using a confidence propagation decoder. Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

4. The method according to claim 3, characterized in that, The step of using a bit-flipping decoder to correct erroneous bits in the codeword includes: The bit-flipping decoder is used to perform at least one round of first iteration operation until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails after the maximum number of iterations, the SW value corresponding to the last N first iteration operations is determined; N is greater than or equal to 2. The first average SW value is determined based on the N SW values; If the average value of the first SW is less than the first SW value, the confidence propagation decoder is used to perform a hard decoding operation on the codeword after the decoding failure. If the average value of the first SW is greater than or equal to the first SW value and less than the second threshold, the initial codeword is hard-decoded using a confidence propagation decoder. If the average value of the first SW is greater than or equal to the second threshold, a soft decoding operation is performed on the initial codeword using a confidence propagation decoder.

5. The method according to claim 3, characterized in that, The step of performing hard decoding on the codeword using a belief propagation decoder includes: The confidence propagation decoder is used to perform at least one round of second iteration operation until the codeword after the iteration operation satisfies the decoding decision and / or reaches the set maximum number of iterations; if decoding still fails until the maximum number of iterations, the SW value corresponding to the last M iteration operations is determined; M is greater than or equal to 2. The second average SW value is determined based on the SW values ​​of the M times; If the average value of the second SW is less than the fourth threshold, the initial codeword is soft-decoded using the confidence propagation decoder. If the average value of the second SW is greater than or equal to the fourth threshold, then the decoding operation is abandoned.

6. The method according to claim 3, characterized in that, The adjusted number of voltage axes is at least one; The step of selecting to perform a hard decoding operation or a soft decoding operation based on the third SW value includes: If there are multiple voltage axes in at least one voltage axis whose corresponding third SW values ​​are greater than or equal to the first threshold and less than the second threshold, then the voltage axis with the smallest third SW value is selected as the selected voltage axis, and the confidence propagation decoder performs a hard decoding operation based on the selected voltage axis.

7. The method according to claim 6, characterized in that, The method further includes: If the third SW value corresponding to each voltage axis in at least one voltage axis is greater than the second threshold and less than the fourth threshold, the confidence propagation decoder is used to perform a soft decoding operation on the codeword.

8. The method according to claim 6, characterized in that, Reread the codeword and calculate the third SW value under the adjusted voltage axis, including: If the first SW value is less than the third threshold and the difference between the first SW value and the third threshold is less than the first difference threshold, the codeword is reread using all preset voltage axes and the third SW value is calculated respectively. If the difference between the first SW value and the fifth threshold is less than the second difference threshold, the codeword is reread using the voltage axis in the first range with the offset from the default voltage axis, and the third SW value is calculated respectively; the fifth threshold is the intermediate value between the second threshold and the third threshold; If the first SW value is greater than the second threshold and the difference between the first SW value and the second threshold is less than the third difference threshold, the codeword is reread using the voltage axis with the smallest offset from the default voltage axis and the third SW value is calculated.

9. The method according to claim 1, characterized in that, The step of performing the corresponding decoding operation based on the comparison result includes: If the first SW value is greater than or equal to the fourth threshold, the decoding operation for the codeword is abandoned.

10. The method according to claim 1, characterized in that, Before comparing the first SW value with the target threshold, the method further includes: The target threshold corresponding to the target verification matrix is ​​determined by querying a preset threshold table based on the target verification matrix. The preset threshold table includes at least one check matrix and a target threshold corresponding to each check matrix. The target threshold includes multiple thresholds used for comparison with the SW value.

11. A step-by-step decoding device, characterized in that, The device includes: The acquisition module is used to acquire codewords and the target verification matrix; The first processing module is used to determine the first SW value based on the codeword and the target parity check matrix; The second processing module is used to compare the first SW value with the target threshold and perform the corresponding decoding operation based on the comparison result.

12. The apparatus according to claim 11, characterized in that, The acquisition module is used to determine the second SW value based on the codeword and the preset initial check matrix; If the second SW value is less than the first SW threshold, then the first verification matrix is ​​selected as the target verification matrix; If the second SW value is greater than or equal to the first SW threshold and less than the second SW threshold, then the second verification matrix is ​​selected as the target verification matrix. If the second SW value is greater than or equal to the second SW threshold, then the third parity check matrix is ​​selected as the target parity check matrix; wherein, the bitrate of the first parity check matrix is ​​greater than the bitrate of the second parity check matrix, and the bitrate of the second parity check matrix is ​​greater than the bitrate of the third parity check matrix.

13. The apparatus according to claim 11, characterized in that, The second processing module is used to correct erroneous bits in the codeword using a bit-flipping decoder if the first SW value is less than the first threshold. If the first SW value is greater than or equal to the first threshold and less than the second threshold, a hard decoding operation is performed on the codeword using a belief propagation decoder. If the first SW value is greater than or equal to the second threshold and less than the third threshold, the voltage axis is adjusted, the codeword is reread under the adjusted voltage axis and the third SW value is calculated, and either hard decoding or soft decoding is performed based on the third SW value. If the first SW value is greater than or equal to the third threshold and less than the fourth threshold, a soft decoding operation is performed on the codeword using a confidence propagation decoder. Wherein, the second threshold is greater than the first threshold, the third threshold is greater than the second threshold, and the fourth threshold is greater than the third threshold.

14. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the step-by-step decoding method according to any one of claims 1 to 10.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the step-by-step decoding method according to any one of claims 1 to 10.

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