FPGA-based BP imaging sinc interpolation optimization method and device

Abstract

The application discloses a BP imaging Sinc interpolation optimization method and device based on FPGA and belongs to the technical field of radar signal processing. The method realizes seamless connection of data through double-BRAM ping-pong buffering. Fixed-point and floating-point mixed operation is adopted to optimize the slant range and index calculation module and the Sinc coefficient array calculation module, wherein fixed-point is used for general calculation, floating-point is used for square root and division, resource consumption is significantly reduced, and precision is improved. Efficient interpolation calculation pipeline processing is realized through a parallel fixed-point multiplication and addition array. While guaranteeing high-precision interpolation, the application greatly reduces LUT, register and DSP resource occupation of the FPGA, and significantly improves the calculation speed and imaging quality of BP real-time imaging.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of radar signal processing, and particularly relates to a BP imaging Sinc interpolation optimization method and device based on FPGA. BACKGROUND

[0002] The BP (Back Projection) algorithm is one of the core algorithms in radar imaging, and the precision and efficiency of interpolation calculation of the BP algorithm directly affect the imaging quality and real-time performance. The Sinc interpolation has a significant advantage in the BP algorithm due to its excellent spectral preservation characteristics, but it faces the challenges of high computational complexity and resource consumption in hardware implementation.

[0003] In the prior art, a Sinc interpolation method based on RAM block and pipeline design is proposed in Chinese patent (publication number CN107193784A), which reduces the hardware complexity through formula optimization and division design, but does not optimize the data access mode of the BP algorithm. Chinese patent (publication number CN105117196A) proposes a parallel Sinc interpolation method based on FPGA, which aims to solve the problem of low efficiency of serial interpolation. The method uses a lookup table to store interpolation kernel coefficients, and combines a parallel multiply-add tree to achieve high-speed interpolation. However, the design results in large storage resource consumption, and the precision is limited by the size of the lookup table. In addition, the existing solutions are mostly general architectures, which do not combine the real-time performance requirements of the BP algorithm for targeted design, resulting in limited computational efficiency.

[0004] Current Sinc interpolation implementation mainly adopts pure fixed-point or pure floating-point strategy. The pure floating-point scheme can guarantee high precision, but the FPGA resource consumption is too large to meet the real-time requirements; the pure fixed-point scheme has lower resource occupation, but in the scene of large numerical square root or small numerical division, the precision loss or resource utilization rate is easily caused by unreasonable bit width design. Therefore, how to balance the calculation precision and efficiency under limited hardware resources has become a key problem to be solved in real-time BP imaging. SUMMARY

[0005] To solve the above technical problems, the application provides a BP imaging Sinc interpolation optimization method and device based on FPGA, which significantly reduces resource consumption while ensuring interpolation precision through full-pipeline parallel architecture and fixed-point-floating-point collaborative calculation, providing a feasible solution for efficient BP imaging on the FPGA platform.

[0006] To achieve the above purpose, the technical solution adopted by the application is as follows:

[0007] A BP imaging Sinc interpolation optimization method based on FPGA, the method comprising:

[0008] Step 1: using a double-BRAM ping-pong buffer structure to cache a one-dimensional sampling complex sequence input;

[0009] Step 2, calculate the Euclidean distance between the track coordinates and the imaging grid coordinates to obtain the slant range, and generate an interpolation index based on the slant range, wherein in the slant range calculation process, after the difference, square and accumulation operations are completed by fixed-point operation, the square root calculation is realized by floating-point operation;

[0010] Step 3, according to the integer part of the interpolation index, eight sampling data on both sides of the interpolation point are read from the BRAM in parallel;

[0011] Step 4, according to the decimal part of the interpolation index, eight sinc interpolation coefficients are generated by parallel calculation using fixed-point addition, subtraction and multiplication operations and floating-point division;

[0012] Step 5, the eight sinc interpolation coefficients and the corresponding eight sampling data are input into the parallel multiplication and addition array module, and the multiplication and accumulation operation is completed by the fixed-point multiplier and the three-level fixed-point addition tree, and the final interpolation result is output.

[0013] On the other hand, the application provides a BP imaging Sinc interpolation optimization device based on FPGA, comprising:

[0014] The cache module is used to cache the input one-dimensional sampling complex sequence by using a double-BRAM ping-pong cache structure;

[0015] The slant range and index calculation module is used to calculate the Euclidean distance between the track coordinates and the imaging grid coordinates to obtain the slant range, and generate an interpolation index based on the slant range, wherein in the slant range calculation process, after the difference, square and accumulation operations are completed by fixed-point operation, the square root calculation is realized by floating-point operation;

[0016] The sampling data reading module is used to read eight sampling data on both sides of the interpolation point from the BRAM in parallel according to the integer part of the interpolation index;

[0017] The Sinc coefficient array calculation module is used to generate eight sinc interpolation coefficients by parallel calculation using fixed-point addition, subtraction and multiplication operations and floating-point division according to the decimal part of the interpolation index;

[0018] The interpolation calculation module is used to input the eight sinc interpolation coefficients and the corresponding eight sampling data into the parallel multiplication and addition array module, complete the multiplication and accumulation operation by the fixed-point multiplier and the three-level fixed-point addition tree, and output the final interpolation result.

[0019] In a third aspect, the application provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the foregoing BP imaging Sinc interpolation optimization method based on FPGA.

[0020] In a fourth aspect, the present application provides a computer readable storage medium, which stores executable instructions, and the instructions, when executed by a processor, enable the processor to implement the foregoing FPGA-based BP imaging Sinc interpolation optimization method.

[0021] The present application has the following advantages:

[0022] Efficiency and throughput are improved: through full pipelining and parallel design, the slant distance index calculation, Sinc coefficient generation and parallel multiplication and addition operation are organically integrated, eliminating the data dependency and calculation bottleneck in the traditional scheme, realizing efficient pipelining processing of the eight-point Sinc interpolation of the BP algorithm, greatly improving the imaging speed and data throughput, and meeting the real-time requirement.

[0023] Optimize hardware resource utilization: a fixed-point and floating-point mixed precision strategy is adopted, floating-point calculation is introduced for square root and division operation on the basis of overall fixed-point, and resource waste caused by unreasonable bit width in the pure fixed-point scheme is avoided. The resource consumption of each module is significantly reduced, and the hardware overhead of FPGA is significantly reduced.

[0024] Improve interpolation precision and imaging quality: through floating-point operation optimization of key calculation nodes (such as slant distance and index calculation), the precision problem of pure fixed-point scheme in large number square root and small number division is solved. Experiments show that the calculation precision of slant distance and index is improved by 3 orders of magnitude compared with the pure fixed-point scheme, and the precision of Sinc coefficient is improved by 1-2 orders of magnitude, which ensures high-fidelity imaging effect. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The FPGA-based BP imaging Sinc interpolation optimization method of the present application is shown in the schematic diagram;

[0026] Figure 2 The schematic diagram of slant distance and index calculation is shown in the schematic diagram;

[0027] Figure 3 The schematic diagram of floating-point square root operation is shown in the schematic diagram;

[0028] Figure 4 The schematic diagram of Sinc coefficient array calculation is shown in the schematic diagram;

[0029] Figure 5 The schematic diagram of parallel multiplication and addition array is shown in the schematic diagram. DETAILED DESCRIPTION

[0030] The present application will be further described below in conjunction with the drawings and examples.

[0031] As shown in the drawings, Figure 1 The present application provides an FPGA-based BP imaging Sinc interpolation optimization method, which comprises:

[0032] Step 1: Use a dual BRAM ping-pong buffer structure to buffer the input one-dimensional sampled complex number sequence;

[0033] Step 2: Calculate the Euclidean distance between the track coordinates and the imaging grid coordinates to obtain the slant range. Generate an interpolation index based on the slant range. The difference, square sum, and accumulation operations are performed using fixed-point arithmetic, and the square root is calculated using floating-point arithmetic.

[0034] Step 3: Based on the integer part of the interpolation index (Index0), read the eight sampled data on both sides of the interpolation point in parallel from the BRAM;

[0035] Step 4: Based on the decimal part of the interpolation index (Index1), generate eight sinc interpolation coefficients by parallel calculation of fixed-point addition, subtraction, multiplication and floating-point division.

[0036] Step 5: Input the eight sinc interpolation coefficients and the corresponding eight sampled data into the parallel multiply-accumulate array module, and complete the multiply-accumulate operation through the fixed-point multiplier and the three-level fixed-point adder tree to output the final interpolation result (result).

[0037] Furthermore, in step 1, the one-dimensional sampled complex sequence (data) to be processed is stored in the control module. Through this data storage control module, the one-dimensional sampled complex sequence is written into the on-chip BRAM (Block RAM) as the data source for subsequent interpolation operations. A dual BRAM ping-pong buffer structure is adopted to hide data write latency and achieve seamless data flow. That is, two independent BRAM storage units are set up; when the first BRAM performs a data write operation, the second BRAM simultaneously performs a data read operation; seamless buffering of the data flow is achieved by alternating read and write operations.

[0038] Furthermore, such as Figure 2 As shown, in step 2, the Euclidean distance, i.e., the slant range, between the track coordinates (x0, y0, z0) and the imaging grid coordinates (x1, y1, z1) is first calculated. This calculation involves subtraction, multiplication, addition, timing adjustments (data is delayed to align with the previous layer's circuitry), and square root operations. Subsequently, the slant range is proportionally transformed, and the interpolation index is calculated. Specifically, the slant range is multiplied by 2fs / c (where c is the speed of light), the minimum echo delay is subtracted, and finally, the result is multiplied by the sampling rate fs to obtain the interpolation index.

[0039] To improve the resource efficiency and computational accuracy of this module, the present invention makes the following optimizations based on the traditional algorithm:

[0040] Fixed-point strategy: A fixed-point scheme is adopted, and all computing cores in the module use fixed-point operations except for square operations. By designing the integer and decimal bit widths of each intermediate variable, the calculation accuracy is maximized under the premise of ensuring that the data does not overflow. Compared with floating-point operations, this strategy can significantly reduce resource consumption and fully exploit the advantages of fixed-point operations.

[0041] Index calculation formula reconstruction: To solve the problem of large variation in the order of magnitude of intermediate variables in the traditional index calculation formula, the calculation process is redesigned. The traditional algorithm first multiplies the slant range by 2 / c, resulting in a very small intermediate variable value, and then multiplies it by fs to enlarge it to the original order of magnitude. This process requires a very high decimal bit width, which can easily cause accuracy loss. The optimized algorithm process is first multiplied by , and then subtracted by (that is, index = (r x 2 x fs / c) - (delay x fs), where r is the final slant range value, fs is the sampling rate, c is the speed of light, and delay is the minimum echo delay). This method avoids large changes in the order of magnitude of intermediate variables, effectively reduces the bit width requirement while ensuring calculation accuracy, thereby saving hardware resources.

[0042] Floating square root operation: The traditional pure fixed-point square root operation is usually implemented using the CORDIC algorithm. However, the input and output bit width limitations of the CORDIC core result in the integer bit width occupying the decimal bit width in large numerical square root operations, reducing the calculation accuracy. In addition, the full-bit-width CORDIC core consumes a lot of resources. Especially in the slant range calculation of the BP imaging algorithm, high accuracy is required to ensure the accuracy of interpolation. However, due to the large square value of the slant range, the integer bit width usually needs to exceed 20 bits, further exacerbating the problem of rising bit width and decreasing slant range calculation accuracy. To solve this problem, as shown in Figure 3 , the invention uses floating-point square root operation instead of fixed-point square root operation. Specifically, the three-dimensional coordinate difference between the flight path coordinates and the imaging grid coordinates is calculated, the dimensional difference is squared and accumulated (i.e., the square of the slant range), the accumulated result is converted to a floating-point number for floating-point square root operation, and the square root result is converted back to a fixed-point number as the final slant range value for subsequent index calculation. This scheme not only reduces resource consumption but also significantly improves calculation accuracy, fully exploiting the advantages of floating-point operations.

[0043] After the above optimization, compared with full floating point operation, the key computing resource consumption is significantly reduced, wherein the lookup table (LUT) saves about 77%, the register saves about 75%, and the DSP resource saves about 32%. At the same time, the calculation accuracy of the key variable nodes, the slant distance r and the index index, is basically the same as that of the full floating point operation. Although the resource consumption is slightly higher than that of the full fixed point design, the calculation accuracy of the key variable nodes, the slant distance r and the index index, is improved by about three orders of magnitude compared with the full fixed point scheme.

[0044] Further, as shown in Figure 4 In step 4, in order to realize the full pipelining of the sinc coefficient array calculation module, eight sinc coefficients need to be generated in parallel, which involves eight addition and subtraction operations, eight multiplication operations and eight division operations. Although the full floating point scheme can guarantee the calculation accuracy, it will bring high multiplication and addition operation resource consumption. Although the pure fixed point scheme can reduce resource consumption, since the numerical range of the sinc coefficient is usually less than 1, and in order to ensure accuracy, the divisor and the dividend need to have a high bit width, therefore the fixed point division will cause low resource utilization due to the waste of integer bit width, and further increase the overall resource consumption.

[0045] In order to solve the above problems, the present application optimizes the resource utilization of the module, and the specific scheme is as follows:

[0046] Fixed point strategy: except for the division operation, all other operations are processed by fixed point, and the bit width is carefully designed to reduce resource consumption as much as possible under the premise of ensuring calculation accuracy.

[0047] Floating point division optimization: in order to solve the problem of resource waste of fixed point division caused by high bit width of divisor and dividend when eight sinc coefficients are calculated in parallel, the present application introduces floating point division. Specifically, the eight denominators and one numerator are converted into floating point numbers, and then eight floating point divisions are performed in parallel, and finally the eight floating point sinc coefficients obtained are converted back to fixed point numbers. Specifically, the decimal part of the index is input into the CORDIC module to calculate the sin value required by the Sinc function (as the numerator). At the same time, the decimal part is processed by eight parallel adders and subtractors, and then multiplied by π to generate eight corresponding denominators. Subsequently, the numerator and the denominator are converted into single precision floating point numbers for floating point division, and finally the floating point result is converted back to fixed point representation. Through this mixed precision method, the waste of integer bit width in fixed point division can be avoided, thereby improving the resource utilization.

[0048] Compared with the full floating-point scheme, the key computing resource consumption of the sinc coefficient array calculation module is significantly reduced through the above-mentioned fixed-point and floating-point mixed optimization strategy. Specifically, the lookup table (LUT) saves about 10%, and the register saves about 5%. At the same time, the mixed precision scheme ensures the calculation complexity, and the calculation accuracy of eight sinc coefficients is basically the same as that of full floating-point operation, meeting the demand of high-precision interpolation. Compared with the pure fixed-point scheme, the scheme significantly reduces the key computing resource consumption while achieving higher calculation accuracy. The lookup table (LUT) saves about 41%, the register saves about 61%, and the calculation accuracy of eight sinc coefficients is improved by one to two orders of magnitude, effectively improving the interpolation quality.

[0049] Further, as shown in Figure 5 The step 5, for the real part and the imaginary part of the sampling data, respectively, eight multipliers are used for multiplication operation in parallel, and then a three-layer adder is used to build an addition tree to finally obtain the interpolation result. The first layer includes 4 adders, which are respectively used to receive the operation results of each two multipliers, the second layer includes 2 adders, which are respectively used to receive the operation results of each two first-layer adders, and the third layer includes 1 adder, which is used to receive the operation results of the two adders in the second layer, that is, the interpolation result. In order to reduce resource consumption, the fixed-point design is adopted in this module. Compared with the pure floating-point version, the fixed-point design can save about 95% of the lookup table (LUT) resources and about 80% of the register resources. At the same time, the accuracy of the final interpolation result is basically the same as that of the pure floating-point calculation result, meeting the accuracy requirement of the system.

[0050] Overall, the fixed-point and floating-point mixed precision method adopted by the interpolation module can achieve a significant saving of about 46% of the LUT resources compared with the pure floating-point implementation. At the same time, in the simulation point target data set test, the accuracy is basically the same as that of the pure floating-point method.

[0051] On the other hand, the present application provides a BP imaging Sinc interpolation optimization device based on FPGA, which comprises various modules capable of realizing each step of the foregoing method, specifically comprising:

[0052] The cache module is used for caching the input one-dimensional sampling complex sequence by using a double-BRAM ping-pong cache structure.

[0053] The slant range and index calculation module is used for calculating the Euclidean distance between the track coordinates and the imaging grid coordinates to obtain the slant range, and generating the interpolation index based on the slant range. In the slant range calculation process, after the difference, square and accumulation operations are completed by fixed-point operation, the square root calculation is realized by floating-point operation.

[0054] The sampling data reading module is used for reading eight sampling data on both sides of the interpolation point from the BRAM in parallel according to the integer part of the interpolation index.

[0055] A sinc coefficient array calculation module is configured to generate eight sinc interpolation coefficients in parallel by using fixed-point addition, subtraction and multiplication operations and floating-point division according to the decimal part of the interpolation index;

[0056] An interpolation calculation module is configured to input the eight sinc interpolation coefficients and corresponding eight sample data into a parallel multiplication and addition array module, complete multiplication and accumulation operations by using fixed-point multipliers and a three-level fixed-point addition tree, and output a final interpolation result.

[0057] In a third aspect, the present application provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the foregoing FPGA-based BP imaging Sinc interpolation optimization method.

[0058] In a fourth aspect, the present application provides a computer-readable storage medium having stored executable instructions, which, when executed by a processor, enable the processor to implement the foregoing FPGA-based BP imaging Sinc interpolation optimization method.

[0059] The above-described specific embodiments further illustrate the purposes, technical solutions and beneficial effects of the present application, and it should be understood that the above-described specific embodiments are merely specific embodiments of the present application and are not intended to limit the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A FPGA-based Sinc interpolation optimization method for BP imaging, characterized in that, The method includes: Step 1: Use a dual BRAM ping-pong buffer structure to buffer the input one-dimensional sampled complex number sequence; including: setting up two independent BRAM storage units, when the first BRAM performs a data write operation, the second BRAM simultaneously performs a data read operation, and achieves seamless buffering of the data stream by alternating between read and write operations; Step 2: Calculate the Euclidean distance between the track coordinates and the imaging grid coordinates to obtain the slant range. Based on the slant range, generate an interpolation index. During the slant range calculation, fixed-point arithmetic is used to perform the difference, square sum, and accumulation operations, followed by floating-point arithmetic to perform the square root calculation. This includes: The three-dimensional coordinate difference between the track coordinates and the imaging grid coordinates is calculated. Fixed-point square operations are performed on the differences in each dimension, and the results are accumulated. The accumulated results are converted to floating-point numbers, and a floating-point square root operation is performed. The square root result is then converted back to a fixed-point number as the final slant range value. The generation of the interpolation index based on the slant range includes: index = (r×2×fs / c) - (delay×fs), Where r is the final slant range, fs is the sampling rate, c is the speed of light, and delay is the minimum echo delay; Step 3: Based on the integer part of the interpolation index, read the eight sampled data on both sides of the interpolation point in parallel from the BRAM; Step 4: Based on the decimal part of the interpolation index, generate eight sinc interpolation coefficients by parallel calculation using fixed-point addition, subtraction, multiplication and floating-point division. Step 5: Input the eight sinc interpolation coefficients and the corresponding eight sampled data into the parallel multiply-accumulate array module, and complete the multiply-accumulate operation through the fixed-point multiplier and the three-level fixed-point adder tree to output the final interpolation result.

2. The FPGA-based Sinc interpolation optimization method for BP imaging according to claim 1, characterized in that, In step 4, the calculation of the eight sinc interpolation coefficients adopts a mixed precision strategy, in which addition, subtraction, and multiplication operations use customized variable-length fixed-point operations, and division operations use single-precision floating-point operations.

3. The FPGA-based Sinc interpolation optimization method for BP imaging according to claim 1, characterized in that, In step 5, the parallel multiply-accumulate array module includes eight parallel complex multipliers and a three-layer complex addition tree structure. The first layer includes four complex adders, which are used to receive the operation results of every two multipliers. The second layer includes two complex adders, which are used to receive the operation results of every two adders in the first layer. The third layer includes one complex adder, which is used to receive the operation results of the two adders in the second layer, i.e., the interpolation result.

4. The FPGA-based Sinc interpolation optimization method for BP imaging according to claim 3, characterized in that, Each multiplier and adder supports variable-length fixed-point arithmetic, with the bit width adjusted as needed.

5. A FPGA-based Sinc interpolation optimization device for BP imaging, characterized in that, include: The caching module is used to cache the input one-dimensional sampled complex number sequence using a dual BRAM ping-pong cache structure; it includes: setting up two independent BRAM storage units, when the first BRAM performs a data write operation, the second BRAM simultaneously performs a data read operation, and achieving seamless buffering of the data stream by alternating between read and write operations; The slant range and index calculation module is used to calculate the Euclidean distance between the track coordinates and the imaging grid coordinates to obtain the slant range, and to generate an interpolation index based on the slant range. During the slant range calculation process, fixed-point arithmetic is used to perform difference, square sum, and accumulation operations, followed by floating-point arithmetic to perform square root calculations. This includes: The three-dimensional coordinate difference between the track coordinates and the imaging grid coordinates is calculated. Fixed-point square operations are performed on the differences in each dimension, and the results are accumulated. The accumulated results are converted to floating-point numbers, and a floating-point square root operation is performed. The square root result is then converted back to a fixed-point number as the final slant range value. The generation of the interpolation index based on the slant range includes: index = (r×2×fs / c) - (delay×fs), Where r is the final slant range, fs is the sampling rate, c is the speed of light, and delay is the minimum echo delay; The sampling data reading module is used to read eight sampling data points on both sides of the interpolation point in parallel from the BRAM according to the integer part of the interpolation index. The Sinc coefficient array calculation module is used to generate eight sinc interpolation coefficients in parallel using fixed-point addition, subtraction, multiplication and floating-point division based on the decimal part of the interpolation index. The interpolation calculation module is used to send the eight sinc interpolation coefficients and the corresponding eight sampled data into the parallel multiply-accumulate array module, and complete the multiply-accumulate operation through a fixed-point multiplier and a three-level fixed-point adder tree to output the final interpolation result.

6. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When one or more programs are executed by the one or more processors, the one or more processors implement the FPGA-based BP imaging Sinc interpolation optimization method according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, It stores executable instructions that, when executed by a processor, enable the processor to implement the FPGA-based BP imaging Sinc interpolation optimization method as described in any one of claims 1-4.

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