Preparation method of semiconductor device
By using the ALD process to form multiple dielectric layers in the trenches of flash memory devices and modifying the trench profile, the problems of trench overhang and void defects are solved, thereby improving the electrical performance of the devices.
Patent Information
- Application Number
- CN202510969573.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-11-11
AI Technical Summary
In flash memory devices, cantilever defects appear at the internal lateral dimension contraction points of the trench, resulting in void defects at the bottom of the trench, which affects electrical performance.
The ALD process is used to form multiple dielectric layers in the trench, and the trench contour is made into an inverted trapezoid shape by back etching to avoid the occurrence of cantilever defects and void defects.
It eliminates cantilever defects inside the trench, avoids void defects, and improves the electrical performance of flash memory devices.
Smart Images
Figure CN120936028A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for preparing a semiconductor device. Background Technology
[0002] With the development of specialized processes, the contours of trenches in the inter-layer dielectric of flash memory devices have become increasingly diverse. Trenches are typically wider at the bottom and narrower at the top. During the deposition of oxide (dielectric) layers or other material layers in the trenches, overhang defects are prone to occur at the lower middle section of the trench (the junction of the wider bottom and narrower top) where the lateral dimensions shrink. This can also be understood as the oxide (dielectric) layer or other material layer in the trench prematurely sealing at the location where the lateral dimensions shrink, resulting in void defects at the bottom of the trench, thereby affecting the electrical performance of the flash memory device. Summary of the Invention
[0003] This application provides a method for fabricating a semiconductor device, which can solve the problem that the trench of a flash memory device is prematurely sealed by the material layer at the location of internal lateral dimension shrinkage, resulting in void defects at the bottom of the trench, thereby affecting the electrical performance of the flash memory device.
[0004] This application provides a method for fabricating a semiconductor device, including:
[0005] A semiconductor structure is provided, wherein a trench is formed in the semiconductor structure, wherein the trench includes: a first sub-trench and a second sub-trench, the first sub-trench is located above the second sub-trench and communicates with the second sub-trench, and the lateral opening size of the first sub-trench is smaller than the lateral opening size of the second sub-trench;
[0006] A first dielectric layer is formed using an ALD process. The first dielectric layer covers the sidewalls of the first sub-trench and the sidewalls and bottom wall of the second sub-trench, as well as the surface of the semiconductor structure.
[0007] The first dielectric layer on the sidewall of the first sub-trench, a portion of the first dielectric layer on the sidewall of the second sub-trench, and the first dielectric layer on the surface of the semiconductor structure are etched back.
[0008] A second dielectric layer is formed using an ALD process. The second dielectric layer covers the first dielectric layer on the sidewalls of the first sub-trench and the sidewalls and bottom walls of the second sub-trench, as well as the surface of the semiconductor structure.
[0009] A portion of the second dielectric layer on the sidewall of the first sub-trench and the second dielectric layer on the surface of the semiconductor structure are etched back to make the remaining space of the trench in the shape of an inverted trapezoid.
[0010] A third dielectric layer is formed using an ALD process, which fills all remaining space in the trench and covers the surface of the semiconductor structure.
[0011] Optionally, in the method for fabricating the semiconductor device, the semiconductor structure includes at least: a substrate, a gate dielectric layer, a floating gate layer, an ONO film layer, a control gate layer, a fourth dielectric layer, and an active region. The gate dielectric layer is located on the surface of the substrate, the floating gate layer covers the gate dielectric layer, the ONO film layer covers the floating gate layer, the control gate layer covers the ONO film layer, the fourth dielectric layer covers the control gate layer, and the connected first sub-trench and second sub-trench are located in the fourth dielectric layer, the control gate layer, the ONO film layer, the floating gate layer, and the gate dielectric layer. The active region is located in the substrate at the bottom of the second sub-trench.
[0012] Optionally, in the method for fabricating the semiconductor device, after forming the third dielectric layer using the ALD process, the method further includes etching the third dielectric layer, the second dielectric layer, and the first dielectric layer at the middle position of the trench to the surface of the substrate to form a contact hole.
[0013] Optionally, in the method for fabricating the semiconductor device, after forming the contact hole, the method further includes: forming a metal material layer, wherein the metal material layer fills the entire contact hole and contacts the active region.
[0014] Optionally, in the method for fabricating the semiconductor device, a SiCoNi etching process is used to etch back the first dielectric layer on the sidewall of the first sub-trench, a portion of the first dielectric layer on the sidewall of the second sub-trench, and the first dielectric layer on the surface of the semiconductor structure.
[0015] Optionally, in the method for fabricating the semiconductor device, a SiCoNi etching process is used to etch back a portion of the second dielectric layer on the sidewall of the first sub-trench and the second dielectric layer on the surface of the semiconductor structure, so that the remaining space of the trench is inverted trapezoidal.
[0016] Optionally, in the method for fabricating the semiconductor device, the first dielectric layer, the second dielectric layer, and the third dielectric layer are made of silicon dioxide.
[0017] Optionally, in the method for fabricating the semiconductor device, the fourth dielectric layer is made of silicon nitride.
[0018] The technical solution of this application has at least the following advantages:
[0019] In this application, an ALD process is first used to form a first dielectric layer in the first and second sub-trenches. Then, the first dielectric layer on the sidewall of the first sub-trench and a portion of the first dielectric layer on the sidewall of the second sub-trench are etched back. This fills and modifies the space near the sidewall of the second sub-trench, making the lateral opening size of the second sub-trench smaller than or equal to the lateral opening size of the first sub-trench, thereby eliminating cantilever defects in the trench. Furthermore, an ALD process is used to form a second dielectric layer on the sidewall of the first sub-trench and on the first dielectric layer. Then, a portion of the second dielectric layer on the sidewall of the first sub-trench is etched back. This modifies the trench contour into an inverted trapezoidal shape. Finally, an ALD process is used to form a third dielectric layer to fill the remaining space in the trench. This avoids premature sealing of the trench at the location where the internal lateral dimension shrinks, eliminating cantilever defects and preventing void defects at the bottom of the trench, thus improving the electrical performance of the flash memory device. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0021] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;
[0022] Figures 2-7 This is a schematic diagram of the semiconductor structure in each process step of the semiconductor device fabrication according to an embodiment of the present invention;
[0023] The reference numerals in the attached figures are explained as follows:
[0024] 10-Substrate, 11-Active region, 20-Gate dielectric layer, 30-Floating gate layer, 40-ONO film layer, 50-Control gate layer, 60-Fourth dielectric layer, 70-Trench, 71-First sub-trench, 72-Second sub-trench, 81-First dielectric layer, 82-Second dielectric layer, 83-Third dielectric layer. Detailed Implementation
[0025] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0026] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0028] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0029] This application provides a method for fabricating a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method for fabricating the semiconductor device includes:
[0030] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a trench-formed semiconductor structure according to an embodiment of this application. A semiconductor structure is provided, taking a flash memory device as an example. The semiconductor structure includes at least: a substrate 10, a gate dielectric layer 20, a floating gate layer 30, an ONO film layer 40, a control gate layer 50, a fourth dielectric layer 60, and an active region 11. The gate dielectric layer 20 is located on the surface of the substrate 10. The floating gate layer 30 covers the gate dielectric layer 20. The ONO film layer 40 covers the floating gate layer 30. The control gate layer 50 covers the ONO film layer 40. The fourth dielectric layer 60 covers the control gate layer 50.
[0031] In this embodiment, the fourth dielectric layer 60 is made of silicon nitride.
[0032] Furthermore, a trench 70 is formed in the semiconductor structure 10, the trench including a first sub-trench 71 and a second sub-trench 72. The first sub-trench 71 is located above and communicates with the second sub-trench 72, and the lateral opening size of the first sub-trench 71 is smaller than the lateral opening size of the second sub-trench 72. The communicating first sub-trench 71 and second sub-trench 72 are located in the fourth dielectric layer 60, the control gate layer 50, the ONO film layer 40, the floating gate layer 30, and the gate dielectric layer 20. The active region 11 is located in the substrate 10 at the bottom of the second sub-trench 72.
[0033] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the first dielectric layer according to an embodiment of this application. The first dielectric layer 81 is formed by ALD process. The first dielectric layer 81 covers the sidewalls of the first sub-trench 71 and the sidewalls and bottom wall of the second sub-trench 72, as well as the surface covering the fourth dielectric layer 60.
[0034] In this embodiment, the first dielectric layer 81 is made of silicon dioxide.
[0035] Preferably, the thickness of the first dielectric layer 81 is 200 angstroms to 230 angstroms.
[0036] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the first dielectric layer is etched back according to an embodiment of this application. The first dielectric layer 81 on the sidewall of the first sub-trench 71, a portion of the first dielectric layer 81 on the sidewall of the second sub-trench 72, and the first dielectric layer 81 on the surface of the fourth dielectric layer 60 are etched back to fill and modify the space near the sidewall of the second sub-trench 72. The remaining space of the second sub-trench 72 is modified into an inverted trapezoid, so that the lateral opening size of the second sub-trench 72 is less than or equal to the lateral opening size of the first sub-trench 71. This avoids the situation where the junction of the second sub-trench 72 and the first sub-trench 71 is sealed in advance by the first dielectric layer 81 and / or the second dielectric layer 82, thus eliminating the cantilever defect in the trench.
[0037] Preferably, the SiCoNi etching process is used to etch back the first dielectric layer 81 on the sidewall of the first sub-trench 71, a portion of the first dielectric layer 81 on the sidewall of the second sub-trench 72, and the first dielectric layer 81 on the surface of the fourth dielectric layer 60.
[0038] The SiCoNi etching process is a pre-cleaning process with a high SiO2 / Si etching selectivity ratio of at least 20:1. This effectively removes the first dielectric layer 81 on the sidewall of the first sub-trench 71, a portion of the first dielectric layer 81 on the sidewall of the second sub-trench 72, and the first dielectric layer 81 on the surface of the fourth dielectric layer 60, thereby modifying the contour morphology of the trench.
[0039] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the second dielectric layer according to an embodiment of this application. The second dielectric layer 82 is formed by ALD process. The second dielectric layer 82 covers the sidewalls of the first sub-trench 71 and the first dielectric layer 81 on the sidewalls and bottom walls of the second sub-trench 72, as well as the surface of the fourth dielectric layer 60.
[0040] In this embodiment, the material of the second dielectric layer 82 is silicon dioxide.
[0041] Preferably, the thickness of the second dielectric layer 82 is 200 angstroms to 230 angstroms.
[0042] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the second dielectric layer is etched back according to an embodiment of this application. Part of the second dielectric layer 82 on the sidewall of the first sub-trench 71 and the second dielectric layer 82 on the surface of the fourth dielectric layer 60 are etched back to make the remaining space of the trench 70 form an inverted trapezoid.
[0043] Preferably, a SiCoNi etching process is used to etch back a portion of the second dielectric layer 82 on the sidewall of the first sub-trench 71 and the second dielectric layer 82 on the surface of the fourth dielectric layer 60, so that the remaining space of the trench 70 is inverted trapezoidal, that is, the remaining space of the combination of the first sub-trench 71 and the second sub-trench 72 is inverted trapezoidal.
[0044] Finally, proceed to step S6: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the third dielectric layer in an embodiment of this application. The third dielectric layer 83 is formed using an ALD process. The third dielectric layer 83 fills all the remaining space of the trench 70 and covers the surface of the fourth dielectric layer 60.
[0045] In this embodiment, the third dielectric layer 83 is made of silicon dioxide.
[0046] Preferably, the thickness of the third dielectric layer 83 is 550 angstroms to 650 angstroms.
[0047] Furthermore, the method for fabricating the semiconductor device may further include: etching the third dielectric layer 83, the second dielectric layer 82 and the first dielectric layer 81 at the middle position of the trench 70 to the substrate surface to form a contact hole (not shown).
[0048] Preferably, after forming the contact hole, the method for fabricating the semiconductor device may further include: forming a metal material layer (not shown), the metal material layer filling the entire contact hole and contacting the active region 11 to bring out the active region 11.
[0049] In this application, an ALD process is first used to form a first dielectric layer in the first and second sub-trenches. Then, the first dielectric layer on the sidewall of the first sub-trench and a portion of the first dielectric layer on the sidewall of the second sub-trench are etched back. This fills and modifies the space near the sidewall of the second sub-trench, making the lateral opening size of the second sub-trench smaller than or equal to the lateral opening size of the first sub-trench, thereby eliminating cantilever defects in the trench. Furthermore, an ALD process is used to form a second dielectric layer on the sidewall of the first sub-trench and on the first dielectric layer. Then, a portion of the second dielectric layer on the sidewall of the first sub-trench is etched back. This modifies the trench contour into an inverted trapezoidal shape. Finally, an ALD process is used to form a third dielectric layer to fill the remaining space in the trench. This avoids premature sealing of the trench at the location where the internal lateral dimension shrinks, eliminating cantilever defects and preventing void defects at the bottom of the trench, thus improving the electrical performance of the flash memory device.
[0050] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor structure is provided, wherein a trench is formed in the semiconductor structure, wherein the trench includes: a first sub-trench and a second sub-trench, the first sub-trench is located above the second sub-trench and communicates with the second sub-trench, and the lateral opening size of the first sub-trench is smaller than the lateral opening size of the second sub-trench; A first dielectric layer is formed using an ALD process. The first dielectric layer covers the sidewalls of the first sub-trench and the sidewalls and bottom wall of the second sub-trench, as well as the surface of the semiconductor structure. The first dielectric layer on the sidewall of the first sub-trench, a portion of the first dielectric layer on the sidewall of the second sub-trench, and the first dielectric layer on the surface of the semiconductor structure are etched back. A second dielectric layer is formed using an ALD process. The second dielectric layer covers the first dielectric layer on the sidewalls of the first sub-trench and the sidewalls and bottom walls of the second sub-trench, as well as the surface of the semiconductor structure. A portion of the second dielectric layer on the sidewall of the first sub-trench and the second dielectric layer on the surface of the semiconductor structure are etched back to make the remaining space of the trench in the shape of an inverted trapezoid. A third dielectric layer is formed using an ALD process, which fills all remaining space in the trench and covers the surface of the semiconductor structure.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The semiconductor structure includes at least: a substrate, a gate dielectric layer, a floating gate layer, an ONO film layer, a control gate layer, a fourth dielectric layer, and an active region. The gate dielectric layer is located on the surface of the substrate. The floating gate layer covers the gate dielectric layer. The ONO film layer covers the floating gate layer. The control gate layer covers the ONO film layer. The fourth dielectric layer covers the control gate layer. A first sub-trench and a second sub-trench that are connected are located in the fourth dielectric layer, the control gate layer, the ONO film layer, the floating gate layer, and the gate dielectric layer. The active region is located in the substrate at the bottom of the second sub-trench.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, After forming the third dielectric layer using the ALD process, the method for fabricating the semiconductor device further includes etching the third dielectric layer, the second dielectric layer, and the first dielectric layer at the middle position of the trench to the surface of the substrate to form a contact hole.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, After forming the contact hole, the method for fabricating the semiconductor device further includes: forming a metal material layer that fills the entire contact hole and contacts the active region.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first dielectric layer on the sidewall of the first sub-trench, a portion of the first dielectric layer on the sidewall of the second sub-trench, and the first dielectric layer on the surface of the semiconductor structure are etched back using the SiCoNi etching process.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, A portion of the second dielectric layer on the sidewall of the first sub-trench and the second dielectric layer on the surface of the semiconductor structure are etched back using a SiCoNi etching process, so that the remaining space of the trench is inverted trapezoidal.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first dielectric layer, the second dielectric layer, and the third dielectric layer are made of silicon dioxide.
8. The method for fabricating a semiconductor device according to claim 2, characterized in that, The fourth dielectric layer is made of silicon nitride.