Preparation method of high-electron-mobility transistor and high-electron-mobility transistor

Abstract

The embodiment of the invention relates to a preparation method of a high-electron-mobility transistor and the high-electron-mobility transistor, and the method comprises the steps: providing an epitaxial wafer which comprises a substrate, a channel layer, a barrier layer, a passivation supporting layer and a gate material layer; removing a part of the gate material layer to form a gate layer, and exposing the passivation support layer through the removed part of the gate material layer; a passivation main body layer is epitaxially grown on the surface of the exposed passivation supporting layer, the passivation main body layer grows to cover the top surface of the gate layer, and the passivation supporting layer is a single crystal material layer and is in lattice matching with the passivation main body layer; a gate electrode is formed through the passivation body layer in conductive connection with the gate layer, and a source electrode and a drain electrode are formed through the passivation body layer and the passivation support layer in conductive connection with the two-dimensional electron gas channel. Therefore, the crystal quality of the passivation main body layer is guaranteed, the reliability of the device is improved, and the current collapse phenomenon is inhibited.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a high electron mobility transistor and the high electron mobility transistor itself. Background Technology

[0002] High Electron Mobility Transistor (HEMT) is a field-effect transistor based on the high mobility characteristics of two-dimensional electron gas (2DEG) in a heterojunction. It has high electron mobility at low temperature and low electric field, enabling high-speed and low-noise operation.

[0003] In existing HEMT devices, the reliability of the device is improved by adjusting and designing the passivation layer, especially the test results of current collapse and environmental reliability tests. However, due to the lattice mismatch between the passivation layer and the underlying film, a large number of interface states are generated between the passivation layer and the underlying film. The resulting passivation layer often has poor crystal quality, which affects the reliability of HEMT devices. Summary of the Invention

[0004] In view of the above, this application provides a method for fabricating a high electron mobility transistor and a high electron mobility transistor in order to solve at least one problem existing in the background art.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a high electron mobility transistor, the method comprising:

[0006] An epitaxial wafer is provided, the epitaxial wafer including a substrate and a channel layer, a barrier layer, a passivation support layer and a gate material layer sequentially formed on the substrate by an epitaxial growth process, wherein at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel;

[0007] A portion of the gate material layer is removed, leaving a portion of the gate material layer located within a predetermined gate formation region as the gate layer. The passivation support layer is exposed via the removed portion of the gate material layer.

[0008] A passivation host layer is epitaxially grown on the exposed surface of the passivation support layer, the passivation host layer being grown to cover the top surface of the gate layer, and the passivation support layer being a single-crystal material layer and lattice-matched with the passivation host layer;

[0009] A gate electrode is formed that is electrically connected to the gate layer through the passivation host layer, and a source electrode and a drain electrode are formed that are electrically connected to the two-dimensional electron gas channel through the passivation host layer and the passivation support layer.

[0010] In conjunction with the first aspect of this application, in an alternative embodiment, the provision of the epitaxial wafer includes:

[0011] The passivation support layer is formed by in-situ epitaxial growth on the barrier layer.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, removing a portion of the gate material layer includes:

[0013] A patterned mask layer is formed on the gate material layer;

[0014] The gate material layer is etched using the patterned mask layer as a mask to remove the portion of the gate material layer that is not covered by the patterned mask layer. During the etching process, the passivation support layer serves as an etching stop layer.

[0015] In conjunction with the first aspect of this application, in an optional embodiment, the materials of both the passivation support layer and the passivation body layer comprise AlN-based insulating materials and / or BN-based insulating materials.

[0016] In conjunction with the first aspect of this application, in an optional embodiment, the material of the passivation support layer and the material of the passivation host layer include at least one of the following: AlN, BN, BAlN, InAlN, InBAlN.

[0017] In conjunction with the first aspect of this application, in an optional embodiment, the thickness of the passivation support layer is greater than or equal to 0.5 nm; the thickness of the passivation body layer is greater than the thickness of the passivation support layer.

[0018] Secondly, embodiments of this application provide a high electron mobility transistor, comprising:

[0019] Substrate;

[0020] A channel layer and a barrier layer are sequentially formed on the substrate by an epitaxial growth process, wherein at least a portion of the channel layer near the region of the barrier layer is used to form a two-dimensional electron gas channel;

[0021] A passivation support layer is formed on the barrier layer by an epitaxial growth process, wherein the passivation support layer is a single crystal material layer;

[0022] A gate layer covering a portion of the passivation support layer;

[0023] A passivation host layer covering the passivation support layer and the gate layer, the passivation host layer being formed by epitaxial growth on the surface of the passivation support layer not covered by the gate layer, the passivation support layer being lattice-matched with the passivation host layer;

[0024] A gate electrode that is electrically connected to the gate layer through the passivation host layer, and a source electrode and a drain electrode that are electrically connected to the two-dimensional electron gas channel through the passivation host layer and the passivation support layer.

[0025] In conjunction with the second aspect of this application, in an optional embodiment, the materials of both the passivation support layer and the passivation body layer comprise AlN-based insulating materials and / or BN-based insulating materials.

[0026] In conjunction with a second aspect of this application, in an optional embodiment, the material of the passivation support layer and the material of the passivation host layer include at least one of the following: AlN, BN, BAlN, InAlN, InBAlN.

[0027] In conjunction with the second aspect of this application, in an optional embodiment, the thickness of the passivation support layer is greater than or equal to 0.5 nm; the thickness of the passivation host layer is greater than the thickness of the passivation support layer.

[0028] The high electron mobility transistor fabrication method and high electron mobility transistor provided in this application embodiment involve setting a passivation support layer and epitaxially growing a passivation host layer on the surface of the passivation support layer. The passivation support layer is a single crystal material layer and its lattice matches that of the passivation host layer. In this way, the passivation support layer serves as a growth support layer for the passivation host layer, which helps to ensure the crystal quality of the passivation host layer, thereby improving the reliability of the device and suppressing current collapse.

[0029] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0030] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0031] Figure 1 A schematic flowchart illustrating the fabrication method of a high electron mobility transistor provided in an embodiment of this application;

[0032] Figures 2 to 11 This is a cross-sectional structural diagram of the high electron mobility transistor provided in the embodiments of this application during the fabrication process. Detailed Implementation

[0033] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0035] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0037] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0040] This application provides a method for fabricating a high electron mobility transistor. Please refer to [link / reference]. Figure 1 The method includes:

[0041] S1. Provide an epitaxial wafer, the epitaxial wafer including a substrate and a channel layer, a barrier layer, a passivation support layer and a gate material layer sequentially formed on the substrate by an epitaxial growth process, wherein at least a portion of the channel layer is close to the region of the barrier layer for forming a two-dimensional electron gas channel.

[0042] S2. Remove part of the gate material layer, retain the portion of the gate material layer located within the gate preset formation area as the gate layer, and expose the passivation support layer through the removed portion of the gate material layer;

[0043] S3. A passivation host layer is epitaxially grown on the surface of the exposed passivation support layer. The passivation host layer is grown to the top surface covering the gate layer. The passivation support layer is a single crystal material layer and its lattice matches that of the passivation host layer.

[0044] S4. Form a gate electrode that is electrically connected to the gate layer through the passivation host layer, and form a source electrode and a drain electrode that are electrically connected to the two-dimensional electron gas channel through the passivation host layer and the passivation support layer.

[0045] Understandably, in this embodiment of the application, a passivation support layer is provided, and a passivation host layer is epitaxially grown on the surface of the passivation support layer. The passivation support layer is a single crystal material layer and its lattice matches that of the passivation host layer. In this way, the passivation support layer serves as a growth support layer for the passivation host layer, which helps to ensure the crystal quality of the passivation host layer, thereby improving the reliability of the device and suppressing current collapse.

[0046] Below, we will combine Figures 2 to 11 The fabrication method and beneficial effects of the high electron mobility transistor provided in the embodiments of this application will be further described in detail.

[0047] First, please refer to Figure 2 We provide epitaxial wafers.

[0048] The epitaxial wafer includes a substrate 100, which can be made of any suitable material known to those skilled in the art, such as a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate.

[0049] The substrate 100 may include an upper surface for forming a HEMT device and a lower surface opposite to the upper surface. Ignoring the flatness of the upper and lower surfaces, the plane containing the upper and lower surfaces of the substrate 100, or more precisely, the center plane of the upper and lower surfaces, is defined as the plane containing the substrate 100. The direction parallel to the plane containing the substrate 100 is the direction along the plane of the substrate 100. The direction perpendicular to the plane containing the substrate 100 can also be called the thickness direction of the substrate 100. This thickness direction is the stacking direction for subsequent deposition of various material layers on the substrate 100, or the height direction of the device.

[0050] Substrate 100 is a growth substrate, and channel layer 131, barrier layer 132, etc. are epitaxial layers formed on the growth substrate using epitaxial growth process.

[0051] The channel layer 131 and the barrier layer 132 constitute a heterojunction structure 130. At least a portion of the region of the channel layer 131 adjacent to the barrier layer 132 is used to form a two-dimensional electron gas channel 133 (see reference). Figure 6 Specifically, the band gap width of the barrier layer 132 is greater than that of the channel layer 131, which causes electrons in the wide-bandgap barrier layer 132 and electrons on the surface of the barrier layer 132 to overflow and move toward the interface of the channel layer 131 near the barrier layer 132 and be confined in the potential well formed at the interface, thereby forming a two-dimensional electron gas (2DEG).

[0052] To improve the crystal quality of the channel layer 131, a nucleation layer 110 and a buffer layer 120 may be formed between the substrate 100 and the heterojunction structure 130 (specifically, the substrate 100 and the channel layer 131); wherein the nucleation layer 110 is located between the substrate 100 and the buffer layer 120. In addition, other epitaxial layers may also be included on the substrate 100, which is not specifically limited in this application.

[0053] The channel layer 131 can be made of N-group alloy materials, including but not limited to GaN, AlGaN, InGaN, InAlGaN, InAlScN, AlScN, InScN, etc. Furthermore, the channel layer 131 can be an undoped material layer (e.g., an undoped GaN layer), thereby causing the channel layer 131 to exhibit high resistance at least in the portion below the two-dimensional electron gas.

[0054] The material of the barrier layer 132 includes any material capable of forming a two-dimensional electron gas channel with the channel layer 131. Specifically, the material of the barrier layer 132 can also be an N-group alloy material, such as gallium nitride-based alloys, specifically one or more of AlGaN, AlScN, InAlGaN, etc. Furthermore, the material of the barrier layer 132 can be an undoped material (e.g., an undoped AlGaN layer); or, the barrier layer 132 can also be an N-doped material layer (e.g., an N-type doped AlGaN layer), thus facilitating the induction of a higher density two-dimensional electron gas.

[0055] As an optional practical application, the high electron mobility transistor in this application is specifically a gallium nitride high electron mobility transistor, i.e., a GaN HEMT device.

[0056] In one specific application, the channel layer 131 is made of gallium nitride; the barrier layer 132 is made of gallium nitride-based alloy, specifically aluminum gallium nitride.

[0057] On the substrate 100, a passivation support layer 140 is also formed by an epitaxial growth process. The passivation support layer 140 can be grown directly on the surface of the barrier layer 132; of course, this application does not exclude the possibility of other material layers between the two. The passivation support layer 140 forms a transition between the barrier layer 132 and the passivation host layer, which can release stress more smoothly and reduce dislocations.

[0058] In order to grow a high-quality passivation body layer in subsequent processes, the passivation support layer 140 is a single-crystal material layer and lattice-matched with the passivation body layer. The selection of growing a single-crystal material layer is not only for the consideration of providing growth support for the passivation body layer, but also conducive to making the epitaxial growth quality of the gate material layer 150 better. The passivation support layer 140 is lattice-matched with the passivation body layer. Specifically, the material of the passivation support layer 140 is selected from materials with the same or similar lattice constants as the material of the passivation body layer, so as to reduce defects and ensure the crystal quality of the passivation body layer.

[0059] It should be understood that the lattice matching degree is an important index reflecting the matching degree of the crystal structures of two materials, specifically manifested as the proximity of their lattice constants. When the lattice constants of two materials are very close, it is called lattice matching; if the difference is large, it is called lattice mismatch. The lattice matching in this application is a broad concept rather than a narrow concept, that is, it is not limited to perfect matching, but includes both the case of the same lattice constant and the case of close lattice constants.

[0060] As an optional specific implementation manner, the material of the passivation support layer 140 includes AlN-based insulating materials and / or BN-based insulating materials.

[0061] Further optionally, the material of the passivation support layer 140 includes at least one of the following: AlN, BN, BAlN, InAlN, InBAlN. Specifically, for example, the passivation support layer 140 is an AlN layer, a BN layer, a B a Al 1-a N layer (0 < a < 1), In b Al 1-b N layer (0 < b < 1), or In c B d Al 1-c-d N layer (0 < c < 1, 0 < d < 1, 0 < c + d < 1) at least one of them.

[0062] Generally speaking, SiO2, SiN, etc. are also commonly used passivation layer materials in GaN HEMT devices. However, SiO2 / SiN is lattice-mismatched with AlGaN and often shows an amorphous state after deposition, resulting in a large number of dangling bonds and interface states between it and the underlying single-crystal AlGaN. If the interface between AlGaN (barrier layer material) and the passivation layer is not good, then the 2DEG is easily adsorbed by the upper passivation layer, causing the conduction ability of the device to deteriorate.

[0063] In the embodiments of this application, when it is required that the passivation support layer 140 is a single-crystal material layer, AlN-based insulating materials and / or BN-based insulating materials are a relatively good choice.

[0064] Optionally, AlN-based and / or BN-based insulating materials may also be doped with at least one of the impurity elements such as C, Fe, and Mg to ensure high resistance insulation.

[0065] As an optional specific implementation, the thickness of the passivation support layer 140 is greater than or equal to 0.5 nm.

[0066] When the thickness of the passivation support layer 140 is less than 0.5 nm, not only is the epitaxial growth process difficult to control, but the passivation support layer 140 is also easily removed in the subsequent step of removing part of the gate material layer, thereby causing damage to the barrier layer 132 below it; while the thickness of the passivation support layer 140 is greater than or equal to 0.5 nm, which can ensure that it provides growth support for the passivation host layer, and at the same time can serve as an etching stop layer in the subsequent step of removing part of the gate material layer.

[0067] In the final fabricated device, the portion of the passivation support layer 140 between the gate layer and the barrier layer 132 can also reduce gate leakage current and increase the gate threshold voltage. Therefore, the upper limit of the thickness of the passivation support layer 140 can be selected according to actual design requirements.

[0068] As an optional specific implementation, a passivation support layer 140 is formed by in-situ epitaxial growth on the barrier layer 132.

[0069] In-situ epitaxial growth refers to continuous growth without changing equipment and growth chambers. This avoids contact with the atmospheric environment during sample transfer, thus preventing sample oxidation and contamination. Furthermore, continuous in-situ epitaxial growth can achieve film interfaces with strong chemical bonding and thermal conductivity. This reduces the interface states between the passivation support layer 140 and the underlying film layer, allowing the passivation support layer 140 to have better crystal quality.

[0070] Next, please continue to refer to... Figure 2 The epitaxial wafer also includes a gate material layer 150 stacked on the passivation support layer 140.

[0071] The gate material layer 150 can be a P-type gate material layer. Further, the material of the gate material layer 150 can include a P-type oxide or a P-type nitride. In a specific example, the material of the gate material layer 150 can include one or more of nickel oxide, copper oxide, tungsten oxide, and vanadium oxide; or, the material of the gate material layer 150 can include p-type doped GaN (p-GaN), etc., and this application does not specifically limit this.

[0072] Since the gate material layer 150 is formed by epitaxial growth on the passivation support layer 140, and the passivation support layer 140 is a single crystal material layer, the epitaxial growth quality of the gate material layer 150 can be guaranteed to be good.

[0073] Understandably, the epitaxial wafer used to fabricate HEMT devices has been improved in this application embodiment. In conventional epitaxial wafers, the gate material layer 150 (usually p-GaN) serves as a cap layer, which covers the surface of the barrier layer 132. In this application embodiment, a passivation support layer 140 is also epitaxially grown between the barrier layer 132 and the gate material layer 150.

[0074] Next, please refer to Figure 3 and Figure 4 Step etching is performed to define the active region of the device.

[0075] Specifically, for example, a first patterned photoresist layer 310 is formed on the gate material layer 150; step etching is performed using the first patterned photoresist layer 310 as a mask to define the active region of the device; and finally, the first patterned photoresist layer 310 is removed.

[0076] Next, please refer to Figure 5 and Figure 6 A portion of the gate material layer 150 is removed, leaving a portion of the gate material layer 150 located within the gate preset formation region as the gate layer 151. The passivation support layer 140 is exposed through the removed portion of the gate material layer 150.

[0077] In actual fabrication, the step of removing a portion of the gate material layer 150 may include: forming a patterned mask layer on the gate material layer 150 (to distinguish it from the patterned mask layers in other photolithography etching steps, it can be named the second patterned mask layer 320); using this patterned mask layer as a mask to etch the gate material layer 150 to remove the portion of the gate material layer 150 not covered by the patterned mask layer. The formed gate layer 151 can be referenced... Figure 6 .

[0078] It is worth noting that in conventional epitaxial wafers, the gate material layer 150 covers the surface of the barrier layer 132. In the same step of removing part of the gate material layer 150 to form the gate layer 151, the etching process can easily damage the barrier layer 132, resulting in a worse interface state. However, in this embodiment, since a passivation support layer 140 is provided between the barrier layer 132 and the gate material layer 150, the passivation support layer 140 acts as an etching stop layer during the etching process, protecting the barrier layer 132.

[0079] Please refer to further information. Figure 6, after etching the gate material layer 150 into the gate layer 151, the two-dimensional electron gas channel 133 under the gate layer 151 is depleted to serve as the channel region of the HEMT device; in the part of the heterojunction structure 130 that is not under the gate layer 151, that is, in the part corresponding to the removed part of the gate material layer 150, a two-dimensional electron gas channel 133 is formed in the region of the channel layer 131 close to the barrier layer 132.

[0080] Next, please refer to Figure 7 . On the surface of the exposed passivation support layer 140, a passivation main body layer 160 is epitaxially grown, and the passivation main body layer 160 grows to cover the top surface of the gate layer 151.

[0081] Obviously, the passivation main body layer 160 is also a single crystal material layer and is lattice-matched with the passivation support layer 140.

[0082] Due to the setting of the passivation support layer 140, the passivation main body layer 160 can achieve high-quality epitaxial growth, thus ensuring the passivation effect, improving the reliability of the device, and weakening the current collapse phenomenon.

[0083] It should be understood that although "on..." in this application means that it can be directly located on other layers, there can also be intermediate layers; for example, "the channel layer 131 formed on the substrate 100" means that the channel layer 131 can be directly formed on the substrate 100, or there can also be a nucleation layer 110 and a buffer layer 120, etc. formed between the substrate 100 and the channel layer 131. However, "epitaxially growing the passivation main body layer 160 on the surface of the exposed passivation support layer 140" means that the surface of the exposed passivation support layer 140 is the growth basis of the passivation main body layer 160, and the passivation main body layer 160 extends outward on the surface of the passivation support layer 140 for a certain distance, and the grown passivation main body layer 160 is in direct contact with the passivation support layer 140.

[0084] As an optional specific implementation manner, the material of the passivation main body layer 160 includes an AlN-based insulating material and / or a BN-based insulating material.

[0085] Further optionally, the material of the passivation main body layer 160 includes at least one of the following: AlN, BN, BAlN, InAlN, InBAlN. Specifically, for example, the passivation main body layer 160 is an AlN layer, a BN layer, B a Al 1-a N layer (0 < a < 1), In b Al 1-b N layer (0 < b < 1), or In c B d Al 1-c-d N layer (0 < c < 1, 0 < d < 1, 0 < c + d < 1) at least one of them.

[0086] Understandably, by adjusting the composition of B and / or In, the lattice constant of AlN-based insulating materials can be adjusted, and thus the lattice constant can be adjusted from being close to being the same as that of AlN.

[0087] The materials of the passivation support layer 140 and the passivation body layer 160 can be selected from any of the following:

[0088] Both the passivation support layer 140 and the passivation host layer 160 are made of AlN;

[0089] Both the passivation support layer 140 and the passivation host layer 160 are made of BN.

[0090] Both the passivation support layer 140 and the passivation host layer 160 are made of BAlN;

[0091] The passivation support layer 140 is made of AlN, and the passivation host layer 160 is made of BAlN;

[0092] The passivation support layer 140 is made of BN, and the passivation host layer 160 is made of BAlN;

[0093] The passivation support layer 140 is made of InAlN, and the passivation host layer 160 is made of InBAlN;

[0094] The passivation support layer 140 is made of BAlN, and the passivation host layer 160 is made of InBAlN.

[0095] Understandably, the above is not an exhaustive list.

[0096] As an optional specific implementation, the thickness of the passivation host layer 160 is greater than the thickness of the passivation support layer 140. Understandably, the passivation support layer 140 serves as the growth support layer for the passivation host layer 160, while the passivation host layer 160 is the main structure responsible for passivation. The passivation host layer 160 has sufficient thickness to ensure the passivation effect, thereby ensuring the reliability of the device.

[0097] Next, please refer to Figure 8 and Figure 9 A source electrode 181 and a drain electrode 182 are formed that are electrically connected to the two-dimensional electron gas channel 133 through the passivation host layer 160 and the passivation support layer 140.

[0098] Specifically, you can refer to the following: Figure 8 The passivation host layer 160 and passivation support layer 140 are etched to form openings exposing the source and drain preset formation regions. In actual processes, a patterned mask layer can first be formed on the passivation host layer 160, and then the etching process can be performed using the patterned mask layer as a mask. Then refer to... Figure 9A source ohmic contact layer 171 and a drain ohmic contact layer 172 are formed within the source and drain openings, respectively, thereby reducing the contact resistance between the metal material and the semiconductor material. Finally, the source and drain openings are filled with metal material to form a source electrode 181 and a drain electrode 182, respectively.

[0099] Please refer to Figure 10 A gate electrode 183 is formed that passes through the passivation host layer 160 and is electrically connected to the gate layer 151.

[0100] It should be understood that, although Figures 8 to 10 The example is shown in the form of forming the source electrode 181 and the drain electrode 182 first, and then forming the gate electrode 183. However, those skilled in the art can adjust the order according to actual needs, and this application does not make specific limitations in this regard.

[0101] In specific fabrication, an opening can be formed within the passivation host layer 160 to expose a predetermined area for forming the gate electrode, and the opening can be filled with metal material to fabricate the gate electrode 183. The step of forming the opening can also be achieved by first forming a patterned mask layer, and then performing an etching process using the patterned mask layer as a mask. An ohmic contact layer can also be provided below the gate electrode 183; this application does not specifically limit this.

[0102] Next, please refer to Figure 11 The above method may further include: forming an interlayer dielectric layer 190 and a metal interconnect structure 200; wherein the interlayer dielectric layer 190 covers the source electrode 181, the drain electrode 182, and the gate electrode 183; the metal interconnect structure 200 is formed in the interlayer dielectric layer 190 on the source electrode 181, the drain electrode 182, and the gate electrode 183, and the metal interconnect structure 200 also extends onto the interlayer dielectric layer 190; the metal interconnect structure 200 may specifically include conductive vias and wiring layers, etc. A second passivation layer 220, as well as source pads 211, drain pads 212, and gate pads 213 are formed on the interlayer dielectric layer 190. The source electrode 181, the drain electrode 182, and the gate electrode 183 are led out to the source pads 211, the drain pads 212, and the gate pads 213, respectively, through the corresponding metal interconnect structures 200.

[0103] Based on this, the present application also provides a high electron mobility transistor, which is prepared by any of the above-described methods for preparing a high electron mobility transistor.

[0104] In addition, please refer to Figure 11This application also provides a high electron mobility transistor, comprising: a substrate 100; a channel layer 131 and a barrier layer 132 sequentially formed on the substrate 100 by an epitaxial growth process, wherein at least a portion of the channel layer 131 adjacent to the barrier layer 132 is used to form a two-dimensional electron gas channel 133; a passivation support layer 140 formed on the barrier layer 132 by an epitaxial growth process, wherein the passivation support layer 140 is a single crystal material layer; a gate layer 151 covering a portion of the passivation support layer 140; and a gate layer 151 covering a portion of the passivation support layer 140. The passive support layer 140 and the gate layer 151 are passivation host layer 160, which is formed by epitaxial growth on the surface of the passive support layer 140 not covered by the gate layer 151. The passive support layer 140 and the passive host layer 160 are lattice matched. The gate electrode 183 is electrically connected to the gate layer 151 through the passive host layer 160, and the source electrode 181 and the drain electrode 182 are electrically connected to the two-dimensional electron gas channel 133 through the passive host layer 160 and the passive support layer 140.

[0105] As an optional specific implementation, the passivation support layer 140 is formed by in-situ epitaxial growth.

[0106] As an optional specific implementation, the passivation support layer 140 serves as an etch stop layer in the process of forming the gate layer 151.

[0107] As an optional specific implementation, the materials of the passivation support layer 140 and the passivation body layer 160 both include AlN-based insulating materials and / or BN-based insulating materials.

[0108] As an optional specific implementation, the materials of the passivation support layer 140 and the passivation body layer 160 include at least one of the following: AlN, BN, BAlN, InAlN, and InBAlN.

[0109] As an optional specific implementation, the thickness of the passivation support layer 140 is greater than or equal to 0.5 nm; the thickness of the passivation body layer 160 is greater than the thickness of the passivation support layer 140.

[0110] It should be noted that the high electron mobility transistor embodiments provided in this application and the high electron mobility transistor fabrication method embodiments belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0111] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for fabricating a high electron mobility transistor, characterized in that, The method includes: An epitaxial wafer is provided, the epitaxial wafer including a substrate and a channel layer, a barrier layer, a passivation support layer and a gate material layer sequentially formed on the substrate by an epitaxial growth process, wherein at least a portion of the channel layer near the barrier layer is used to form a two-dimensional electron gas channel; A portion of the gate material layer is removed, leaving a portion of the gate material layer located within a predetermined gate formation region as the gate layer. The passivation support layer is exposed via the removed portion of the gate material layer. A passivation host layer is epitaxially grown on the exposed surface of the passivation support layer, the passivation host layer being grown to cover the top surface of the gate layer, and the passivation support layer being a single-crystal material layer and lattice-matched with the passivation host layer; A gate electrode is formed that is electrically connected to the gate layer through the passivation host layer, and a source electrode and a drain electrode are formed that are electrically connected to the two-dimensional electron gas channel through the passivation host layer and the passivation support layer.

2. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The provided epitaxial wafer includes: The passivation support layer is formed by in-situ epitaxial growth on the barrier layer.

3. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The removal of a portion of the gate material layer includes: A patterned mask layer is formed on the gate material layer; The gate material layer is etched using the patterned mask layer as a mask to remove the portion of the gate material layer that is not covered by the patterned mask layer. During the etching process, the passivation support layer serves as an etching stop layer.

4. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The materials of the passivation support layer and the passivation body layer both include AlN-based insulating materials and / or BN-based insulating materials.

5. The method for fabricating a high electron mobility transistor according to claim 4, characterized in that, The materials of the passivation support layer and the passivation host layer include at least one of the following: AlN, BN, BAlN, InAlN, and InBAlN.

6. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The thickness of the passivation support layer is greater than or equal to 0.5 nm; the thickness of the passivation host layer is greater than the thickness of the passivation support layer.

7. A high electron mobility transistor, characterized in that, include: Substrate; A channel layer and a barrier layer are sequentially formed on the substrate by an epitaxial growth process, wherein at least a portion of the channel layer near the region of the barrier layer is used to form a two-dimensional electron gas channel; A passivation support layer is formed on the barrier layer by an epitaxial growth process, wherein the passivation support layer is a single crystal material layer; A gate layer covering a portion of the passivation support layer; A passivation host layer covering the passivation support layer and the gate layer, the passivation host layer being formed by epitaxial growth on the surface of the passivation support layer not covered by the gate layer, the passivation support layer being lattice-matched with the passivation host layer; A gate electrode that is electrically connected to the gate layer through the passivation host layer, and a source electrode and a drain electrode that are electrically connected to the two-dimensional electron gas channel through the passivation host layer and the passivation support layer.

8. The high electron mobility transistor according to claim 7, characterized in that, The materials of the passivation support layer and the passivation body layer both include AlN-based insulating materials and / or BN-based insulating materials.

9. The high electron mobility transistor according to claim 8, characterized in that, The materials of the passivation support layer and the passivation host layer include at least one of the following: AlN, BN, BAlN, InAlN, and InBAlN.

10. The high electron mobility transistor according to claim 7, characterized in that, The thickness of the passivation support layer is greater than or equal to 0.5 nm; the thickness of the passivation host layer is greater than the thickness of the passivation support layer.

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