AC input power supply fault detection circuit and electronic device with AC input power supply
By designing an AC input PFD sub-circuit with different detection thresholds and time delays, the problem of insufficient adaptability of existing power supply fault detection circuits under different voltage drop scenarios is solved, achieving rapid response and improved safety, and meeting the application requirements of multiple standards.
Patent Information
- Application Number
- CN202380096415.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-04-24
- Publication Date
- 2025-11-11
AI Technical Summary
Existing AC input power supply fault detection circuits cannot simultaneously meet the requirements of detection speed and accuracy under different voltage drop scenarios, cannot adapt to different application standards, and have insufficient response speed in emergency situations.
The design includes at least two AC input PFD sub-circuits with different detection thresholds and time delays. The AC input power is converted to DC bus voltage through a voltage divider and a three-phase bridge, and a PFD signal is output in case of a fault. Fast response is achieved using components such as optocouplers and transistors.
It achieves rapid response under different voltage drop conditions, meets the requirements of standards such as SEMI F47 and IEC 61800-3, improves the safety and adaptability of electronic devices in the event of failure, simplifies circuit design and reduces costs.
Smart Images
Figure CN120936893A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and more specifically, to AC input power supply fault detection (PFD) circuits and electronic devices having AC input power. Background Technology
[0002] In electronic devices with AC input, such as motor drives or frequency converters in control system applications, there is a risk of unexpected malfunctions such as sudden interruption or unplanned stoppage of AC power. In some applications, such as machine tool processing and vertical transmission, a momentary power outage may cause the motion system to malfunction, leading to unexpected movements, which is very dangerous for machining and may even threaten the safety of the user.
[0003] Therefore, those skilled in the art are dedicated to finding solutions for AC power supply fault detection. Summary of the Invention
[0004] According to embodiments of this application, an AC input PFD circuit and an electronic device with an AC input power supply are provided to expand the application range of the AC input PFD circuit.
[0005] The AC input PFD circuit provided in the embodiments of this application includes: at least two AC input PFD sub-circuits having different detection thresholds corresponding to different time delays. Each AC input PFD sub-circuit is set with a detection threshold and is used to detect the DC bus voltage converted from the AC input power supply. When the AC input power supply fails and the DC bus voltage drops to the detection threshold, a PFD signal indicating that the AC input power supply has failed is output after the corresponding time delay.
[0006] The electronic device with AC input power provided in the embodiments of this application includes: a voltage divider circuit for reducing the high voltage of the AC input power to a desired low voltage; and a three-phase bridge for converting the desired low voltage into a DC bus voltage; the electronic device further includes the aforementioned AC input PFD circuit.
[0007] As can be seen from the above technical solutions, in the embodiments of this application, since the AC input PFD circuit includes at least two AC input PFD sub-circuits with different detection thresholds corresponding to different time delays, the circuit can provide different response speeds under different degrees of DC bus voltage drop, thereby meeting the requirements of different standards such as SEMI F47 and other general standards such as IEC 61800-3 and expanding the application range of the circuit, making the circuit highly adaptable.
[0008] In addition, a sub-circuit of the AC input PFD circuit can improve the response speed of the detection circuit when the DC bus voltage drops significantly, so that the control module can receive the PFD signal as soon as possible and then control the motor to achieve safe shutdown.
[0009] Furthermore, in this example, only three resistors, two capacitors, three diodes, one optocoupler, and one transistor are added, thereby improving the safety of the electronic device at a lower cost. In another example, integrated circuits (ICs) can be used to replace some electronic components, thus simplifying circuit design and installation. Attached Figure Description
[0010] To better understand this application, reference should be made to the following detailed embodiments in conjunction with the accompanying drawings, wherein similar reference numerals refer to corresponding parts throughout the drawings.
[0011] Figure 1 This is a schematic diagram showing a portion of the structure of an electronic device with an AC input power supply.
[0012] Figure 2 This is a schematic diagram illustrating an AC input PFD circuit according to an embodiment of this application.
[0013] Figure 3 This is a schematic diagram illustrating an AC input PFD circuit according to another embodiment of this application.
[0014] The attached figures are labeled as follows:
[0015]
[0016] Detailed Implementation
[0017] Figure 1 This is a schematic diagram showing a portion of the structure of an electronic device with an AC input power supply. For example... Figure 1As shown, an electronic device with an AC input power supply includes a voltage divider circuit 11, a three-phase bridge 12, and an AC input PFD circuit 13. The voltage divider circuit 11 reduces the high voltage of the AC input power supply to a desired relatively low voltage, and then the three-phase bridge 12 converts this relatively low voltage into a DC voltage, which may be referred to as the DC bus voltage. The AC input PFD circuit 13 is equipped with a detection threshold and is used to detect the DC bus voltage and output a PFD signal. When the AC input power supply malfunctions and the DC bus voltage drops to the detection threshold, the AC input PFD circuit 13 can output a PFD signal indicating an AC input power supply malfunction after a preset time delay. The PFD signal can be active low; that is, if the PFD signal outputs a low level, it indicates an AC power input malfunction, and if the PFD signal outputs a high level, it indicates that the AC power input is in a normal state. In other words, the PFD signal indicating an AC input power supply malfunction can be a low-level PFD signal. Of course, in another example, the PFD signal can be active high; that is, in another example, the PFD signal indicating an AC input power supply malfunction can be a high-level PFD signal. Alternatively, the preset time delay can be determined according to SEMI F47 and other general standards such as IEC 61800-3.
[0018] exist Figure 1 In the AC input PFD circuit 13, there are sampling capacitor C1, first discharge resistor R1 of sampling capacitor C1, Zener diode D1, current limiting resistor R2, optocoupler U1, delay capacitor C2, second discharge resistor R3 of delay capacitor C2, and pull-up resistor R4.
[0019] The sampling capacitor C1 is used to sample the DC bus voltage. One end of the sampling capacitor C1 is connected to the DC bus of the electronic device containing the AC input, and the other end of the sampling capacitor C1 is connected to the reference voltage terminal REF.
[0020] The first discharge resistor R1 is used to discharge the sampling capacitor C1 when the AC input power supply fails. The first discharge resistor R1 is connected in parallel with the sampling capacitor C1 and can adjust the charging and discharging time of the sampling capacitor C1.
[0021] Zener diode D1 has a breakdown threshold corresponding to the detection threshold; for example, the breakdown threshold may be approximately equal to the detection threshold. When the AC input power is normal, the voltage across sampling capacitor C1 is greater than the breakdown threshold, causing Zener diode D1 to break down and clamp the voltage across sampling capacitor C1. When the AC input power fails, the voltage across sampling capacitor C1 decreases due to the discharge of the first discharge resistor R1, and when the voltage across sampling capacitor C1 falls below the breakdown threshold, Zener diode D1 is turned off. The cathode of Zener diode D1 is connected to one end of current-limiting resistor R2, and the anode of Zener diode D1 is connected to the anode of optocoupler U1.
[0022] The current-limiting resistor R2 is used to limit the current of the Zener diode D1. The other end of the current-limiting resistor R2 is connected to the DC bus.
[0023] The cathode of optocoupler U1 is connected to the reference voltage terminal REF, the collector of optocoupler U1 is connected to one end of the pull-up resistor R4, and the emitter of optocoupler U1 is connected to one end of the time-delay capacitor C2. Optocoupler U1 conducts when Zener diode D1 breaks down and turns off when Zener diode D1 is cut off.
[0024] The other end of the delay capacitor C2 is grounded. When the optocoupler U1 is turned on, indicating that the AC input power supply is normal, the delay capacitor C2 provides a high-level PFD signal to the control module 14 of the electronic device. When the optocoupler U1 is turned off, indicating that the AC input power supply is faulty, the delay capacitor C2 provides a low-level PFD signal to the control module 14 after a preset time delay due to the discharge of the second discharge resistor R3.
[0025] The second discharge resistor R3 is used to discharge the time-delay capacitor C2 when the optocoupler U1 is turned off. The second discharge resistor R3 is connected in parallel with the time-delay capacitor C2 and can adjust the charging and discharging times of the time-delay capacitor C2. For example, the discharge time can be approximately equal to a preset time delay, meaning the discharge time can be adjusted by the second discharge resistor R3 according to the preset time delay. The time delay is to avoid EMC noise and short-term interruptions.
[0026] The other end of the pull-up resistor R4 is connected to the power supply.
[0027] When the electronic device is a servo drive product, the AC input PFD circuit needs to meet various requirements for different applications, such as the SEMI F47 standard in the semiconductor industry and other general standards like IEC 61800-3. However, Figure 1 The solutions provided are insufficient to meet the requirements of various voltage drop scenarios. The detection speed and accuracy are constrained by the circuit parameters, making it impossible to achieve both adaptability and rapid response simultaneously.
[0028] Therefore, in the embodiments of this application, in order to meet the various requirements of different applications, at least two AC PFD sub-circuits with different detection thresholds are provided. When the voltage of the AC input power supply drops significantly, one AC PFD sub-circuit can quickly pull down the detection voltage and output a low-level PFD signal indicating that the AC input power supply has failed. Therefore, even in emergency situations, the response speed can be improved, and the system can be safely shut down when the support capacity of the bus capacitor is weakened.
[0029] Reference will now be made to the examples shown in the accompanying drawings. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the present application. Furthermore, the drawings are illustrative of the examples, wherein the components shown are not necessarily essential for implementing the present application. In other instances, well-known components, parts, and circuits have not been described in detail to avoid unnecessarily obscuring aspects of the examples.
[0030] Figure 2 This is a schematic diagram illustrating an AC input PFD circuit according to an embodiment of this application. Figure 2 As shown, with Figure 1 compared to, Figure 2 The AC input PFD circuit includes at least two AC input PFD sub-circuits 21 and 22, each with a different detection threshold corresponding to a different time delay. Figure 2 (Taking two AC input PFD sub-circuits 21 and 22 as an example). Each of at least two AC input PFD sub-circuits 21 and 22 is provided with a detection threshold and is used to detect the DC bus voltage converted from the AC input power supply. When the AC input power supply fails and the DC bus voltage drops to the detection threshold, a PFD signal indicating that the AC input power supply has failed is output after a corresponding time delay. The detection thresholds of different AC input PFD sub-circuits may be different. In addition, in the embodiments of this application, for the sake of simplicity, the case of AC input power supply interruption is also included in the case of AC input power supply failure, that is, when the AC input power supply is interrupted, it can be considered that the AC input power supply has failed.
[0031] Figure 2 The AC input PFD sub-circuit 21 in the middle can be connected with Figure 1 The AC input PFD circuit 13 is the same as that in the above circuit. That is, the AC input PFD sub-circuit 21 may also include a sampling capacitor C1, a first discharge resistor R1, a Zener diode D1, a current-limiting resistor R2, an optocoupler U1, a delay capacitor C2, a second discharge resistor R3, and a pull-up resistor R4, and the functions and connections of these components can be the same as those in the above circuit. Figure 1The components in this embodiment have the same function and connection relationship. Specifically, the sampling capacitor C1 is used to sample the DC bus voltage; the first discharge resistor R1 is connected in parallel with the sampling capacitor C1 and is used to discharge the sampling capacitor C1 when the AC input power supply fails; the Zener diode D1 is provided with a first breakdown threshold corresponding to a first detection threshold. For example, the first breakdown threshold can be approximately equal to the first detection threshold. The Zener diode is used to break down and clamp the voltage on the sampling capacitor C1 when the AC input power supply is normal, and is also used to discharge the sampling capacitor C1 when the AC input power supply fails and the sampling capacitor C1 fails. The sampling capacitor C1 is turned off when the voltage on it drops to the first breakdown threshold; the current-limiting resistor R2 is used to limit the current of the Zener diode D1; the optocoupler U1 is used to turn on when the Zener diode D1 breaks down and turn off when the Zener diode D1 is turned off; the delay capacitor C2 is used to provide a high-level PFD signal when the optocoupler U1 is on and a low-level PFD signal when the optocoupler U1 is off; the second discharge resistor R3 is connected in parallel with the delay capacitor C2 and is used to discharge the delay capacitor C2 according to the first time delay when the optocoupler U1 is turned off. In this embodiment, the sampling capacitor C1 can be referred to as the first sampling capacitor C1, the current-limiting resistor R2 can be referred to as the first current-limiting resistor R2, the Zener diode D1 can be referred to as the first Zener diode D1, and the optocoupler U1 can be referred to as the first optocoupler U1.
[0032] Figure 2 The AC input PFD sub-circuit 22 may include a second sampling capacitor C3, a third sampling capacitor C4, a third discharge resistor R5, a first isolation diode D2, a second isolation diode D3, a second Zener diode D4, a second current limiting resistor R6, a second optocoupler U2, a transistor Q1, and a fourth discharge resistor R7.
[0033] The second sampling capacitor C3 is used to sample the DC bus voltage. The first terminal of the second sampling capacitor C3 is connected to the DC bus, and the second terminal of the sampling capacitor C3 is connected to the reference voltage terminal REF.
[0034] The third discharge resistor R5 is used to discharge the second sampling capacitor C3 when the AC input power supply fails. The third discharge resistor R5 is connected in parallel with the second sampling capacitor C3, and the charging and discharging times of the second sampling capacitor C3 can be adjusted.
[0035] In this embodiment, the second sampling capacitor C3 has a small capacitance, and it discharges rapidly when the DC bus voltage drops. Therefore, the voltage of the second sampling capacitor C3 can reflect the state of the AC input power supply.
[0036] The third sampling capacitor C4 is used to sample the DC bus voltage and provide a stable voltage reference. The first terminal of the third sampling capacitor C4 is connected to the cathode of the first isolation diode D2, and the other terminal of the third sampling capacitor C4 is connected to the reference voltage terminal REF.
[0037] In this embodiment, the capacitance of the third sampling capacitor C4 is larger than that of the second sampling capacitor C3. After the initial AC input power is turned on and the third sampling capacitor C4 is fully charged, the voltage of the third sampling capacitor C4 is quite stable and does not change rapidly as the voltage of C3 decreases. Therefore, the third sampling capacitor C4 can provide a stable voltage reference.
[0038] The anode of the first isolation diode D2 is connected to the first terminal of the second sampling capacitor C3, and is used to isolate the current between the third sampling capacitor C4 and the second sampling capacitor C3.
[0039] The anode of the second isolation diode D3 is connected to the third sampling capacitor C4, and the cathode of the second isolation diode D3 is connected to the first sampling capacitor C1. The second isolation diode D3 is used to isolate the current between the first sampling capacitor C1 and the third sampling capacitor C4.
[0040] The first isolation diode D2 and the second isolation diode D3 are used to control the direction of current flow among the first sampling capacitor C1, the second sampling capacitor C3 and the third sampling capacitor C4, and to ensure that the first sampling capacitor C1 and the third sampling capacitor C4 do not charge the second sampling capacitor C3 during the DC bus voltage drop.
[0041] The second Zener diode D4 is provided with a second breakdown threshold corresponding to the second detection threshold; for example, the second breakdown threshold may be approximately equal to the second detection threshold. When the AC input power supply fails and the voltage difference between the third sampling capacitor C4 and the second sampling capacitor C3 is greater than the second breakdown threshold, the second Zener diode D4 is broken down. When the AC input power supply is normal, or when the AC input power supply fails but the voltage difference between the third sampling capacitor C4 and the second sampling capacitor C3 is less than the second breakdown threshold, the second Zener diode D4 cannot be broken down and is instead turned off. The cathode of the second Zener diode D4 is connected to the first terminal of the third sampling capacitor C4, and the anode of the second Zener diode D4 is connected to one end of the second current-limiting resistor R6.
[0042] The second current-limiting resistor R6 is used to limit the current of the second Zener diode D4. The other end of the second current-limiting resistor R6 is connected to the anode of the second optocoupler U2.
[0043] The cathode of the second optocoupler U2 is connected to the second sampling capacitor C3, the collector of the optocoupler U2 is connected to the power supply, and the emitter of the optocoupler U2 is connected to the base of the transistor Q1. The second optocoupler U2 conducts when the second Zener diode D4 is broken down and turns off when the second Zener diode D4 is turned off.
[0044] The collector of transistor Q1 is connected to one end of the fourth discharge resistor R7, and the emitter of transistor Q1 is grounded. Transistor Q1 is turned on when the second optocoupler U2 is turned on, and turned off when the second optocoupler U2 is turned off.
[0045] The other end of the fourth discharge resistor R7 is connected to one end of the time-delay capacitor C2. The fourth discharge resistor R7 is used to discharge the time-delay capacitor C2 according to the second time delay when the transistor Q1 is turned on. The fourth discharge resistor R7 can adjust the charging and discharging time of the time-delay capacitor C2; for example, the discharging time can be approximately equal to the second time delay, meaning the discharging time can be adjusted by the fourth discharge resistor R7 according to the second time delay.
[0046] Therefore, the delay capacitor C2 is used to provide a high-level PFD signal when the first optocoupler U1 is turned on and the optocoupler U2 is turned off, and to provide a low-level PFD signal when the optocoupler U1 is turned off or the optocoupler U2 is turned on.
[0047] In this embodiment, the first detection threshold is greater than the second detection threshold, and the first time delay is greater than the second time delay. Therefore, in this embodiment, if the AC input power supply fails and the voltage difference between the third sampling capacitor C4 and the second sampling capacitor C3 is greater than the second breakdown threshold, the second Zener diode D4 breaks down. Then, the second optocoupler U2 turns on and the transistor Q1 turns on. The delay capacitor C2 discharges through the fourth discharge resistor R7 and the transistor Q1, resulting in a low-level PFD signal output and being uploaded after the second time delay. If the AC input power supply fails and the voltage on the first sampling capacitor C1 is less than the first breakdown threshold, the delay capacitor C2 discharges through the second discharge resistor R3, resulting in a low-level PFD signal output and being uploaded after the first time delay.
[0048] In the example, the first detection threshold can be 40% of the normal DC bus voltage, and the first time delay can be 200ms. The second detection threshold can be 5% of the normal DC bus voltage, and the second time delay can be 5ms. If the AC input power supply voltage drops to 40%, the voltage of the second sampling capacitor C3 drops instantaneously, and the voltage of the third sampling capacitor C4 drops slowly. However, the voltage difference between the third sampling capacitor C4 and the second sampling capacitor C3 is insufficient to cause the second Zener diode D4 to break down. Therefore, the delay capacitor C2 discharges through the second discharge resistor R3, and its voltage is pulled down to 0.8V after 200ms. If the AC input power supply voltage drops to 5%, the voltage difference between the third sampling capacitor C4 and the second sampling capacitor C3 causes the second Zener diode D4 to break down. Then, the delay capacitor C2 discharges through the fourth discharge resistor R7, and its voltage is pulled down to 0V within 5ms.
[0049] Figure 3 This is a schematic diagram illustrating an AC input PFD circuit according to another embodiment of this application. Figure 3 As shown, the AC input PFD circuit may include a detection chip 31, a first sampling capacitor C1, a delay capacitor C2, a second discharge resistor R3, a second sampling capacitor C3, a third discharge resistor R5, a third sampling capacitor C4, and a fifth discharge resistor R8. Figure 2 Compared to the AC input PFD circuit shown, the detection chip 31 is equivalent to... Figure 2 The first discharge resistor R1, the first Zener diode D1, the first current-limiting resistor R2, the first optocoupler U1, the pull-up resistor R4, the first isolation diode D2, the second isolation diode D3, the second Zener diode D4, the second current-limiting resistor R6, the second optocoupler U2, the transistor Q1, and the fourth discharge resistor R7 are integrated into a single chip.
[0050] like Figure 3 As shown, the detection chip 31 includes 8 pins, where pin 1 is the first input pin, which can be called INA; pin 3 is the second input pin, which can be called INB; pin 2 is the first reference pin, which can be called DC; pin 4 is the second reference pin, which can be called REF; pin 5 is the power supply pin, which can be called Vcc; pin 6 is the fault output pin, which can be called FO; pin 7 is the ground pin, which can be called GND; and pin 8 is the auxiliary adjustment pin, which can be called DA. The second input pin INB is connected to the DC bus of the electronic device, the second reference pin REF is connected to the reference voltage terminal REF of the electronic device, the power supply pin Vcc is connected to the power supply, and the ground pin GND is grounded.
[0051] One end of the first sampling capacitor C1 is connected to the first input pin INA and the DC bus of the electronic device, and the other end of the first sampling capacitor C1 is connected to the reference voltage terminal REF of the electronic device. The first sampling capacitor C1 is used to sample the DC bus voltage.
[0052] One end of the delay capacitor C2 is connected to the fault output pin FO, and the other end of the delay capacitor C2 is grounded. The delay capacitor C2 is used to provide a high-level PFD signal or a low-level PFD signal.
[0053] The second discharge resistor R3 is connected in parallel with the delay capacitor C2 and is used to discharge the delay capacitor C2 according to a first time delay under the control of the detection chip 31. The second discharge resistor R3 can adjust the charging and discharging time of the delay capacitor C2 according to the first time delay.
[0054] One end of the fifth discharge resistor R8 is connected to the fault output pin FO, and the other end is connected to the auxiliary adjustment pin DA. The fifth discharge resistor R8 is used to assist in discharging the delay capacitor C2 according to the second time delay under the control of the detection chip 31. The fifth discharge resistor R8 can adjust the charging and discharging time of the delay capacitor C2 according to the second time delay.
[0055] One end of the second sampling capacitor C3 is connected to the second input pin INB, and the other end of the second sampling capacitor C3 is connected to the reference voltage terminal REF. The second sampling capacitor C3 is used to sample the DC bus voltage.
[0056] The third discharge resistor R5 is connected in parallel with the second sampling capacitor C3 and is used to discharge the second sampling capacitor C3 when the AC input power supply fails.
[0057] One end of the third sampling capacitor C4 is connected to the first reference pin DC, and the other end is connected to the reference voltage terminal REF. The third sampling capacitor C4 is used to sample the DC bus voltage. The capacitance of the third sampling capacitor C4 is greater than that of the second sampling capacitor C3. The voltage at the first reference pin DC is relatively stable and is used to provide a reference for the second input pin INB.
[0058] The first sampling capacitor C1, the delay capacitor C2, the second discharge resistor R3, and the detection chip 31 constitute an AC input PFD sub-circuit 31, which can be referred to as sub-circuit A; and the second sampling capacitor C3, the third discharge resistor R5, the third sampling capacitor C4, the delay capacitor C2, the fifth discharge resistor R8, and the detection chip 31 constitute another AC input PFD sub-circuit 32, which can be referred to as sub-circuit B. Sub-circuits A and B correspond to different time delays and voltage drop levels. That is, sub-circuit A corresponds to the first time delay, and sub-circuit B corresponds to the second time delay. This can simultaneously meet the requirements of different international and industry standards.
[0059] There is optocoupler isolation between PIN1 to PIN4 and between PIN5 and PIN8, and the requirements for pin insulation spacing and creepage distance depend on the system voltage level to ensure that safety requirements are met.
[0060] The detection chip 31 has two thresholds: a first detection threshold corresponding to sub-circuit A and a second detection threshold corresponding to sub-circuit B. When the input voltage of the AC power supply is normal, PIN1, PIN2, and PIN3 correspond to stable DC voltages with almost no voltage difference between them. The voltage difference between PIN3 and PIN4 is greater than the second detection threshold. The output voltage of PIN6 is high, indicating that there is no power supply fault.
[0061] When the input voltage of the AC input power supply drops rapidly to an extremely low level, and the voltage difference between PIN1 and PIN2 is greater than the second detection threshold, PIN6 outputs a low-level PFD signal, thereby detecting the power failure of the electronic device in a very short time.
[0062] When the input voltage of the AC power supply begins to decrease, the voltage difference between PIN3 and PIN4 also decreases. When the voltage difference between PIN3 and PIN4 (i.e., the voltage across the first sampling capacitor C1) is less than the first detection threshold, PIN6 outputs a low-level PFD signal, thereby accurately determining the power-down behavior of the electronic device.
[0063] As can be seen from the above technical solutions, in the embodiments of this application, since the AC input PFD circuit includes at least two AC input PFD sub-circuits with different detection thresholds corresponding to different time delays, the circuit can provide different response speeds under different degrees of AC input power supply failure, thereby meeting the requirements of different standards such as SEMI F47 and other general standards such as IEC 61800-3 and expanding the application range of the circuit, making the circuit highly adaptable.
[0064] In addition, a sub-circuit of the AC input PFD circuit can improve the response speed of the detection circuit when the DC bus voltage drops significantly, so that the control module can receive the low-level PFD signal indicating that the AC input power supply has failed as soon as possible, and then control the motor to achieve safe shutdown.
[0065] Furthermore, in this example, only three resistors, two capacitors, three diodes, one optocoupler, and one transistor are added, thereby improving the safety of the electronic device at a lower cost. In another example, integrated circuits can be used to replace some electronic components, thus simplifying circuit design and installation.
[0066] It should be understood that, as used herein, the singular form “a(a)” (“a(a)”, “a(an)”, “the”) is intended to include the plural form unless the context clearly supports an exception. It should also be understood that “and / or” as used herein is intended to include any and all possible combinations of one or more items in the associated list.
[0067] The number of embodiments in this application is for illustrative purposes only and does not imply any advantage of the implementation.
[0068] For purposes of explanation, the foregoing description has been illustrated with reference to specific examples. However, the illustrative arguments above are not intended to be exhaustive or to limit this application to the precise form disclosed. In light of the above teachings, many modifications and variations are possible. The examples were chosen and described in order to best explain the principles of this application and its practical application, thereby enabling others skilled in the art to best utilize this application and various examples with various modifications suitable for the particular intended use.
Claims
1. An AC input power supply fault detection (PFD) circuit, characterized in that, include: At least two AC input PFD sub-circuits have different detection thresholds corresponding to different time delays. Each AC input PFD sub-circuit is configured with a detection threshold and is used to detect the DC bus voltage converted from the AC input power supply. When the AC input power supply fails and the DC bus voltage drops to the detection threshold, a PFD signal indicating that the AC input power supply has failed is output after the corresponding time delay.
2. The AC input PFD circuit according to claim 1, characterized in that, The at least two AC input PFD sub-circuits include two AC input PFD sub-circuits, one of the two AC input PFD sub-circuits is provided with a first detection threshold corresponding to a first time delay, and the other AC input PFD sub-circuit is provided with a second detection threshold corresponding to a second time delay; wherein the first detection threshold is greater than the second detection threshold, and the first time delay is greater than the second time delay.
3. The AC input PFD circuit according to claim 2, characterized in that, One of the two AC input PFD sub-circuits includes: The first sampling capacitor (C1) is used to sample the DC bus voltage; A first discharge resistor (R1) is connected in parallel with the sampling capacitor (C1) and is used to discharge the first sampling capacitor (C1) when the AC input power supply fails. A first Zener diode (D1) is provided with a first breakdown threshold equal to the first detection threshold, which is used to break down and clamp the voltage on the sampling capacitor (C1) when the AC input power supply is normal, and to be cut off when the AC input power supply fails and the voltage on the first sampling capacitor (C1) drops to the first breakdown threshold. The first current-limiting resistor (R2) is used to limit the current of the first Zener diode (D1); A first optocoupler (U1) is used to turn on when the first Zener diode (D1) is broken down and to turn off when the first Zener diode (D1) is turned off. A delay capacitor (C2) is used to provide a high-level PFD signal when the first optocoupler (U1) is turned on and a low-level PFD signal when the first optocoupler (U1) is turned off. The second discharge resistor (R3) is connected in parallel with the delay capacitor (C2) and is used to discharge the delay capacitor (C2) according to a first time delay when the first optocoupler (U1) is turned off.
4. The AC input PFD circuit according to claim 3, characterized in that, The other AC input PFD sub-circuit in the two AC input PFD sub-circuits includes: The second sampling capacitor (C3) is used to sample the DC bus voltage; The third discharge resistor (R5) is connected in parallel with the second sampling capacitor (C3) and is used to discharge the second sampling capacitor (C3) when the AC input power supply fails. The third sampling capacitor (C4) is used to sample the DC bus voltage; A first isolation diode (D2) is used to isolate the current between the third sampling capacitor (C4) and the second sampling capacitor (C3); The second isolation diode (D3) is used to isolate the current between the first sampling capacitor (C1) and the third sampling capacitor (C4); The second Zener diode (D4) is provided with a second breakdown threshold equal to the second detection threshold, and is used to break down when the AC input power supply fails and the voltage difference between the third sampling capacitor (C4) and the second sampling capacitor (C3) is greater than the second breakdown threshold, and to be cut off when the AC input power supply is normal or when the AC input power supply fails but the voltage difference between the third sampling capacitor (C4) and the second sampling capacitor (C3) is less than the second breakdown threshold; The second current-limiting resistor (R6) is used to limit the current of the second Zener diode (D4); The second optocoupler (U2) is used to turn on when the second Zener diode (D4) is broken down and to turn off when the second Zener diode (D4) is turned off; Transistor (Q1) is used to turn on when the second optocoupler (U2) is turned on and to turn off when the second optocoupler (U2) is turned off; The fourth discharge resistor (R7) is used to discharge the delay capacitor (C2) according to the second time delay when the transistor (Q1) is turned on. The delay capacitor (C2) is further used to provide a low-level PFD signal when the optocoupler (U2) is turned on.
5. The AC input PFD circuit according to claim 2, characterized in that, The two AC input PFD sub-circuits include: The detection chip (31) includes: a first input pin (INA), a second input pin (INB), a first reference pin (DC), a second reference pin (REF), a power supply pin (Vcc), a ground pin (GND), a fault output pin (FO), and an auxiliary adjustment pin (DA), wherein the second reference pin (REF) is connected to a reference voltage terminal REF, the power supply pin (Vcc) is connected to a power supply, and the ground pin (GND) is grounded; A first sampling capacitor (C1) is connected at one end to the first input pin (INA) and the DC bus of the electronic device, and at the other end to the reference voltage terminal REF of the electronic device. The first sampling capacitor is used to sample the DC bus voltage. A delay capacitor (C2) is provided, one end of which is connected to the fault output pin (FO) and the other end of which is grounded. The delay capacitor is used to provide a high-level PFD signal or a low-level PFD signal. The second discharge resistor (R3) is connected in parallel with the delay capacitor (C2) and is used to discharge the delay capacitor (C2) according to the first time delay under the control of the detection chip (31). A fifth discharge resistor (R8) is provided, one end of which is connected to the fault output pin (FO) and the other end of which is connected to the auxiliary adjustment pin (DA). The fifth discharge resistor is used to assist in discharging the delay capacitor (C2) according to the second time delay under the control of the detection chip (31). The second sampling capacitor (C3) has one end connected to the second input pin (INB) and the other end connected to the reference voltage terminal REF. The second sampling capacitor is used to sample the DC bus voltage. The third discharge resistor (R5) is connected in parallel with the second sampling capacitor (C3) and is used to discharge the second sampling capacitor (C3) when the AC input power supply fails. A third sampling capacitor (C4) is connected at one end to the first reference pin (DC) and at the other end to the reference voltage terminal REF. The third sampling capacitor is used to sample the DC bus voltage. The first sampling capacitor (C1), the delay capacitor (C2), the second discharge resistor (R3), and the detection chip (31) constitute one of the two AC input PFD sub-circuits; The second sampling capacitor (C3), the third discharge resistor (R5), the third sampling capacitor (C4), the delay capacitor (C2), the fifth discharge resistor (R8), and the detection chip (31) constitute another AC input PFD sub-circuit in the two AC input PFD sub-circuits; The detection chip (31) is provided with a first detection threshold and a second detection threshold. When the AC input power supply fails, and the voltage difference between the third sampling capacitor (C4) and the second sampling capacitor (C3) is greater than the second detection threshold or the voltage on the first sampling capacitor (C1) is less than the first detection threshold, the fault output pin (FO) outputs a low-level PFD signal.
6. An electronic device having an AC input power supply, comprising: Voltage divider circuit (11), which is used to reduce the high voltage of the AC input power supply to the required low voltage; as well as A three-phase bridge (12) is used to convert the required low voltage into a DC bus voltage; characterized in that the electronic device further comprises: The AC input PFD circuit according to any one of claims 1 to 5.
7. The electronic device with AC input power supply according to claim 6, characterized in that, The electronic device is a motor driver or frequency converter.
8. The electronic device with AC input power supply according to claim 7, characterized in that, The motor driver includes a servo driver.