Modularized server core module, server mainboard and server signal routing method

Abstract

The invention provides a modular server core module, a server mainboard and a server signal routing method, and belongs to the technical field of server design. The module comprises a module board card; the module board card is characterized in that a CPU core is provided with a DDR interface, the DDR interface is connected with a plurality of memory channels, and each memory channel is connected with a memory module; the CPU core is connected with the first array connector, the BIOS chip, the time sequence control chip and the clock chip; the clock chip is connected with the CPU core; the clock chip is further connected with the time sequence control chip, and the time sequence control chip is further connected with the first array connector through the second I2C bus and the system bus. According to the invention, through modular design, flexible combination of server core components and dynamic routing optimization resource allocation are realized, performance and maintainability are improved, and diversified application scene requirements are met.

Description

Technical Field

[0001] This application belongs to the field of server design technology, specifically relating to a modular server core module, a server motherboard, and a server signal routing method. Background Technology

[0002] With the development of information technology, various industries have an ever-increasing demand for data computing, storage, and information exchange. As a key device to meet these demands, the performance, flexibility, and maintainability of servers are crucial. In particular, the development of heterogeneous computing and high-density data centers places even higher demands on server performance.

[0003] The current development of servers suffers from the following shortcomings: First, there is a lack of interface standardization. While there are many high-performance processors on the market, some (such as the Phytium S5000C) have design features, such as the absence of dedicated sockets, forcing the motherboard to use a hard-soldered integrated design. This means that maintenance requires replacing the entire motherboard, increasing repair costs and causing inconvenience for subsequent server maintenance and upgrades. Second, there is rigid scalability. Traditional server motherboard designs are often relatively fixed, for example, with the CPU, memory, and interface circuits fixedly coupled, making it impossible to dynamically adapt to changes in application scenarios and requirements, thus limiting the server's flexibility and scalability. For example, single-socket / dual-socket configurations require redesigning the motherboard, and PCIe lanes cannot be allocated to heterogeneous interfaces such as USB / SATA as needed. Furthermore, the complex soldering process during server motherboard production and assembly leads to low production efficiency, reduced yield, and difficulty in quickly replacing faulty components during maintenance, increasing maintenance costs and complexity.

[0004] Therefore, there is an urgent need for a motherboard design solution that can improve server design flexibility, manufacturing efficiency, and ease of maintenance. Summary of the Invention

[0005] In a first aspect, embodiments of this application provide a modular server core module, including module boards; The module board contains a CPU core, a first array connector, a timing control chip, a clock chip, and a BIOS chip. The CPU core is equipped with a DDR interface, which is connected to several memory channels, and each memory channel is connected to a memory module. The CPU core is connected to the first array connector through the first UART bus, the first PCIe bus, and the C2C bus; it is connected to the BIOS chip through the SPI bus; it is connected to the timing control chip through the L bus, the first I2C bus, the second UART bus, and the GPIO signal line; and it is connected to the clock chip through the clock signal line. The clock chip is also connected to the timing control chip, which is in turn connected to the first array connector via the second I2C bus and the SYS bus.

[0006] Furthermore, the CPU core uses the Phytium S5000C series CPU core, including three models: 64-core, 32-core, and 16-core.

[0007] Furthermore, the CPU core has two DDR interfaces, which are positioned opposite each other on both sides of the CPU core. Each DDR interface connects to 4 memory channels, and each memory channel connects to a memory module consisting of 9 DDR5 memory chips.

[0008] Furthermore, the timing control chip uses a CPLD or MCU chip; The clock signal lines include 33M clock signal lines, 100M clock signal lines, and 156M clock signal lines; The first array connector uses a 688-pin array connector.

[0009] Secondly, embodiments of this application also provide a server motherboard for connecting to the modular server core module described in the first aspect, including a signal conversion unit and at least one second array connector; The upper end of the second array connector is inserted into the first array connector; The lower end of the second array connector is equipped with a UART bus, a second PCIE bus, a third PCIE bus, a fourth PCIE bus, and a SYS bus; The UART bus is connected to a DB9 interface, the second PCIe bus is connected to a USB controller, the USB controller is connected to several USB interfaces, the third PCIe bus is connected to a SATA controller, the SATA controller is connected to several SATA interfaces, the fourth PCIe bus is connected to a PCIe slot, and the SYS bus is connected to a power module.

[0010] Thirdly, embodiments of this application also provide a modular server signal routing method, based on the server motherboard described in the second aspect, comprising the following steps: S1. Receive the native signal set output by the modular server core module through the first array connector, the native signal set including the first UART signal U1, the first PCIE signal P1 and the C2C interconnect signal C1; S2. Dynamic routing is achieved by interlocking the first array connector with the second array connector: The first UART signal U1 is directly connected to the DB9 interface; The first PCIe signal P1 is split into three independent sub-channel signals: the first sub-channel signal P1a, the second sub-channel signal P1b, and the third sub-channel signal P1c. The first sub-channel signal P1a is directly connected to the PCIe slot, the second sub-channel signal P1b is converted to the USB protocol by the USB controller to communicate with the USB interface, and the third sub-channel signal P1c is converted to the SATA protocol by the SATA controller to communicate with the SATA interface. When multiple modular server core modules are detected, the C2C interconnect signals C1 of each module are directly connected through the onboard C2C link of the server motherboard.

[0011] Furthermore, it also includes the following steps: S3. Perform dynamic resource allocation: USB controller statistics of real-time USB load traffic And report to the timing control chip via the second I2C bus; SATA controller statistics of real-time SATA load flow And report to the timing control chip via the second I2C bus; The timing control chip adjusts according to real-time USB load flow. and real-time SATA load traffic And use the following formula to allocate PCIe lanes:

[0012]

[0013] in, This is the total number of allocatable PCIe sub-channels. It is the preset USB weighting coefficient.

[0014] Furthermore, when the number of modular server core modules on the server board is two, the following steps are also included: S4. Perform load balancing: S41. Perform PCIe load rate collection: Each timing control chip calculates the PCIe load rate of its CPU core:

[0015] in, It refers to the number of packages received. It refers to the number of packets sent. It is the theoretical bandwidth of a single channel. It is a statistical unit of time; S42. Execute master-slave collaboration: The master timing controller chip is configured to collect PCIe load rate data from the slave timing controller chip via a C2C link, and the load balancing factor is calculated using the following formula. :

[0016] in, It is the PCIe load rate of the main CPU core. It is the PCIe load rate of the CPU core; S43. Execution Channel Migration: When load balancing factor Less than the preset equalization threshold At that time, the main timing control chip calculates the number of migration channels. :

[0017] in, It is the PCIe load rate of the main CPU core. It's based on the CPU core's PCIe load rate. These are preset coefficients. It is the floor function. This refers to the number of PCIe lanes available to the main CPU core. This refers to the number of available PCIe lanes on the CPU core. The migration from high-load CPU cores to low-load CPU cores is based on the calculated number of migration channels. Perform PCIe channel migration.

[0018] As can be seen from the above technical solutions, this application has the following advantages: The modular server core module, server motherboard, and server signal routing method provided in this application achieve flexible combination, dynamic routing, and resource allocation of server core components through modular design and signal routing, thereby improving server performance, scalability, and maintainability, and solving the problems of lack of interface standardization, rigid scalability, and inconvenient maintenance in existing server designs. Attached Figure Description

[0019] To more clearly illustrate the technical solution of this application, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the modular server core module of the present invention.

[0021] Figure 2 This is a schematic diagram of an embodiment of the single-socket server motherboard of the present invention.

[0022] Figure 3 This is a schematic diagram of an embodiment of the dual-socket server motherboard of the present invention.

[0023] Figure 4 This is a flowchart illustrating the modular server signal routing method of the present invention.

[0024] The components are as follows: 1-CPU core; 2-First array connector; 3-Timing control chip; 4-Clock chip; 5-BIOS chip; 6-DDR interface; 7-Memory module; 8-Second array connector; 9-DB9 interface; 10-USB controller; 11-USB interface; 12-SATA controller; 13-SATA interface; 14-PCIE slot; 15-Power module. Detailed Implementation

[0025] Various embodiments of this disclosure will be described more fully in the following detailed description of the modular server core module. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0026] For example, the continuous development of information technology has led to a surge in demand for data computing, storage, and information exchange across various industries. As the core equipment supporting these functions, servers have become particularly important in terms of performance, flexibility, and maintainability. Especially with the increasing prevalence of heterogeneous computing and high-density data centers, server performance faces unprecedented challenges.

[0027] However, current server development suffers from the following shortcomings: First, the lack of interface standardization. Although the market offers a wide variety of high-performance processors, some processors (such as the Phytium S5000C) require motherboards to be integrated using a hard soldering method due to design factors, such as the absence of dedicated sockets. This not only necessitates replacing the entire motherboard during maintenance, increasing repair costs, but also creates significant inconvenience for subsequent maintenance and upgrades. Second, a lack of flexibility in scalability. Traditional server motherboard designs are relatively fixed, tightly coupling the CPU, memory, and interface circuits, making dynamic adjustments impossible based on application scenarios and needs, severely restricting the server's flexibility and scalability. For example, changing from single-socket to dual-socket configurations requires redesigning the motherboard, and PCIe lanes cannot be flexibly allocated to different types of interfaces such as USB and SATA as needed. Furthermore, the complex soldering process in server motherboard manufacturing leads to low production efficiency and low yield rates, while the difficulty in quickly replacing faulty components during maintenance further increases maintenance costs and complexity.

[0028] In conclusion, developing a motherboard design solution that can enhance server design flexibility, improve manufacturing efficiency, and enhance maintenance convenience has become a top priority.

[0029] To address the aforementioned issues, this embodiment provides a modular server core module. Through modular design, it enables flexible combination of core server components, dynamic routing to optimize resource allocation, improves performance and maintainability, and adapts to diverse application scenarios.

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Please see Figure 1 The diagram shown is a schematic of a modular server core module in a specific embodiment. The module includes module boards. The module board contains a CPU core 1, a first array connector 2, a timing control chip 3, a clock chip 4, and a BIOS chip 5; CPU core 1 is equipped with DDR interface 6, which is connected to several memory channels, and each memory channel is connected to a memory module 7. CPU core 1 is connected to the first array connector 2 via the first UART bus, the first PCIe bus, and the C2C bus; it is connected to the BIOS chip 5 via the SPI bus; it is connected to the timing control chip 3 via the L bus, the first I2C bus, the second UART bus, and the GPIO signal line; and it is connected to the clock chip 4 via the clock signal line. Clock chip 4 is also connected to timing control chip 3, and timing control chip 3 is also connected to first array connector 2 through second I2C bus and SYS bus; It should be noted that the module board, by integrating core components, provides stable and reliable physical support and electrical connections, facilitating production and maintenance; the CPU core 1 uses the Phytium S5000C series processor, which has high-performance computing capabilities, meeting the server's requirements for processing speed and efficiency; the first array connector 2 enables rapid connection and signal transmission between the core module and the server motherboard, improving the system's flexibility and scalability; the timing control chip 3, through a CPLD or MCU chip, precisely controls the working timing of the CPU core and other components, ensuring stable system operation; the clock chip 4 provides high-precision clock signals to other components of the CPU core 1, ensuring synchronized and coordinated system operation; the BIOS chip 5 stores the firmware program required for system startup and initialization, providing basic support for the server's normal startup and operation.

[0032] This embodiment integrates key components such as the CPU core, array connector, and timing control chip onto a module board, forming an independent functional module, which facilitates production and maintenance. Through the DDR interface and multiple memory channels, it supports large-capacity memory expansion, meeting the server's demands for high-performance computing and big data processing. It employs multiple bus connection methods, including UART, PCIe, and C2C, providing rich interfaces to meet the connection needs of different devices and application scenarios. Through the clock chip and timing control chip, it provides stable clock and control signals to the CPU core and other components, ensuring stable system operation.

[0033] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, another modular server core module is provided, which includes module boards; The module board contains a CPU core 1, a first array connector 2, a timing control chip 3, a clock chip 4, and a BIOS chip 5; CPU core 1 is equipped with DDR interface 6, which is connected to several memory channels, and each memory channel is connected to a memory module 7. CPU core 1 is connected to the first array connector 2 via the first UART bus, the first PCIe bus, and the C2C bus; it is connected to the BIOS chip 5 via the SPI bus; it is connected to the timing control chip 3 via the L bus, the first I2C bus, the second UART bus, and the GPIO signal line; and it is connected to the clock chip 4 via the clock signal line. The first PCIe bus uses the PCIe 5.0 protocol; Clock chip 4 is also connected to timing control chip 3, and timing control chip 3 is also connected to first array connector 2 through second I2C bus and SYS bus; The CPU core 1 uses the Phytium S5000C series CPU core, including three models: 64 cores, 32 cores, and 16 cores. The CPU core of the Phytium S5000C series supports BMC management daughter cards and multiple operating systems such as KylinOS, OpenEuler OS, and UnionTech OS. CPU core 1 has two DDR interfaces 6, and the two DDR interfaces 6 are positioned opposite each other on both sides of CPU core 1. Each DDR interface 6 connects to 4 memory channels, and each memory channel connects to a memory module 7 containing 9 DDR5 memory chips; It should be noted that the two DDR6 interfaces connect a total of 8 memory channels, support a memory frequency of 4000MHz, support a maximum memory capacity of 2.0TB, and each memory module supports a standard PCIe Gen5 expansion slot, providing flexible expansion configurations, with optional support for 10 PCIe Gen5 expansion slots. Timing control chip 3 uses a CPLD or MCU chip; The clock signal lines include 33M clock signal lines, 100M clock signal lines, and 156M clock signal lines; The first array connector 2 uses a 688-pin array connector.

[0034] like Figure 2 As shown, the following is an embodiment of a server motherboard provided in this disclosure. The motherboard is used to connect the modular server core module described in the above two embodiments, and includes a signal conversion unit and a second array connector 8. The upper end of the second array connector 8 is inserted into the first array connector 2; The lower end of the second array connector 8 is equipped with a UART bus, a second PCIE bus, a third PCIE bus, a fourth PCIE bus, and a SYS bus; The UART bus is connected to a DB9 interface 9, the second PCIe bus is connected to a USB controller 10, the USB controller 10 is connected to several USB interfaces 11, the third PCIe bus is connected to a SATA controller 12, the SATA controller 12 is connected to several SATA interfaces 13, the fourth PCIe bus is connected to a PCIe slot 14, and the SYS bus is connected to a power module 15. For example, there are 4 USB ports and 4 SATA ports; Power module 15 includes a DC-DC unit and an LDO unit; One end of the DC-DC unit is connected to an external power source, and the other end is connected to the LDO unit; The DC-DC unit converts the external power supply voltage into an intermediate voltage to supply the LDO unit. The LDO unit then converts the intermediate voltage into different voltages, which are supplied to the CPU core 1, timing control chip 2, clock chip 4, BIOS chip 5, and memory module 7 respectively via the SYS bus. It should be noted that the signal conversion unit realizes the conversion and adaptation between different signals, such as converting PCIe signals into USB, SATA and other interface signals to meet diverse interface requirements; the second array connector is plugged into the first array connector of the core module to realize fast signal transmission and flexible configuration, and improve the scalability of the system.

[0035] This embodiment uses the signal conversion unit of the second array connector 8 to achieve flexible routing and conversion of different signals, adapting to various interface requirements; it supports multiple interfaces such as DB9, USB, SATA, and PCIE to meet the expansion needs of the server in different application scenarios; and through the DC-DC and LDO units of the power module 15, it provides a stable and reliable power supply to the core components of the server to ensure normal system operation.

[0036] The S500C server's modular design allows for the free disassembly of CPU core modules. These modules are compatible with various server motherboards, simplifying the design process by requiring only the necessary interfaces and functions. This significantly reduces design costs and complexity. For example, to create a single-socket server with PCIe, USB, and SATA interfaces, only a simple design is needed. Figure 2 The server motherboard shown leads the PCIe signal of the core module to the motherboard PCIe slot through a 688-pin connector, and converts the other two PCIe signals into USB and SATA interfaces through the USB controller and SATA controller.

[0037] Furthermore, as a refinement and extension of the specific implementation methods of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, as follows: Figure 3As shown, another server motherboard is provided for connecting the modular server core module described in the two embodiments above, including a signal conversion unit and two second array connectors 8; The upper end of the second array connector 8 is inserted into the first array connector 2; The lower end of the second array connector 8 is equipped with a UART bus, a second PCIE bus, a third PCIE bus, a fourth PCIE bus, and a SYS bus; The UART bus is connected to a DB9 interface 9, the second PCIe bus is connected to a USB controller 10, the USB controller 10 is connected to several USB interfaces 11, the third PCIe bus is connected to a SATA controller 12, the SATA controller 12 is connected to several SATA interfaces 13, the fourth PCIe bus is connected to a PCIe slot 14, and the SYS bus is connected to a power module 15. For example, there are 4 USB ports and 4 SATA ports; Power module 15 includes a DC-DC unit and an LDO unit; One end of the DC-DC unit is connected to an external power source, and the other end is connected to the LDO unit; The DC-DC unit converts the external power supply voltage into an intermediate voltage to supply the LDO unit. The LDO unit then converts the intermediate voltage into different voltages, which are supplied to the CPU core 1, timing control chip 2, clock chip 4, BIOS chip 5, and memory module 7 respectively via the SYS bus. There are two second array connectors 8. The second array connectors 8 are also connected to a C2C bus for communication between CPU cores 1 of different module boards.

[0038] It should be noted that if a dual-processor server is required, an additional second RAID connector 8 should be added to the server motherboard. The C2C (CPU interconnect signal) of the two RAID connectors 8 should be linked on the server motherboard, as follows: Figure 3 As shown, this design allows for easy replacement of expensive CPU core modules during debugging. In terms of production and assembly, it eliminates complex soldering processes, improving server yield. During later maintenance, because the CPU core module and motherboard are connected via a 688-pin connector, faulty CPU core modules or motherboards can be flexibly replaced while retaining good components, reducing maintenance costs and complexity.

[0039] like Figure 4 As shown, the following is an embodiment of a modular server signal routing method provided by this disclosure, based on the above two server motherboards, including the following steps: S1. Receive the native signal set output by the modular server core module through the first array connector, the native signal set including the first UART signal U1, the first PCIE signal P1 and the C2C interconnect signal C1; S2. Dynamic routing is achieved by interlocking the first array connector with the second array connector: The first UART signal U1 is directly connected to the DB9 interface; The first PCIe signal P1 is split into three independent sub-channel signals: the first sub-channel signal P1a, the second sub-channel signal P1b, and the third sub-channel signal P1c. The first sub-channel signal P1a is directly connected to the PCIe slot, the second sub-channel signal P1b is converted to the USB protocol by the USB controller to communicate with the USB interface, and the third sub-channel signal P1c is converted to the SATA protocol by the SATA controller to communicate with the SATA interface. When multiple modular server core modules are detected, the C2C interconnect signals C1 of each module are directly connected through the onboard C2C link of the server motherboard.

[0040] This embodiment receives the native signal set and performs dynamic routing to achieve flexible signal allocation and conversion, meeting the connection needs of different devices and application scenarios; it dynamically adjusts the PCIe channel allocation according to real-time load traffic to ensure efficient utilization of server resources and improve system performance.

[0041] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, and to fully illustrate the specific implementation process in this embodiment, another modular server signal routing method is provided, which includes the following steps: S1. Receive the native signal set output by the modular server core module through the first array connector, the native signal set including the first UART signal U1, the first PCIE signal P1 and the C2C interconnect signal C1; It should be noted that the native signal set output by the receiving core module provides the basic data for subsequent signal processing and routing; S2. Dynamic routing is achieved by interlocking the first array connector with the second array connector: The first UART signal U1 is directly connected to the DB9 interface; The first PCIe signal P1 is split into three independent sub-channel signals: the first sub-channel signal P1a, the second sub-channel signal P1b, and the third sub-channel signal P1c. The first sub-channel signal P1a is directly connected to the PCIe slot, the second sub-channel signal P1b is converted to the USB protocol by the USB controller to communicate with the USB interface, and the third sub-channel signal P1c is converted to the SATA protocol by the SATA controller to communicate with the SATA interface. When multiple modular server core modules are detected, the C2C interconnect signals C1 of each module are directly connected through the onboard C2C link of the server motherboard. It should be noted that by dynamically routing the native signal set, flexible signal allocation and conversion can be achieved to meet the connectivity needs of different devices and application scenarios. S3. Perform dynamic resource allocation: USB controller statistics of real-time USB load traffic And report to the timing control chip via the second I2C bus; SATA controller statistics of real-time SATA load flow And report to the timing control chip via the second I2C bus; The timing control chip adjusts according to real-time USB load flow. and real-time SATA load traffic And use the following formula to allocate PCIe lanes:

[0042]

[0043] in, This is the total number of allocatable PCIe sub-channels. It is the preset USB weighting coefficient; When there are two modular server core modules on the server board, the following steps are also included: It should be noted that the PCIe channel allocation is dynamically adjusted based on real-time load traffic to ensure efficient utilization of server resources and improve system performance. S4. Perform load balancing: S41. Perform PCIe load rate collection: Each timing control chip calculates the PCIe load rate of its CPU core:

[0044] in, It refers to the number of packages received. It refers to the number of packets sent. It is the theoretical bandwidth of a single channel. It is a statistical unit of time; S42. Execute master-slave collaboration: The master timing controller chip is configured to collect PCIe load rate data from the slave timing controller chip via a C2C link, and the load balancing factor is calculated using the following formula. :

[0045] in, It is the PCIe load rate of the main CPU core. It is the PCIe load rate of the CPU core; S43. Execution Channel Migration: When load balancing factor Less than the preset equalization threshold At that time, the main timing control chip calculates the number of migration channels. :

[0046] in, It is the PCIe load rate of the main CPU core. It's based on the CPU core's PCIe load rate. These are preset coefficients. It is the floor function. This refers to the number of PCIe lanes available to the main CPU core. This refers to the number of available PCIe lanes on the CPU core. The migration from high-load CPU cores to low-load CPU cores is based on the calculated number of migration channels. Perform PCIe lane migration; It should be noted that in a multi-core module environment, load balancing strategies are used to optimize the use of PCIe channels, avoid resource waste and performance bottlenecks, and improve the overall performance and reliability of the system.

[0047] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0048] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A modular server core module, characterized in that, Including module boards; The module board contains a CPU core, a first array connector, a timing control chip, a clock chip, and a BIOS chip. The CPU core is equipped with a DDR interface, which is connected to several memory channels, and each memory channel is connected to a memory module. The CPU core is connected to the first array connector through the first UART bus, the first PCIe bus, and the C2C bus; it is connected to the BIOS chip through the SPI bus; it is connected to the timing control chip through the L bus, the first I2C bus, the second UART bus, and the GPIO signal line; and it is connected to the clock chip through the clock signal line. The clock chip is also connected to the timing control chip, which is in turn connected to the first array connector via the second I2C bus and the SYS bus.

2. The modular server core module according to claim 1, characterized in that, The CPU core used is the Phytium S5000C series CPU core, which includes three models: 64-core, 32-core, and 16-core.

3. The modular server core module according to claim 1, characterized in that, The CPU core has two DDR interfaces, which are positioned opposite each other on both sides of the CPU core. Each DDR interface connects to 4 memory channels, and each memory channel connects to a memory module consisting of 9 DDR5 memory chips.

4. The modular server core module according to claim 1, characterized in that, The timing control chip uses a CPLD or MCU chip; The clock signal lines include 33M clock signal lines, 100M clock signal lines, and 156M clock signal lines; The first array connector uses a 688-pin array connector.

5. A server motherboard for connecting to a modular server core module as described in any one of claims 1-4, characterized in that, Includes a signal conversion unit and at least one second array connector; The upper end of the second array connector is inserted into the first array connector; The lower end of the second array connector is equipped with a UART bus, a second PCIE bus, a third PCIE bus, a fourth PCIE bus, and a SYS bus; The UART bus is connected to a DB9 interface, the second PCIe bus is connected to a USB controller, the USB controller is connected to several USB interfaces, the third PCIe bus is connected to a SATA controller, the SATA controller is connected to several SATA interfaces, the fourth PCIe bus is connected to a PCIe slot, and the SYS bus is connected to a power module.

6. The server motherboard according to claim 5, characterized in that, The power module includes a DC-DC unit and an LDO unit; One end of the DC-DC unit is connected to an external power source, and the other end is connected to the LDO unit; The DC-DC unit converts the external power supply voltage into an intermediate voltage to supply the LDO unit. The LDO unit then converts the intermediate voltage into different voltages, which are supplied to the CPU core, timing control chip, clock chip, BIOS chip, and memory module via the SYS bus.

7. The server motherboard according to claim 5, characterized in that, When the number of second array connectors is greater than one, the second array connectors are also connected to a C2C bus for communication between CPU cores of different module boards.

8. A modular server signal routing method, based on the server motherboard according to any one of claims 5-7, characterized in that, Includes the following steps: S1. Receive the native signal set output by the modular server core module through the first array connector, the native signal set including the first UART signal U1, the first PCIE signal P1 and the C2C interconnect signal C1; S2. Dynamic routing is achieved by interlocking the first array connector with the second array connector: The first UART signal U1 is directly connected to the DB9 interface; The first PCIe signal P1 is split into three independent sub-channel signals: the first sub-channel signal P1a, the second sub-channel signal P1b, and the third sub-channel signal P1c. The first sub-channel signal P1a is directly connected to the PCIe slot, the second sub-channel signal P1b is converted to the USB protocol by the USB controller to communicate with the USB interface, and the third sub-channel signal P1c is converted to the SATA protocol by the SATA controller to communicate with the SATA interface. When multiple modular server core modules are detected, the C2C interconnect signals C1 of each module are directly connected through the onboard C2C link of the server motherboard.

9. The modular server signal routing method according to claim 8, characterized in that, It also includes the following steps: S3. Perform dynamic resource allocation: USB controller statistics of real-time USB load traffic And report to the timing control chip via the second I2C bus; SATA controller statistics of real-time SATA load flow And report to the timing control chip via the second I2C bus; The timing control chip adjusts according to real-time USB load flow. and real-time SATA load traffic And use the following formula to allocate PCIe lanes: in, This is the total number of allocatable PCIe sub-channels. It is the preset USB weighting coefficient.

10. The modular server signal routing method according to claim 9, characterized in that, When there are two modular server core modules on the server board, the following steps are also included: S4. Perform load balancing: S41. Perform PCIe load rate collection: Each timing control chip calculates the PCIe load rate of its CPU core: in, It refers to the number of packages received. It refers to the number of packets sent. It is the theoretical bandwidth of a single channel. It is a statistical unit of time; S42. Execute master-slave collaboration: The master timing controller chip is configured to collect PCIe load rate data from the slave timing controller chip via a C2C link, and the load balancing factor is calculated using the following formula. : in, It is the PCIe load rate of the main CPU core. It is the PCIe load rate of the CPU core; S43. Execution Channel Migration: When load balancing factor Less than the preset equalization threshold At that time, the main timing control chip calculates the number of migration channels. : in, It is the PCIe load rate of the main CPU core. It's based on the CPU core's PCIe load rate. These are preset coefficients. It is the floor function. This refers to the number of PCIe lanes available to the main CPU core. This refers to the number of available PCIe lanes on the CPU core. The migration from high-load CPU cores to low-load CPU cores is based on the calculated number of migration channels. Perform PCIe channel migration.

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