Method of manufacturing semiconductor layer and transistor

Abstract

The invention provides a method of manufacturing a semiconductor layer and a transistor. The method of manufacturing a semiconductor layer includes: preparing an insulating layer including silicon oxide; forming a metal mask on the insulating layer; performing an oxygen plasma process on the metal mask; the metal mask is removed; and loading the insulating layer into a chamber to form the semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor layer and a transistor comprising the semiconductor layer manufactured by the method. Background Technology

[0002] As a next-generation semiconductor material, layered semiconductor materials are attracting attention due to their flexibility and transparency.

[0003] As for applications requiring features such as film thickness and high mobility (tens to hundreds of cm), 2 Transition metal dichalcogenides (TMDCs) are gaining attention as materials for next-generation electronic devices with properties such as high conduction / cutoff ratio (V / s) and high on / off ratio. For example, research is underway on TMDCs as channel materials for transparent and flexible display thin-film transistors, channel materials to overcome scaling in electronic devices, and materials for electronic sensors with high sensitivity properties. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for manufacturing a semiconductor layer that is easy to manufacture and has improved reliability, and a transistor comprising the semiconductor layer manufactured by the method.

[0005] According to embodiments of the present disclosure, a method for manufacturing a semiconductor layer includes: preparing an insulating layer comprising silicon oxide; forming a metal mask on the insulating layer; performing an oxygen plasma process on the metal mask; removing the metal mask; and loading the insulating layer into a chamber to form a semiconductor layer.

[0006] In an embodiment, the thickness of the insulating layer can be in the range of approximately 200 nanometers to approximately 400 nanometers.

[0007] In one embodiment, the insulating layer may include a first region and a second region having different surface energies from each other, using the oxygen plasma process.

[0008] In an embodiment, the first region may have a higher surface energy than the second region.

[0009] In an embodiment, the first region may be hydrophilic, and the second region may be hydrophobic.

[0010] In an embodiment, the first region may include Si-OH bonds, and the second region may include Si-O-Si bonds.

[0011] In an embodiment, the metal mask may include at least one selected from molybdenum (Mo), gold (Au), silver (Ag), copper (Cu), and titanium (Ti).

[0012] In an embodiment, the metal mask may have a thickness in the range of approximately 50 nanometers to approximately 150 nanometers.

[0013] In one embodiment, after a metal layer is formed on the insulating layer, the metal mask can be formed by a patterning process.

[0014] In an embodiment, the oxygen plasma process can be performed at a power range of approximately 150W to approximately 250W.

[0015] In an embodiment, the oxygen plasma process can be performed for a period of time ranging from approximately 200 seconds to approximately 400 seconds.

[0016] In an embodiment, the method may further include the step of injecting a precursor, a reactant, and an inert gas into the chamber to form the semiconductor layer.

[0017] In an embodiment, the precursor may be injected in an amount ranging from about 0.3 mg to about 0.7 mg, and the reactant may be injected in an amount ranging from about 330 mg to about 370 mg.

[0018] In an embodiment, the reactant may be injected in an amount ranging from about 500 to about 1000 times the amount injected in the precursor.

[0019] In an embodiment, the precursor and the reactant can react to form a semiconductor layer with a layered structure on the first region.

[0020] In an embodiment, the semiconductor layer having the layered structure may comprise a material of chemical formula XY. a The compound is represented by X, where X is one of Mo, W, Zr and Re, Y is one of S, Se and Te, and a can be a natural number greater than or equal to 1.

[0021] In an embodiment, the semiconductor layer having the layered structure may include at least one compound selected from MoS2, MoSe2, WS2, WSe2, MoTe2, WTe2, ZrS2, ZrSe2, ZrTe2, ReS2, ReSe2 and ReTe2.

[0022] According to an embodiment, the transistor includes: a substrate; a semiconductor layer disposed on the substrate; a gate electrode overlapping a portion of the semiconductor layer; and a source electrode and a drain electrode electrically connected to the semiconductor layer. The semiconductor layer is manufactured by the method described above.

[0023] According to embodiments of this disclosure, a method of manufacturing a semiconductor layer includes: preparing a substrate comprising silicon; forming an insulating layer comprising silicon oxide on the substrate; forming a metal layer on the insulating layer; patterning the metal layer to form a metal mask having opening regions; performing an oxygen plasma process on the metal mask, the oxygen plasma process forming a first region of the insulating layer exposed by the opening regions of the metal mask during the execution of the oxygen plasma process and a second region of the insulating layer covered by the metal mask during the execution of the oxygen plasma process; and forming the semiconductor layer on the first region. The first region is hydrophilic, and the second region is hydrophobic.

[0024] In one embodiment, the first region has a higher surface energy than the second region.

[0025] In an embodiment, the semiconductor layer is formed on the first region by a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, an atomic layer deposition process, or a sputtering process.

[0026] In one embodiment, the first region has a contact angle in the range of approximately 5 degrees or less. The second region has a contact angle in the range of approximately 30 degrees to approximately 60 degrees.

[0027] According to embodiments, a method for manufacturing a semiconductor layer that is easy to manufacture and has improved reliability can be provided, as well as a transistor comprising the semiconductor layer manufactured by the method. Attached Figure Description

[0028] Figure 1 This is a cross-sectional view showing a transistor according to an embodiment of the present disclosure.

[0029] Figures 2 to 10 This is a schematic diagram of some components of a method for manufacturing a semiconductor layer according to embodiments of the present disclosure.

[0030] Figure 11A It is an optical image of a semiconductor layer fabricated according to an example, and Figure 11B It is a measurement Figure 11A A diagram showing the height of each pattern in the diagram.

[0031] Figure 12 These are scanning electron microscope (SEM) images of semiconductor layers manufactured according to embodiments of the present disclosure.

[0032] Figure 13 It is a Raman diagram of a semiconductor layer manufactured according to an embodiment of the present disclosure.

[0033] Figure 14It is a Raman mapping image of a semiconductor layer manufactured according to an embodiment of the present disclosure.

[0034] Figures 15 to 17 This is an atomic force microscope (AFM) image of a plasma-treated surface according to an embodiment of the present disclosure.

[0035] Figure 18 This is a lateral force microscope (LFM) image of a plasma-treated surface according to an embodiment of the present disclosure.

[0036] Figure 19 This is a diagram illustrating the lateral forces for each region according to embodiments of the present disclosure. Detailed Implementation

[0037] In the following, various non-limiting embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the disclosure. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein.

[0038] To clearly explain the embodiments of this disclosure, parts unrelated to the description may be omitted, and the same or similar components are given the same reference numerals throughout the specification.

[0039] Furthermore, for ease of explanation, the dimensions and thicknesses of each component shown in the accompanying drawings may be arbitrarily illustrated, and the embodiments of this disclosure are not necessarily limited to the dimensions and thicknesses shown. In the drawings, thicknesses may be enlarged to clearly represent the individual layers and regions. And in the drawings, the thicknesses of some layers and regions may be exaggerated for ease of explanation.

[0040] Furthermore, when a portion of a layer, membrane, region, or plate is referred to as being "above" or "on" another portion, this includes not only cases where the portion is "directly above" the other portion, but also cases where there is another portion between the portion and the other portion. Conversely, when an element is referred to as being "directly above" another element, there is no intervening element. Additionally, "above" or "on" a reference component means disposed above or below the reference component, and does not necessarily mean disposed "above" or "on" the reference component in a direction opposite to gravity.

[0041] Furthermore, throughout the specification, unless specifically stated otherwise, when a part, component, or element is referred to as "comprising" a certain component, this means that the part, component, or element may also include other components, rather than excluding other components.

[0042] Furthermore, throughout the instruction manual, when "on a plane" is mentioned, it means when the target part is viewed from above, and when "on a cross section" is mentioned, it means when the target part is cut perpendicularly and viewed from the side.

[0043] In the following text, reference will be made to Figure 1 A transistor according to an embodiment is described. Figure 1 This is a cross-sectional view showing a transistor according to an embodiment.

[0044] refer to Figure 1 According to embodiments, transistors can be disposed on a substrate SUB. In embodiments, the substrate SUB may include transparent glass. However, embodiments of this disclosure are not limited thereto, and the substrate SUB may include various materials such as transparent plastic or metal.

[0045] In this embodiment, the buffer layer may also be disposed on the substrate SUB (e.g., directly on the substrate SUB). The buffer layer can prevent impurity ions from diffusing into the semiconductor layer ACT, prevent moisture or external air penetration, and planarize the surface. In this embodiment, the buffer layer may be composed of inorganic materials.

[0046] The semiconductor layer ACT can be disposed on the substrate SUB.

[0047] In this embodiment, the semiconductor layer ACT comprises a two-dimensional semiconductor material. A two-dimensional semiconductor material refers to a semiconductor material with a layered structure in which the component atoms are bonded to each other in a two-dimensional manner. Two-dimensional semiconductor materials possess excellent electrical properties and can maintain high mobility even when the thickness is reduced to the nanometer scale without significantly altering the properties of the two-dimensional semiconductor material.

[0048] In embodiments, the two-dimensional semiconductor material may include a material having a band gap in the range of about 0.1 eV to about 3.0 eV. However, embodiments of this disclosure are not necessarily limited thereto. In embodiments, the two-dimensional semiconductor material may include, for example, transition metal dichalcogenides (TMDC), black phosphorus, or graphene.

[0049] The semiconductor layer ACT may include, for example, a semiconductor material having a layered structure. In an embodiment, the semiconductor material having a layered structure may be a transition metal dichalcogenide (TMDC).

[0050] In an embodiment, the semiconductor material having a layered structure may include materials with the chemical formula XY. aThe compound is represented by X, which is one of Mo, W, Zr, and Re; Y is one of S, Se, and Te; and a can be a natural number greater than or equal to 1. For example, in embodiments, semiconductor materials having a layered structure may include at least one of MoS2, MoSe2, WS2, WSe2, MoTe2, WTe2, ZrS2, ZrSe2, ZrTe2, ReS2, ReSe2, and ReTe2.

[0051] The two-dimensional semiconductor material constituting the semiconductor layer ACT can have a single-layer or multi-layer structure, and each layer can have a thickness at the atomic level. For example, in embodiments, the two-dimensional semiconductor material can include 1 to 10 layers. For example, the two-dimensional semiconductor material can include 1 to 5 layers. However, the embodiments of this disclosure are not limited to this.

[0052] In this embodiment, the thickness of the semiconductor layer ACT (e.g., its length in the thickness direction of the substrate SUB) can be less than or equal to approximately 1.5 nm. The relatively thin thickness of the semiconductor layer ACT can improve the flexibility of the transistor.

[0053] The semiconductor layer ACT may also include predetermined dopants to control the mobility of the two-dimensional semiconductor material. In embodiments, the two-dimensional semiconductor material may be doped with p-type or n-type dopants. The p-type or n-type dopants may be doped using ion implantation or chemical doping.

[0054] In the embodiments, the semiconductor layer ACT can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or sputtering.

[0055] The gate insulating layer GI can be disposed on the semiconductor layer ACT and the substrate SUB (e.g., directly disposed on the semiconductor layer ACT and the substrate SUB). In embodiments, the gate insulating layer GI may include inorganic materials such as silicon nitride, silicon oxide, etc.

[0056] The gate electrode GE may be disposed on the gate insulating layer GI (e.g., directly disposed on the gate insulating layer GI). The gate electrode GE may (e.g., in a plan view) overlap with the semiconductor layer ACT. Although this specification shows an embodiment in which the gate electrode GE is disposed above the semiconductor layer ACT, the embodiments disclosed herein are not limited thereto, and in some embodiments, the gate electrode GE may be disposed below the semiconductor layer ACT.

[0057] The gate electrode GE may include a metal, a conductive nitride, or a conductive oxide. In embodiments, the metal may include at least one of, for example, Au, Ti, W, Mo, Pt, and Ni. The conductive nitride may include, for example, TiN, TaN, WN, etc., and the conductive oxide may include, for example, ITO (indium tin oxide), IZO (indium zinc oxide), etc. However, embodiments of this disclosure are not necessarily limited thereto.

[0058] The interlayer insulating layer (ILD) can be disposed on the gate electrode GE and the gate insulating layer GI (e.g., directly disposed on the gate electrode GE and the gate insulating layer GI). The interlayer insulating layer (ILD) can include organic insulating materials or inorganic insulating materials.

[0059] The source electrode SE and drain electrode DE can be disposed on the interlayer insulating layer ILD (e.g., directly disposed on the interlayer insulating layer ILD). In an embodiment, each of the source electrode SE and drain electrode DE can be physically and electrically connected to the semiconductor layer ACT through contact holes formed in the interlayer insulating layer ILD and the gate insulating layer GI.

[0060] The aforementioned semiconductor layer ACT, gate electrode GE, source electrode SE, and drain electrode DE can form a transistor. However, the aforementioned semiconductor layer ACT is not limited to this and can be applied to memory devices such as dynamic random access memory (DRAM) devices. The memory device can have a structure in which the aforementioned semiconductor layer ACT and capacitors are electrically connected to each other. Furthermore, devices containing the aforementioned semiconductor layer ACT can be applied to various electronic devices. For example, devices containing the aforementioned semiconductor layer ACT can be used for arithmetic operations, program execution, temporary data retention, etc., in electronic devices such as mobile devices, computers, laptop computers, sensors, network devices, neuromorphic devices, etc. A method for manufacturing the aforementioned semiconductor layer ACT according to an embodiment of this disclosure is described below.

[0061] In the following text, reference will be made to Figures 2 to 10 A method for manufacturing a semiconductor layer used to form the semiconductor layer included in the aforementioned transistor is discussed. Figures 2 to 10 This is a schematic diagram of some components of a method for manufacturing a semiconductor layer according to some embodiments of the present disclosure.

[0062] First, refer to Figure 2An insulating layer IL1 is prepared and disposed on a first substrate SUB1. For example, in an embodiment, the first substrate SUB1 may include silicon (Si), and the insulating layer IL1 may include a silicon oxide material. In an embodiment, the thickness of the insulating layer IL1 may be in the range of about 200 nanometers to about 400 nanometers, such as about 300 nanometers. In embodiments where the insulating layer IL1 meets the above-mentioned thickness, the insulating layer IL1 may be divided into hydrophobic and hydrophilic regions in adjacent areas while maintaining its insulating capability.

[0063] refer to Figure 3 In this embodiment, a metal layer is then deposited on the insulating layer IL1, and the deposited metal layer is patterned to form a metal mask. The portion of the metal layer corresponding to the location where a semiconductor layer will be deposited later can be removed using a patterning process.

[0064] In embodiments, the thickness of the metal mask can range from approximately 50 nanometers to approximately 150 nanometers, such as approximately 100 nanometers. In embodiments where the thickness of the metal mask meets the above-mentioned numerical range, the metal mask can be used to provide a suitable surface energy difference on the insulating layer IL1 during the oxygen plasma process.

[0065] The metal mask according to the embodiments may include a metallic material, and for example, may include at least one of molybdenum (Mo), gold (Au), silver (Ag), copper (Cu), and titanium (Ti). However, the embodiments of this disclosure are not limited thereto.

[0066] A metal mask can be a thin film of a single metal, a thin film containing two or more metals, or a multilayer metal thin film containing different metals.

[0067] In an embodiment, such as Figure 4 As shown, an oxygen plasma process is performed on a metal mask. In an embodiment, the oxygen plasma process can be performed at a power ranging from approximately 150 W to approximately 250 W for a time period ranging from approximately 200 seconds to approximately 400 seconds. For example, in an embodiment, the oxygen plasma process can be performed at a power of approximately 200 W for approximately 300 seconds.

[0068] When performing an oxygen plasma process, the surface of the insulating layer IL1 exposed by the metal mask can be modified to be hydrophilic. This maximizes the difference in surface properties between the portion of the insulating layer IL1 covered by the metal mask and the portion exposed by the openings in the metal mask.

[0069] After that, as Figure 5 The image shows the removal of the metal mask.

[0070] like Figure 6 As shown, the insulating layer IL1 may include a first region R1 and a second region R2 having different surface energies. In an embodiment, the first region R1 may be a hydrophilic region, and the second region R2 may be a hydrophobic region. The first region R1 may correspond to a metal mask (see reference). Figure 4 The opening region of ), and the second region R2 can correspond to the region covered by the metal mask during the oxygen plasma process.

[0071] The hydrophilic first region R1 can have a relatively high surface energy. Conversely, the hydrophobic second region R2 can have a relatively low surface energy. The surface energy of the first region R1 can be greater than that of the second region R2. For example, the first region R1 can have a higher surface energy than the second region R2.

[0072] like Figure 7 As shown, in an embodiment, the first region R1 is masked by a metal mask (see reference) during an oxygen plasma process. Figure 4 The first region R1 is exposed, and thus, the Si-O bonds originally present in the insulating layer IL1 are broken by the oxygen plasma, and new Si-OH bonds are formed through reaction with neighboring H2O. Due to this bonding, the first region R1 can include dangling bonds, and the surface energy of the first region R1 can be increased. Conversely, since the second region R2 is covered by a metal mask, the Si-O-Si bonds in the insulating layer IL1 can be preserved. The second region R2 maintains a stable bonding state and can have a relatively low surface energy.

[0073] For reference, the second region R2 can exhibit the following characteristics: Figure 8 The high contact angle shown is illustrated. The first region R1 can have, for example, a high contact angle. Figure 9 The low contact angle shown. For example, in an embodiment, the first region R1 may have a contact angle in the range of about 5 degrees or less, and the second region R2 may have a contact angle in the range of about 30 degrees to about 60 degrees (such as 40 degrees).

[0074] In an embodiment, after forming an insulating layer IL1 comprising a first region R1 and a second region R2 using the aforementioned process, the insulating layer IL1 can be loaded onto, for example... Figure 10 The chamber CH shown is used to form a semiconductor layer. This disclosure describes an embodiment in which the method of forming the semiconductor layer uses chemical vapor deposition. However, the embodiments of this disclosure are not limited to this, and the semiconductor layer can be formed using various methods such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or sputtering processes.

[0075] In an embodiment, precursor P1, reactant RE, and inert gas G1 may be injected into chamber CH. Although this specification describes an embodiment in which one precursor is used as an example, the embodiments disclosed herein are not limited thereto, and in some embodiments two or more precursors may be used. Precursor P1 and reactant RE may react within chamber CH to form a semiconductor layer ACT on a first region R1 (such as a region having a hydrophilicity).

[0076] For example, in an embodiment, precursor P1 may include MoO3 and may be injected into chamber CH in an amount ranging from about 0.3 mg to about 0.7 mg. Additionally, reactant RE may include S and may be injected into chamber CH in an amount ranging from about 330 mg to about 370 mg. In an embodiment, reactant RE may be injected in an amount ranging from about 500 to about 1000 times the amount of precursor P1 injected. For example, precursor P1 may be injected in an amount of about 0.5 mg, and reactant RE may be injected in an amount of about 350 mg. The inert gas G1 according to an embodiment may include at least one of Ar, N2, and mixtures thereof.

[0077] The semiconductor layer ACT according to an embodiment may include a semiconductor material having a layered structure. In an embodiment, the semiconductor material having a layered structure may include a semiconductor material with the chemical formula XY. a The compound is represented by X, which is one of Mo, W, Zr, and Re; Y is one of S, Se, and Te; and a can be a natural number greater than or equal to 1. For example, in embodiments, semiconductor materials having a layered structure may include at least one compound selected from MoS2, MoSe2, WS2, WSe2, MoTe2, WTe2, ZrS2, ZrSe2, ZrTe2, ReS2, ReSe2, and ReTe2.

[0078] Using the manufacturing method according to embodiments of the present disclosure, the desired pattern can be easily provided by providing an insulating layer having hydrophilic and hydrophobic regions and forming a semiconductor layer directly on the hydrophilic region of the insulating layer. Furthermore, the precision and accuracy of the pattern are improved, and the problem of residual material can be solved.

[0079] In the following text, reference will be made to Figures 11A to 19 The properties of the semiconductor layer manufactured according to the embodiments were tested. Figure 11A It is an optical image of a semiconductor layer manufactured according to an example. Figure 11B It is a measurement Figure 11A A graph showing the height of each pattern in the diagram, and Figure 12 These are scanning electron microscope (SEM) images of semiconductor layers manufactured according to embodiments of the present disclosure. Figure 13This refers to the Raman image of a semiconductor layer manufactured according to embodiments of the present disclosure. Figure 14 It is a Raman mapping image of a semiconductor layer manufactured according to embodiments of the present disclosure, and Figures 15 to 17 These are atomic force microscopy (AFM) images of plasma-treated surfaces according to embodiments of the present disclosure. Figure 18 These are lateral force microscopy (LFM) images of a plasma-treated surface according to embodiments of the present disclosure, and Figure 19 This is a diagram illustrating the lateral forces for each region according to embodiments of the present disclosure.

[0080] Figure 11A These are optical microscope images of insulating layers disposed therein, formed by a method for manufacturing semiconductor layers according to embodiments of the present disclosure. Reference Figure 11A As can be seen, the semiconductor layer is repeatedly formed only in the first region, which is hydrophilic.

[0081] Figure 11B It is aimed at Figure 11A The height diagram of the insulating layer and semiconductor layer. When the height of the insulating layer is set to the reference point (0nm), it is confirmed that... Figure 11A The semiconductor layer in the structure is stably and repeatedly formed with an average height of 1.5 nm.

[0082] Figure 12 These are scanning electron microscope (SEM) images of an example of a semiconductor layer fabricated using a specific pattern. For example... Figure 12 As shown, the semiconductor layer can be manufactured and modified into various shapes according to the user's needs. Therefore, it is confirmed that various types of patterning are possible by providing an insulating layer including hydrophilic and hydrophobic regions and by stably depositing semiconductor material on the insulating layer.

[0083] Figure 13 It is a Raman image of a semiconductor layer manufactured according to an embodiment, and Figure 14 This is a Raman mapping image of a semiconductor layer manufactured according to an embodiment. Reference Figure 13 and Figure 14 It is confirmed that all semiconductor layers manufactured according to embodiments of the present disclosure comprise MoS2 containing Mo and S.

[0084] refer to Figures 15 to 17 This is an AFM image of the insulating layer when an oxygen plasma process is performed at a power of 200W and a process time of 300s. Figure 15 It is an image representing both the hydrophobic region (i.e., the second region R2) and the hydrophilic region (i.e., the first region R1). Figure 16 It means corresponding to Figure 15 The image of the hydrophobic region B in the image, and Figure 17 It means corresponding to Figure 15 Image of C in the hydrophilic region.

[0085] Figure 16 The root mean square (RMS) value of the surface roughness for the hydrophobic region is approximately 0.13 nm, and Figure 17 The root mean square (RMS) value for the surface roughness of the hydrophilic region is approximately 0.19 nm.

[0086] Figure 18 This is an LFM image of a portion of an insulating layer manufactured according to an embodiment, and Figure 19 It shows along Figure 18 The diagram shows the lateral forces along line D-D'. (Refer to...) Figure 19 The diagram and reference Figure 18 It was confirmed that a lateral force of approximately 615 mV to 622 mV appeared in the first region R1, which exhibits hydrophilicity. Therefore, it was confirmed that the surface energy of the first region R1 is relatively high compared to the surface energy of the second region R2, and that the first region R1 possesses relatively high attractive properties. Thus, when the insulating layer according to the embodiment is loaded into a chamber for depositing semiconductor material, it can be observed that the semiconductor material is stably formed only in the first region R1.

[0087] Although the non-limiting embodiments of this disclosure have been described in detail above, the scope of the embodiments of this disclosure is not limited thereto, and various modifications can be made by those skilled in the art and are included within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor layer, wherein, The method includes: Prepare an insulating layer including silicon oxide; A metal mask is formed on the insulating layer; An oxygen plasma process is performed on the metal mask; Remove the metal mask; and The insulating layer is loaded into the chamber to form the semiconductor layer.

2. The method for manufacturing the semiconductor layer according to claim 1, wherein, The thickness of the insulating layer is in the range of 200 nanometers to 400 nanometers.

3. The method for manufacturing the semiconductor layer according to claim 1, wherein, The insulating layer, obtained through the oxygen plasma process, comprises a first region and a second region that have different surface energies from each other.

4. The method for manufacturing the semiconductor layer according to claim 3, wherein, The first region has a higher surface energy than the second region.

5. The method for manufacturing the semiconductor layer according to claim 3, wherein, The first region is hydrophilic, and the second region is hydrophobic.

6. The method for manufacturing the semiconductor layer according to claim 3, wherein: The first region includes Si-OH bonds; and The second region includes Si-O-Si bonds.

7. The method for manufacturing the semiconductor layer according to claim 1, wherein, The metal mask includes at least one selected from Mo, Au, Ag, Cu, and Ti.

8. The method for manufacturing the semiconductor layer according to claim 1, wherein, The metal mask has a thickness in the range of 50 nanometers to 150 nanometers.

9. The method for manufacturing the semiconductor layer according to claim 1, wherein, After a metal layer is formed on the insulating layer, the metal mask is formed by a patterning process.

10. The method for manufacturing the semiconductor layer according to claim 1, wherein, The oxygen plasma process is performed at a power range of 150W to 250W.

11. The method for manufacturing the semiconductor layer according to claim 1, wherein, The oxygen plasma process is performed for a period of time ranging from 200 to 400 seconds.

12. The method for manufacturing the semiconductor layer according to claim 3, wherein, The method further includes the step of injecting a precursor, reactant, and inert gas into the chamber to form the semiconductor layer.

13. The method of manufacturing the semiconductor layer according to claim 12, wherein: The precursor is injected in an amount ranging from 0.3 mg to 0.7 mg; and The reactants are injected in amounts ranging from 330 mg to 370 mg.

14. The method of manufacturing the semiconductor layer according to claim 12, wherein, The reactant is injected in an amount ranging from 500 to 1000 times the amount injected into the precursor.

15. The method of manufacturing the semiconductor layer according to claim 12, wherein, The precursor and the reactant react to form a semiconductor layer with a layered structure on the first region.

16. The method of manufacturing the semiconductor layer according to claim 15, wherein: The semiconductor layer having the layered structure comprises components of the chemical formula XY a The compound represented, Where X is one of Mo, W, Zr and Re, Y is one of S, Se and Te, and a is a natural number greater than or equal to 1.

17. The method of manufacturing the semiconductor layer according to claim 16, wherein, The semiconductor layer having the layered structure includes at least one compound selected from MoS2, MoSe2, WS2, WSe2, MoTe2, WTe2, ZrS2, ZrSe2, ZrTe2, ReS2, ReSe2 and ReTe2.

18. A transistor, wherein, The transistor includes: Base; A semiconductor layer is disposed on the substrate; The gate electrode overlaps with a portion of the semiconductor layer; and The source and drain electrodes are electrically connected to the semiconductor layer. The semiconductor layer is manufactured by the method for manufacturing the semiconductor layer as described in claim 1.

19. The transistor of claim 18, wherein, The semiconductor layer comprises components with the chemical formula XY. a The compound represented, Where X is one of Mo, W, Zr and Re, Y is one of S, Se and Te, and a is a natural number greater than or equal to 1.

20. The transistor of claim 19, wherein, The semiconductor layer includes at least one compound selected from MoS2, MoSe2, WS2, WSe2, MoTe2, WTe2, ZrS2, ZrSe2, ZrTe2, ReS2, ReSe2 and ReTe2.

21. A method for manufacturing a semiconductor layer, wherein, The method includes: Preparation of a substrate including silicon; An insulating layer comprising silicon oxide is formed on the substrate; A metal layer is formed on the insulating layer; Pattern the metal layer to form a metal mask with opening regions; An oxygen plasma process is performed on the metal mask, wherein the oxygen plasma process forms a first region of the insulating layer exposed by the opening area of ​​the metal mask during the execution of the oxygen plasma process, and a second region of the insulating layer covered by the metal mask during the execution of the oxygen plasma process; and The semiconductor layer is formed on the first region. The first region is hydrophilic, and the second region is hydrophobic.

22. The method according to claim 21, wherein, The first region has a higher surface energy than the second region.

23. The method according to claim 21, wherein, The semiconductor layer is formed on the first region by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or sputtering.

24. The method according to claim 21, wherein: The first region has a contact angle in the range of 5 degrees or less; and The second region has a contact angle in the range of 30 to 60 degrees.

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