High-throughput through hole defect detection system and method

Abstract

The invention provides a high-flux through hole defect detection system and method. The system comprises a wafer bearing unit, a gas supply unit and a piezoelectric array detection unit, the wafer bearing unit is used for bearing a wafer to be tested, and a plurality of through silicon vias are formed in the wafer to be tested; the gas supply unit is used for providing gas flow for the first surface of the wafer to be tested and enabling the gas flow to pass through the silicon through hole; and the piezoelectric array detection unit is located below the wafer bearing unit and is used for sensing airflow penetrating through the through silicon vias and judging whether the through silicon vias in the corresponding area of the wafer to be detected are through or not. According to the scheme, detection is directly carried out after the through hole etching process, and the detection result can be fed back in real time to adjust the TSV process; the detection airflow can cover the whole surface area of the wafer, and the test result of global detection is more comprehensive and objective; the test system is simple, the test process is convenient, and high-throughput and low-cost detection covering through holes of multiple sizes can be realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high-throughput via defect detection system and method. Background Technology

[0002] Through-Silicon Via (TSV) technology is a core technology for 3D integration and 2.5D packaging. It enables electrical interconnection between chips by creating vertically conductive vias on a silicon wafer. Current TSV processes are still immature and various defects may arise during fabrication. With the rapid development of advanced packaging technologies such as 3D ICs and high-bandwidth memory (HBM), TSV inspection technology has become particularly crucial.

[0003] TSV (Through Silicon Via) processes typically involve two steps: the formation of silicon vias and the filling of conductive materials (such as copper, tungsten, or polysilicon). Ensuring complete conductivity of the silicon vias is fundamental to achieving high-performance TSVs. However, current technologies lack effective methods for detecting the structural integrity of silicon vias, and existing via detection methods suffer from several problems. Firstly, current detection processes are usually performed after the conductive material is filled, relying on subsequent electrical measurements to determine if the via is fully open. However, electrical testing is slow, costly, and cannot achieve high-throughput testing. Furthermore, electrical testing is a delayed detection method, meaning that even if a via process problem is discovered at this stage, it cannot be remedied. Secondly, existing detection methods often employ sampling and localized inspection, making it difficult to cover large areas of vias. Additionally, different via sizes place different demands on testing equipment, increasing overall costs. While existing technologies offer methods for acquiring via morphology and obtaining clear images, these methods are inefficient and require expensive equipment, limiting their application to laboratory testing and preventing high-throughput, low-cost detection of multiple via sizes in mass-produced wafers.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] The purpose of this invention is to provide a high-throughput through-hole defect detection system and method to achieve high-throughput, low-cost detection covering through-holes of multiple sizes.

[0006] To address the aforementioned issues, in a first aspect, a high-throughput via defect detection system is provided, comprising a wafer carrier unit, a gas supply unit, and a piezoelectric array detection unit; The wafer carrier unit is used to carry the wafer under test, and the wafer under test has multiple through-silicon vias formed therein; The gas supply unit is used to provide airflow to the first surface of the wafer under test and to allow the airflow to pass through the through-silicon via. The piezoelectric array detection unit is located below the wafer carrier unit and is used to sense the airflow passing through the through-silicon via (TSV) and determine whether the TSV in the corresponding area of ​​the wafer under test is penetrated.

[0007] This application performs testing immediately after the via etching process, which is a non-hysteresis testing method. The test results can be fed back in real time to adjust the TSV process. Through airflow testing, it can cover the entire surface area of ​​each wafer, which is a global test rather than a local test, and the test results are more comprehensive and objective. The test system is simple and the test process is convenient, which can achieve high throughput and low cost testing covering vias of multiple sizes.

[0008] The piezoelectric array detection unit includes a piezoelectric sensor array; the piezoelectric sensor array is formed by arranging multiple piezoelectric sensors in an array, and the piezoelectric sensors are used to sense the airflow passing through the through-silicon via and convert the pressure generated by the airflow into an electrical signal.

[0009] The piezoelectric array detection unit further includes a signal analysis module, which comprises a signal amplification module, an analog-to-digital conversion module, and a data processing module connected in sequence. The signal amplification module is used to receive and amplify the electrical signal. The analog-to-digital conversion module is used to convert the amplified electrical signal into a digital signal. The data processing module is used to analyze the digital signal to determine whether the through-silicon via (TSV) in the corresponding region of the wafer under test is through.

[0010] In the piezoelectric sensor array, the size of the piezoelectric sensor is smaller than the size of the through-silicon via (TSV), and each TSV corresponds to multiple piezoelectric sensors. This improves the accuracy of test results and allows for adaptation to different TSV sizes.

[0011] When the piezoelectric sensor generates the electrical signal under the action of the airflow, the through-silicon via in the corresponding region of the wafer under test is considered to be a through-silicon via.

[0012] The wafer carrier unit includes a height adjustment device and a wafer carrier section connected together; the wafer carrier section is used to carry the wafer under test; the height adjustment device is used to adjust the vertical distance between the wafer under test and the piezoelectric array detection unit.

[0013] An opening structure is formed on the wafer carrier; the opening structure is used to expose the second surface corresponding to the test area of ​​the wafer under test; the test area is the area in the wafer under test in which the through-silicon via is formed.

[0014] The gas supply unit is a nitrogen supply unit or a compressed air supply unit; the gas supply unit also includes a pressure regulating unit and a flow regulating unit, used to regulate the pressure and flow rate of the gas flow accordingly.

[0015] On the other hand, this application also provides a high-throughput through-hole defect detection method, including: S1. Provide a wafer to be tested, wherein a plurality of through-silicon vias are formed in the wafer to be tested; S2. Provide a piezoelectric sensor array such that the wafer under test is positioned above the piezoelectric sensor array; S3. Provide an airflow to the first surface of the wafer under test, so that the airflow passes through the through-silicon via and acts on the piezoelectric sensor array; S4. Collect and analyze the electrical signals generated by the piezoelectric sensor array, and determine whether the through-silicon via in the corresponding region of the wafer under test is penetrated based on the electrical signals.

[0016] In steps S3 to S4, a periodically varying airflow is provided to sweep the first surface of the wafer under test, so that the piezoelectric sensor array generates an alternating electrical signal accordingly, and the through-silicon via in the corresponding region of the wafer under test is determined based on the alternating electrical signal.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) The detection is performed directly after the via etching process, which is a non-hysteresis detection, and the detection results can be fed back in real time to adjust the TSV process; 2) The test area can cover the entire surface area of ​​each wafer, and the test results of global detection are more comprehensive and objective; 3) The test system is simple and the test process is convenient, which can achieve high throughput and low cost detection covering multiple sizes of vias. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a high-throughput through-hole defect detection system provided by the present invention.

[0020] Figure 2 This is a schematic diagram of a high-throughput through-hole defect detection process provided by the present invention. Detailed Implementation

[0021] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0022] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0023] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0024] Example 1 like Figure 1 The diagram shown is a schematic diagram of a high-throughput through-hole defect detection system provided in an embodiment of the present invention.

[0025] refer to Figure 1 The present invention provides a high-throughput through-hole defect detection system, including a wafer carrier unit 3, a gas supply unit 2 and a piezoelectric array detection unit 1.

[0026] The wafer carrier unit 3 is used to support the wafer under test 4, which has multiple through-silicon vias (TSVs). The wafer carrier unit 3 can mount the wafer under test 4 and adjust its position to cooperate with the gas supply unit 2 and the piezoelectric array detection unit 1 to complete the detection. It is understood that the wafer carrier unit 3 is not necessarily limited to a single, independent structure; it can be any part of the system capable of supporting the wafer under test 4.

[0027] It can be understood that wafer 4 under test refers to the wafer that has just completed through-silicon via (TSV) etching, meaning that wafer 4 under test contains multiple TSVs. Specifically, wafer 4 under test has two opposing surfaces, namely the first surface and the second surface (also generally referred to as the surface and bottom surface). Normally, TSVs penetrate wafer 4 under test (i.e., TSVs penetrate both the first and second surfaces). However, due to limitations of existing TSV processes, not all TSVs in wafer 4 under test are completely etched through; some TSVs may not be etched through. Therefore, there are two types of TSVs in wafer 4 under test: through-silicon vias 40 and non-through-silicon vias 41. It can be understood that the non-through-silicon vias 41 are the via defects that this solution aims to identify.

[0028] Gas supply unit 2 is used to provide airflow to the first surface of wafer 4 under test and to allow the airflow to pass through the through-silicon via; piezoelectric array detection unit 1, located below wafer carrier unit 3, is used to sense the airflow passing through the through-silicon via and to determine whether the through-silicon via in the corresponding area of ​​wafer 4 under test is penetrated.

[0029] For specific details, please refer to the following references. Figure 1 and Figure 2 As shown in the figure, a high-pressure gas flow is supplied to the wafer under test 4 through the gas supply unit 2. When a through-silicon via (TSV) 40 exists in a certain area of ​​the wafer under test 4, the gas flow will pass through the TSV 40 and reach the piezoelectric array detection unit 1 below the wafer under test 4. The piezoelectric array detection unit 1 will generate an electrical signal under the action of the gas flow, so it can be considered that the TSV in the corresponding area on the wafer under test 4 is through-silicon via. Similarly, since the positions of all TSVs in the wafer under test 4 are known, when the piezoelectric array detection unit 1 corresponding to certain TSV areas does not generate an electrical signal, it indicates that the TSV in this area of ​​the wafer under test 4 is a non-through-silicon via 41. That is, this scheme detects the gas flow passing through the TSV through the piezoelectric array detection unit 1 below the wafer under test 4. The area that senses the gas flow will generate an electrical signal, indicating that there is a corresponding through-silicon via 40, otherwise it is a non-through-silicon via 41.

[0030] Continue to refer to Figure 1 In this embodiment, the piezoelectric array detection unit 1 includes a piezoelectric sensor array 10 and a signal analysis module 11. The piezoelectric sensor array 10 is formed by arranging multiple piezoelectric sensors 100 in an array. The piezoelectric sensors 100 are used to sense the airflow passing through the through-silicon via and convert the pressure generated by the airflow into an electrical signal. The signal analysis module 11 is used to receive and analyze the electrical signal generated by the piezoelectric sensor array 10 and determine whether the through-silicon via in the corresponding area of ​​the wafer 4 under test is penetrated based on the electrical signal.

[0031] Specifically, in this embodiment, the signal analysis module 11 includes a signal amplification module, an analog-to-digital conversion module, and a data processing module connected in sequence; wherein, the signal amplification module is used to receive and amplify electrical signals; the analog-to-digital conversion module is used to convert the amplified electrical signals into digital signals; and the data processing module is used to analyze the digital signals to determine whether the through-silicon vias in the corresponding area of ​​the wafer 4 under test are penetrated.

[0032] It is understood that in this embodiment, the piezoelectric sensor 100, signal amplification module, analog-to-digital conversion module, and data processing module can all be implemented using existing technologies, and will not be elaborated further here.

[0033] It is understood that in this embodiment, the piezoelectric array detection unit 1 includes a piezoelectric sensor array 10 and a signal analysis module 11. In other embodiments, the piezoelectric array detection unit 1 may only include the piezoelectric sensor array 10, and then a separate signal analysis module 11 may be provided to receive and analyze the electrical signals generated by the piezoelectric sensor array 10.

[0034] Please continue to refer to the reference. Figure 1 and Figure 2 As shown, in order to ensure that the airflow passing through the through-silicon via (TSV) is sensed and captured by the piezoelectric sensor array 10 as much as possible and to reduce measurement errors, in this embodiment, the size of the piezoelectric sensor 100 in the piezoelectric sensor array 10 is smaller than the size of the TSV (i.e., the projected area of ​​the piezoelectric sensor 100 in the piezoelectric sensor array 10 is smaller than the projected area of ​​the TSV in the piezoelectric sensor array 10), and its arrangement density is extremely high, so as to fully ensure that each TSV can correspond to multiple piezoelectric sensors 100. In this way, not only can the missed detection be reduced (each TSV corresponds to multiple piezoelectric sensors 100, and the data of multiple piezoelectric sensors 100 can be combined to comprehensively determine whether it is through), but it can also adapt to different TSV sizes (the size of the piezoelectric sensor 100 is very small, and when detecting TSVs of different sizes, only the number of piezoelectric sensors 100 corresponding to each TSV is changed. Only the setting parameters need to be adjusted, and the device itself does not need to be changed).

[0035] In this embodiment, the wafer carrier unit 3 includes a height adjustment device 30 and a wafer carrier portion 31 connected to each other. The wafer carrier portion 31 carries the wafer under test 4. An opening structure is formed on the wafer carrier portion 31 to expose the second surface corresponding to the test area of ​​the wafer under test 4. It can be understood that the test area is the area in the wafer under test 4 where through-silicon vias (TSVs) are formed. The height adjustment device 30 is used to adjust the vertical distance between the wafer under test 4 and the piezoelectric array detection unit 1 below. Depending on the size and depth of the TSVs in the wafer under test 4, the wafer under test 4 and the piezoelectric sensor array 10 can be in contact or non-contact configuration. In this embodiment, a non-contact design is adopted, and the distance between them can be at the micrometer to millimeter level.

[0036] It is understood that the main purpose of the wafer carrier unit 3 is to position the wafer under test 4 at a suitable location (which can be called the test position) on the piezoelectric array detection unit 1. Therefore, this application does not impose many restrictions on the structure of the wafer carrier unit 3, as long as the above-mentioned function can be achieved. That is, the wafer carrier unit 3 can be implemented using various existing clamping and carrying mechanisms. For example, in some embodiments, the wafer carrier unit 3 can be a clamping wafer carrier unit 3, which clamps the wafer under test 4 with a suitable clamping component, so that the wafer under test 4 is positioned on the piezoelectric array detection unit 1 (which can be contact or non-contact).

[0037] It is understood that the wafer carrier unit 3 is not necessarily limited to an independent structure; it can be any part of the system capable of carrying the wafer under test 4. For example, in some embodiments, the wafer carrier unit 3 can also be a non-independent mechanism, such as a carrier structure formed within the piezoelectric array detection unit 1 (i.e., the wafer carrier unit 3 is a part of the piezoelectric array detection unit 1), thereby ensuring that the wafer under test 4 can be placed in a suitable testing position. Of course, in some embodiments, the wafer carrier unit 3 can also be a carrier structure formed within the gas supply unit 2 (i.e., the wafer carrier unit 3 is a part of the gas supply unit 2), so that the wafer under test 4 can be placed in a suitable testing position by adjusting the relative positions of the gas supply unit 2 and the piezoelectric array detection unit 1.

[0038] In this embodiment, the gas supply unit 2 is either a nitrogen supply unit or a compressed air supply unit, used to provide nitrogen or compressed air accordingly. Using compressed air is less expensive, while using nitrogen, although increasing costs, reduces potential contamination of the wafer 4 under test. The gas supply unit 2 also includes a pressure regulation unit and a flow rate regulation unit, used to regulate the pressure and flow rate of the gas flow. It is understood that for different wafers 4 under test (the size, thickness, structure, and the size and depth of the through-silicon vias on them can all be different), a suitable process window can be found by adjusting the pressure and flow rate of the gas flow to achieve the corresponding detection. It is understood that in this embodiment, the gas supply unit 2, as well as its pressure regulation unit and flow rate regulation unit, can all be implemented using existing technologies, and will not be elaborated upon here.

[0039] To adapt to different detection scenarios, the gas supply unit 2 can provide a constant airflow or a periodic airflow; similarly, the generated electrical signal can also be processed as a DC signal or an alternating signal (the AC or DC processing is selected according to the through-hole design and the sensitivity of the electrical signal).

[0040] Example 2 The present invention also provides a high-throughput through-hole defect detection method, comprising the following steps: S1. Provide a wafer to be tested, wherein a plurality of through-silicon vias are formed in the wafer; S2. Provide a piezoelectric sensor array so that the wafer under test is positioned above the piezoelectric sensor array; S3. Provide airflow to the first surface of the wafer under test, allowing the airflow to pass through the through-silicon via and act on the piezoelectric sensor array; S4. Collect and analyze the electrical signals generated by the piezoelectric sensor array, and determine whether the through-silicon vias in the corresponding area of ​​the wafer under test are penetrated based on the electrical signals.

[0041] Furthermore, in steps S3 to S4, a periodically varying airflow is provided to sweep the first surface of the wafer under test, so that the piezoelectric sensor array generates an alternating electrical signal accordingly, and the through-silicon via (TSV) in the corresponding region of the wafer under test is determined based on the alternating electrical signal.

[0042] Example 3 The present invention also provides a high-throughput through-hole defect detection method, which can be performed based on the high-throughput through-hole defect detection system in Embodiment 1, and includes the following steps: S1. Provide a wafer to be tested, wherein a plurality of through-silicon vias are formed in the wafer; S2. Provide a piezoelectric sensor array so that the wafer under test is positioned above the piezoelectric sensor array; S3. Provide airflow to the first surface of the wafer under test, allowing the airflow to pass through the through-silicon via and act on the piezoelectric sensor array; S4. Collect and analyze the electrical signals generated by the piezoelectric sensor array, and determine whether the through-silicon vias in the corresponding area of ​​the wafer under test are penetrated based on the electrical signals.

[0043] Furthermore, in steps S3 to S4, a periodically varying airflow is provided to sweep the first surface of the wafer under test, so that the piezoelectric sensor array generates an alternating electrical signal accordingly, and the through-silicon via (TSV) in the corresponding region of the wafer under test is determined based on the alternating electrical signal.

[0044] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0045] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A high-throughput through-hole defect detection system, characterized in that, This includes a wafer carrier unit, a gas supply unit, and a piezoelectric array detection unit; The wafer carrier unit is used to carry the wafer under test, and the wafer under test has multiple through-silicon vias formed therein; The gas supply unit is used to provide airflow to the first surface of the wafer under test and to allow the airflow to pass through the through-silicon via. The piezoelectric array detection unit is located below the wafer carrier unit and is used to sense the airflow passing through the through-silicon via (TSV) and determine whether the TSV in the corresponding area of ​​the wafer under test is penetrated.

2. The high-throughput through-hole defect detection system according to claim 1, characterized in that, The piezoelectric array detection unit includes a piezoelectric sensor array; The piezoelectric sensor array is formed by arranging multiple piezoelectric sensors in an array. The piezoelectric sensors are used to sense the airflow passing through the through-silicon via and convert the pressure generated by the airflow into an electrical signal.

3. The high-throughput through-hole defect detection system according to claim 2, characterized in that, The piezoelectric array detection unit also includes a signal analysis module, which includes a signal amplification module, an analog-to-digital conversion module, and a data processing module connected in sequence. The signal amplification module is used to receive and amplify the electrical signal; The analog-to-digital converter module is used to convert the amplified electrical signal into a digital signal; The data processing module is used to analyze the digital signal to determine whether the through-silicon via (TSV) in the corresponding region of the wafer under test is penetrated.

4. The high-throughput through-hole defect detection system according to claim 2, characterized in that, In the piezoelectric sensor array, the size of the piezoelectric sensor is smaller than the size of the through-silicon via, and each through-silicon via corresponds to multiple piezoelectric sensors.

5. The high-throughput through-hole defect detection system according to claim 2, characterized in that, When the piezoelectric sensor generates the electrical signal under the action of the airflow, the through-silicon via in the corresponding region of the wafer under test is considered to be a through-silicon via.

6. The high-throughput through-hole defect detection system according to claim 1, characterized in that, The wafer carrier unit includes a height adjustment device and a wafer carrier section connected together; The wafer carrier is used to carry the wafer to be tested; The height adjustment device is used to adjust the vertical distance between the wafer under test and the piezoelectric array detection unit.

7. The high-throughput through-hole defect detection system according to claim 6, characterized in that, An opening structure is formed on the wafer carrier portion; The opening structure is used to expose the second surface corresponding to the test area of ​​the wafer under test; The test area is the region in the wafer under test where the through-silicon via is formed.

8. The high-throughput through-hole defect detection system according to claim 1, characterized in that, The gas supply unit is a nitrogen supply unit or a compressed air supply unit; The gas supply unit further includes a pressure regulating unit and a flow regulating unit, which are used to regulate the pressure and flow rate of the gas flow accordingly.

9. A high-throughput through-hole defect detection method, characterized in that, include: S1. Provide a wafer to be tested, wherein a plurality of through-silicon vias are formed in the wafer to be tested; S2. Provide a piezoelectric sensor array such that the wafer under test is positioned above the piezoelectric sensor array; S3. Provide an airflow to the first surface of the wafer under test, so that the airflow passes through the through-silicon via and acts on the piezoelectric sensor array; S4. Collect and analyze the electrical signals generated by the piezoelectric sensor array, and determine whether the through-silicon via in the corresponding region of the wafer under test is penetrated based on the electrical signals.

10. The high-throughput through-hole defect detection method according to claim 9, characterized in that, In steps S3 to S4, a periodically varying airflow is provided to sweep the first surface of the wafer under test, so that the piezoelectric sensor array generates an alternating electrical signal accordingly, and the through-silicon via in the corresponding region of the wafer under test is determined based on the alternating electrical signal.

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