IGBT chip and preparation method thereof

Abstract

The invention discloses an IGBT (Insulated Gate Bipolar Translator) chip and a preparation method thereof. The method comprises the following steps: depositing an oxide layer on an epitaxial layer as a barrier layer; etching a terminal structure; a groove structure is formed through photoetching, and the distance between adjacent grooves located at the edge position of the chip is gradually increased in equal proportion along with the increase of the distance between the grooves and the center position of the chip; depositing polycrystalline silicon, and completely filling the inside of the groove with the polycrystalline silicon; performing polycrystalline etching to enable a polycrystalline silicon interface to be slightly lower than the top of the groove; photoetching a source region to form an N + region and a P + region; forming an isolation dielectric layer on the barrier layer by adopting a CVD (Chemical Vapor Deposition) deposition mode; carrying out photoetching trepanning on the isolation dielectric layer, and enabling the hole pitch formed by photoetching trepanning to be consistent with the groove pitch; according to the IGBT chip, the negative influence of the edge effect on the performance of the IGBT chip can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to an IGBT chip and its fabrication method. Background Technology

[0002] IGBT chips, also known as insulated-gate bipolar transistors, are composite, fully controllable, voltage-driven power semiconductor devices composed of a bipolar junction transistor (BJT) and an insulated-gate field-effect transistor (GFET). They combine the advantages of high input impedance of MOSFETs and low on-state voltage drop of GFETs. In traditional IGBT chips, when current flows through the corners, the current density concentrates at those corners due to obstruction and reflection, resulting in increased current density. This phenomenon, known as the edge effect, causes uneven heating of the IGBT chip, reducing reliability. Therefore, developing a new IGBT chip fabrication method to overcome these problems in existing technologies is a direction that requires further research in this field. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating IGBT chips that can effectively reduce the edge effects of the fabricated IGBT chips.

[0004] This invention discloses a method for fabricating an IGBT chip, which includes the following steps:

[0005] Step 100: Deposit an oxide layer on the epitaxial layer as a barrier layer;

[0006] Step 200: Etch the terminal structure on the barrier layer;

[0007] Step 300: A trench structure is formed on the barrier layer by photolithography. The trench structure includes: trenches located at the center of the chip are arranged at equal intervals, and trenches located at the edge of the chip are arranged in a manner in which the spacing between adjacent trenches increases proportionally with the distance of the trenches from the center of the chip.

[0008] Step 400: Deposit polysilicon on the barrier layer to completely fill the interior of the trench;

[0009] Step 500: Perform polysilicon etching so that the polysilicon interface is slightly lower than the top of the trench;

[0010] Step 600: Source region photolithography, forming N+ and P+ regions on the barrier layer;

[0011] Step 700: An isolation dielectric layer is formed on the barrier layer by CVD deposition;

[0012] Step 800: Perform photolithography to create holes in the isolation dielectric layer, ensuring that the hole spacing formed by the photolithographically created holes is consistent with the trench spacing.

[0013] Step 900: Deposit a metal layer on the isolation dielectric layer and etch out the source and gate.

[0014] Preferably, in the above IGBT chip fabrication method, step 100 includes:

[0015] A silicon wafer is selected as the epitaxial layer, and an oxide layer with a thickness of 5KÅ-7KÅ is deposited on the silicon wafer as a barrier layer.

[0016] Preferably, in the above IGBT chip fabrication method, step 300 includes:

[0017] Photoresist is coated on the silicon wafer, and after exposure, the trench structure is etched using a dry etching method. The trench structure includes: N trenches on the chip that are farthest from the chip center, and the spacing between adjacent trenches increases by a times as the distance between the trenches and the chip center increases; the spacing between adjacent trenches of the remaining trenches on the chip is the same; the value of N is in the range of 10 to 20; the value of a is in the range of 1.03 to 1.06.

[0018] Preferably, in the above IGBT chip fabrication method, step 300 includes:

[0019] A gate oxide layer is formed inside the trench using a thermal oxidation process.

[0020] Preferably, in the above IGBT chip fabrication method, step 400 includes:

[0021] Polysilicon is deposited to completely fill the interior of the trench; excess polysilicon on the surface is removed by dry etching, so that the polysilicon interface is slightly lower than the top of the trench.

[0022] The present invention also discloses an IGBT chip, which is fabricated using any of the IGBT chip fabrication methods described above.

[0023] Compared with existing technologies, the present invention can significantly reduce the current density at the edge of the IGBT chip, thus effectively reducing the negative impact of edge effects on the performance of the IGBT chip. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the chip structure formed in step 100 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0025] Figure 2This is a schematic diagram of the chip structure formed in step 200 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0026] Figure 3 This is a schematic diagram of the chip structure formed in step 300 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0027] Figure 4 This is a schematic diagram of the chip structure formed in step 400 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0028] Figure 5 This is a schematic diagram of the chip structure formed in step 500 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0029] Figure 6 This is a schematic diagram of the chip structure formed in step 600 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0030] Figure 7 This is a schematic diagram of the chip structure formed in step 700 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0031] Figure 8 This is a schematic diagram of the chip structure formed in step 800 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0032] Figure 9 This is a schematic diagram of the chip structure formed in step 900 of Example 1. The left end of the diagram is the center position of the chip, and the right end is the edge position of the chip.

[0033] Figure 10 The current simulation diagram is for existing similar products.

[0034] Figure 11 This is a current simulation diagram for Example 1.

[0035] Figure 12 This is a current density detection graph for existing similar products.

[0036] Figure 13 This is a current density detection graph from Example 1.

[0037] Figure 14 This is the current density detection graph for Example 2.

[0038] Figure 15 This is the current density detection graph for Example 3.

[0039] The component names corresponding to the various reference numerals in the figure are as follows:

[0040] 110, P+ layer; 120, N+ buffer layer; 130, N-epi layer; 210, barrier layer; 220, termination structure; 230, trench; 240, polysilicon; 310, N+ region; 320, P+ region; 400, isolation dielectric layer; 410, dielectric layer opening; 500, metal layer. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Example 1, please refer to Figure 1-9 :

[0043] The chip fabrication method for a 1200V-100AIGBT includes the following steps:

[0044] Step 100: Select a silicon wafer with a resistivity of 65 ohm·cm as the epitaxial layer, and deposit an oxide layer with a thickness of 6 kÅ on the epitaxial layer as a barrier layer 210.

[0045] Step 200: Etch terminal structure 220 on the barrier layer 210;

[0046] Step 300: Photoresist is coated on the silicon wafer, and after exposure, the trench 230 structure with a depth of 5 μm is etched using a dry etching method. The trench 230 structure includes: the 20 trenches 230 furthest from the chip center on the chip, and the spacing between adjacent trenches 230 increases by a factor of 1.05 as the distance of the trench 230 from the chip center increases; the spacing between adjacent trenches of the remaining trenches 230 on the chip is the same; that is, the spacing between the trench 230 furthest from the chip center and the second furthest from the chip center is the same as the spacing between the second furthest from the chip center and the third furthest from the chip center. The spacing of the furthest trench 230 is 1.05 times the distance between the two furthest trenches from the chip center; the spacing between the second furthest trench 230 and the third furthest trench 230 from the chip center is 1.05 times the distance between the third furthest trench 230 and the fourth furthest trench 230 from the chip center... and so on, the spacing between the nineteenth furthest trench 230 and the twentieth furthest trench 230 from the chip center is 1.05 times the distance between the twentieth furthest trench 230 and the twenty-first furthest trench 230 from the chip center; while the spacing of all other trenches 230 on the chip is the same.

[0047] Step 400: A gate oxide layer with a thickness of 1 kÅ is formed inside each trench 230 using a thermal oxidation process, and polysilicon 240 is deposited on the barrier layer 210 to completely fill the interior of the trench 230 with polysilicon 240.

[0048] Step 500: Perform polysilicon etching: Use dry etching to remove excess polysilicon 240, so that the interface of polysilicon 240 is slightly lower than the top of trench 230;

[0049] Step 600: Source region photolithography: As1E15 and B1E14 are implanted on the barrier layer 210 to form N+ and P+ regions respectively;

[0050] Step 700: A 1µm thick isolation dielectric layer 400 is deposited on the barrier layer 210 using CVD deposition; in this example, the isolation dielectric layer 400 is a BPSG layer.

[0051] Step 800: Perform photolithography to create holes in the isolation dielectric layer 400, and ensure that the spacing between the holes formed by the photolithography is consistent with the spacing between the trenches 230;

[0052] Step 900: Deposit a metal layer 500 on the isolation dielectric layer 400. In this example, the metal layer 500 is an aluminum layer. Finally, etch out the source and gate.

[0053] Example 2:

[0054] The chip fabrication method for a 1200V-100AIGBT includes the following steps:

[0055] Step 100: Select a silicon wafer with a resistivity of 65 ohm·cm as the epitaxial layer, and deposit an oxide layer with a thickness of 6 kÅ on the epitaxial layer as a barrier layer;

[0056] Step 200: Etch the terminal structure on the barrier layer;

[0057] Step 300: Coat the silicon wafer with photoresist, and after exposure, use dry etching to create the trench structure with a depth of 5µm. The trench structure includes: the 15 trenches furthest from the chip center, with the spacing between adjacent trenches increasing by a factor of 1.03 as the trench distance from the chip center increases; the spacing between adjacent trenches of the remaining trenches on the chip is the same; that is, the distance between the trench furthest from the chip center and the second furthest trench from the chip center is equal to the distance between the second furthest trench from the chip center and the trench furthest from the chip center. The spacing between the three furthest trenches is 1.03 times the distance between the two furthest trenches from the chip center; the spacing between the two furthest trenches from the chip center is 1.03 times the distance between the two furthest trenches from the chip center, and so on. The spacing between the two furthest trenches from the chip center is 1.03 times the distance between the two furthest trenches from the chip center, and so on. The spacing between the three furthest trenches from the chip center is 1.03 times the distance between the two furthest trenches from the chip center, and so on. The spacing between all other trenches on the chip is the same.

[0058] Step 400: A 1 kÅ thick gate oxide layer is formed inside each trench using a thermal oxidation process, and polysilicon is deposited on the barrier layer to completely fill the inside of the trench with polysilicon;

[0059] Step 500: Perform polysilicon etching: Use dry etching to remove excess polysilicon, so that the polysilicon interface is slightly lower than the top of the trench;

[0060] Step 600: Source region photolithography: As1E15 and B1E14 are implanted on the barrier layer to form N+ and P+ regions respectively;

[0061] Step 700: A 1µm thick isolation dielectric layer is deposited on the barrier layer using CVD deposition; in this example, the isolation dielectric layer is a BPSG layer.

[0062] Step 800: Perform photolithography to create holes in the isolation dielectric layer, ensuring that the hole spacing formed by the photolithographically created holes is consistent with the trench spacing.

[0063] Step 900: Deposit a metal layer on the isolation dielectric layer, in this example the metal layer is an aluminum layer; finally etch out the source and gate.

[0064] Example 3:

[0065] The chip fabrication method for a 1200V-100AIGBT includes the following steps:

[0066] Step 100: Select a silicon wafer with a resistivity of 65 ohm·cm as the epitaxial layer, and deposit an oxide layer with a thickness of 6 kÅ on the epitaxial layer as a barrier layer;

[0067] Step 200: Etch the terminal structure on the barrier layer;

[0068] Step 300: Coat the silicon wafer with photoresist, and after exposure, use dry etching to create the trench structure with a depth of 5µm. The trench structure includes: the 10 trenches furthest from the chip center, with the spacing between adjacent trenches increasing by a factor of 1.06 as the trench distance from the chip center increases; the spacing between adjacent trenches of the remaining trenches on the chip is the same; that is, the distance between the trench furthest from the chip center and the second furthest trench from the chip center is equal to the distance between the second furthest trench from the chip center and the trench furthest from the chip center. The spacing between the three furthest trenches is 1.06 times the distance between the two furthest trenches from the chip center; the spacing between the two furthest trenches from the chip center is 1.06 times the distance between the two furthest trenches from the chip center, and so on. The spacing between the two furthest trenches from the chip center is 1.06 times the distance between the two furthest trenches from the chip center, and so on. The spacing between the three furthest trenches from the chip center is 1.06 times the distance between the two furthest trenches from the chip center, and so on. The spacing between all other trenches on the chip is the same.

[0069] Step 400: A 1 kÅ thick gate oxide layer is formed inside each trench using a thermal oxidation process, and polysilicon is deposited on the barrier layer to completely fill the inside of the trench with polysilicon;

[0070] Step 500: Perform polysilicon etching: Use dry etching to remove excess polysilicon, so that the polysilicon interface is slightly lower than the top of the trench;

[0071] Step 600: Source region photolithography: As1E15 and B1E14 are implanted on the barrier layer to form N+ and P+ regions respectively;

[0072] Step 700: A 1µm thick isolation dielectric layer is deposited on the barrier layer using CVD deposition; in this example, the isolation dielectric layer is a BPSG layer.

[0073] Step 800: Perform photolithography to create holes in the isolation dielectric layer, ensuring that the hole spacing formed by the photolithographically created holes is consistent with the trench spacing.

[0074] Step 900: Deposit a metal layer on the isolation dielectric layer, in this example the metal layer is an aluminum layer; finally etch out the source and gate.

[0075] Comparative sample: A 1200V-100AIGBT chip of the same size fabricated using existing processes.

[0076] Experimental Comparison: Simulation experiments were conducted on the IGBT chip obtained in Example 1 and the chip of the comparison sample, respectively. Please refer to [reference needed for comparison of simulation results]. Figures 10-11 ,based on Figure 10-11 We can see that the chip in the comparison sample has the highest current density at the chip edge. However, the improved chip in Example 1 has a significantly lower current density at the chip edge.

[0077] Current density measurements were performed on the IGBT chips obtained in Examples 1-3 and the chips of the comparative sample, respectively. For a comparison of the current density measurement results, please refer to [reference needed]. Figures 12-15 At the same time, based on Figure 12-15 We can see that the chip in the comparison sample has a large current spike at the edge, while the chips in Examples 1-3 do not have a corresponding large current spike at the edge. Therefore, the IGBT chips constructed in Examples 1-3 effectively reduce the negative impact of edge effects on the performance of IGBT chips compared to existing similar products.

[0078] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating an IGBT chip, characterized in that, Includes the following steps: Step 100: Deposit an oxide layer on the epitaxial layer as a barrier layer; Step 200: Etch the terminal structure on the barrier layer; Step 300: A trench structure is formed on the barrier layer by photolithography. The trench structure includes: trenches located at the center of the chip are arranged at equal intervals, and trenches located at the edge of the chip are arranged in a manner in which the spacing between adjacent trenches increases proportionally with the distance of the trenches from the center of the chip. Step 400: Deposit polysilicon on the barrier layer to completely fill the interior of the trench; Step 500: Perform polysilicon etching so that the polysilicon interface is slightly lower than the top of the trench; Step 600: Source region photolithography, forming N+ and P+ regions on the barrier layer; Step 700: An isolation dielectric layer is formed on the barrier layer by CVD deposition; Step 800: Perform photolithography to create holes in the isolation dielectric layer, ensuring that the hole spacing formed by the photolithographically created holes is consistent with the trench spacing. Step 900: Deposit a metal layer on the isolation dielectric layer and etch out the source and gate.

2. The IGBT chip fabrication method according to claim 1, characterized in that, Step 100 includes: A silicon wafer is selected as the epitaxial layer, and an oxide layer with a thickness of 5KÅ-7KÅ is deposited on the silicon wafer as a barrier layer.

3. The IGBT chip fabrication method according to claim 2, characterized in that, Step 300 includes: Photoresist is coated on the silicon wafer, and after exposure, the trench structure is etched using a dry etching method. The trench structure includes: N trenches on the chip that are farthest from the chip center, and the spacing between adjacent trenches increases by a times as the distance between the trenches and the chip center increases; the spacing between adjacent trenches of the remaining trenches on the chip is the same; the value of N is in the range of 10 to 20; the value of a is in the range of 1.03 to 1.

06.

4. The IGBT chip fabrication method according to claim 3, characterized in that, Step 300 includes: forming a gate oxide layer inside the trench using a thermal oxidation process.

5. The IGBT chip fabrication method according to claim 4, characterized in that, Step 400 includes: depositing polysilicon to completely fill the interior of the trench with polysilicon; and using dry etching to remove excess polysilicon from the surface layer so that the polysilicon interface is slightly lower than the top of the trench.

6. An IGBT chip, characterized in that: It is prepared by the IGBT chip preparation method according to any one of claims 1-5.

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