Semiconductor device capacitor voltage test system and method

Abstract

The invention belongs to the technical field of electronic measurement, and discloses a system and a method for testing capacitor voltage of a semiconductor device. Through the power supply circuit based on combination of high-frequency PWM boost and a symmetric topology voltage-multiplying chain, the bottleneck problem that the existing portable equipment is difficult to efficiently generate a wide-range symmetric bipolar high-voltage bias power supply in a compact volume is solved; according to the differential pulse breadth measurement circuit based on alternating current and direct current isolation, measurement pulses with opposite phases are injected and differential sampling is carried out, so that the problem of low reliability in a field environment due to the fact that an existing single-end measurement method is extremely sensitive to common-mode noise and ground wire interference is solved, and the measurement precision and stability are improved; a software time sequence control method based on dynamic output baseline correction is provided, each bias point is achieved through an intelligent sequence of stabilization-output baseline evaluation-measurement-compensation, and the slow response phenomenon existing in an existing method is solved.

Description

Technical Field

[0001] This invention belongs to the field of electronic measurement technology, and in particular relates to a semiconductor device capacitance-voltage (CV) testing system and method, which is applicable to the characterization of the electrical properties of semiconductor devices and materials. Background Technology

[0002] Capacitance-voltage (CV) testing is a fundamental and crucial analytical method for characterizing the physical properties of semiconductor devices and materials. By precisely measuring how the capacitance of a device (such as a MOS capacitor or transistor structure) changes with a DC bias voltage applied across its terminals, a series of key physical and electrical parameters, such as semiconductor doping type and concentration distribution, oxide layer thickness, flat-band voltage, threshold voltage, and semiconductor-insulator interface trap state density, can be extracted non-destructively. Therefore, CV testing plays an indispensable role in semiconductor process development and monitoring, device reliability assessment and failure analysis, and the research of novel electronic materials, and has long been highly valued by both academia and industry.

[0003] Currently, high-precision CV testing tasks remain largely confined to specialized laboratory environments, heavily reliant on large, complex benchtop semiconductor parameter analyzers manufactured by leading international instrument manufacturers such as Keysight and Keithley. While these devices offer superior performance, their bulky size, high cost, and complex operation make them unsuitable for the growing demand for portable applications, such as rapid in-situ process control and quality monitoring on semiconductor production lines, or timely fault diagnosis and failure analysis at the equipment site. Therefore, developing a truly portable CV testing system that integrates a wide-range high-voltage bias source with high-precision capacitance measurement capabilities has become a pressing and valuable technological direction in this field.

[0004] Despite academic exploration and prototype design of portable CV systems both domestically and internationally in recent years, no mature commercial product has yet emerged that fully meets the needs of industrial applications. To overcome the limitations of traditional AC LCR bridges in terms of integration and cost, some cutting-edge technologies are shifting towards measurement methods based on pulse charging timing. The core principle is to apply a small voltage step pulse to the capacitor under test based on a known DC bias voltage, and then accurately measure the time required for the capacitor to charge from the step-start voltage to a preset threshold voltage, thus deducing the capacitance value. However, to fully and reliably implement this technology in a portable system, the following three interrelated core technical challenges remain:

[0005] First, generating and ensuring the symmetry of high-voltage bias is a key challenge. Complete device characterization often requires bipolar bias voltages of tens or even hundreds of volts (e.g., ±90V) to explore its full characteristics in the depletion, inversion, and accumulation regions. In portable devices with strict size and power consumption constraints, traditional power frequency transformers are excluded due to their inherent bulkiness and inefficiency. While conventional DC boost circuits can efficiently generate positive high voltages, simultaneously generating a strictly symmetrical and performance-matched negative high voltage typically requires a separate and complex circuit, significantly increasing design complexity, cost, and size. This makes it difficult for existing solutions to economically and efficiently cover a wide range of bipolar bias requirements under miniaturization conditions.

[0006] Secondly, the measurement method has poor anti-interference capability. The equipment inevitably operates in complex electromagnetic environments such as factories and field sites. The traditional single-ended pulse timing scheme directly references the system ground in its measurement circuit, making it extremely sensitive to power supply noise, ground potential fluctuations, and common-mode interference from external coupling. Even microvolt-level noise disturbances can be amplified during the charging timing process, causing significant deviations in the measurement results and limiting its reliability and repeatability in real industrial environments.

[0007] Finally, precise characterization methods for slow physical processes remain lacking. Many key degradation mechanisms in semiconductor devices, such as the slow trapping effect in the insulating layer and the charge trapping and release processes at the semiconductor-insulator interface, typically have response time constants ranging from milliseconds to several seconds. If a fixed hardware timing sequence is used, the pulse charging timing method, which prioritizes measurement speed, is essentially a fast measurement. Its measurement time window (typically in the microsecond range) is much smaller than the response time of these slow processes, thus failing to provide sufficient response and equilibration time, resulting in an inability to accurately capture the true impact of these effects on device capacitance.

[0008] In general, the pulse charging timing method offers a new technical direction for overcoming the limitations of traditional AC measurement methods. However, existing designs are mostly based on simple single-ended injection comparator timing circuits. While these schemes are structurally simple, they suffer from systemic shortcomings in three core areas: high-voltage power generation, measurement interference immunity, and slow response process characterization. These challenges collectively result in the fact that a truly mature, fully functional portable high-voltage CV testing system has yet to be developed. Summary of the Invention

[0009] The purpose of this invention is to propose a semiconductor device capacitance voltage testing system. This system proposes a Boost-voltage doubler power supply circuit based on high-frequency switching conversion and a symmetrical topology voltage doubler chain to efficiently and compactly convert low-voltage DC input into a symmetrical ±90V high-voltage rail, thereby solving the bottleneck problem of traditional solutions in generating a wide-range, symmetrical bipolar bias power supply within a portable size. At the same time, by constructing a differential pulse width modulation measurement circuit, the measured capacitance value is converted into the pulse width of a differential square wave signal and finally demodulated into an analog voltage. From the hardware architecture perspective, common-mode noise and ground interference are suppressed, thereby solving the problem of low reliability and susceptibility to interference in field environments of existing single-ended measurement methods.

[0010] To achieve the above objectives, the present invention adopts the following technical solution: A semiconductor device capacitance voltage testing system includes a low-voltage power supply circuit, a Boost-voltage doubler power supply circuit, an MCU, a high-voltage bias control circuit, an AC / DC isolation circuit, and a differential pulse width modulation measurement circuit. The low-voltage power supply circuit provides the initial low-voltage power to the entire system; The Boost-voltage doubler power supply circuit is used to receive the low-voltage DC input from the low-voltage power supply circuit and generate a pair of stable, symmetrical and isolated high-voltage bipolar power rails as power rails for the high-voltage operational amplifier circuit. The high-voltage bias control circuit includes a signal processing circuit and a high-voltage operational amplifier circuit; The MCU outputs a low-voltage control signal through its built-in dual-channel DAC according to the preset scanning program; After the low-voltage control signal undergoes polarity conversion and buffering by the signal processing circuit, it is linearly amplified by the high-voltage operating discharge circuit, and the DC bias voltage from -90V to +90V is applied to the component under test (DUT) in differential form through the AC-DC isolation circuit. At each stable DC bias point, an AC measurement pulse is coupled to the DUT. The capacitance response of the DUT is captured by the differential pulse width modulation measurement circuit and converted into a signal in which the pulse width is monotonic with the capacitance value. This signal is eventually fed back to the input of the MCU, which calculates the actual capacitance value. The calculated actual capacitance value is paired with the current DC bias voltage to generate a CV curve point by point.

[0011] Furthermore, based on the aforementioned system, this invention also proposes a software timing control method based on dynamic output baseline correction, aiming to resolve the contradiction between existing measurement methods in characterizing slow response and effectively suppressing leakage current.

[0012] This method achieves this at each bias point through a smart sequence of "stabilization-evaluation of output baseline-measurement-compensation".

[0013] A method for testing the capacitance voltage of a semiconductor device, the method comprising the following steps: Step 1. Apply bias and stabilize the system; A target DC bias voltage is applied to the capacitor under test (DUT) through a high-voltage bias control circuit. The DC bias voltage is applied only to the DUT through an AC-DC isolation circuit. After the DC bias voltage is applied, the MCU waits for a preset time to allow the slow physical processes inside the DUT to fully respond and reach quasi-static equilibrium. Step 2. Baseline error assessment and measurement signal acquisition; After the waiting period ends, the MCU acquires the DC analog voltage signal U_adc output by the analog signal conditioning front-end circuit AFE; the MCU analyzes the U_adc signal and evaluates the equivalent baseline offset U_offset_measured caused by the slow response; U_offset_measured represents the DC offset in the AFE output caused by slow response non-ideal factors; The MCU further acquires the U_adc signal to obtain the raw ADC sample value ADC_measured_raw; Wherein, ADC_measured_raw represents the uncorrected raw ADC sample value, and ADC_measured_raw contains the output generated by the capacitance information and the equivalent baseline offset U_offset_measured; Step 3. Software algorithm compensation; The MCU calculates a correction factor K_adc_compensated, which represents the correction factor used to compensate for the ADC sampled values; where K_adc_compensated is proportional to the equivalent baseline offset U_offset_measured. The MCU uses K_adc_compensated to correct ADC_measured_raw, obtaining the true ADC sample value that excludes the influence of non-ideal factors: ADC_true = ADC_measured_raw - K_adc_compensated; Wherein, ADC_true represents the ADC sample value after correction, which reflects the capacitance information of the DUT; Step 4. Calculation of the capacitance under test: Based on ADC_true, the MCU uses the transfer function U_adc = M × U0 + N of the AFE to inversely obtain the theoretical DC voltage U0_compensated = (ADC_true - N) / M of the DPWM core output; Where U0_compensated represents the compensated DPWM core output voltage obtained by AFE inversion; N represents the bias constant of AFE; M represents the gain coefficient of AFE; and U0 represents the compensated voltage.

[0014] The MCU substitutes U0_compensated into the theoretical model of the DPWM core, as shown in the following formula: U0 = U_high ×( (Cdut - C_ref) / (Cdut + C_ref) ); Where U_high represents the charging high level of the DPWM core; Cdut represents the capacitance value of the DUT; C_ref represents the known calibration value of the fixed reference capacitor C2; and the capacitance value Cdut of the DUT is calculated according to the above formula. MCU calculates the normalized intermediate variable X: X = U0_compensated / U_high; Where X represents the normalized ratio of U0_compensated to U_high; The MCU obtains the capacitance value of the DUT through algebraic operations, using the following formula: Cdut = C_ref× (1 + X) / (1 - X); Step 5. Data storage and iteration; The MCU pairs and stores the Cdut value with the current target DC bias voltage, and iteratively executes steps 1 to 5 above to complete the CV characteristic curve measurement within the preset bias range.

[0015] The present invention has the following advantages: As described above, this invention relates to a semiconductor device capacitor voltage testing system and method. Regarding system composition, this invention proposes a high-voltage generation circuit (i.e., a Boost-voltage multiplier power supply circuit) based on Boost converter and symmetrical voltage multiplier chains. This circuit is a power supply circuit combining two sets of symmetrical Cockcroft-Walton voltage multiplier chains driven by a high-frequency boost-type switching converter U23 (ADP1612ARMZ-R7). This circuit utilizes U23 and energy storage inductor L1 to convert low-voltage DC into high-frequency square wave energy, which is then synchronously and symmetrically charged through a positive voltage multiplier chain (composed of diodes U25-U33, U12, etc.) and a negative voltage multiplier chain (composed of diodes U13-U22, etc.). This solution solves the bottleneck problem in existing portable devices where it is difficult to efficiently generate a wide-range (±90V in this embodiment) symmetrical bipolar high-voltage bias within a compact size, providing a stable and reliable power supply foundation for the high-voltage operational amplifier U9 in the high-voltage operational amplifier circuit. Furthermore, this invention proposes a differential pulse width modulation (PWM) measurement circuit to resist common-mode interference. This circuit primarily consists of a differential pulse width modulation measurement front-end composed of a D-type flip-flop U3 (SN74LS74N) and a dual-channel comparator U1 (LM393N). The circuit injects opposite-phase charging currents into the total capacitance under test (reference capacitance C2 + DUT) via charging resistors R3 and R4 through the complementary output pins of U3 (forward modulation pulse output pin 1Q and reverse modulation pulse output pin 1Q#), converting the capacitance value into a change in pulse width. Subsequently, a signal conditioning circuit composed of operational amplifier U2 (LM358DR2G) processes this differential signal. This differential drive and processing hardware architecture fundamentally suppresses common-mode noise and ground interference, solving the problem of extreme sensitivity and low reliability in field environments inherent in existing single-ended measurement methods, and significantly improving measurement accuracy and stability. Furthermore, this invention also designs a symmetrical bipolar high-voltage bias control circuit based on dual-channel unipolar DACs. This bias generation circuit adopts a "low-voltage precision control synthesis, high-voltage linear amplification" design, utilizing two independent unipolar DAC outputs (DAC1, DAC2) from an MCU (e.g., an STM32 microcontroller), along with an analog operational circuit composed of general-purpose operational amplifiers U10 and U11, to synthesize a high-precision bipolar reference signal in the low-voltage domain. This bipolar reference signal is then linearly amplified at a high rate by a high-voltage operational amplifier U9 (OPA462IDDAR). This scheme solves the problem of how to achieve high linearity, symmetry, and seamless zero-crossing bipolar high-voltage scanning function with extremely low cost and hardware complexity, significantly reducing system cost and design complexity. Finally, this invention also proposes a software compensation and differential measurement method combining dynamic output baseline correction. This method is a software measurement method implemented in an MCU.At each DC bias point, the method effectively addresses the problem of slow response characterization in existing measurement techniques through an intelligent timing sequence of "stabilization-evaluation of output baseline-measurement-compensation". Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the composition and workflow of the high-voltage capacitor voltage (CV) testing system in an embodiment of the present invention. Figure 2 This is a structural diagram of the Boost-voltage doubler power supply circuit in an embodiment of the present invention; Figure 3 This is a structural diagram of the high-voltage bias control circuit in an embodiment of the present invention; Figure 4 This is a structural diagram of the differential pulse width modulation measurement circuit in an embodiment of the present invention. Detailed Implementation

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Example Current measurement methods based on pulse charging timing suffer from low signal-to-noise ratios when detecting minute pF-level capacitance changes, and are susceptible to parasitic parameters and electromagnetic interference, leading to unstable measurement results. Furthermore, portable systems require efficient generation of wide-range, symmetrical bipolar high-voltage biases (e.g., ±90V) within a compact space, a challenge that traditional solutions struggle to balance size, efficiency, and symmetry. Additionally, characterizing slow response processes such as semiconductor interface traps requires sufficiently long bias settling times, but this introduces accumulated leakage current, interfering with the voltage measurement reference and causing measurement errors. Existing technologies face a dilemma: extending the settling time increases leakage current errors, while shortening it fails to accurately capture slow response processes. To address the technical bottlenecks in high-voltage power generation, measurement anti-interference capabilities, and slow response process characterization in existing portable CV testing equipment, this invention provides a portable high-voltage CV testing system and method integrating a high-voltage power supply, a differential measurement front-end, and intelligent timing control software.

[0018] Specifically, this invention employs a hardware-software co-design scheme. The hardware section designs a Boost-voltage multiplier circuit based on high-frequency switching conversion and a symmetrical voltage multiplier topology, which efficiently converts low-voltage DC input into a symmetrical ±90V high-voltage rail, overcoming the bottleneck of high-voltage generation in portable devices. The measurement section uses a differential pulse width modulation circuit to convert the capacitance value into a differential square wave pulse width, then demodulates it into an analog voltage. The differential architecture suppresses common-mode noise and ground interference, improving anti-interference capabilities. On the software side, intelligent timing control and algorithm compensation are implemented in the MCU. By executing a cyclic sequence of "stabilization-baseline evaluation-measurement-compensation" at each bias point, the system provides sufficient stabilization time for the slow response process while actively measuring and compensating for baseline errors caused by leakage current, thus fundamentally resolving the contradiction between slow response characterization and leakage current suppression.

[0019] like Figure 1 As shown, the semiconductor device capacitance voltage testing system in this embodiment includes a low-voltage power supply circuit, a Boost-voltage multiplier circuit, an MCU, a high-voltage bias control circuit, an AC / DC isolation circuit, and a differential pulse width modulation measurement circuit.

[0020] The system is supplied with initial low-voltage power through a low-voltage power supply circuit.

[0021] One path is sent to the STM32 microcontroller and other low-voltage analog circuits; the other path is sent to the Boost power supply circuit, which generates a symmetrical ±90V high voltage as the power rail for the high-voltage operational amplifier circuit.

[0022] The Boost power supply circuit is used to receive the low-voltage DC input from the low-voltage power supply circuit and generate a pair of stable, symmetrical and isolated high-voltage bipolar power rails as power rails for the high-voltage operational amplifier circuit.

[0023] The high-voltage bias control circuit consists of two parts: a signal processing circuit and a high-voltage operational amplifier circuit.

[0024] According to the preset scanning program, the STM32 microcontroller outputs a low-voltage control signal through its built-in dual-channel DAC. After the low-voltage control signal is polarity-reversed and buffered by the signal processing circuit, it drives the high-voltage operational amplifier circuit.

[0025] The high-voltage operational amplifier circuit is used to linearly amplify the low-voltage control signal and apply the -90V to +90V DC bias voltage generated by the Boost-voltage multiplier circuit to the device under test (DUT) in differential form through the AC-DC isolation circuit.

[0026] At each stable DC bias point, an AC measurement pulse is coupled to the DUT. The capacitance response of the DUT is captured by the differential pulse width modulation measurement circuit and converted into a signal whose pulse width is monotonically related to the capacitance value.

[0027] The signal is eventually fed back to the ADC input of the STM32 microcontroller. The STM32 microcontroller calculates the actual capacitance value and matches it with the current DC bias voltage to generate a CV curve point by point.

[0028] The Boost-type power supply circuit is the power source for the entire system, used to generate a pair of stable, symmetrical and isolated high-voltage bipolar power rails (+90V and -90V in the embodiment) from a single low-voltage DC input (such as +3.3V).

[0029] The high-voltage bias control circuit is used to receive the low-voltage, unipolar control signal from the MCU (output via DAC) and accurately and linearly convert it into a wide-range (-90V to +90V) continuously scannable bipolar high voltage.

[0030] This high voltage is applied to the device under test (DUT) as the DC bias voltage V_bias in the CV test.

[0031] The function of the differential pulse width modulation measurement circuit is to linearly convert the capacitance value of the component under test (DUT) into an analog signal, which can be easily captured with high precision by the hardware ADC of the MCU (e.g., using an STM32 microcontroller).

[0032] The boost-multiplier circuit provides the high-voltage power necessary for the normal operation of the high-voltage operational amplifier U9. Without a stable, clean ±90V power supply, U9 will be unable to output the required high-voltage bias.

[0033] Among them, the high-voltage operational amplifier U9 is the core component in the high-voltage bias control circuit.

[0034] like Figure 2 As shown, the Boost-voltage doubler power supply circuit in this embodiment includes the following two circuits: The high-frequency boost circuit is used to initially boost the +3.3V DC input voltage of the received low-voltage power supply circuit and convert it from DC form into the high-frequency energy source required by the voltage multiplier circuit. And a Cockcroft-Walton voltage multiplier circuit with symmetrical topology is used to receive the high-frequency energy source output from the high-frequency boost circuit, and amplify its voltage amplitude step by step to the target value of ±90V through multi-stage passive charge pumping.

[0035] The high-frequency boost converter circuit includes a high-frequency boost-type switching converter U23 and an energy storage inductor L1.

[0036] U23 preferably uses the ADP1612ARMZ-R7 device. A +3.3V DC input voltage is applied to VIN (pin 6) and the enable control pin EN (pin 3) of U23; connecting EN directly to VIN ensures that the chip starts working immediately upon power-up.

[0037] L1 is connected between the input pin VIN of U23 and the output pin SW (pin 5) of the internal power switch.

[0038] After the high-frequency boost converter U23 is powered on, its internal oscillator starts working, driving the internal MOSFET power switch to switch on and off at a very high frequency (MHz level).

[0039] When the internal switching transistor of SW is grounded, a low-resistance path is formed from VIN through the energy storage inductor L1 to ground, and the current flows rapidly through the inductor L1. According to the inductor characteristics, the current increases linearly, storing the input electrical energy in L1 in the form of a magnetic field.

[0040] When the switch inside the SW pin is suddenly turned off, the current path through the energy storage inductor L1 is cut off. Since the inductor current cannot change abruptly, the magnetic field energy stored in L1 will be instantly converted into electrical energy.

[0041] At this time, the SW pin outputs a series of high-peak, high-frequency square wave pulses (voltage spikes).

[0042] The amplitude of this voltage spike is much higher than the input +3.3V, thus boosting the voltage; a series of high-peak, high-frequency square wave pulses are output on the SW pin, which is the high-frequency energy source for the subsequent voltage multiplier circuit.

[0043] The high-frequency Boost converter circuit also includes a closed-loop feedback network for sampling from the internal power switch output pin SW; the closed-loop feedback network consists of two voltage divider resistors R30 and R31, a Schottky diode U24, and a capacitor C39.

[0044] Schottky diode U24 and capacitor C39 form a peak detector to capture the peak voltage of the output pulse from the internal power switch output pin SW. Two voltage divider resistors R30 and R31 divide this peak voltage.

[0045] The voltage after voltage division is sent to the feedback input pin FB of the high-frequency boost switching converter U23; the high-frequency boost switching converter U23 internally compares the voltage of the feedback input pin FB with the target voltage.

[0046] If the voltage at the feedback input pin FB is higher than the target voltage, the on-time of the internal switch will be reduced, thus lowering the duty cycle; conversely, if the voltage at FB is not higher than the target voltage, the on-time of the internal switch will be increased, thus increasing the duty cycle.

[0047] Through this negative feedback mechanism, the peak voltage of the pulse output from the SW pin of the high-frequency boost switching converter U23 is precisely stabilized at the target value set by the ratio of the voltage divider resistors R30 and R31.

[0048] In addition, the high-frequency Boost circuit also includes a loop compensation network (i.e., an RC compensation network) to adjust the frequency response characteristics of the feedback loop, ensuring that the loop can work stably under various load conditions and preventing oscillations or slow response.

[0049] The loop compensation network includes a compensation resistor R29 and a compensation capacitor C1. R29 and C1 are connected in series between the compensation pin COMP (pin 1) of U23 and ground. The GND pin (pin 2) of U23 is connected to system ground.

[0050] like Figure 2 As shown, the voltage multiplier circuit consists of two sets of five-stage CW voltage multiplier chains with completely mirrored structures and identical topologies; the input terminals of both voltage multiplier chains are connected to the output pin SW of the internal power switch and share the same high-frequency energy source.

[0051] The two level 5 CW voltage multiplier chains are a positive +90V voltage multiplier chain and a negative -90V voltage multiplier chain, respectively.

[0052] The positive +90V voltage multiplier chain adopts a five-stage pumping structure, which includes: Multiple coupling capacitors C3, C40, C42, C44, and C46 (each located in a different pumping structure) are used. One end of coupling capacitor C3 is connected to the SW excitation source of the high-frequency Boost circuit to transfer energy during the AC cycle of the square wave.

[0053] Multiple energy storage and filtering capacitors C4, C41, C43, C45, and C47 (located in each stage of the pumping structure) are used to store the charge pumped up by each stage of the pumping structure and gradually increase the DC voltage.

[0054] And multiple rectifier diodes U25, U26, U27, U28, U29, U30, U31, U32, U33, U12 (every two rectifier diodes are in the first-stage pumping structure, for example, U25 and U26 are in the first-stage pumping structure).

[0055] They form a unidirectional charge transport path, ensuring that charge can only be pumped from low potential to high potential step by step.

[0056] Each pumping stage consists of a coupling capacitor, two rectifier diodes, and an energy storage and filtering capacitor. For example, the coupling capacitor C3, rectifier diodes U25 and U26, and energy storage and filtering capacitor C4 constitute the first-stage pumping structure.

[0057] The SW pin is connected to one end of C3 and the anode of U25, and the other end of C3 is connected to the cathode of U26. The cathode of U25 is connected to the anode of U26 and to one end of C4, while the other end of the energy storage and filtering capacitor C4 is grounded.

[0058] This "trapezoidal" structure of "coupling capacitor-diode pair-energy storage and filter capacitor" is cascaded sequentially. For example, coupling capacitor C40, rectifier diodes U27 and U28, and energy storage and filter capacitor C41 constitute the second-stage pumping structure.

[0059] The cathode of U26 is also connected to one end of C40 and the anode of U27. The other end of C40 is connected to the cathode of U28. The cathode of U27 and the anode of U28 are adjacent and connected to one end of C41. The other end of the energy storage and filtering capacitor C41 is grounded.

[0060] The second-stage "coupling capacitor-diode pair-energy storage and filter capacitor" structure is formed by coupling capacitor C40, diodes U27 and U28, and energy storage and filter capacitor C41, and so on. Figure 2 As shown.

[0061] The structure repeats for five stages until the last stage, where the cathode of diode U12 is used as the +90V high-voltage output terminal.

[0062] Similarly, the negative +90V voltage multiplier chain adopts a five-stage pumping structure, which includes: Multiple coupling capacitors C22, C20, C18, C16, and C14 (each located in a different pumping structure) are used to transfer energy during the AC cycle of a square wave. One end of C22 is connected to the SW excitation source of the high-frequency Boost circuit.

[0063] Multiple energy storage and filtering capacitors C23, C21, C19, C17, and C15 are located in each stage of the pumping structure, respectively, to store the charge pumped up by each stage of the pumping structure and gradually increase the DC voltage.

[0064] And multiple rectifier diodes U13, U14, U15, U16, U17, U18, U19, U20, U21, U22 (every two rectifier diodes are in the first-stage pumping structure, for example, U13 and U14 are in the first-stage pumping structure).

[0065] They form a unidirectional charge transport path, ensuring that charge can only be pumped from low potential to high potential step by step.

[0066] Each pumping stage consists of a coupling capacitor, two rectifier diodes, and an energy storage and filtering capacitor; for example, the coupling capacitor C22, rectifier diodes U22 and U21, and energy storage and filtering capacitor C23 constitute the fifth pumping stage.

[0067] like Figure 2 As shown, pin SW connects one end of C22 to the cathode of U22, and the other end of C22 is connected to the anode of U21. The anode of U22 is connected to the cathode of U21 and to one end of C23, while the other end of C23 is grounded.

[0068] This "trapezoidal" structure of "coupling capacitor-diode pair-energy storage and filter capacitor" is cascaded sequentially. For example, coupling capacitor C20, rectifier diodes U20 and U19, and energy storage and filter capacitor C21 constitute the fourth-stage pumping structure.

[0069] The anode of U21 is also connected to one end of the energy storage capacitor C20 in the previous stage pumping structure. This negative chain structure is a mirror image of the positive chain topology, with all diodes facing opposite directions. After five cascaded stages, the anode of diode U13 serves as the -90V high-voltage output terminal.

[0070] The Boost-voltage doubler power supply circuit is based on charge pumping and is driven by a high-frequency square wave energy source output from the SW pin.

[0071] Because the topologies of the positive and negative voltage multiplier chains are completely symmetrical and share the same excitation source, their charge pumping processes alternate synchronously and mirror-like within the two half-cycles of the SW pin, thereby efficiently generating symmetrical bipolar high-voltage output.

[0072] The positive +90V charge pumping process (the gradual rise of positive charge) can be decomposed into two alternating stages: First half-cycle: during the charging phase, the voltage at the SW pin is 0V.

[0073] For each stage of the forward chain, its corresponding coupling capacitor (e.g., C3 in the first stage) is forward-biased through the preceding diode (e.g., U25) and connected to the system reference potential (ground). At this time, C3 is charged, and its right-hand potential is clamped at approximately +0.7V (diode forward voltage drop), providing charge reserves for voltage boosting in the next half-cycle.

[0074] Second half-cycle: Pumping / lifting phase, the voltage at the SW pin jumps instantaneously from 0V to the peak voltage Vp.

[0075] Due to the physical property that capacitor voltage cannot change abruptly, the voltage difference across C3 must be maintained during the instant of voltage jump. Since the potential at its left end is forcibly raised by Vp, the potential at its right end must also be raised by Vp accordingly, reaching approximately Vp + 0.7V.

[0076] At this point, the high potential at the right end of C3 causes its subsequent diode (e.g., U26) to conduct in the forward direction, while the preceding diode U25 is reverse-biased because its anode is 0V. Thus, the charge stored in C3 and given a higher potential energy is "pumped" through U26 to the first energy storage and filtering capacitor (e.g., C4) to charge it.

[0077] The voltage across C4 will gradually build up and stabilize at approximately Vp. At this point, the first stage of charge pumping is complete, successfully raising the DC potential from 0V to approximately Vp. This "charge-pump" cycle is iteratively repeated in the subsequent four stages of the circuit.

[0078] Each stage uses the DC voltage established by the previous stage as its "ground" potential, and then raises it again by approximately Vp. The charge flow is unidirectionally transmitted along the progressively increasing "potential ladder" formed by U25 to U12.

[0079] Ultimately, the voltage converges at the +90V output terminal, forming a stable positive high voltage output.

[0080] The negative -90V charge pumping process (step-by-step extraction of positive charge) works exactly like the positive chain. It can be understood as the step-by-step "extraction" of positive charge, thereby creating a negative potential at the output.

[0081] First half-cycle: Preparation phase. During this phase, the SW pin voltage is high at Vp. For each stage of the negative chain, its corresponding coupling capacitor (e.g., C22 in the first stage) is connected to the SW terminal through its preceding diode (e.g., U22).

[0082] Second Half Cycle: Pump / Pull-Down Phase. During this phase, the voltage at the SW pin drops instantaneously from Vp to 0V. The left-hand potential of C22 is forcibly pulled down by Vp, causing its right-hand potential to be correspondingly "pull-down" to an extremely low negative potential (approximately -Vp).

[0083] At this point, the extremely low negative potential causes the subsequent diode (e.g., U21) to conduct in the forward direction, while the preceding diode U22 is reverse-biased and cut off. Thus, the extremely low potential of C22 "draws" positive charge from the energy storage and filtering capacitor (e.g., C23) (equivalent to injecting electrons into it). As C23 continuously loses positive charge, its potential relative to system ground gradually decreases and eventually stabilizes at approximately -Vp. At this point, the fifth stage of negative pumping is complete, successfully "pulling down" the 0V DC potential to approximately -Vp.

[0084] This process is repeated iteratively in subsequent stages. Positive charges are extracted step by step from the final -90V output terminal and flow down the "staircase" formed by U13 to U22, where the potential decreases step by step, and finally flow into the system ground.

[0085] Ultimately, the -90V output terminal forms a stable negative high voltage due to the continuous loss of positive charge.

[0086] The Boost-type voltage multiplier circuit is a symmetrical bipolar high-voltage generation circuit that helps solve the bottleneck problem in existing portable devices where it is difficult to efficiently generate a wide range of symmetrical bipolar high-voltage bias within a compact size.

[0087] The high-voltage bias control circuit is used to accurately convert the low-voltage, digital control intent generated by the STM32 microcontroller into a highly linear, wide dynamic range (-90V to +90V) analog DC high voltage applied to the device under test.

[0088] This voltage, referred to as the DC bias voltage V_bias in CV testing, is the basis for performing a capacitance characteristic scan.

[0089] In order to maximize the use of general-purpose, low-cost components while ensuring extremely high precision and linearity, the high-voltage bias control circuit in this embodiment adopts a two-stage cascaded design strategy of "low-voltage precision control synthesis and high-voltage linear amplification".

[0090] The high-voltage bias control circuit converts the low-voltage instructions output by the STM32 microcontroller into a highly linear, symmetrical, and seamless zero-crossing bipolar high-voltage bias. It consists of a cascaded signal processing circuit and a high-voltage operational amplifier circuit.

[0091] The signal processing circuit is responsible for combining the two independent, unipolar DAC signals built into the STM32 microcontroller into a precise bipolar low-voltage reference signal. It mainly includes a negative signal generation path and a signal merging path.

[0092] The input nodes of the signal processing circuit are DAC1 and DAC2. These two nodes are directly connected to the two DAC output pins of the MCU. The MCU can precisely control these two pins to output any voltage between 0V and +3.3V.

[0093] The negative signal generation path includes a first operational amplifier U10, an input resistor R1, and a feedback resistor R20; wherein, the input resistor R1 and the feedback resistor R20 constitute an inverting amplifier.

[0094] The first operational amplifier U10 is, for example, a dual operational amplifier (using one channel of a dual operational amplifier). The second digital-to-analog converter output node DAC2 of the MCU is connected to one end of the input resistor R1. DAC2 outputs a voltage signal from 0 to 3.3V.

[0095] The other end of the input resistor R1 is connected to the inverting input terminal 1IN- of U10; the feedback resistor R20 is connected between the output terminal 1OUT and the inverting input terminal 1IN- of the first operational amplifier U10; the non-inverting input terminal 1IN+ of U10 is directly grounded.

[0096] The first operational amplifier U10 outputs a voltage from -3.3V to 0V at its output terminal 1OUT (pin 1).

[0097] When DAC2 outputs a unipolar voltage signal from 0V to +3.3V, the inverting amplifier (configured as unity gain, i.e., R1=R20) precisely converts it into a negative voltage signal from -3.3V to 0V and outputs it from its output terminal 1OUT.

[0098] The signal combining path includes a second operational amplifier U11, two input resistors R21 and R22, and a non-inverting adder consisting of a feedback network. In this embodiment, the second operational amplifier U11 is, for example, a dual operational amplifier.

[0099] Similarly, U11 is also a single channel using only a dual operational amplifier.

[0100] The output terminal 1OUT of the first operational amplifier U10 is connected to one end of an input resistor R21; the first digital-to-analog converter output node DAC1 of the MCU is connected to one end of another input resistor R22.

[0101] The other ends of input resistors R21 and R22 are connected together to the non-inverting input terminal 1IN+ of the second operational amplifier U11.

[0102] The output terminal 1OUT of U11 is connected to its inverting input terminal 1IN- through a feedback network consisting of two feedback resistors R23 and R24, configured as a voltage follower or a non-inverting amplifier with a specific gain.

[0103] The in-phase adder superimposes the positive signal from DAC1 of the MCU and the negative signal from U10.

[0104] Since DAC1 and DAC2 are time-division driven, only one of the two inputs is non-zero at any given time. Therefore, the output of U11 can generate a continuous, seamless zero-crossing, low-voltage bipolar reference signal ranging from -3.3V to +3.3V.

[0105] In this embodiment, U10 and U11 both use LM358DR2G devices, for example.

[0106] The high-voltage operational amplifier circuit is responsible for amplifying the bipolar low-voltage reference signal synthesized by the pre-processing circuit at a high power ratio, ultimately generating the required high-voltage bias. The core of this circuit is a high-voltage operational amplifier U9.

[0107] The two power supply pins of U9, V+ and V-, are connected to the +90V and -90V high-voltage power rails generated by the Boost-voltage doubler circuit, respectively. The non-inverting input terminal +IN of U9 is directly connected to the output of the second operational amplifier U11.

[0108] The high-voltage operational amplifier U9 is used to receive the bipolar low-voltage reference signal output by the second operational amplifier U11.

[0109] The high-voltage output terminal OUT of U9 is fed back to its inverting input terminal -IN through a closed-loop feedback network consisting of two feedback resistors R26 and R27; the high-voltage output terminal OUT of U9 is connected to one terminal of the component under test (DUT) through an AC-DC isolation circuit.

[0110] U9 and its closed-loop feedback network constitute a high-voltage in-phase amplifier. Its closed-loop gain G is precisely set by the ratio of the feedback resistors R26 and R27 in the closed-loop feedback network. Specifically, the gain G = 1 + R26 / R27.

[0111] The U9 amplifier linearly amplifies the low-voltage reference signal from -3.3V to +3.3V by a factor of G, thereby generating a continuous high-voltage bias from -90V to +90V at its output, synchronized with the DAC digital instructions, and applying it to the device under test (DUT).

[0112] The boost-voltage power supply circuit and the high-voltage bias control circuit are used to provide a stable operating environment for the DUT.

[0113] After the system provides a stable high-voltage bias working environment for the DUT, the differential pulse width modulation measurement circuit uses differential pulse width modulation (DPWM) technology to convert the capacitance value Cdut of the DUT into a single-ended analog voltage signal that can be accurately acquired by the MCU's ADC.

[0114] The DPWM technology is an ideal choice for high-precision capacitance measurement due to its excellent linearity and anti-interference capabilities.

[0115] To achieve this goal, the differential pulse width modulation (PWM) measurement circuit employs a cascaded architecture, with the conversion chain as follows: capacitor → pulse width → differential square wave → single-ended analog signal. The differential pulse width modulation (PWM) measurement circuit includes: The differential pulse width modulation capacitance detection circuit is responsible for linearly converting the capacitance value of the component under test (DUT) into a differential square wave signal, the pulse width of which, i.e., the duty cycle, is proportional to the capacitance value.

[0116] The analog signal conditioning front-end circuit is used to perform low-pass filtering on the differential square wave signal, and demodulate it through subtraction and level-up operations to convert it into an analog signal whose voltage range matches the voltage range of the MCU's ADC.

[0117] The differential pulse width modulation capacitance detection circuit consists of a logic AND drive unit U3, a dual-channel comparator U1, and a differential RC network including the arm under test R3, DUT, and the reference arm R4, C2.

[0118] The differential pulse width modulation capacitance detection circuit linearly converts the measured capacitance value into a differential square wave signal with a pulse width proportional to the capacitance value through self-excited oscillation. The formula is as follows: u_AB = u_A - u_B.

[0119] like Figure 4 As shown, the core circuit of differential pulse width modulation includes: The logic and drive unit U3 uses a D-type flip-flop. Its positive modulation pulse output pin 1Q and negative modulation pulse output pin 1Q# complementary output signals serve as differential drive sources, denoted as u_A and u_B respectively. Dual comparator U1 is used to sense the RC charging process and trigger the state flip of U3; The differential RC network consists of an upper arm charging path comprising a charging resistor R3 and a DUT, and a lower arm charging path comprising a charging resistor R4 and a reference capacitor C2; as well as two reset diodes D1 and D2.

[0120] The 1Q# pin of U3 is connected to the cathode of the reset diode D1 and one end of the charging resistor R3; the anode of D1 and the other end of the charging resistor R3 are connected, and are connected to DUT through the isolation capacitor C48.

[0121] The 1Q pin of U3 is connected to the cathode of the reset diode D2 and one end of the charging resistor R4; the anode of D2 and the other end of 4 are connected, and one end of C2 is connected to C2. The other end of C2 is connected to DUT through the isolation capacitor C49.

[0122] The 5V voltage signal is divided by voltage divider resistors U5 and R2 to obtain a reference voltage, which is then connected to the positive input pin IN1+ of comparator 1 and the positive input pin IN2+ of comparator 2 of the dual comparator U1 as a reference voltage.

[0123] Pull-up resistors U6 and U7 are connected to 5V at one end and to the OUT pin at the other end for output pull-up.

[0124] U6 and U7 are essential pull-up resistors used to compensate for the fact that the open-collector output of the LM393 comparator cannot generate a high level on its own, ensuring a stable and complete digital signal for the subsequent digital logic chip U3.

[0125] The positive input pin IN1+ of comparator 1 of dual comparator U1 and the positive pin IN2- of comparator 2 of dual comparator U1 are connected to the positive terminals of reset diodes D1 and D2 respectively, and are used to receive input signals for comparison with reference voltage.

[0126] The OUT1 output pin is connected to the 1CP clock input pin of U3, and the OUT2 pin is connected to the asynchronous clear pin 1RD# of U3.

[0127] The difference signal u_AB = u_A - u_B between u_A and u_B constitutes the core signal carrying the modulation information, namely the differential square wave signal.

[0128] In this embodiment, U3 may be an SN74LS74N device, and U1 may be an LM393N device.

[0129] The analog signal conditioning front-end circuit performs demodulation and conversion. This analog signal conditioning front-end circuit is based on a core operational amplifier U2 and is provided with a reference voltage by a precision 1.6V reference source U8.

[0130] In this embodiment, U2 uses an LM358DR2G device, and U8 uses an LP3993-16B3F device.

[0131] The analog signal conditioning front-end circuit performs low-pass filtering on the input differential square wave signal to extract the DC component, and performs subtraction and level boosting operations, finally generating a clean and stable single-ended analog voltage signal at the output node H1.

[0132] The voltage range of the single-ended analog voltage signal is perfectly matched with the ADC of the MCU (such as the STM32 microcontroller).

[0133] According to the basic physical laws of RC circuit charging, when a capacitor starts charging from 0V to the threshold voltage Ur, and the final charging voltage is U_high, the expression for its charging time T is: T = R ×C × ln( U_high / (U_high - Ur) ); Where R represents voltage and C represents capacitance.

[0134] Applying this theory to the two half-cycles of this circuit, the pulse widths T_A and T_B are accurately derived as follows: T_A = R3_ref × (Cdut) × ln( U_high / (U_high - Ur) ).

[0135] T_B = R4_ref × C_ref × ln( U_high / (U_high - Ur) ).

[0136] Where U_high is the high output level of U3 (approximately +5V), Ur is the threshold voltage of U1, R3_ref is the resistance value of R3, and R4_ref is the resistance value of R4.

[0137] Within the oscillation core, u_A and u_B are rectangular waves with a period of T = T_A + T_B. u_A is U_high during the T_A time interval and 0V during the T_B time interval. u_B is U_high during the T_B time interval and 0V during the T_A time interval.

[0138] According to the theory of differential pulse width modulation circuit, the DC voltage U0 obtained after passing the differential signal u_AB = u_A - u_B through low-pass filtering is its average value over one cycle.

[0139] The expression for U0 is: U0 = (1 / (T_A + T_B)) × [ (U_high × T_A) + (-U_high × T_B) ].

[0140] After sorting, we get: U0 = U_high × ( (T_A - T_B) / (T_A + T_B) ).

[0141] Where U_A_dc = U_high × (T_A / (T_A + T_B)) is the DC component of the u_A rectangular pulse, and U_B_dc = U_high × (T_B / (T_A + T_B)) is the DC component of the u_B rectangular pulse.

[0142] T_A = R3_ref × Cdut × Const_ln; T_B = R4_ref × C_ref × Const_ln.

[0143] Let Const_ln = ln( U_high / (U_high - Ur) ), which is a constant that is constant under specific circuit parameters.

[0144] Substituting the expressions for T_A and T_B into the formula for U0, we get: U0 = U_high × ( (R3_ref × Cdut × Const_ln - R4_ref × C_ref ×Const_ln) / (R3_ref × Cdut × Const_ln + R4 _ref × C_ref × Const_ln) ).

[0145] As can be seen from the above formula, the constant term Const_ln is completely canceled out: U0 = U_high × ( (R3_ref × Cdut - R4_ref × C_ref) / (R3_ref × Cdut+ R4_ref × C_ref) ).

[0146] In the circuit design, high-precision matching resistors are selected so that R3_ref = R4_ref = R, and resistor R can also be canceled out, that is: U0 = U_high × ( (Cdut - C_ref) / (Cdut+ C_ref) ); Where Cdut is the capacitance value of the component under test.

[0147] Therefore, it can be seen that the DC voltage U0 obtained after low-pass filtering is directly proportional to the ratio of the difference to the sum of the two capacitors (the component under test and the reference capacitor). This is a highly linear relationship, which enables accurate capacitance measurement.

[0148] The analog signal conditioning front-end circuit includes a precision reference source U8, an operational amplifier U2, a differential subtractor, an adder with level boost, and an output filter, such as PZ254V-11-02P.

[0149] The core operational amplifier U2 of the analog signal conditioning front-end circuit is an LM358DR2G (a dual-channel operational amplifier), which forms a low-pass filter, subtraction, and level-up circuit. The precision reference source U8 is an LP3993-16B3F, used to provide a 1.6V reference.

[0150] The analog signal conditioning front-end circuit is connected to the ADC of the STM32 microcontroller through interface H1.

[0151] The analog signal conditioning front-end circuit outputs a DC analog voltage signal U_adc, and has a final output node interface H1 that connects to the MCU's ADC, so as to accurately convert the capacitance value into an analog voltage signal that can be acquired by the microcontroller.

[0152] The analog signal conditioning front-end circuit is used to receive the complementary outputs 1Q and 1Q# from the D-type flip-flop U3, and through a series of analog calculations, finally extracts and conditions the single-ended analog voltage that is linearly related to the capacitance value.

[0153] The subtractor circuit is composed of the first-stage operational amplifier of operational amplifier U2, input resistors R7 and R8, pull-down resistor R9, and feedback resistor R10. It is used to subtract the voltage-divided u_A and u_B signals to obtain the difference signal u_AB and output it.

[0154] where u_AB = u_A - u_B.

[0155] The positive modulation pulse output pin 1Q of the logic and drive unit U3 is connected to one end of the input resistor R8 through two voltage divider resistors R6 and R5. The other end of the input resistor R8 is connected to the inverting input terminal 1IN- of the first-stage operational amplifier.

[0156] One end of the input resistor R7 is connected between the two voltage divider resistors R6 and R5, and the other end is connected to the positive input terminal 1IN+ of the first-stage operational amplifier; one end of the pull-down resistor R9 is connected between the positive input terminal 1IN+ of the first-stage operational amplifier and the input resistor R7, and the other end is grounded; the feedback resistor R10 is set between the output terminal 1OUT of the first-stage operational amplifier and the first negative input terminal 1IN-.

[0157] The inverted modulation pulse output pin 1Q# of the logic and drive unit U3 is connected to the inverting input terminal 1IN- of the first stage operational amplifier of the operational amplifier U2 through the input resistor R8; the output terminal 1OUT of the first stage operational amplifier outputs the difference signal u_AB, which is used as the output input to the adder circuit composed of the second stage operational amplifier of the operational amplifier U2, two input resistors R11 and R12, and two feedback resistors R13 and R14.

[0158] The output terminal 1OUT of the first-stage operational amplifier is connected to the positive input pin 2IN+ of the second-stage operational amplifier through the input resistor R11; the 5V voltage is converted into a 1.6V reference voltage after passing through the precision reference source U8, and then connected to the positive input pin 2IN+ of the second-stage operational amplifier through the input resistor R12.

[0159] One feedback resistor R14 is connected between the positive input pin 2IN+ and the output pin 2OUT of the second-stage operational amplifier, and another feedback resistor R13 is connected to the positive input pin 2IN+ at one end and grounded at the other end. The output signal of the second-stage operational amplifier, 2OUT, is a DC analog voltage signal U_adc. The spike signal in the output signal is filtered out by the output filter and finally output through port H1. Port H1 is connected to the ADC of the MCU.

[0160] The output filter interface H1 is connected to one end of resistor R19, and the other end of R19 is connected to pin 2OUT of U2. Capacitor C13 is connected between H1 and ground. R19 and C13 form an RC filter circuit to filter out noise. The spike signal in the output signal at the output terminal 2OUT of the second-stage operational amplifier is filtered out by the filter and finally output through port H1.

[0161] Filter capacitors C11 and C12 are used to filter out noise; feedback resistors R13 and R14 form the feedback loop of the adder circuit.

[0162] The operation of the analog signal conditioning front-end circuit is a cascaded signal processing flow: First, the subtractor circuit receives the original high-frequency square wave signals u_A and u_B from U3. This subtractor circuit utilizes the limited bandwidth of U2 itself to naturally achieve a low-pass filtering effect while performing differential subtraction, effectively filtering out high-frequency harmonics and directly extracting the DC component carrying capacitance information, generating a DC voltage centered at ground (0V). This DC voltage signal is then fed into the adder circuit.

[0163] The adder circuit with level-up function sums the output signal of the subtractor circuit with a stable bias voltage provided by a precision reference source U8, and precisely shifts the entire dynamic range of the signal from a bipolar domain centered at 0V to a unipolar voltage domain centered at 1.6V that perfectly matches the input range of the STM32 microcontroller ADC.

[0164] Finally, before being output to interface H1, this voltage flows through a passive RC low-pass filter consisting of resistor R19 and capacitor C13. This filter performs a final "purification" process on the signal, further filtering out any possible residual high-frequency noise, ensuring that the analog signal U_adc finally sent to the MCU is an extremely stable and pure DC voltage.

[0165] This invention further proposes a method to significantly improve the system's measurement accuracy and long-term stability by implementing differential measurement at the functional level through software scheduling and algorithm processing of an MCU (STM32 microcontroller). This method time-division multiplexes the same physical measurement channel, and its core idea and execution steps are as follows.

[0166] The semiconductor device capacitance voltage testing method in this embodiment includes the following steps: Step 1. Apply bias and stabilize the system A preset target DC bias voltage is precisely applied to the device under test (DUT) via a high-voltage bias control circuit. After the bias voltage is applied, the MCU executes a preset soak time to ensure that the slow charge state caused by interface traps and other factors inside the DUT fully responds and reaches quasi-static equilibrium.

[0167] Step 2. Baseline error assessment and signal acquisition.

[0168] After the stabilization waiting period ends, the controller performs the following operations: 2.1. Baseline offset assessment.

[0169] The MCU first acquires and analyzes the DC analog voltage signal U_adc output by the analog signal conditioning front-end (AFE) to quantify the equivalent baseline offset introduced by non-ideal factors such as slow response process, denoted as U_offset_measured.

[0170] 2.2. Raw signal acquisition.

[0171] The MCU then performs formal signal acquisition, obtaining the uncorrected raw ADC sample value ADC_measured_raw. This raw value is the superposition result of the actual capacitance information of the DUT and U_offset_measured.

[0172] Step 3. Software compensation based on baseline offset.

[0173] To eliminate the impact of non-ideal factors on measurement accuracy, the controller executes a software compensation algorithm: Step 3.1. Calculation of correction factor: The MCU calculates an ADC correction factor K_adc_compensated proportional to the measured equivalent baseline offset U_offset_measured, which represents the correction factor used to compensate for the ADC sampled values.

[0174] K_adc_compensated is proportional to the equivalent baseline offset U_offset_measured.

[0175] Step 3.2. Sample value correction: The MCU uses the correction factor K_adc_compensated to correct the original ADC sample value ADC_measured_raw to remove the influence of baseline offset, obtaining an ADC sample value ADC_true that truly reflects the DUT capacitance information. This results in a true ADC sample value that eliminates the influence of non-ideal factors. This correction process follows the following relationship: ADC_true = ADC_measured_raw - K_adc_compensated.

[0176] Here, ADC_true represents the ADC sampled value after correction, which reflects the capacitance information of the DUT.

[0177] Step 4. Accurate calculation of the capacitance Cdut to be tested.

[0178] The MCU uses the compensated real ADC sampling value ADC_true to accurately calculate the capacitance value of the DUT through two-stage inverse operations.

[0179] Step 4.1. Simulate the inverse operation of the front-end pass function: The MCU performs an inverse operation on ADC_true based on the pre-calibrated AFE gain coefficient (M) and bias constant (N) to retrieve the compensated DC voltage U0_compensated, which is theoretically output by the DPWM core circuit. U0_compensated = (ADC_true - N) / M.

[0180] Wherein, U0_compensated represents the compensated DPWM core output voltage obtained from AFE inversion.

[0181] Step 4.2. Inverse operation of the DPWM core model and capacitor value calculation: The MCU substitutes U0_compensated into the theoretical model of the DPWM core circuit and calculates the value of the capacitor to be measured, Cdut, through the following algebraic operation: U0 = U_high ×( (Cdut - C_ref) / (Cdut + C_ref) ).

[0182] Where U_high represents the charging high level of the DPWM core; Cdut represents the capacitance value of the DUT; and C_ref represents the known calibration value of the fixed reference capacitor C2. The capacitance value Cdut of the DUT is calculated according to the above formula.

[0183] First, calculate the normalized intermediate variable X, expressed by the following formula: X = U0_compensated / U_high.

[0184] Where U_high is the known charging high level of the DPWM core circuit. X represents the normalized ratio of U0_compensated to U_high; then, the final capacitor value Cdut is obtained through the analytical inverse function of the model: Cdut = C_ref × ( (1 + X) / (1 - X) ).

[0185] Step 5. Data storage and iterative scanning.

[0186] The MCU pairs the final calculated capacitance value Cdut with the currently applied target DC bias voltage value and stores it as a valid data point (V, C).

[0187] Subsequently, the MCU steps the target DC bias voltage to the next preset value and repeats steps 1 to 5 until the scan of the entire preset bias range is completed, and finally generates a complete CV characteristic curve.

[0188] Finally, a complete and accurate measurement of the CV characteristic curve is completed.

[0189] The software timing control method based on dynamic baseline correction proposed in this invention solves the fundamental contradiction in existing measurement methods that characterize slow responses (requiring long settling times) through an intelligent sequence of "stabilization-evaluation of output baseline-measurement-compensation" at each bias point, making accurate quasi-static CV testing possible. This invention achieves active compensation for inherent non-ideal effects of devices through the proposed method, improving measurement accuracy and solving the interference problem of slow physical processes.

[0190] The present invention, through the technical solution consisting of three hardware modules and a core software algorithm described in detail above, achieves one or more significant beneficial effects compared to existing technologies. These effects work together to make it possible to achieve high-precision capacitance characteristic characterization of complex semiconductor devices on a portable, low-cost platform.

[0191] By combining hardware and software differential measurements, a balance of high precision, high stability, and low cost is achieved. Specifically, this is reflected in: eliminating system common-mode error, reducing the stringent requirements for hardware component precision, and lowering costs. It eliminates the need for extremely expensive, ultra-high-precision resistor and voltage reference chips. The system's accuracy is primarily guaranteed by the accuracy of the reference capacitor C_2 and the accuracy of the STM32 microcontroller's capture time. The former is obtained through a one-time precise calibration, while the latter is highly guaranteed by the high-speed hardware timer built into the modern STM32 microcontroller. This design approach shifts the focus of accuracy assurance from expensive analog hardware to flexible software algorithms and one-time calibration, significantly reducing the system's bill of materials (BOM).

[0192] Furthermore, this invention achieves a high degree of system integration, miniaturization, and flexibility. Specifically, the Boost-voltage multiplier power supply circuit adopts a high-frequency Boost boost + CW voltage multiplier chain topology. High-frequency operation (MHz level) allows the energy storage inductor L1 and all voltage multiplier capacitors to be small surface-mount components (SMD), completely eliminating the bulky and inefficient power frequency transformers used in traditional high-voltage power supplies. High voltage generation is also entirely based on integrated operational amplifiers and surface-mount components. The entire system can be integrated onto a very small printed circuit board (PCB), making it ideal for portable devices and space-constrained applications. The Boost-voltage multiplier power supply circuit employs a high-efficiency switching power supply and passive charge pump technology, achieving energy conversion efficiency far exceeding traditional linear regulators or transformer solutions, thereby reducing system power consumption and heat generation, making it particularly suitable for battery-powered applications. Complex measurement timing control, scan waveform generation (such as scan rate, step size, and voltage range), and error compensation algorithms are all implemented by the STM32 microcontroller's software (firmware). This hardware-software decoupling design brings great flexibility. Users can change test parameters, optimize compensation algorithms, and even add entirely new test functions (such as pulse Ct test) through simple firmware upgrades without making any hardware changes, giving the system strong scalability and lifespan.

[0193] This invention provides a complete, end-to-end high-precision capacitance measurement solution, fundamentally solving the core technical pain points when measuring slow-response, trap-containing, and other non-ideal devices. It also achieves significant comprehensive advantages in multiple dimensions such as system accuracy, stability, cost, size, and flexibility. It provides a powerful and easy-to-use new testing tool for semiconductor material research, device characterization, failure analysis, and other fields. It realizes high-precision, high-interference-resistant portable CV testing, and can complete the complete electrical characterization from fast pulse to quasi-static in the field environment, eliminating the dependence on expensive benchtop equipment.

[0194] Of course, the above description is only a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. It should be noted that any equivalent substitutions or obvious modifications made by those skilled in the art under the guidance of this specification fall within the scope of this specification and should be protected by the present invention.

Claims

1. A semiconductor device capacitance-voltage testing system, characterized in that, It includes a low-voltage power supply circuit, a Boost-voltage doubler power supply circuit, an MCU, a high-voltage bias control circuit, an AC / DC isolation circuit, and a differential pulse width modulation measurement circuit; The low-voltage power supply circuit provides the initial low-voltage power to the entire system; The Boost-voltage doubler power supply circuit is used to receive the low-voltage DC input from the low-voltage power supply circuit and generate a pair of stable, symmetrical and isolated high-voltage bipolar power rails as power rails for the high-voltage operational amplifier circuit. The high-voltage bias control circuit includes a signal processing circuit and a high-voltage operational amplifier circuit; The MCU outputs a low-voltage control signal through its built-in dual-channel DAC according to the preset scanning program; After the low-voltage control signal undergoes polarity conversion and buffering by the signal processing circuit, it is linearly amplified by the high-voltage operating discharge circuit, and the DC bias voltage from -90V to +90V is applied to the component under test (DUT) in differential form through the AC-DC isolation circuit. At each stable DC bias point, an AC measurement pulse is coupled to the DUT. The capacitance response of the DUT is captured by the differential pulse width modulation measurement circuit and converted into a signal in which the pulse width is monotonic with the capacitance value. This signal is eventually fed back to the input of the MCU, which calculates the actual capacitance value. The calculated actual capacitance value is paired with the current DC bias voltage to generate a CV curve point by point.

2. The semiconductor device capacitance-voltage testing system according to claim 1, characterized in that, The Boost-voltage doubler power supply circuit includes: The high-frequency boost circuit is used to initially boost the +3.3V DC input voltage of the received low-voltage power supply circuit and convert it from DC form into the high-frequency energy source required by the voltage multiplier circuit. And a Cockcroft-Walton voltage multiplier circuit with symmetrical topology is used to receive the high-frequency energy source output from the high-frequency boost circuit, and amplify its voltage amplitude step by step to the target value of ±90V through multi-stage passive charge pumping.

3. The semiconductor device capacitance-voltage testing system according to claim 2, characterized in that, The high-frequency boost converter circuit includes a high-frequency boost switching converter (U23) and an energy storage inductor (L1). The DC input voltage is applied to the input pin (VIN) and enable pin (EN) of the high-frequency boost switching converter (U23). The energy storage inductor (L1) is connected between the input pin (VIN) of the high-frequency boost switching converter (U23) and the internal power switch output pin (SW) of the high-frequency boost switching converter (U23); When the internal power switch output pin (SW) is grounded, a low-resistance path is formed from the input pin (VIN) through the energy storage inductor (L1) to ground; when the internal power switch output pin (SW) is suddenly turned off, the current path flowing through the energy storage inductor (L1) is cut off, and the magnetic field energy stored in the energy storage inductor (L1) is instantly converted into electrical energy. The internal power switch output pin (SW) outputs a square wave pulse as a high-frequency energy source for the voltage multiplier circuit. The high-frequency Boost converter circuit also includes a closed-loop feedback network for sampling from the internal power switch output pin (SW); the closed-loop feedback network consists of two voltage divider resistors (R30, R31), a Schottky diode (U24), and a capacitor (C39); A Schottky diode (U24) and a capacitor (C39) form a peak detector to capture the peak voltage of the output pulse from the internal power switch output pin (SW), while two voltage divider resistors (R30, R31) divide this peak voltage. The voltage after voltage division is sent to the feedback input pin (FB) of the high-frequency boost switching converter (U23). The high-frequency boost switching converter (U23) compares the voltage of the feedback input pin (FB) with the target voltage. If the voltage of the feedback input pin (FB) is higher than the target voltage, the on-time of the internal switch is reduced, i.e., the duty cycle is reduced. Conversely, if the voltage of the feedback input pin (FB) is not higher than the target voltage, the on-time of the internal switch is increased, i.e., the duty cycle is increased.

4. The semiconductor device capacitance-voltage testing system according to claim 3, characterized in that, The voltage multiplier circuit consists of two sets of five-stage CW voltage multiplier chains with completely mirrored structures and identical topologies; the input terminals of the two voltage multiplier chains are both connected to the output pin (SW) of the internal power switch and share the same high-frequency energy source; The two level 5 CW voltage multiplier chains are a positive +90V voltage multiplier chain and a negative -90V voltage multiplier chain, respectively; The positive +90V voltage multiplier chain adopts a five-stage pumping structure, which includes: Multiple coupling capacitors (C3, C40, C42, C44, C46), one end of which is connected to the SW excitation source of the high-frequency Boost circuit, for transferring energy in the AC cycle of the square wave; Multiple energy storage and filtering capacitors (C4, C41, C43, C45, C47) are used to store the charge pumped up by each stage of the pumping structure and gradually increase the DC voltage. And multiple rectifier diodes (U25, U26, U27, U28, U29, U30, U31, U32, U33, U12), which constitute a unidirectional charge transport path, ensuring that charge can only be pumped from low potential to high potential step by step; Each pumping structure consists of a coupling capacitor, two rectifier diodes, and an energy storage and filtering capacitor. The negative +90V voltage multiplier chain adopts a five-stage pumping structure, which includes: Multiple coupling capacitors (C22, C20, C18, C16, C14), one end of which is connected to the SW excitation source of the high-frequency Boost circuit, for transferring energy in the AC cycle of the square wave; Multiple energy storage and filtering capacitors (C23, C21, C19, C17, C15) are used to store the charge pumped up by each stage of the pumping structure and gradually increase the DC voltage. And multiple rectifier diodes (U13, U14, U15, U16, U17, U18, U19, U20, U21, U22), which constitute a unidirectional charge transport path, ensuring that charge can only be pumped from low potential to high potential step by step; Each pumping structure consists of a coupling capacitor, two rectifier diodes, and an energy storage and filtering capacitor. The orientation of all diodes in the negative -90V voltage multiplier chain is completely opposite to that of all diodes in the positive +90V voltage multiplier chain.

5. The semiconductor device capacitance-voltage testing system according to claim 1, characterized in that, The signal processing circuit includes a negative signal generation path and a signal merging path; The negative signal generation path includes a first operational amplifier (U10), an input resistor (R1), and a feedback resistor (R20); wherein the input resistor (R1) and the feedback resistor (R20) constitute an inverting amplifier. The second digital-to-analog converter output node (DAC2) of the MCU is connected to one end of the input resistor (R1); The second digital-to-analog converter output node (DAC2) outputs a voltage signal from 0 to 3.3V; The other end of the input resistor (R1) is connected to the inverting input terminal (1IN-) of the first operational amplifier (U10); the feedback resistor (R20) is connected between the output terminal (1OUT) and the inverting input terminal (1IN-) of the first operational amplifier (U10); The non-inverting input (1IN+) of the first operational amplifier (U10) is directly grounded; The output terminal (1OUT) of the first operational amplifier (U10) outputs a voltage from -3.3V to 0V; The signal combining path includes a second operational amplifier (U11), two input resistors (R21, R22), and a non-inverting adder consisting of a feedback network; this feedback network consists of two feedback resistors (R23, R24). The output terminal (1OUT) of the first operational amplifier (U10) is connected to one end of an input resistor (R21); the first digital-to-analog converter output node (DAC1) of the MCU is connected to one end of another input resistor (R22); The other ends of the two input resistors (R21, R22) are connected together to the non-inverting input (1IN+) of the second operational amplifier (U11); the output (1OUT) of the second operational amplifier (U11) is connected to its inverting input (1IN-) through a feedback network. The in-phase adder superimposes the positive signal from DAC1 of the MCU and the negative signal from U10; Since DAC1 and DAC2 are time-division driven, only one of the two inputs is non-zero at any given time; therefore, the output of U11 generates a continuous, seamless zero-crossing, low-voltage bipolar reference signal ranging from -3.3V to +3.3V.

6. The semiconductor device capacitance-voltage testing system according to claim 5, characterized in that, The high-voltage operational amplifier circuit includes a high-voltage operational amplifier (U9); the two power supply pins (V+, V-) of the high-voltage operational amplifier (U9) are connected to the +90V and -90V high-voltage power rails of the Boost-voltage doubler power supply circuit, respectively. The non-inverting input (+IN) of the high-voltage operational amplifier (U9) is directly connected to the output of the second operational amplifier (U11) to receive the bipolar low-voltage reference signal synthesized by the signal processing circuit. The high-voltage output (OUT) of the high-voltage operational amplifier (U9) is directly connected to one terminal of the device under test (DUT) through an AC-DC isolation circuit. The high-voltage operational amplifier (U9) is used to apply a DC bias voltage to the device under test (DUT). The high-voltage operational amplifier circuit also includes a closed-loop feedback network; the high-voltage output (OUT) of the high-voltage operational amplifier (U9) is fed back to the inverting input terminal (-IN) of the high-voltage operational amplifier (U9) through the closed-loop feedback network.

7. The semiconductor device capacitance-voltage testing system according to claim 1, characterized in that, The differential pulse width modulation measurement circuit includes: The differential pulse width modulation capacitance detection circuit is responsible for linearly converting the capacitance value of the component under test (DUT) into a differential square wave signal, the pulse width of which, i.e., the duty cycle, is proportional to the capacitance value. And an analog signal conditioning front-end circuit, used to perform low-pass filtering on the differential square wave signal, and demodulate it through subtraction and level-up operations to convert it into an analog signal whose voltage range matches the voltage range of the MCU's ADC.

8. The semiconductor device capacitance-voltage testing system according to claim 7, characterized in that, The differential pulse width modulation capacitance detection circuit is responsible for converting capacitance information into a differential square wave signal, and includes: The logic and drive unit (U3) uses a D-type flip-flop, and its positive modulation pulse output pin (1Q) and negative modulation pulse output pin (1Q#) provide complementary output signals as differential drive sources, denoted as u_A and u_B respectively; A dual comparator (U1) is used to sense the RC charging process and trigger the state toggling of the logic and drive unit (U3); The differential RC network consists of an upper arm charging path containing a charging resistor (R3) and a DUT, and a lower arm charging path containing a charging resistor (R4) and a reference capacitor (C2). And two reset diodes (D1, D2) and two isolation capacitors (C48, C49); The inverted modulation pulse output pin (1Q#) of the logic and drive unit (U3) is connected to the cathode of the reset diode (D1) and one end of the charging resistor (R3); the anode of the reset diode (D1) and the other end of the charging resistor (R3) are connected and connected to the DUT through the isolation capacitor (C48). The positive modulation pulse output pin (1Q) of the logic and drive unit (U3) is connected to the cathode of the reset diode (D2) and one end of the charging resistor (R4); the anode of the reset diode (D2) and the other end of the charging resistor (R4) are connected, and are in turn connected to the reference capacitor (C2), the isolation capacitor (C49) and the DUT.

9. The semiconductor device capacitance-voltage testing system according to claim 8, characterized in that, The analog signal conditioning front-end circuit includes a precision reference source (U8), an operational amplifier (U2), and an output filter; the operational amplifier (U2) adopts a two-stage operational amplifier structure to construct low-pass filtering, subtraction, and level-up circuits; The precision reference source (U8) serves as a precision reference source, providing a 1.6V reference voltage; The subtractor circuit consists of the first-stage operational amplifier of operational amplifier (U2), input resistors (R7, R8), pull-down resistor (R9), and feedback resistor (R10). It is used to subtract the voltage-divided u_A and u_B signals to obtain the difference signal u_AB and output it, where u_AB = u_A - u_B. The positive modulation pulse output pin (1Q) of the logic and drive unit (U3) is connected to one end of the input resistor (R8) through two voltage divider resistors (R6, R5), and the other end of the input resistor (R8) is connected to the inverting input terminal (1IN-) of the first stage operational amplifier of the operational amplifier (U2). One end of the input resistor (R7) is connected between the two voltage divider resistors (R6, R5), and the other end is connected to the positive input terminal (1IN+) of the first stage operational amplifier of the operational amplifier (U2); one end of the pull-down resistor (R9) is connected between the positive input terminal (1IN+) of the first stage operational amplifier and the input resistor (R7), and the other end is grounded; the feedback resistor (R10) is set between the output terminal (1OUT) of the first stage operational amplifier and the first negative input terminal (1IN-); The inverted modulation pulse output pin (1Q#) of the logic and drive unit (U3) is connected to the inverting input (1IN-) of the first stage operational amplifier of the operational amplifier (U2) through the input resistor (R8); the output (1OUT) of the first stage operational amplifier outputs the difference signal u_AB, which is used as the output input to the adder composed of the second stage operational amplifier of the operational amplifier (U2), two input resistors (R11, R12), and two feedback resistors (R13, R14); The output (1OUT) of the first-stage operational amplifier is connected to the positive input pin (2IN+) of the second-stage operational amplifier through the input resistor (R11); the 5V voltage is converted into a 1.6V reference voltage through the precision reference source (U8), and then connected to the positive input pin (2IN+) of the second-stage operational amplifier through the input resistor (R12). One feedback resistor (R14) is connected between the positive input pin (2IN+) and the output pin (2OUT) of the second-stage operational amplifier, and another feedback resistor (R13) is connected to the positive input pin (2IN+) at one end and grounded at the other end; The output signal (2OUT) of the second-stage operational amplifier is a DC analog voltage signal U_adc. The spike signal in the output signal is filtered out by the output filter and finally output through the H1 port, which is connected to the ADC of the MCU.

10. A method for testing the capacitance voltage of a semiconductor device, based on the semiconductor device capacitance voltage testing system according to any one of claims 1 to 9, characterized in that, The method includes the following steps: Step 1. Apply bias and stabilize the system; A target DC bias voltage is applied to the capacitor under test (DUT) through a high-voltage bias control circuit. The DC bias voltage is applied only to the DUT through an AC-DC isolation circuit. After the DC bias voltage is applied, the MCU waits for a preset time to allow the slow physical processes inside the DUT to fully respond and reach quasi-static equilibrium. Step 2. Baseline error assessment and measurement signal acquisition; After the waiting period ends, the MCU acquires the DC analog voltage signal U_adc output by the analog signal conditioning front-end circuit AFE; the MCU analyzes the U_adc signal and evaluates the equivalent baseline offset U_offset_measured caused by the slow response; Where U_offset_measured represents the DC offset in the AFE output caused by slow response non-ideal factors; The MCU further acquires the U_adc signal to obtain the raw ADC sample value ADC_measured_raw; Where ADC_measured_raw represents the uncorrected raw ADC sample value, and ADC_measured_raw contains the output generated by the capacitance information and the equivalent baseline offset U_offset_measured; Step 3. Software algorithm compensation; The MCU calculates a correction factor K_adc_compensated, which represents the correction factor used to compensate for the ADC sampled values; where K_adc_compensated is proportional to the equivalent baseline offset U_offset_measured. The MCU uses K_adc_compensated to correct ADC_measured_raw, thus obtaining the true ADC sample value: ADC_true = ADC_measured_raw - K_adc_compensated; Where ADC_true represents the ADC sampled value after correction, which reflects the DUT capacitance information; Step 4. Calculation of the capacitance under test: Based on ADC_true, the MCU uses the transfer function U_adc = M × U0 + N of the AFE to invert and obtain the theoretical DC voltage U0_compensated = (ADC_true - N) / M of the differential pulse width modulation (DPWM) core output. Where U0_compensated represents the compensated DPWM core output voltage obtained by AFE inversion; N represents the bias constant of AFE; M represents the gain coefficient of AFE; and U0 represents the compensated voltage value. The MCU substitutes U0_compensated into the theoretical model of the DPWM core, as shown in the following formula: U0 = U_high ×( (Cdut - C_ref) / (Cdut + C_ref) ); Where U_high represents the charging high level of the DPWM core; Cdut represents the capacitance value of the DUT; C_ref represents the known calibration value of the fixed reference capacitor C2; and the capacitance value Cdut of the DUT is calculated according to the above formula. MCU calculates the normalized intermediate variable X: X = U0_compensated / U_high: Where X represents the normalized ratio of U0_compensated to U_high; The MCU obtains the capacitance value of the DUT through algebraic operations, using the following formula: Cdut = C_ref× (1 + X) / (1 - X); Step 5. Data storage and iteration; The MCU pairs and stores the value of Cdut with the current target DC bias voltage, and iteratively executes steps 1 to 5 above to complete the CV characteristic curve measurement within the preset bias range.

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