Identifying thread errors

Abstract

The invention relates to identifying thread errors. Apparatuses, systems, and techniques for performing exclusive allocation of processing resources to applications in operation during operation to allow exclusive failure reporting between applications. In at least one embodiment, a processor includes one or more circuitry to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

Description

TECHNICAL FIELD

[0001] At least one embodiment is directed to assigning GPU processing resources to execute operational applications with as little resource downtime as possible while maintaining operational exclusivity. At least one embodiment is directed to keeping track of exclusive operational assignments to allow for exclusive fault reporting between multiple parallel operational applications. At least one embodiment is directed to causing execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one of the one or more threads encountering an error. BACKGROUND

[0002] Processor resource assignments can result in resources being idle at runtime and / or impede fault differentiation between one or more applications being executed in parallel. Methods for performing resource assignments within a processor, particularly a GPU, can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 An example of a fault identification system is shown in accordance with at least one embodiment;

[0004] Figure 2 An example of a reassignment request to modify an application’s access to processing resources is shown in accordance with at least one embodiment;

[0005] Figure 3 An example of a system for managing application processing resource needs is shown in accordance with at least one embodiment;

[0006] Figure 4 An example process for altering an application’s processing resource needs and recording the alterations to the application’s processing resource needs is shown in accordance with at least one embodiment;

[0007] Figure 5 An example of a processor is shown in accordance with at least one embodiment;

[0008] Figure 6 An example data center is shown in accordance with at least one embodiment;

[0009] Figure 7 A processing system is shown in accordance with at least one embodiment;

[0010] Figure 8 A computer system is shown in accordance with at least one embodiment;

[0011] Figure 9 A system is shown in accordance with at least one embodiment;

[0012] Figure 10An exemplary integrated circuit is shown in accordance with at least one embodiment;

[0013] Figure 11 A computing system is shown in accordance with at least one embodiment;

[0014] Figure 12 An APU is shown in accordance with at least one embodiment;

[0015] Figure 13 A CPU is shown in accordance with at least one embodiment;

[0016] Figure 14 An exemplary accelerator integration slice is shown in accordance with at least one embodiment;

[0017] Figures 15A-15B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0018] Figure 16A A graphics core is shown in accordance with at least one embodiment;

[0019] Figure 16B A GPGPU is shown in accordance with at least one embodiment;

[0020] Figure 17A A parallel processor is shown in accordance with at least one embodiment;

[0021] Figure 17B A processing cluster is shown in accordance with at least one embodiment;

[0022] Figure 17C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0023] Figure 18 A graphics processor is shown in accordance with at least one embodiment;

[0024] Figure 19 A processor is shown in accordance with at least one embodiment;

[0025] Figure 20 A processor is shown in accordance with at least one embodiment;

[0026] Figure 21 A graphics processor core is shown in accordance with at least one embodiment;

[0027] Figure 22 A PPU is shown in accordance with at least one embodiment;

[0028] Figure 23 A GPC is shown in accordance with at least one embodiment;

[0029] Figure 24A stream multiprocessor is shown in accordance with at least one embodiment;

[0030] Figure 25 A software stack of a programming platform is shown in accordance with at least one embodiment;

[0031] Figure 26 A CUDA implementation of the software stack of Figure 25 is shown in accordance with at least one embodiment;

[0032] Figure 27 A ROCm implementation of the software stack of Figure 25 is shown in accordance with at least one embodiment;

[0033] Figure 28 An OpenCL implementation of the software stack of Figure 25 is shown in accordance with at least one embodiment;

[0034] Figure 29 Software supported by a programming platform is shown in accordance with at least one embodiment;

[0035] Figure 30 Compiled code executed on the programming platform of Figures 25-28 is shown in accordance with at least one embodiment;

[0036] Figure 31 More detailed compiled code executed on the programming platform of Figures 25-28 is shown in accordance with at least one embodiment;

[0037] Figure 32 Conversion of source code prior to compilation of the source code is shown in accordance with at least one embodiment;

[0038] Figure 33A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0039] Figure 33B A system configured to compile and execute CUDA source code of Figure 33A using a CPU and a CUDA-enabled GPU is shown in accordance with at least one embodiment;

[0040] Figure 33C A system configured to compile and execute CUDA source code of Figure 33A using a CPU and a non-CUDA-enabled GPU is shown in accordance with at least one embodiment;

[0041] Figure 34 An exemplary kernel converted by the CUDA to HIP conversion tool of Figure 33C is shown in accordance with at least one embodiment;

[0042] Figure 35 FIG. 1 illustrates a system for migrating CUDA code to data parallel C++ code according to at least one embodiment; Figure 33C FIG. 2 illustrates a non-CUDA-enabled GPU according to at least one embodiment;

[0043] Figure 36 FIG. 3 illustrates how threads of an exemplary CUDA grid are mapped to different compute units of a GPU according to at least one embodiment; Figure 35 FIG. 4 illustrates how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment; and

[0044] Figure 37 FIG. 5 illustrates components of a system for accessing large language models according to at least one embodiment.

[0045] Figure 38 FIG. 6 illustrates a flow diagram of a method for migrating CUDA code to data parallel C++ code according to at least one embodiment. DETAILED DESCRIPTION

[0046] In the following description, numerous specific details are set forth to provide a thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept can be practiced without one or more of these specific details.

[0047] In at least one embodiment, systems and methods implemented in accordance with the present disclosure are used to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one of the one or more threads encountering an error.

[0048] In at least one embodiment, a running GPU executes an application (e.g., a process, a client, a kernel, and / or other designation of software executed by one or more GPUs) on one or more SMs (e.g., stream multiprocessors, compute units, CUDA cores, stream processors, cores, and / or other designation of a processing compute group). In at least one embodiment, the SMs execute threads of an application, where the application is coded as one or more sequences of instructions to be executed. In at least one embodiment, an application can be assigned an exclusively assigned SM, where only that application can be executed by threads executed by one or more kernels executed by the indicated SM, but not by threads executed by other SMs. In at least one embodiment, usage of SMs by a given application can vary, resulting in one or more SMs being idle during runtime. In at least one embodiment, assigning exclusively assigned SMs allows a fault reporting structure to isolate fault reporting based on resolution to a single SM. In at least one embodiment, in these fault reporting systems, a SM can report a fault, but due to potential fault eliminating ability to report operational data (e.g., a fault causes one or more corresponding SMs to be completely unable to report any information indicative of a cause of the fault), a driver receiving the fault indication can be unable to accurately identify which SM failed and at what time. In at least one embodiment, an application can use one or more systems to allow for scaling running resources without exclusivity. In at least one embodiment, for example, in a pool of 100 SMs designated as SM1-SM100, a first application (“application 1”) can run in a range of SM1-SM60. In at least one embodiment, a second application (“application 2”) can run in a range of SM40-SM100. In at least one embodiment, without other applications, SM1-39 and SM61-100 are dedicated to respective applications, but SM40-SM60 are capable of executing portions of either application as needed. In at least one embodiment, such a system can improve running efficiency, as it reduces a likelihood of running loss due to SM idleness. In at least one embodiment, for example, if SM50 fails, an operational driver can be unable to identify which designated application was actively executing at time of failure, and thus must terminate both applications to prevent risk. In at least one embodiment, a third application (“application 3”) designated to execute only on SM1-SM5 can not have to be terminated if it is also executing, as only applications 1 and 2 can have been executing on SM50 at time of failure.

[0049] In at least one embodiment, a system can be implemented in which exclusively assigned SMs are assigned to a given core and / or thread, with operating SM assignment made at the start of processing. In at least one embodiment, the system is used to enable a certain request source (e.g., an operating application, an idle SM, an operating driver, and / or any other source needed to allow accurate application of SMs related to application needs) to issue a software request to generate and / or change SM exclusive assignments. In at least one embodiment, such a system is used to pause operation, reassign exclusive assigned SM rights to reallocate them to needed needs, and resume operation using these new assignments. In at least one embodiment, such a system is used to maintain a tracking system (e.g., a table, a database, a hash, an ordered list, and / or any other method for tracking operating assignments) to track changes in SM assignments. In at least one embodiment, such a system is used to enable changes in SM needs for running an application while maintaining exclusivity of SMs to isolate error reporting for a faulty SM, allowing for selective stopping (e.g., termination, pausing, and / or rescheduling one or more threads, cores, and / or other processing designations) of faulty threads executing on the faulty SM. In at least one embodiment, such a system and method of tracking changes in SM assignments enables identification of information associated with a faulty application and / or thread regardless of availability of that information from SM reporting.

[0050] In the foregoing and following description, various techniques are described. For the sake of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the techniques implemented. However, it will also be apparent to one skilled in the art that the techniques described below can be practiced in different configurations without the specific details. In addition, well-known features can be omitted or simplified in order not to obscure the techniques being described.

[0051] In at least one embodiment, as used in any implementation described herein, the term “module” refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein unless otherwise specified or understood from context. In at least one embodiment, software can be embodied as software packages, code, and / or instructions that are executable on a processing circuit, and “hardware” as used in any implementation described herein can include, among other things, fixed functions circuits, programmable circuits, state machine circuits, fixed function circuits, execution unit circuits, and / or firmware that is stored in memory and executed on processing circuitry. In at least one embodiment, a module can be embodied by a circuit that is part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), etc.).

[0052] In at least one embodiment, systems such as system 100, system 200, system 300, process 400, and / or system 500 include a set of one or more hardware and / or software computing resources having instructions that, when executed, perform one or more communication processes such as those described herein. In at least one embodiment, system 100, system 200, system 300, process 400, and / or system 500 include one or more software programs executable on computer hardware, one or more applications executable on computer hardware, and / or variations thereof. In at least one embodiment, one or more processes of system 100, system 200, system 300, process 400, and / or system 500 are performed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU), as described below) in any suitable manner, including sequentially, in parallel, and / or variations thereof. In at least one embodiment, system 100, system 200, system 300, process 400, and / or system 500 implement and perform operations described herein using a machine learning training framework such as PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks, such that execution of one or more threads corresponding to one or more respective kernels is selectively stopped based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, as an example, training a neural network model includes using a server (e.g., an NVIDIA DGX server) that further includes at least a GPU (e.g., an AMD MI200, VEGAL 10, VEGO20, and ARCTURUS), an optimizer (e.g., an ADAM OPTIMIZER), or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using a GAN loss).

[0053] Figure 1An example of a fault identification system 100 ("system 100") is shown, in accordance with at least one embodiment. In at least one embodiment, system 100 includes a processor 102, an application 1 108, an application 2 110, and / or a fault 114. In at least one embodiment, processor 102 includes an application assigner 104. In at least one embodiment, application assigner 104 includes an exclusive mask 112. In at least one embodiment, application 1 108 and / or application 2 110 include one or more SMs 106A-D (referred to herein individually and / or collectively as "SMs 106"). In at least one embodiment, one or more SMs 106 are included in either of application 1 108 and application 2 110. In at least one embodiment, SMs 106 (e.g., stream multiprocessors, compute units, stream processors, and / or shared processors) are compute groups within a GPU.

[0054] In at least one embodiment, a processor (such as processor 102) is used to indicate information, such as information indicating a processor (e.g., Figure 5 502) of a GPU. In at least one embodiment, processor 102 is an external combination of hardware and / or software that executes a process (e.g., Figure 4 400) in at least one embodiment. In at least one embodiment, processor 102 can be a CPU that executes GPU task driver software. In at least one embodiment, processor 102 executes application assigner 104 and / or maintains tracking software to maintain a list of SM and / or other sub-processor designations assigned to any given application running under said active driver control. In at least one embodiment, processor 102 can receive notification of a fault 114. In at least one embodiment, if such notification is received, processor 102 can refer to said tracking of sub-processor assignments to determine which application (e.g., application 1 108 and / or application 2 110) faulted, resulting in the indicated application being terminated.

[0055] In at least one embodiment, a processor (e.g., Figure 5The processor(s) 502 in the system 500 uses the application assigner 104 to indicate information, such as information indicative of programs that direct GPU operations (e.g., GPU drivers and / or one or more portions of one or more GPU drivers). In at least one embodiment, the application assigner 104 is software that manages the exclusive mask 112 and any other hardware, software, and / or combinations thereof necessary to maintain GPU operations. In at least one embodiment, the application assigner 104 can assign a sub-processor (e.g., SM 106) to any particular application (e.g., application 1 108 and / or application 2 110) to allow it to run, preventing said application from executing on any more sub-processors than indicated. In at least one embodiment, the application assigner 104 can maintain a record of assignments made to one or more applications to allow external or post-processing determinations of SM assignments at a given time. In at least one embodiment, the application assigner 104 can receive a request to change SM assignments corresponding to one or more applications, resulting in a suspension of operations, a change of assigned SMs, a record of new assignments and / or other specified information, and a resumption of operations under the new assignments.

[0056] In at least one embodiment, the processor(s) (e.g., Figure 5 The processor(s) 502 in the system 500 uses the one or more SMs 106 to indicate information, such as information representative of streaming multiprocessors, compute units, stream processors, GPU cores, or any other subset of processing units within a processor, particularly a GPU. In at least one embodiment, the SM 106 can be part of a designated operation assignment for an application being executed by a controlled processor. In at least one embodiment, the SM 106 performs computational operations related to an application (e.g., application 1 108 and / or application 2 110) that has been assigned and is running. In at least one embodiment, the SM 106 can be assigned to execute one application exclusively. In at least one embodiment, the SM 106 can be assigned to two or more applications simultaneously. In at least one embodiment, in such a case, the SM 106 is executing one of its potential applications at any time. In at least one embodiment, the SM 106 has a priority structure that prevents an application from preventing an application already running from running. In at least one embodiment, the SM 106 executes one or more software threads corresponding to one or more kernels, any one of which can fault, causing a fault report (e.g., fault 114) to be generated. In at least one embodiment, the SM 106 can fault, causing a fault report (e.g., fault 114) to be generated.

[0057] In at least one embodiment, the processor(s) (e.g.,Figure 5 The processor 502 uses applications (e.g., application 1 108 and / or application 2 110) to indicate information, such as information indicating scheduled applications (e.g., clients, processes, and / or other designations of software executed by the processor) running within one or more SMs within the processor (particularly the GPU). In at least one embodiment, applications may be designated to perform processing work on one or more SMs. In at least one embodiment, an application may generate a fault (e.g., fault 114) due to a processing failure in the hardware and / or software. In at least one embodiment, the application generating the fault may generate another fault while also reporting the fault. In at least one embodiment, in this case, the non-exclusive reporting structure cannot identify more than one fault, which results in any fault requiring the termination of all possible applications. In at least one embodiment, the non-exclusive reporting structure allows any given set of one or more SMs to be assigned to more than one application simultaneously. In at least one embodiment, the SMs executing within such assignments execute one of the assignments at any given time. In at least one embodiment, the application that reports a fault using an exclusively assigned SM (e.g., where the SM is only assigned to execute threads and / or kernels associated with only one application, such as application 1 108 or application 2 110) can allow for guaranteed exclusive application faults, thereby allowing fault-free applications to continue running while exclusively terminating the faulty application. In at least one embodiment, it may be impossible to determine which assigned application was executing a fault generated by one or more non-exclusively assigned SMs (e.g., fault 114) at the time of the fault, resulting in the termination of all potential applications.

[0058] In at least one embodiment, the processor (e.g., Figure 5 The processor 502 in the process uses an exclusivity mask 112 to indicate information, such as hardware and / or software information that allows the scope of one or more SMs to be exclusively assigned to one or more applications. In at least one embodiment, the exclusivity mask 112 operates as part of the application assigner 104 to allow applications to run on no more than one or more sets of SMs.

[0059] In at least one embodiment, the processor (e.g., Figure 5The processor 502 in the process uses fault 114 to indicate information such as a reported malfunction, runtime error, failure, and / or other failure-specific information indicating the inability to continue processing a thread corresponding to the kernel. In at least one embodiment, fault 114 is generated by one or more SMs executing one or more parts of an application. In at least one embodiment, fault 114 indicates a fault in an SM exclusive to other SMs. In at least one embodiment, fault 114 indicates a fault in an SM, a thread executing on said SM, and / or the kernel corresponding to said thread. In at least one embodiment, fault 114 may not indicate which application was running at the time of the fault. In at least one embodiment, fault 114 is used to identify a faulty and / or potentially faulty application, thereby terminating said application.

[0060] In at least one embodiment, system 100 includes one or more processors configured to cause the execution of one or more threads corresponding to one or more respective cores to selectively halt, at least in part, based on at least one of the one or more threads encountering an error, and / or otherwise perform the operations described herein. In at least one embodiment, system 100 is Figures 1-5 The system shown is included Figures 1-5 The system shown and / or otherwise includes Figures 1-5 The system shown is configured such that the execution of one or more threads corresponding to one or more corresponding kernels is selectively halted, at least in part, based on at least one of the one or more threads encountering an error, and / or the operations described herein are performed in a different manner. In at least one embodiment, system 100 performs... Figures 1-5 The illustrated one or more processes, such as those for causing the execution of one or more threads corresponding to one or more corresponding kernels to selectively stop at least in part based on at least one of the one or more threads encountering an error, and / or otherwise performing the operations described herein. In at least one embodiment, system 100 performs... Figures 6-38 The one or more processes shown, such as those for causing the execution of one or more threads corresponding to one or more corresponding kernels to be selectively stopped at least in part based on at least one of the one or more threads encountering an error, and / or otherwise performing the operations described herein.

[0061] Figure 2An example system 200 for processing resource assignments is shown according to at least one embodiment. In at least one embodiment, system 200 includes a reassignment request 202, an application assigner 104, an original application assignment 204, a modified application assignment 206, and / or one or more SMs 106. In at least one embodiment, system 200 is used to... Figure 1 One or more components of system 100.

[0062] In at least one embodiment, the processor (e.g., Figure 5 The processor 502 in the process uses a reassignment request 202 to indicate information, such as information indicating a request from a user (e.g., a user interface), that indicates changes to one or more applications (e.g., the original application assignment 204) utilizing exclusively assigned SMs (which cannot execute the application with the desired efficiency), to expand the specified exclusively assigned SMs. In at least one embodiment, the reassignment request 202 is generated by the user and / or user interface and / or application scheduling and assignment software (e.g., a GPU driver) to indicate the expansion or reduction of the required operational SMs for a given application. In at least one embodiment, it is generated by an application assigner (e.g., ...). Figure 1 The application assigner 104 in the application receives a reassignment request 202 to allow a pause in operation, thereby allowing a new exclusive SM assignment. In at least one embodiment, the reassignment request 202 may be an API (Application Programming Interface) call, information saved to shared memory, and / or any indication of a requested change to the SM assignment. In at least one embodiment, for example, the indicated original assignment (e.g., original application assignment 204) may not have the required operating resources, so the application may generate a reassignment request 202 to indicate a new required operating assignment (e.g., the application-modified assignment 206). In at least one embodiment, if possible, the application assigner (e.g., ...) receives a reassignment request 202 to allow a pause in operation, thereby allowing a new exclusive SM assignment. Figure 1 The application assigner 104 in the middle can pause the operation, reassign the exclusive SM access, and resume the operation of the requesting application using the new extended or reduced SM assignment.

[0063] In at least one embodiment, the processor (e.g., Figure 5 The processor 502 in the process uses application assignments (e.g., original application assignment 204 and / or modified application assignment 206) to indicate information, such as instructions to be given by the processor (e.g., Figure 5information accessed by the operations of a given application performed by one or more SMs within the processor 502). In at least one embodiment, application assignments include one or more SMs that are exclusively assigned to an indicated application, which indicates a maximum number of SMs that the application can operate on. In at least one embodiment, application assignments can be recorded within application assignor 104 to maintain a record of the assigned SM assignments. In at least one embodiment, application assignments can prevent other applications from causing any given SM and / or set of SMs to be assigned to any other application.

[0064] In at least one embodiment, system 200 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to be selectively stopped based at least in part on at least one thread of the one or more threads encountering an error, and / or to perform other operations as described herein. In at least one embodiment, system 200 is Figures 1-5 In at least one embodiment, system 200 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to be selectively stopped based at least in part on at least one thread of the one or more threads encountering an error, and / or to perform other operations as described herein. In at least one embodiment, system 200 is Figures 1-5 In at least one embodiment, system 200 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to be selectively stopped based at least in part on at least one thread of the one or more threads encountering an error, and / or to perform other operations as described herein. In at least one embodiment, system 200 is Figures 1-5 In at least one embodiment, system 200 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to be selectively stopped based at least in part on at least one thread of the one or more threads encountering an error, and / or to perform other operations as described herein. In at least one embodiment, system 200 is Figures 1-5 In at least one embodiment, system 200 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to be selectively stopped based at least in part on at least one thread of the one or more threads encountering an error, and / or to perform other operations as described herein. In at least one embodiment, system 200 is Figures 6-38 In at least one embodiment, system 200 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to be selectively stopped based at least in part on at least one thread of the one or more threads encountering an error, and / or to perform other operations as described herein. In at least one embodiment, system 200 is

[0065] Figure 3An example system 300 for managing application processing resource requirements is illustrated according to at least one embodiment. In at least one embodiment, system 300 includes a runtime driver 302 and / or a processor 308. In at least one embodiment, runtime driver 302 includes one or more input reassignment requests 202, an application assigner 104, an application assignment table 304, and / or one or more output operation assignments 306. In at least one embodiment, processor 308 is used to execute application 1 108 and / or application 2 110.

[0066] In at least one embodiment, the processor (e.g., Figure 5 The processor 502 in the process uses the runtime driver 302 to indicate information, such as instructing the execution of operations to maintain and control one or more processors (e.g., Figure 3 and / or Figure 5 The runtime driver 302 provides information on the hardware and / or software operations of processes within processor 308 and / or processor 502. In at least one embodiment, the runtime driver 302 may be executed by one or more GPUs, CPUs, GPGPUs, and / or other processors. In at least one embodiment, the runtime driver 302 receives input in the form of a reassignment request 202, which instructs the reassignment of assigned SMs for one or more applications. In at least one embodiment, the runtime driver 302 outputs an operation assignment 306, which reassigns the SMs to all applications executed by processor 308. In at least one embodiment, the runtime driver 302 also executes an application assigner 104 to perform reassignment and maintain an application assignment table in memory. In at least one embodiment, the runtime driver 302 may be terminated, thereby terminating all applications controlled by said runtime driver 302 and / or continuing to operate under the control of one or more other runtime drivers 302.

[0067] In at least one embodiment, the processor (e.g., Figure 5application assigner 104 and / or runtime driver 302 to determine a failing application using application assignment table 304 ("table 304"). In at least one embodiment, table 304 is data stored in memory. In at least one embodiment, table 304 allows a failing SM to be referenced to table 304, thereby allowing a determination of which application a failing SM was assigned to, in order to allow exclusive termination of the application. In at least one embodiment, table 304 can be converted to data to be stored in memory after completion of processing of one or more applications. In at least one embodiment, table 306 allows application assigner 104 and / or runtime driver 302 to determine a failing application.

[0068] In at least one embodiment, processor (e.g., processor 502) in system 500 uses processor 308 to indicate information such as information indicating one or more processing units (e.g., GPUs, CPUs, GPGPUs, and / or any other designation of processing units) executing one or more applications (e.g., application 1 108 and / or application 2 110) in Figure 2 In at least one embodiment, processor (e.g., processor 502) in system 500 uses processor 308 to indicate information such as information indicating one or more processing units (e.g., GPUs, CPUs, GPGPUs, and / or any other designation of processing units) executing one or more applications (e.g., application 1 108 and / or application 2 110) in Figure 1 In at least one embodiment, processor 308 is processor 502 in system 500. In at least one embodiment, processor 308 is any combination of hardware and / or software for executing one or more applications under control of one or more runtime drivers 302. Figure 5 In at least one embodiment, processor 308 is processor 502 in system 500. In at least one embodiment, processor 308 is any combination of hardware and / or software for executing one or more applications under control of one or more runtime drivers 302.

[0069] In at least one embodiment, system 300 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error, and / or to otherwise perform operations described herein. In at least one embodiment, system 300 is a system shown in Figures 1-5 In at least one embodiment, system 300 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error, and / or to otherwise perform operations described herein. In at least one embodiment, system 300 is a system shown in Figures 1-5 In at least one embodiment, system 300 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error, and / or to otherwise perform operations described herein. In at least one embodiment, system 300 is a system shown in Figures 1-5 In at least one embodiment, system 300 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error, and / or to otherwise perform operations described herein. In at least one embodiment, system 300 is a system shown in Figures 1-5one or more processes discussed in the background, such as for causing execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one of the one or more threads encountering an error, and / or otherwise performing the operations described herein. In at least one embodiment, system 300 performs Figures 6-38 one or more processes discussed in the background, such as for causing execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one of the one or more threads encountering an error, and / or otherwise performing the operations described herein.

[0070] Figure 4 A flow diagram illustrating an example process 400 for altering and recording changes to application processing resource requirements is shown in accordance with at least one embodiment. In at least one embodiment, one or more processors (e.g., processor(s) 502 in system 500) Figure 5 In at least one embodiment, process 400 is used by processor(s) 502 in system 500 to reassign exclusively assigned operational SMs between one or more applications during runtime. In at least one embodiment, process 400 includes one or more steps: start 402, then iterate to receive a reassignment request 404, then pause operations 406, then reassign exclusively assigned SMs 408, then update assignment tracking 410, then resume operations 412, then end 414. In at least one embodiment, process 400 then continues to output an updated tracking indication for SM assignments and continues operations until one or more new indicated reassignment requests are provided.

[0071] In at least one embodiment, part or all of process 400 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions to cause the functionality described herein and is implemented as a computer-implemented process stored in computer-readable storage medium that, when executed by a computer system, causes the computer system to perform steps of the process. Figure 5the code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) collectively executed on the processor(s) 502 in the computing device 500. In at least one embodiment, the code is stored on a computer-readable storage medium that represents a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, computer-readable instructions used to perform at least some of process 400 are not stored only using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not include a transitory signal’s in-transceiver data storage circuitry (e.g., buffers, caches, and queues). In at least one embodiment, process 400 is performed at least in part on a computer system such as the computer systems described elsewhere in this disclosure. In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 400.

[0072] In at least one embodiment, a processor (e.g., Figure 5 In at least one embodiment, a processor (e.g., Figure 1 In at least one embodiment, process 400 can then iterate to receive reassignment requests 404, where one or more reassignment requests are received (e.g., by one or more application assigners 104 in the computing device 500) and processed to determine new SM assignments between the currently operating applications. In at least one embodiment, process 400 can then iterate to suspend operations 406, where operations on all applications and / or all applications within the scope of the requested changes to SM assignments are suspended to prevent further operations, and / or new operations are suspended. In at least one embodiment, suspending operations and / or starting operations are not required, and SM assignments can be updated without suspension during active runtime. In at least one embodiment, process 400 can then iterate to reassign exclusively assigned SMs 408, where the newly determined SM assignments (e.g., application changed assignments 206 in the computing device 500) are applied, overriding previous assignments to allocate new operational resource limits for operating applications. In at least one embodiment, process 400 can then iterate to update assignment tracking 410, where application tracking (e.g., application tracking 208 in the computing device 500) is updated to reflect the newly determined SM assignments. In at least one embodiment, process 400 can then iterate to resume operations 412, where operations on all applications and / or all applications within the scope of the requested changes to SM assignments are resumed to allow further operations, and / or new operations are resumed. In at least one embodiment, process 400 can then iterate to end 414, where process 400 ends. Figure 2 In at least one embodiment, process 400 can then iterate to receive reassignment requests 404, where one or more reassignment requests are received (e.g., by one or more application assigners 104 in the computing device 500) and processed to determine new SM assignments between the currently operating applications. In at least one embodiment, process 400 can then iterate to suspend operations 406, where operations on all applications and / or all applications within the scope of the requested changes to SM assignments are suspended to prevent further operations, and / or new operations are suspended. In at least one embodiment, suspending operations and / or starting operations are not required, and SM assignments can be updated without suspension during active runtime. In at least one embodiment, process 400 can then iterate to reassign exclusively assigned SMs 408, where the newly determined SM assignments (e.g., application changed assignments 206 in the computing device 500) are applied, overriding previous assignments to allocate new operational resource limits for operating applications. In at least one embodiment, process 400 can then iterate to update assignment tracking 410, where application tracking (e.g., application tracking 208 in the computing device 500) is updated to reflect the newly determined SM assignments. In at least one embodiment, process 400 can then iterate to resume operations 412, where operations on all applications and / or all applications within the scope of the requested changes to SM assignments are resumed to allow further operations, and / or new operations are resumed. In at least one embodiment, process 400 can then iterate to end 414, where process 400 ends. Figure 3application assignment table 304) is updated (e.g., by one or more application assigners 104 in Figure 1 application assignment table 304) is updated (e.g., by one or more application assigners 104 in

[0073] In at least one embodiment, a processor uses process 400 including one or more steps for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, by way of example, a machine-readable medium having stored thereon a set of instructions which, if executed by one or more processors, cause the one or more processors to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, process 400 includes Figures 1-5 the system shown in FIG. 8, included in the system shown in FIG. 9, and / or otherwise includes the system shown in FIG. 10 for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, process 400 is performed by one or more systems shown in FIG. 8, such as for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. Figures 1-5 the system shown in FIG. 8, included in the system shown in FIG. 9, and / or otherwise includes the system shown in FIG. 10 for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, process 400 is performed by one or more systems shown in FIG. 8, such as for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. Figures 1-5 the system shown in FIG. 8, included in the system shown in FIG. 9, and / or otherwise includes the system shown in FIG. 10 for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, process 400 is performed by one or more systems shown in FIG. 8, such as for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. Figures 1-5 the system shown in FIG. 8, included in the system shown in FIG. 9, and / or otherwise includes the system shown in FIG. 10 for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, process 400 is performed by one or more systems shown in FIG. 8, such as for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. Figures 6-38 the system shown in FIG. 8, included in the system shown in FIG. 9, and / or otherwise includes the system shown in FIG. 10 for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, process 400 is performed by one or more systems shown in FIG. 8, such as for causing execution of one or more threads corresponding to one or more respective cores to be selectively stopped and / or otherwise perform operations described herein based at least in part on at least one of the one or more threads encountering an error.

[0074] Figure 5An example system 500 of a processor is shown in accordance with at least one embodiment. In at least one embodiment, processor 502 executes one or more processes such as those described herein to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, processor 502 executes processes described in connection with Figures 1-5 those described in connection with Figures 6-38 those described in connection with

[0075] In at least one embodiment, processor 502 includes one or more processors such as those described in connection with Figures 6-38 In at least one embodiment, processor 502 is any suitable processing unit and / or combination of processing units such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof. In at least one embodiment, processor 502 includes one or more SM assignment tracking modules 504, communication modules 506, driver modules 508, and / or operation modules 510. In at least one embodiment, SM assignment tracking modules 504, communication modules 506, driver modules 508, and / or operation modules 510 are part of processor 502 and / or one or more other processors. In at least one embodiment, SM assignment tracking modules 504, communication modules 506, driver modules 508, and / or operation modules 510 are distributed over a plurality of processors that communicate by way of a bus, network, by writing to shared memory, and / or any suitable communication process, such as those described herein.

[0076] In at least one embodiment, as used in any implementation described herein, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment “hardware”, as used in any implementation described herein, can include, for example, either alone or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry. In at least one embodiment, a module can be embodied by a circuit that is part of a larger system, for example, an integrated circuit (IC), system on chip (SoC), etc. In at least one embodiment, a module is in combination or in combination with any suitable processing unit and / or combination of processing units such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.

[0077] In at least one embodiment, the processor uses the SM assignment tracking module 504 to reassign operational resources within the managed processor used to operate applications and maintains one or more systems to track changes made, thereby allowing proactive runtime assignment checks. In at least one embodiment, the SM assignment tracking module 504 provides output to the communication module 506, driver module 508, and / or operation module 510 in the form of operational assignments for active applications, tracking data associated with said assignments, and / or other data required to track and assign SMs among one or more operational applications. In at least one embodiment, the SM assignment tracking module 504 receives input in the form of requests to change operational SM assignments, instructions to change operational SM assignments, and / or instructions for desired changes to operational SM assignments and / or other data required to track said assignments. In at least one embodiment, the SM assignment tracking module 504 performs a reassignment of operational resources within the managed processor used to operate the application and maintains one or more systems to track changes made, allowing for proactive runtime assignment checks in conjunction with any suitable processing unit and / or combination of processing units (such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof).

[0078] In at least one embodiment, the processor uses communication module 506 to facilitate and perform communication between one or more other modules, system memory and / or external systems, modules and / or memories required for the operation of applications and modules. In at least one embodiment, communication module 506 sends reassignment requests for SM assignments, operation assignments for operating applications, and / or other information and / or communications required for the execution of other modules and / or applications to SM assignment tracking module 504, driver module 508, operation module 510, system memory and / or processes (e.g., ...). Figure 4 The communication module 506 provides output to other hardware and / or software locations required for the operation of process 400. In at least one embodiment, the communication module 506 receives input in the form of any data that needs to be input and / or output to allow operation of the application and / or module within processor 502. In at least one embodiment, the communication module 506, in conjunction with any suitable processing unit and / or combination of processing units (such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof), facilitates and performs communication between one or more other modules, system memory, and / or external systems, modules, and / or memory required for the operation of the application and module.

[0079] In at least one embodiment, processor uses driver module 508 to perform operations necessary to maintain and facilitate operation of other modules within processor 502 and / or applications within those other modules. In at least one embodiment, driver module 508 provides output to communication module 506 in form of data related to operational processes to facilitate operation within one or more other modules of processor 502. In at least one embodiment, driver module 508 receives input in form of data to allow representation of operational status within other modules of processor 502. In at least one embodiment, driver module 508 in combination with any suitable processing unit and / or combination of processing units such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof, performs operations necessary to maintain and facilitate operation of other modules within processor 502 and / or applications within those other modules.

[0080] In at least one embodiment, processor uses operation module 510 to execute one or more applications managed by one or more driver modules 508 and / or SM assignment tracking module 504. In at least one embodiment, operation module 510 provides output to communication module 506 in form of data indicative of operations of one or more operating applications executed by one or more SMs within one or more processors (e.g., processor 502) or resulting from operations of one or more operating applications executed by one or more SMs within one or more processors (e.g., processor 502). In at least one embodiment, operation module 510 receives input in form of data relayed from system memory and / or operational assignments and / or instructions to facilitate and coordinate operations of applications within processors (e.g., Figure 5 In at least one embodiment, operation module 510 in combination with any suitable processing unit and / or combination of processing units such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof, executes one or more applications managed by one or more driver modules 508 and / or SM assignment tracking module 504.

[0081] In at least one embodiment, system 500 includes one or more processors to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop and / or otherwise perform operations described herein based at least in part on at least one thread of said one or more threads encountering an error. In at least one embodiment, system 500 is a system shown in Figures 1-5 In at least one embodiment, system 500 is a system shown in Figures 1-5 In at least one embodiment, system 500 is a system shown in Figures 1-5The system shown is configured to cause the execution of one or more threads corresponding to one or more respective kernels to selectively halt and / or otherwise perform the operations described herein, at least in part, based on at least one of the one or more threads encountering an error. In at least one embodiment, system 500 executes... Figures 1-5 The processes shown herein, such as those for causing the execution of one or more threads corresponding to one or more corresponding kernels to selectively stop and / or otherwise perform the operations described herein based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, system 500 executes... Figures 6-38 The one or more processes shown herein, such as those for causing the execution of one or more threads corresponding to one or more corresponding kernels to be selectively stopped and / or otherwise performed based on at least one of the one or more threads encountering an error.

[0082] Data Center

[0083] Figure 6 An example data center 600 according to at least one embodiment is shown. In at least one embodiment, the data center 600 includes, but is not limited to, a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640.

[0084] In at least one embodiment, such as Figure 6 As shown, the data center infrastructure layer 610 may include a resource coordinator 612, grouped computing resources 614, and node computing resources (“nodes CR”) 616(1)-616(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 616(1)-616(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), data processing units (DPUs) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 616(1)-616(N) may be servers having one or more of the aforementioned computing resources.

[0085] In at least one embodiment, the grouped computing resources 614 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. The individual groups of node CRs within the grouped computing resources 614 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0086] In at least one embodiment, resource coordinator 612 may configure or otherwise control one or more nodes CR616(1)-616(N) and / or grouped computing resources 614. In at least one embodiment, resource coordinator 612 may include a software design infrastructure (“SDI”) management entity for data center 600. In at least one embodiment, resource coordinator 612 may include hardware, software, or some combination thereof.

[0087] In at least one embodiment, such as Figure 6 As shown, framework layer 620 includes, but is not limited to, job scheduler 632, configuration manager 634, resource manager 636, and distributed file system 638. In at least one embodiment, framework layer 620 may include a framework of software 652 supporting software layer 630 and / or one or more applications 642 of application layer 640. In at least one embodiment, software 652 or application 642 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 620 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 638 for large-scale data processing (e.g., "big data"). TM(“Spark”). In at least one embodiment, job scheduler 632 can include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 600. In at least one embodiment, configuration manager 634 can be capable of configuring different tiers, such as software tier 630 and framework tier 620 including Spark and a distributed file system 638 for supporting large scale data processing. In at least one embodiment, resource manager 636 can be capable of managing clustered or grouped computing resources mapped to or allocated for supporting distributed file system 638 and job scheduler 632. In at least one embodiment, clustered or grouped computing resources can include grouped computing resources 614 on data center infrastructure layer 610. In at least one embodiment, resource manager 636 can coordinate with resource orchestrator 612 to manage these mapped or allocated computing resources.

[0088] In at least one embodiment, software 652 included in software tier 630 can include software used by at least portions of node C.R.s 616(1)-616(N), grouped computing resources 614, and / or distributed file system 638 of framework tier 620. One or more types of software can include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0089] In at least one embodiment, one or more application programs 642 included in application tier 640 can include one or more types of application programs used by at least portions of node C.R.s 616(1)-616(N), grouped computing resources 614, and / or distributed file system 638 of framework tier 620. One or more types of application programs can include, but are not limited to, CUDA application programs.

[0090] In at least one embodiment, any of configuration manager 634, resource manager 636, and resource orchestrator 612 can implement any number and type of self-modifying actions based on any number and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions can mitigate data center operators of data center 600 making possibly poor configuration decisions and can avoid underutilized and / or poorly performing portions of a data center.

[0091] In at least one embodiment, one or more systems depicted in relation to the preceding figures are utilized to implement the techniques described in connection with Figures 1-5technology, function and / or process described. In at least one embodiment, at least one component in the preceding figures is used to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the preceding figures performs Figures 1-5 at least one aspect of a component described. In at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the preceding figures, such as a system to perform a process described, for example, in conjunction with Figures 1-5 a system and / or process described, such as a processor comprising one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0092] Computer-based system

[0093] The following figures set forth exemplary computer-based systems that can be used with, or implemented, at least one embodiment, but are not limited to.

[0094] Figure 7 A processing system 700, in accordance with at least one embodiment, is shown. In at least one embodiment, system 700 includes one or more processor(s) 702 and one or more graphics processor(s) 708, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having many processors 702 or processor cores 707. In at least one embodiment, processing system 700 is a processing platform incorporated within a system- on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, processor cores 707 are referred to as computational units or processing units.

[0095] In at least one embodiment, processing system 700 can include or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 700 is a mobile phone, a smart phone, a tablet device, or a web appliance. In at least one embodiment, processing system 700 can also include or be coupled with a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 700 is a television or set-top box device having one or more processors 702 and a graphical interface generated by one or more graphics processors 708.

[0096] In at least one embodiment, one or more processor(s) 702 each include one or more processor cores 707 to process instructions which, when executed, implement the operations for system and user software. In at least one embodiment, each of the one or more processor cores 707 are configured to process a specific instruction set 709. In at least one embodiment, instruction set 709 can facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). In at least one embodiment, multiple processor cores 707 can each process a different instruction set 709, which can include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 707 can also include other processing devices, such as a digital signal processor (DSP).

[0097] In at least one embodiment, processor 702 includes cache memory 704. In at least one embodiment, processor 702 can have single-level or multi-level internal caches. In at least one embodiment, cache memory is shared among various components of processor 702. In at least one embodiment, processor 702 also uses an external cache (e.g., a Level 3 (L3) cache or last level cache (LLC)) (not shown), which can be shared among processor cores 707 using known cache coherency techniques. In at least one embodiment, additionally included in processor 702 are register file 706, which processor 702 can include different types of registers such as integer registers, floating point registers, status registers, and instruction pointer registers, to name a few. In at least one embodiment, register file 706 can include a general register file or other registers.

[0098] In at least one embodiment, one or more processors 702 are coupled with one or more interface buses 710 for passing control information and receiving data signals between processor 702 and other components of system 700. In at least one embodiment, interface bus 710 can be versions of the Peripheral Component Interconnect (PCI) bus, PCI Express bus, Industry Standard Architecture (ISA) bus, Infineon’s Transputer bus, Motorola’s 68000 bus, Advanced Micro Devices’ Amiga Bus, Apple Desktop Bus, Hewlett-Packard’s SmartCache bus, Micro Channel Architecture (MCA) bus, IBM’s Intellibus, z / Architecture, NuBus, Northstar, SBus, Multibus, 80x86 architecture buses, digital telephone system buses, Apple Desktop Bus, Apple Desktop Bus, Digital Equipment Corporation’s VAX-11 bus, PDP bus, Sun Microsystems’ Scalable Parallel Interface (SPI) bus, and industrial-grade buses such as RS-232C, RS-422, RS-423, RS-485, and similar buses. In at least one embodiment, interface bus 710 is not limited to the buses noted above and can include any bus where information is transferred in a digital format between components.

[0099] In at least one embodiment, storage devices 720 can be dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, phase-change or ferroelectric memory devices, or some combination of these or other memory devices capable of performing in a manner similar to that of the memory devices noted above. In at least one embodiment, storage devices 720 can be used as the main memory of processing system 700, to store data 722 and instructions 721 for use when one or more processors 702 executes an application or process. In at least one embodiment, memory controller 716 also couples with an optional external graphics processor 712, which can communicate with one or more graphics processors 708 in processors 702 to perform graphics and media operations. In at least one embodiment, display device 711 can be connected to processor 702. In at least one embodiment, display device 711 can include one or more of an internal display device, as in a mobile electronic device or a laptop computer or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 711 can include a head-mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0100] In at least one embodiment, platform controller hub 730 enables peripherals to connect to storage device 720 and processor 702 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include, but are not limited to, audio controller 746, network controller 734, firmware interface 728, wireless transceiver 726, touch sensors 725, data storage device 724 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 724 can connect to the storage interface via a storage interface bus, e.g., a SATA, or a peripheral bus, e.g., a peripheral component interconnect bus (such as PCI, PCIe). In at least one embodiment, touch sensors 725 can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 726 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 728 enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, network controller 734 can enable network connectivity to one or more private or public networks. In at least one embodiment, a high-performance network controller (not shown) is coupled

[0101] In at least one embodiment, memory controller 716 and instances of platform controller hub 730 can be integrated into a discrete external graphics processor, such as external graphics processor 712. In at least one embodiment, platform controller hub 730 and / or memory controller 716 can be external to one or more processor(s) 702. For example, in at least one embodiment, processing system 700 can include an external memory controller 716 and platform controller hub 730, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that is in communication with processor(s) 702.

[0102] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement the techniques described in connection with Figures 1-5technology, functions, and / or processes described. In at least one embodiment, at least one component in the aforementioned figures is used for causing execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the aforementioned figures performs Figures 1-5 at least one aspect of the component. In at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the aforementioned figures, such as a system that performs Figures 1-5 described systems and / or processes, such as a processor comprising one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0103] Figure 8 A computer system 800 according to at least one embodiment is shown. In at least one embodiment, computer system 800 can be a system with interconnected devices and components, an SOC, or some combination. In at least one embodiment, computer system 800 is formed by a processor 802 that can include execution units to execute an instruction. In at least one embodiment, computer system 800 can include, without limitation, components such as processor 802 that employ execution units including logic to perform algorithms for processing data. In at least one embodiment, computer system 800 can include processors such as Intel Pentium TM , XScale TM and / or StrongARM TM , Core TM or Intel Nervana TM microprocessors, although other systems (including PCs, workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, computer system 800 can execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux, for example), embedded software, and / or graphical user interfaces can also be used.

[0104] In at least one embodiment, the computer system 800 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0105] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 configured to execute a Computational Unified Device Architecture (“CUDA”). (Developed by NVIDIA Corporation, Santa Clara, California) In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 800 is a single-processor desktop or server system. In at least one embodiment, the computer system 800 may be a multiprocessor system. In at least one embodiment, the processor 802 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which allows data signals to be transmitted between the processor 802 and other components in the computer system 800.

[0106] In at least one embodiment, processor 802 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside outside of processor 802. In at least one embodiment, processor 802 may include a combination of internal and external caches. In at least one embodiment, register file 806 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0107] In at least one embodiment, execution unit 808 includes, without limitation, logic to perform integer and floating point operations, including bit fields. Processor 802 can also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 808 can include logic to handle a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809 in instruction set of a general-purpose processor 802, along with associated circuitry to execute the instructions, the general-purpose processor 802 can implement many of the multimedia applications that would otherwise require a graphics processing unit (GPU) to process. In at least one embodiment, by using the full width of a processor’s data bus to perform operations on packed data, many multimedia applications can be accelerated beyond what could be accomplished by using a smaller GPU, which would be limited to the width of a processor bus. In at least one embodiment, by performing operations on packed data, many multimedia applications can be executed more efficiently by processor 802.

[0108] In at least one embodiment, execution unit 808 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 800 can include, without limitation, memory 820. In at least one embodiment, memory 820 can be implemented as a DRAM device, SRAM device, flash memory device, or other storage device. Memory 820 can store data signals represented by instructions 819 and / or data 821 that can be executed by processor 802.

[0109] In at least one embodiment, system logic chip can be coupled to processor bus 810 and memory 820. In at least one embodiment, system logic chip can include, without limitation, a memory controller hub (“MCH”) 816, and processor 802 can communicate with MCH 816 via processor bus 810. In at least one embodiment, MCH 816 can provide a high bandwidth memory path 818 to memory 820 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 816 can also include an integrated graphics processing unit (“GPU”) 812, which can include logic to process graphics

[0110] In at least one embodiment, computer system 800 can use system I / O 822 as a proprietary hub interface bus to couple MCH 816 to I / O controller hub (“ICH”) 830. In at least one embodiment, ICH 830 can provide direct connection to some I / O devices and can be connected to other devices via a local I / O bus. In at least one embodiment, local I / O bus can include, without limitation, a high-speed I / O bus for connecting peripheral devices to memory 820, chipset, and processor 802. Examples can include, without limitation, audio controller 829, firmware hub (“Flash BIOS”) 828, wireless transceiver 826, data storage 824, legacy I / O controller 823 containing user input 825 and keyboard interface, serial expansion port 827 (e.g., USB), and network controller 834. Data storage 824 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0111] In at least one embodiment, Figure 8 A system including interconnected hardware devices or “chips” is shown. In at least one embodiment, Figure 8 An exemplary SoC can be shown. In at least one embodiment, Figure 8 Devices shown in FIG. 8 can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 800 are interconnected using Compute Express Link (CXL) interconnects.

[0112] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is used to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of a component described in relation to Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, e.g., to implement systems and / or processes described in relation to Figures 1-5 In at least one embodiment, a processor comprises one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0113] Figure 9A system 900 according to at least one embodiment is illustrated. In at least one embodiment, system 900 is an electronic device utilizing processor 910. In at least one embodiment, system 900 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, edge device communicatively coupled to one or more local or cloud service providers, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0114] In at least one embodiment, system 900 may include, but is not limited to, processor 910 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, USB (versions 1, 2, and 3) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 9 A system is illustrated, comprising interconnected hardware devices or "chips". In at least one embodiment, Figure 9 An exemplary SoC can be shown. In at least one embodiment, Figure 9 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0115] In at least one embodiment, Figure 9 This may include a display 924, a touchscreen 925, a touchpad 930, a near-field communication unit (“NFC”) 945, a sensor hub 940, a thermal sensor 946, a fast chipset (“EC”) 935, a trusted platform module (“TPM”) 938, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 922, a DSP 960, a solid-state drive (“SSD”) or hard disk drive (“HDD”) 920, a wireless local area network unit (“WLAN”) 950, a Bluetooth unit 952, a wireless wide area network unit (“WWAN”) 956, a global positioning system (GPS) 955, a camera (“USB 3.0 camera”) 954 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 915 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0116] In at least one embodiment, other components can be communicatively coupled to processor 910 by components discussed above. In at least one embodiment, an accelerometer 941, an ambient light sensor (“ALS”) 942, a compass 943, and a gyroscope 944 can be communicatively coupled to a sensor hub 940. In at least one embodiment, a thermal sensor 939, a fan 937, a keyboard 936, and a touchpad 930 can be communicatively coupled to an EC 935. In at least one embodiment, a speaker 963, a headphone 964, and a microphone (“mic”) 965 can be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 962, which in turn can be communicatively coupled to a DSP 960. In at least one embodiment, audio unit 962 can include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 957 can be communicatively coupled to a WWAN unit 956. In at least one embodiment, components such as WLAN unit 950 and Bluetooth unit 952, and WWAN unit 956 can be implemented as a next generation form factor (NGFF).

[0117] In at least one embodiment, one or more systems depicted in relation to preceding figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 preceding figures are utilized to enable execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component of preceding figures performs at least one aspect of a component described in relation to Figures 1-5 preceding figures are utilized to implement one or more systems and / or processes, for example, systems and / or processes described in relation to Figures 1-5 preceding figures, such as a processor comprising one or more circuits to enable execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0118] Figure 10An exemplary integrated circuit 1000 is shown in accordance with at least one embodiment. In at least one embodiment, exemplary integrated circuit 1000 is a SoC, which can be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1000 includes one or more application processors 1005 (e.g., CPUs, DPUs), at least one graphics processor 1010, and can additionally include an image processor 1015 and / or a video processor 1020, any of which can be a modular IP core. In at least one embodiment, integrated circuit 1000 includes peripheral or bus logic including a USB controller 1025, a UART controller 1030, an SPI / SDIO controller 1035, and an I2S / I2C controller 1040. In at least one embodiment, integrated circuit 1000 can include a display device 1045 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1050 and a mobile industry processor interface (MIPI) display interface 1055. In at least one embodiment, storage can be provided by a flash memory subsystem 1060 including flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 1065 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1070. 2 S / I 2 C controller 1040. In at least one embodiment, integrated circuit 1000 can include a display device 1045 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1050 and a mobile industry processor interface (MIPI) display interface 1055. In at least one embodiment, storage can be provided by a flash memory subsystem 1060 including flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 1065 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1070.

[0119] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in connection with Figures 1-5 at least one of the foregoing figures to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of at least one of the foregoing figures performs at least one aspect of a component described in connection with Figures 1-5 at least one of the foregoing figures to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of at least one of the foregoing figures performs at least one aspect of a component described in connection with Figures 1-5 at least one of the foregoing figures to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of at least one of the foregoing figures performs at least one aspect of a component described in connection with

[0120] Figure 11A computing system 1100 is shown in accordance with at least one embodiment. In at least one embodiment, the computing system 1100 includes a processing subsystem 1101 having one or more processor(s) 1102 and a system memory 1104 in communication via an interconnection path 1105 that can include a memory hub 1105. In at least one embodiment, the memory hub 1105 can be a separate component coupled with one or more processors 1102 via individual communication links 1107A to 1107N. In at least one embodiment, the memory hub 1105 can be integrated into one or more processors 1102 via individual communication links 1107A to 1107N so that memory hub 1105 is not a separate component. In at least one embodiment, memory hub 1105 can be operable to communicate with a plurality of system memories 1104A to 1104N.

[0121] In at least one embodiment, processing subsystem 1101 includes one or more parallel processor(s) 1112 coupled to memory hub 1105 via a bus or other communication link 1113. In at least one embodiment, communication link 1113 can be one of many such links which can be implemented as standard system buses structured to accommodate bus mastering capabilities of one or more of the peripheral devices. In at least one embodiment, communication link 1113 can be implemented as a standardized computer communications interface.

[0122] In at least one embodiment, system storage unit 1114 can connect to I / O hub 1107 to provide storage mechanisms for computing system 1100. In at least one embodiment, I / O switches 1116 can be used to provide interface mechanisms to enable connections between I / O hub 1107 and other components such as network adapters 1118 and / or wireless network adapters 1119 that can be integrated into a platform, as well as various other devices that can be added via one or more add-in devices 1120. In at least one embodiment, network adapters 1118 can be Ethernet adapters or another wired network adapters. In at least one embodiment, wireless network adapters 1119 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices that include one or more radios.

[0123] In at least one embodiment, computing system 1100 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., that can also be connected to I / O hub 1107. In at least one embodiment, communication paths interconnecting various Figure 11 Communication paths between various components in FIG. 11 can use any suitable protocol including, for example, PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect, or interconnect protocols).

[0124] In at least one embodiment, parallel processor(s) 1112 include circuitry optimized for graphics and video processing, including for example video output circuitry, and are configured for use in a gaming console, a mobile phone, a personal computer, or other application. In at least one embodiment, parallel processor(s) 1112 include circuitry optimized for general use applications, including for example high-precision floating point, integer and / or Boolean logic. In at least one embodiment, compute units 1120A-1120N are configured to implement a single instruction multiple data (SIMD) execution model. In at least one embodiment, compute units 1120A-1120N are configured to implement a multiple instruction multiple data (MIMD) execution model. In at least one embodiment, one or more of compute units 1120A-1120N include integrated single program multiple data (SPMD) functionality. In at least one embodiment, compute units 1120A-1120N are configured to implement a SIMD with duplication (SDD) execution model.

[0125] In at least one embodiment, one or more systems depicted in relation to the preceding figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 In at least one embodiment, at least one component in the preceding figures is utilized to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the preceding figures performs at least one aspect of a component described in relation to Figures 1-5 In at least one embodiment, one or more systems and / or processes described in relation to the preceding figures are implemented utilizing one or more systems depicted in relation to the preceding figures, for example, a system and / or process described in relation to Figures 1-5 In at least one embodiment, a processor includes one or more circuits to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0126] Processing system

[0127] The following figures set forth, without limitation, exemplary processing systems that can be used to implement at least one embodiment.

[0128] Figure 12 An accelerated processing unit (“APU”) 1200, in accordance with at least one embodiment, is shown. In at least one embodiment, APU 1200 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, APU 1200 can be configured to execute application programs such as CUDA programs. In at least one embodiment, APU 1200 includes, without limitation, core complex 1210, graphics complex 1240, fabric 1260, I / O interface 1270, memory controllers 1280, display controllers 1292, and multimedia engines 1294. In at least one embodiment, APU 1200 can include, without limitation, any combination of any number of core complexes 1210, any number of graphics complexes 1250, any number of display controllers 1292, and any number of multimedia engines 1294. For purposes of illustration, multiple instances of like objects are denoted with reference numerals in which the reference designator is identified with a number and parentheses, and the number in the parentheses identifies the instance.

[0129] In at least one embodiment, core complex 1210 is a CPU, graphics complex 1240 is a GPU, and APU 1200 is a processing unit that integrates, without limitation, core complex 1210 and graphics complex 1240 onto a single chip. In at least one embodiment, some tasks can be assigned to core complex 1210 while other tasks can be assigned to graphics complex 1240. In at least one embodiment, core complex 1210 is configured to execute host control software associated with APU 1200, such as an operating system. In at least one embodiment, core complex 1210 is a master processor of APU 1200 that controls and coordinates the operation of other processors. In at least one embodiment, core complex 1210 issues commands that control the operation of graphics complex 1240. In at least one embodiment, core complex 1210 can be configured to execute host executable code derived from CUDA source code, and graphics complex 1240 can be configured to execute device executable code derived from CUDA source code. In at least one embodiment, cores 1220 are referred to as compute units or arithmetic logic units.

[0130] In at least one embodiment, core complex 1210 includes, without limitation, cores 1220(1)-1220(4) and L3 cache 1230. In at least one embodiment, core complex 1210 can include, without limitation, any number of cores 1220 and any combination and number of caches. In at least one embodiment, cores 1220 are configured to execute instructions of a particular instruction set architecture (“ISA”). In at least one embodiment, each core 1220 is a CPU core.

[0131] In at least one embodiment, each core 1220 includes, without limitation, a fetch / decode unit 1222, an integer execution engine 1224, a floating point execution engine 1226, and an L2 cache 1228. In at least one embodiment, fetch / decode unit 1222 fetches instructions, decodes them, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 1224 and floating point execution engine 1226. In at least one embodiment, fetch / decode unit 1222 can dispatch one micro-instruction to integer execution engine 1224 and another micro-instruction to floating point execution engine 1226 simultaneously. In at least one embodiment, integer execution engine 1224 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 1226 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 1222 dispatches micro-instructions to a single execution engine in place of both integer execution engine 1224 and floating point execution engine 1226.

[0132] In at least one embodiment, each core 1220(i) can access L2 cache 1228(i) included in core 1220(i), where i is an integer representing a particular instance of a core 1220. In at least one embodiment, each core 1220 included in core complex 1210(j) is connected to other cores 1220 included in core complex 1210(j) via L3 cache 1230(j) included in core complex 1210(j), where j is an integer representing a particular instance of a core complex 1210. In at least one embodiment, cores 1220 included in core complex 1210(j) can access all L3 caches 1230(j) included in core complex 1210(j), where j is an integer representing a particular instance of a core complex 1210. In at least one embodiment, L3 cache 1230 can include, without limitation, any number of slices.

[0133] In at least one embodiment, graphics processing engine 1218 can include, without limitation, graphics processing unit(s) (GPU(s)) 1220, graphics memory management unit (GMMU) 1222, and cache(s) 1224. In at least one embodiment, GPU(s) 1220 share GMMU 1222. In at least one embodiment, GMMU 1222 is partitioned. In at least one embodiment, graphics processing engine 1218 includes, without limitation, any number of GPU(s) 1220 and any number (including zero) and type of cache(s) 1224. In at least one embodiment, graphics processing engine 1218 includes, without limitation, any number of specialized graphics hardware.

[0134] In at least one embodiment, graphics complex 1240 includes, without limitation, any number of compute units 1250 and L2 cache 1242. In at least one embodiment, compute units 1250 share L2 cache 1242. In at least one embodiment, L2 cache 1242 is partitioned. In at least one embodiment, graphics complex 1240 includes, without limitation, any number of compute units 1250 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1240 includes, without limitation, any number of specialized graphics hardware.

[0135] In at least one embodiment, each compute unit 1250 includes, without limitation, any number of SIMD units 1252 and shared memory 1254. In at least one embodiment, each SIMD unit 1252 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 1250 can execute any number of thread blocks, but each thread block executes on a single compute unit 1250. In at least one embodiment, a thread block includes, without limitation, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1252 executes a different thread warp. In at least one embodiment, a thread warp is a group of threads (e.g., 16 threads), where each thread in a thread warp belongs to a single thread block and is configured to process a different set of data based on a single instruction set. In at least one embodiment, one or more threads in a thread warp can be disabled using predication. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 1254. In at least one embodiment, each compute unit 1250 includes one or more clusters of thread blocks, where a cluster of thread blocks can enable programming control of locality at a greater granularity than a single thread block of a single streaming multi-processor (SM). In at least one embodiment, a cluster of thread blocks (also referred to as a “cluster”) enables multiple thread blocks running concurrently across streaming multi-processors to synchronize and cooperatively fetch, exchange, or otherwise use data.

[0136] In at least one embodiment, fabric 1260 is a system interconnect that facilitates data and control transmissions across core complex 1210, graphics complex 1240, I / O interface 1270, memory controllers 1280, display controller 1292, and multimedia engine 1294. In at least one embodiment, APU 1200 can include, without limitation, any number and type of system interconnects in addition to or instead of fabric 1260 that facilitate data and control transmissions across any number and type of directly or indirectly linked components that can be internal or external to APU 1200. In at least one embodiment, I / O interface 1270 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1270. In at least one embodiment, peripheral devices coupled to I / O interface 1270 can include, without limitation, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0137] In at least one embodiment, display controller 1292 displays images on one or more display devices, such as liquid crystal display (“LCD”) devices. In at least one embodiment, multimedia engine 1294 includes, without limitation, any number and type of multimedia-related circuitry, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers 1280 facilitate data transfers between APU 1200 and unified system memory 1290. In at least one embodiment, core complex 1210 and graphics complex 1240 share unified system memory 1290.

[0138] In at least one embodiment, APU 1200 implements a memory subsystem that includes, without limitation, memory controllers 1280 and memory devices (e.g., shared memory 1254) that can be dedicated to one component or shared among multiple components. In at least one embodiment, APU 1200 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 cache 1328, L3 cache 1230, and L2 cache 1242), each of which can be private to a component or shared among any number of components (e.g., core 1220, core complex 1210, SIMD unit 1252, compute unit 1250, and graphics complex 1240).

[0139] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement the techniques described in connection withFigures 1-5 The technology, functions, and / or processes described. In at least one embodiment, at least one component in the aforementioned figures is used to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the aforementioned figures performs Figures 1-5 at least one aspect of the component in the middle. In at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the aforementioned figures, such as in conjunction with Figures 1-5 The systems and / or processes described, such as a processor comprising one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0140] Figure 13 A CPU 1300, in accordance with at least one embodiment, is shown. In at least one embodiment, CPU 1300 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, CPU 1300 can be configured to execute application programs. In at least one embodiment, CPU 1300 is configured to execute host control software, such as an operating system. In at least one embodiment, CPU 1300 issues commands that control the operation of an external GPU (not shown). In at least one embodiment, CPU 1300 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, CPU 1300 includes, without limitation, any number of core complexes 1310, fabric 1360, I / O interfaces 1370, and memory controllers 1380.

[0141] In at least one embodiment, core complex 1310 includes, without limitation, cores 1320(1)-1320(4) and L3 cache 1330. In at least one embodiment, core complex 1310 can include, without limitation, any number of cores 1320 and any combination and type of caches. In at least one embodiment, cores 1320 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1320 is a CPU core.

[0142] In at least one embodiment, each core 1320 includes, without limitation, a fetch / decode unit 1322, an integer execution engine 1324, a floating point execution engine 1326, and an L2 cache 1328. In at least one embodiment, fetch / decode unit 1322 fetches instructions, decodes such instructions, generates micro-operations, and dispatches individual micro-instructions to integer execution engine 1324 and floating point execution engine 1326. In at least one embodiment, fetch / decode unit 1322 can concurrently dispatch one micro-instruction to integer execution engine 1324 and another micro-instruction to floating point execution engine 1326. In at least one embodiment, integer execution engine 1324 executes, without limitation, integer and memory operations. In at least one embodiment, floating point engine 1326 executes, without limitation, floating point and vector operations. In at least one embodiment, fetch-decode unit 1322 dispatches micro-instructions to a single execution engine in place of both integer execution engine 1324 and floating point execution engine 1326.

[0143] In at least one embodiment, each core 1320(i) has access to an L2 cache 1328(i) included in core 1320(i), where i is an integer representing a particular instance of core 1320. In at least one embodiment, each core 1320 included in core complex 1310(j) is connected to other cores 1320 in core complex 1310(j) via an L3 cache 1330(j) included in core complex 1310(j), where j is an integer representing a particular instance of core complex 1310. In at least one embodiment, cores 1320 included in core complex 1310(j) have access to all L3 caches 1330(j) included in core complex 1310(j), where j is an integer representing a particular instance of core complex 1310. In at least one embodiment, L3 cache 1330 can include, without limitation, any number of slices.

[0144] In at least one embodiment, structure 1360 is a system interconnect that facilitates data and control transfers across core complexes 1310(1)-1310(N) (where N is a positive integer), I / O interface 1370, and memory controller 1380. In at least one embodiment, in addition to or instead of structure 1360, CPU 1300 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either inside or outside CPU 1300. In at least one embodiment, I / O interface 1370 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1370. In at least one embodiment, peripheral devices coupled to I / O interface 1370 may include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0145] In at least one embodiment, memory controller 1380 facilitates data transfer between CPU 1300 and system memory 1390. In at least one embodiment, core complex 1310 and graphics complex 1340 share system memory 1390. In at least one embodiment, CPU 1300 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1380 and memory devices that may be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1300 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1328 and L3 cache 1330), each cache memory may be component-private or shared among any number of components (e.g., core 1320 and core complex 1310).

[0146] In at least one embodiment, the combination is achieved using one or more systems depicted in relation to the foregoing figures. Figures 1-5 The described techniques, functions, and / or processes. In at least one embodiment, at least one component of the foregoing figures is used to cause the execution of one or more threads corresponding to one or more corresponding kernels to selectively stop at least in part based on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of the foregoing figures performs... Figures 1-5 At least one aspect of the components. In at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the foregoing figures, for example, in combination with Figures 1-5The described system and / or process, such as a processor including one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

[0147] Figure 14 An exemplary accelerator integration slice 1490 is shown in accordance with at least one embodiment. As used herein, a "slice" includes a specified portion of processing resources of an accelerator integration circuit. In at least one embodiment, an accelerator integration circuit provides cache management, memory access, environment management, and interrupt management services on behalf of a number of graphics processing engines of a graphics acceleration module. The graphics processing engines can each comprise a separate GPU. Alternatively, the graphics processing engines can include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module can be a GPU with a plurality of graphics processing engines. In at least one embodiment, a graphics processing engine can be a separate GPU integrated on a common package, line card, or chip as the accelerator integration circuit.

[0148] An application effective address space 1482 within system memory 1414 stores process elements 1483. In one embodiment, process elements 1483 are stored in response to GPU invocations 1481 from applications 1480 executing on processor 1407. Process elements 1483 contain processing state for the corresponding application 1480. A work descriptor (WD) 1484 contained in process element 1483 can be a single job requested by an application or can contain pointers to a queue of jobs. In at least one embodiment, WD 1484 is a pointer to a job request queue in application effective address space 1482.

[0149] Graphics acceleration module 1446 and / or individual graphics processing engines can be shared by all or a subset of processes in a system. In at least one embodiment, a process can include infrastructure for setting up processing state and sending WDs 1484 to graphics acceleration module 1446 to start jobs in a virtualized environment.

[0150] In at least one embodiment, a dedicated process programming model is implemented for owned. In this model, a single process owns a graphics acceleration module 1446 or individual graphics processing engines. As graphics acceleration module 1446 is owned by a single process, a hypervisor initializes the accelerator integration circuit for the owning partition and an operating system initializes the accelerator integration circuit for the owning partition when assigning graphics acceleration module 1446.

[0151] In operation, a WD fetch unit 1491 in accelerator integration slice 1490 fetches the next WD 1484, which includes an indication of work to be completed by one or more graphics processing engines of graphics acceleration module 1446. Data from WD 1484 can be stored in registers 1445 used by memory management unit (MMU) 1439, interrupt management circuit 1447, and / or environment management circuit 1448, as illustrated. For example, one embodiment of MMU 1439 includes segment / page walk circuitry to access segment / page tables 1486 within an OS virtual address space 1485. Interrupt management circuit 1447 can process interrupt events (INTs) 1492 received from graphics acceleration module 1446. Effective addresses 1493 produced by graphics processing engines, when executing graphics operations, are translated to real addresses by MMU 1439.

[0152] In one embodiment, the same set of registers 1445 are replicated for each graphics processing engine and / or graphics acceleration module 1446 and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in accelerator integration slice 1490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0153] Table 1 - Hypervisor Initialized Registers

[0154]

[0155]

[0156] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0157] Table 2 - Operating System Initialized Registers

[0158] 1 Process and thread identification 2 Effective address (EA) environment save / restoration pointer 3 Virtual address (VA) accelerator utilization record pointer 4 Virtual address (VA) storage segment table pointer 5 Privilege mask 6 Work descriptor

[0159] In one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do the work or it can be a pointer to a memory location where the application has set up a command queue of work to be completed.

[0160] In at least one embodiment, one or more systems as depicted in relation to the foregoing figures are utilized to implement the techniques in connection with Figures 1-5technology, function and / or process described. In at least one embodiment, at least one component in the preceding figures is used to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component in the preceding figures performs Figures 1-5 at least one aspect of the component. In at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the preceding figures, for example, in conjunction with a system and / or process described, such as a system and / or process that Figures 1-5 described, such as a processor comprising one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error.

[0161] Figures 15A-15B Exemplary graphics processors in accordance with at least one embodiment are shown. In at least one embodiment, any of the exemplary graphics processors can be fabricated using one or more IP cores. In addition to the illustrated, in at least one embodiment, other logic and circuitry can be included, including additional graphics processor cores, peripheral interface controllers or general-purpose processor cores. In at least one embodiment, an exemplary graphics processor is utilized within an SoC.

[0162] Figure 15A An exemplary graphics processor 1510 of an SoC integrated circuit in accordance with at least one embodiment is shown, which can be fabricated using one or more IP cores. Figure 15B An additional exemplary graphics processor 1540 of an SoC integrated circuit in accordance with at least one embodiment is shown, which can be fabricated using one or more IP cores. In at least one embodiment, Figure 15A The graphics processor 1510 is a low power graphics processor core. In at least one embodiment, the graphics processor 1510 is used in a mobile, handheld, or battery-powered device. Figure 15B The graphics processor 1540 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1510, 1540 can be a variant of the graphics processor 1010. Figure 10 The graphics processor 1010 of FIG. 1.

[0163] In at least one embodiment, graphics processor 1510 includes a vertex processor 1505 and one or more fragment processor(s) 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D, through 1515N-1, and 1515N). In at least one embodiment, graphics processor 1510 can execute different shader programs via separate logic for vertex processing and / or for fragment / pixel processing. In at least one embodiment, vertex processor 1505 is optimized to execute operations on vertex data that frequently process complex, high-precision calculations for geometry transformations, motion blur, and dynamic shading. In at least one embodiment, one or more fragment processor(s) 1515A-1515N are optimized to execute more

[0164] In at least one embodiment, graphics processor 1510 additionally includes one or more MMU(s) 1520A-1520B, cache memory 1525A-1525B, and circuit interconnect 1530A-1530B. In at least one embodiment, one or more MMU(s) 1520A-1520B provide for virtual to physical address mapping for graphics processor 1510, including for vertex processor 1505 and / or fragment processor(s) 1515A-1515N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1525A-1525B. In at least one embodiment, one or more MMU(s) 1520A-1520B can be synchronized with other MMUs within Figure 10 one or more application processor(s) 1005, image processors 1015, and / or video processors 1020, such that each processor 1005-1020 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable graphics processor 1510 to interface with other IP cores within a SoC, either via an internal bus, as shown, or via a direct connection.

[0165] In at least one embodiment, graphics processor 1540 includes Figure 15Aone or more MMUs 1520A-1520B, caches 1525A-1525B, and circuit interconnect 1530A-1530B of graphics processor 1510. In at least one embodiment, graphics processor 1540 includes one or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F, through 1555N-1, and 1555N), which provide for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary from one implementation to another. In at least one embodiment, graphics processor 1540 includes an inter-core task manager 1545, which acts as a thread dispatcher to divide work up among the one or more shader cores 1555A-1555N and binning unit 1558 to accelerate thread dispatch

[0166] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in connection with Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is utilized to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of a component described in connection with Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, e.g., in connection with systems and / or processes described in connection with Figures 1-5 In at least one embodiment, a processor includes one or more circuits to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0167] Figure 16A A graphics core 1600 according to at least one embodiment is shown. In at least one embodiment, graphics core 1600 can be included within graphics processor 1010 of FIG. 1, in at least one embodiment, graphics core 1600 can be a next generation graphics core. Figure 10 In at least one embodiment, graphics core 1600 can be a graphics core as described in connection with FIG. 2. In at least one embodiment, graphics core 1600 includes, without limitation, a front-end 1602, a work distribution unit 1604, a work processing unit 1606, and a render output unit 1608. Figure 15BThe unified shader cores 1555A-1555N. In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, texture units 1618, and cache / shared memory 1620, which are common to the execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 can include multiple slices 1601A-1601N or partitions of each core, and graphics processing units can include multiple instances of graphics core 1600. Slices 1601A-1601N can include support logic including a local instruction cache 1604A-1604N, a thread scheduler 1606A-1606N, a thread dispatcher 1608A-1608N, and a set of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N can include a set of additional functional units (AFUs) 1612A-1612N, floating point units (FPUs) 1614A-1614N, integer arithmetic logic units (ALUs) 1616A-1616N, address computation units (ACUs) 1613A-1613N, double precision floating point units (DPFPUs) 1615A-1615N, and matrix processing units (MPUs) 1617A-1617N. In at least one embodiment, graphics core 1600 is referred to as a compute or arithmetic unit.

[0168] In one embodiment, FPUs 1614A-1614N can perform single precision (32-bit) and half precision (16-bit) floating point operations, while DPFPUs 1615A-1615N can perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 1616A-1616N can perform variable precision integer operations in 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 1617A-1617N can also be configured for mixed precision matrix operations including half precision floating point operations and 8-bit integer operations. In at least one embodiment, MPUs 1617A-1617N can perform a variety of matrix operations to accelerate CUDA programs including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 1612A-1612N can perform additional logical operations not supported by floating point or integer units including trigonometric operations (e.g., Sine, Cosine, etc.).

[0169] Figure 16BA general-purpose graphics processing unit (GPGPU) 1630 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 1630 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1630 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 1630 can be directly linked to other instances of the GPGPU 1630 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1630 includes a host interface 1632 for connection to a host processor. In at least one embodiment, the host interface 1632 is a PCIe interface. In at least one embodiment, the host interface 1632 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1630 receives commands from the host processor and uses a global scheduler 1634 to assign execution threads associated with those commands to a set of computational clusters 1636A-1636H. In at least one embodiment, computing clusters 1636A-1636H share cache memory 1638. In at least one embodiment, cache memory 1638 can be used as an advanced cache of cache memory within computing clusters 1636A-1636H.

[0170] In at least one embodiment, the GPGPU 1630 includes memory 1644A-1644B coupled to the computing cluster 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, memory 1644A-1644B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0171] In at least one embodiment, computing clusters 1636A-1636H each include a set of graphics cores, such as Figure 16A The graphics core 1600 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1636A-1636H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0172] In at least one embodiment, multiple instances of GPGPU 1630 can be configured to operate as a compute cluster. Compute clusters 1636A-1636H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1630 communicate over host interface 1632. In at least one embodiment, GPGPU 1630 includes I / O hub 1639 which couples GPGPU 1630 with GPU links 1640 enabling direct connection to other instances of GPGPU 1630. In at least one embodiment, GPU links 1640 couple to a specialized GPU-to-GPU bridge enabling communication and synchronization among multiple instances of GPGPU 1630. In at least one embodiment, GPU links 1640 couple with a high-speed interconnect to transmit and receive data to other GPGPUs 1630 or parallel processors. In at least one embodiment, multiple instances of GPGPU 1630 are located in separate data processing systems and communicate via a network device accessible via host interface 1632. In at least one embodiment, GPU links 1640 can be configured to connect to a host processor, in addition to, or in lieu of, host interface 1632. In at least one embodiment, GPGPU 1630 can be configured to execute a CUDA program.

[0173] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 the foregoing figures. In at least one embodiment, at least one component of the foregoing figures is used to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component of the foregoing figures performs at least one aspect of a component described in relation to Figures 1-5 the foregoing figures. In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in relation to the foregoing figures, such as, for example, systems and / or processes described in relation to Figures 1-5 the foregoing figures, such as, for example, a processor comprising one or more circuits to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0174] Figure 17A A parallel processor 1700, according to at least one embodiment, is shown. In at least one embodiment, various components of parallel processor 1700 can be implemented using one or more integrated circuit devices, for example programmable processor(s), application specific integrated circuits (ASICs), or FPGAs.

[0175] In at least one embodiment, parallel processor 1700 includes a parallel processing unit 1702. In at least one embodiment, parallel processing unit 1702 includes an I / O unit 1704 that enables communication with other devices, including other instances of parallel processing unit 1702. In at least one embodiment, I / O unit 1704 can be directly connected to other devices. In at least one embodiment, I / O unit 1704 connects with other devices via use of a hub or switch interface, such as memory hub 1705. In at least one embodiment, connections between memory hub 1705 and I / O unit 1704 form a communication link. In at least one embodiment, I / O unit 1704 connects with a host interface 1706 and a memory crossbar switch 1716, where host interface 1706 receives commands directed to processing operations and memory crossbar switch 1716 receives commands directed to memory operations.

[0176] In at least one embodiment, when host interface 1706 receives a command buffer via I / O unit 1704, host interface 1706 can direct work operations to execute those commands to front end 1708. In at least one embodiment, front end 1708 couples with a scheduler 1710, which is configured to distribute commands or other work items to processing array 1712. In at least one embodiment, scheduler 1710 ensures that processing array 1712 is correctly configured and in an active state before tasks are assigned to processing array 1712. In at least one embodiment, scheduler 1710 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller- implemented scheduler 1710 is configurable to perform complex scheduling and work distribution operations, enabling fine-grained or coarse-grained thread dispatch and environment switching for threads executing on processing array 1712. In at least one embodiment, host software can prove a workload for scheduling on processing array 1712 through one of a number of graphics processing doorbells. In at least one embodiment, workload can then be automatically distributed by scheduler 1710 logic within microcontroller including scheduler 1710 on processing array 1712.

[0177] In at least one embodiment, processing array 1712 can include up to “N” processing clusters (e.g., cluster 1714A, cluster 1714B, through cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of processing array 1712 can execute a large number of concurrent threads. In at least one embodiment, scheduler 1710 can allocate work to clusters 1714A-1714N of processing array 1712 using various scheduling and / or work distribution algorithms, which can be determined at least in part by workload arriving at processing array 1712, and / or received from other processor cores, processor arrays, or systems, which can have an established dependency with processing array 1712. In at least one embodiment, scheduling can be handled dynamically by scheduler 1710, or can be aided in part by compiler logic during compilation of program logic configured for execution by processing array 1712. In at least one embodiment, different clusters 1714A-1714N of processing array 1712 can be allocated for processing different types of programs or for performing different types of computations.

[0178] In at least one embodiment, processing array 1712 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 1712 is configured to perform general purpose parallel compute operations. For example, in at least one embodiment, processing array 1712 can include logic to perform processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0179] In at least one embodiment, processing array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1712 can include additional logic to support performance of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, processing array 1712 can be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel

[0180] In at least one embodiment, when parallel processing unit 1702 is used to perform graphics processing, scheduler 1710 can be configured to divide incoming workloads into tasks of approximately equal size to better enable distribution of graphics processing operations across multiple clusters 1714A-1714N of processing array 1712. In at least one embodiment, portions of processing array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display on a display device. In at least one embodiment, intermediate data produced by one or more of clusters 1714A-1714N can be stored in buffers to allow transmission of intermediate data between clusters 1714A-1714N for further processing.

[0181] In at least one embodiment, processing array 1712 can receive processing tasks to be executed from scheduler 1710, which receives commands defining the processing tasks from front end 1708. In at least one embodiment, a processing task can include an index into data to be processed, such as a surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 1710 can be configured to fetch the index corresponding to a task, or can receive the index from front end 1708. In at least one embodiment, front end 1708 can be configured to ensure that processing array 1712 is configured in an effective state before launching a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0182] In at least one embodiment, each of one or more instances of parallel processing unit 1702 can be coupled to a parallel processor memory 1722. In at least one embodiment, parallel processor memory 1722 can be accessed by the processing array 1712, as well as the I / O unit 1704, via a memory crossbar 1716. In at least one embodiment, memory crossbar 1716 can be used to access memory banks 1724A-1724N of parallel processor memory 1722 by the processing array 1712, I / O unit 1704, and possibly other processing units or processing arrays in at least one embodiment. In at least one embodiment, central processing unit 1700 can also be coupled to parallel processor memory 1722 via memory crossbar 1716 and / or via its own dedicated memory crossbar.

[0183] In at least one embodiment, memory units 1724A-1724N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1724A-1724N can also include 3D stacked memory including, without limitation, high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory units 1724A-1724N allowing partition units 1720A-1720N to write portions of each rendering target in parallel to effectively use available bandwidth of parallel processor memory 1722. In at least one embodiment, local instances of parallel processor memory 1722 can be excluded from a unified memory design that utilizes system memory in combination with local cache memory.

[0184] In at least one embodiment, any of clusters 1714A-1714N of processing array 1712 can process data that is to be written into any of memory units 1724A-1724N within parallel processor memory 1722. In at least one embodiment, memory crossbar 1716 can be configured to transmit outputs of each cluster 1714A-1714N to any partition unit 1720A-1720N or another cluster 1714A-1714N, which can perform other processing operations on the outputs. In at least one embodiment, each cluster 1714A-1714N can communicate with memory interface 1718 through memory crossbar 1716 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 1716 has a connection to memory interface 1718 to communicate with I / O unit 1704 and a local instance of parallel processor memory 1722, to enable processing elements within different processing clusters 1714A-1714N to communicate with system memory or other memories not local to the parallel processing elements 1702. In at least one embodiment, memory crossbar 1716 can use virtual channels to separate traffic streams between clusters 1714A-1714N and partition units 1720A-1720N.

[0185] In at least one embodiment, multiple instances of parallel processing unit 1702 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1702 can be configured to operate in coordination with each other to enable single program multiprocessor (SPM) functionality. In at least one embodiment, different instances of parallel processing unit 1702 can be configured to operate in a locked-step computing mode where the different instances of parallel processing unit 1702 execute the same program but execute different iterations of a program (e.g., different iterations of the same loop). In at least one embodiment, some instances of parallel processing unit 1702 can include a higher precision floating point unit relative to other instances of parallel processing unit 1702. In at least one embodiment, a system that incorporates one or more instances of parallel processing unit 1702 or parallel processor 1700 can be implemented in a variety of form factors, including but not limited to desktop, laptop, or hand-held personal computers, servers, workstations, game consoles, and / or embedded systems.

[0186] Figure 17B A processing cluster 1794 is shown according to at least one embodiment. In at least one embodiment, processing cluster 1794 is included in a parallel processing unit. In at least one embodiment, processing cluster 1794 is a Figure 17Aone of the processing clusters 1714A-1714N. In at least one embodiment, processing cluster 1794 can be configured to execute many threads in parallel, where the term “thread” refers to an instance of a particular program executed by a particular group of one or more processing clusters. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads with no or negligible program overhead. In at least one embodiment, Single Instruction Multiple Thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronous threads using a common instruction unit configured to issue instructions to a group of processing engines within each processing cluster 1794.

[0187] In at least one embodiment, operation of processing cluster 1794 can be controlled via a pipeline manager 1732 that is assigned to processing tasks by scheduler 1710. In at least one embodiment, pipeline manager 1732 receives instructions from scheduler 1710 and manages execution of those instructions by graphics multiprocessor 1734 and / or texture unit 1736, in at least one embodiment, graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures can be included within processing cluster 1794. In at least one embodiment, one or more instances of graphics multiprocessor 1734 can be included within processing cluster 1794. In at least one embodiment, graphics multiprocessor 1734 can process data and a data crossbar 1740 can be used to distribute processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, pipeline manager 1732 can facilitate distribution by specifying destinations for processed data as a function of the destination’s source in either a fixed function or programmable manner. Figure 17A

[0188] In at least one embodiment, each graphics multiprocessor 1734 within processing cluster 1794 can include an identical set of functional execution logic (e.g., arithmetic logic units, load store units (LSUs), etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which instructions are issued at a first stage, passed through stages of the pipeline with each stage performing at least one instruction, and results from a last stage are used as inputs to subsequent instruction units at a subsequent stage in the pipeline. In at least one embodiment, there can be one instruction unit for every parallel thread. In at least one embodiment, each instruction unit is configured to process a single instruction and to dispatch that instruction to a function execution unit for execution. In at least one embodiment, functional execution units can be configured to widely vary. For example, in at least one embodiment, a first functional unit implements a SIMD intensive operation such as a matrix by matrix multiplication while a second functional unit implements memory-intensive functions such as determining a memory address. In at least one embodiment, each of the functional units can execute both SIMD and non-SIMD instructions.

[0189] ​In at least one embodiment, instructions sent to the processing cluster 1794 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 1734. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1734, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1734.

[0190] In at least one embodiment, the graphics multiprocessor 1734 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1734 may forgo the internal cache and use a cache memory within the processing cluster 1794 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 may also access partition units (e.g., Figure 17A The L2 cache is located within partition units 1720A-1720N, which are shared among all processing clusters 1794 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1734 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1702 can be used as global memory. In at least one embodiment, the processing cluster 1794 includes multiple instances of the graphics multiprocessor 1734, which can share common instructions and data that can be stored in the L1 cache 1748.

[0191] In at least one embodiment, each processing cluster 1794 may include an MMU 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1745 may reside in Figure 17AThe memory interface 1718 is located within the MMU 1745. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on tiles) and optionally to cache line indices. In at least one embodiment, the MMU 1745 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 1734, the L1 cache 1748, or the processing cluster 1794. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0192] In at least one embodiment, the processing cluster 1794 can be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1734 outputs a processed task to a data crossbar switch 1740 to provide the processed task to another processing cluster 1794 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 1716. In at least one embodiment, a pre-raster operation unit (preROP) 1742 is configured to receive data from the graphics multiprocessor 1734 and direct the data to a ROP unit, which may be associated with a partitioning unit (e.g., [missing information]). Figure 17A The PreROP1742 unit is located together with the partition units 1720A-1720N. In at least one embodiment, the PreROP1742 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0193] Figure 17C A graphics multiprocessor 1796 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1796 is... Figure 17Bgraphics processor 1734. In at least one embodiment, graphics processor 1796 couples with pipeline manager 1732 of processing cluster 1794. In at least one embodiment, graphics processor 1796 has a thread execution pipeline that includes, without limitation, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more GPGPU cores 1762, and one or more LSU’s 1766. GPGPU cores 1762 and LSUs 1766 couple with cache memory 1772 and shared memory 1770 through memory and cache interconnect 1768.

[0194] In at least one embodiment, instruction cache 1752 receives a stream of instructions 1750 to execute from pipeline manager 1732. In at least one embodiment, instructions are cached in instruction cache 1752 and dispatched for execution by instruction unit 1754. In one embodiment, instruction unit 1754 can dispatch instructions to the threads of a thread group, with each thread in the thread group assigned to a different execution lane of GPGPU core 1762. In at least one embodiment, instructions can access any of the local, shared, or global address spaces using addresses specified in the instructions 1750. In at least one embodiment, address mapping unit 1756 can be used to convert addresses in the unified address space into different addresses that can be accessed by LSUs 1766.

[0195] In at least one embodiment, register file 1758 provides a set of registers for functional units of graphics processor 1796. In at least one embodiment, register file 1758 provides temporary storage for operands of the data paths connected to the functional units (e.g., GPGPU cores 1762, LSUs 1766) of graphics processor 1796. In at least one embodiment, register file 1758 is split into registered files 1758 for each functional unit connected to graphics processor 1796. In at least one embodiment, register file 1758 is partitioned between different thread groups executing on graphics processor 1796.

[0196] In at least one embodiment, GPGPU cores 1762 can each include FPUs and / or ALUs for executing instructions for graphics processing. GPGPU cores 1762 can be similar to each other in architecture or can differ from each other in architecture. In at least one embodiment, a first portion of GPGPU cores 1762 includes single precision FPUs and integer ALUs, while a second portion of GPGPU cores 1762 includes double precision FPUs. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics processor 1796 can additionally include one or more fixed function or special purpose logic units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores 1762 can also include fixed or special function logic.

[0197] In at least one embodiment, GPGPU cores 1762 include SIMD logic capable of

[0198] In at least one embodiment, memory and cache interconnect 1768 is an interconnect network that connects each functional unit of graphics multiprocessor 1796 to register file 1758 and shared memory 1770. In at least one embodiment, memory and cache interconnect 1768 is a crossbar interconnect that allows LSUs 1766 to implement load and store operations between shared memory 1770 and register file 1758. In at least one embodiment, register file 1758 can operate at same frequency as GPGPU cores 1762, resulting in very low latency for data transfers between GPGPU cores 1762 and register file 1758. In at least one embodiment, shared memory 1770 can be used to enable communications between threads executing on functional units within graphics multiprocessor 1796. In at least one embodiment, cache memory 1772 can be used to cache data stored in shared memory 1770, for example, to allow data to be accessed more quickly.

[0199] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU can be communicatively coupled to host processor / cores by a bus or other interconnect (e.g., a high speed

[0200] In at least one embodiment, one or more systems as depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in connection with Figures 1-5 At least one component in the foregoing figures is used to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs Figures 1-5at least one embodiment, one or more systems and / or processes are implemented using the one or more systems depicted in the preceding figures, for example, in conjunction with Figures 1-5 A system and / or process described herein, such as a processor, includes one or more circuits for causing execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error.

[0201] Figure 18 A graphics processor 1800 according to at least one embodiment is shown. In at least one embodiment, graphics processor 1800 includes ring interconnect 1802, front-end 1804, media engine 1837, and graphics cores 1880A-1880N. In at least one embodiment, ring interconnect 1802 couples graphics processor 1800 to other processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 1800 is one of a plurality of processors integrated within a multi-core processing system.

[0202] In at least one embodiment, graphics processor 1800 receives batches of commands via ring interconnect 1802. In at least one embodiment, incoming commands are interpreted by a command streamer 1803 in pipeline front-end 1804. In at least one embodiment, graphics processor 1800 includes scalable execution logic to perform 3D geometry processing and media processing via the graphics cores 1880A-1880N. In at least one embodiment, for 3D geometry processing commands, command streamer 1803 supplies commands to geometry pipeline 1836. In at least one embodiment, for at least some media processing commands, command streamer 1803 supplies commands to a video front end 1834, which is coupled to a media engine 1837. In at least one embodiment, media engine 1837 includes a video quality engine (VQE) 1830 for video and image post-processing, and a multi-format encode / decode (MFX) 1833 engine to provide hardware-accelerated media

[0203] In at least one embodiment, graphics processor 1800 includes a scalable thread execution resource featuring a modular graphics core 1880A-1880N (sometimes referred to as a core slice), each having multiple sub-cores 1850A-1850N, 1860A-1860N (sometimes referred to as a core sub-slice). In at least one embodiment, graphics processor 1800 can have any number of graphics cores 1880A-1880N. In at least one embodiment, graphics processor 1800 includes graphics core(s) 1880A having at least a first sub-core 1850A and a second sub-core 1860A. In at least one embodiment, graphics processor 1800 is a low power processor with a single sub-core (e.g., 1850A). In at least one embodiment, graphics processor 1800 includes multiple graphics cores 1880A-1880N each including a set of first sub-cores 1850A-1850N and a set of second sub-cores 1860A-1860N. In at least one embodiment, each of first sub-cores 1850A-1850N includes at least a first set of execution units (EUs) 1852A-1852N and a media / texture sampler 1854A-1854N. In at least one embodiment, each of second sub-cores 1860A-1860N includes at least a second set of execution units (EUs) 1862A-1862N and a sampler 1864A-1864N. In at least one embodiment, each sub-core 1850A-1850N, 1860A-1860N shares a set of shared resources 1870A-1870N. In at least one embodiment, shared resources 1870 include shared cache memory and pixel operation logic.

[0204] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 the foregoing figures. In at least one embodiment, at least one component of the foregoing figures is utilized to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component of the foregoing figures performs at least one aspect of a component described in relation to Figures 1-5 the foregoing figures. In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in relation to the foregoing figures, e.g., in relation to systems and / or processes described in relation to Figures 1-5 the foregoing figures, such as a processor comprising one or more circuits to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0205] Figure 19 A processor 1900 is shown in accordance with at least one embodiment. In at least one embodiment, processor 1900 can include, without limitation, a logic circuit that executes instructions. In at least one embodiment, processor 1900 can execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, processor 1910 can include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany SIMD and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher (“SSEx” in general) technology can hold such packed data operands. In at least one embodiment, processor 1910 can execute instructions to accelerate CUDA programs.

[0206] In at least one embodiment, processor 1900 includes an in-order front-end (“front-end”) 1901 to fetch instructions to be executed and to prepare instructions for execution later in a processor pipeline. In at least one embodiment, front-end 1901 can include several units. In at least one embodiment, an instruction prefetcher 1926 fetches instructions from memory and provides instructions to an instruction decoder 1928 that, in turn, decodes or interprets instructions. In at least one embodiment, for example, instruction decoder 1928 decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “uops” or “microinstructions”) for execution. In at least one embodiment, instruction decoder 1928 parses instructions into operation codes and corresponding data and control fields, which can be used by micro-architecture to use to perform operations. In at least one embodiment, a trace cache 1930 can assemble decoded uops into program ordered sequences or traces in a uop queue 1934 for execution. In at least one embodiment, when trace cache 1930 encounters a complex instruction, a microcode ROM 1932 provides uops needed to complete the operation.

[0207] In at least one embodiment, some instructions can be converted into a single micro- operation, while others can require several micro-operations to complete. In at least one embodiment, if more than four micro-instructions are needed to complete a single instruction, then instruction decoder 1928 can access microcode ROM 1932 to execute the instruction. In at least one embodiment, instructions can be decoded into a small number of micro-instructions to be processed at instruction decoder 1928. In at least one embodiment, if multiple micro-instructions are needed to complete an operation, then the instructions can be stored in microcode ROM 1932. In at least one embodiment, trace cache 1930 references an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading a microcode sequence from microcode ROM 1932 to complete one or more instructions, in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 1932 completes sequencing of micro-operations for an instruction, front-end 1901 of a machine can resume fetching micro-operations from trace cache 1930.

[0208] In at least one embodiment, out-of-order execution engine (“out-of-order engine”) 1903 can prepare instructions for execution. In at least one embodiment, out-of-order execution logic has multiple buffers to smooth and reorder instruction flow to optimize performance as instructions are pipelined down and dispatched for execution. Out-of-order execution engine 1903 includes, without limitation, an allocator / register renamer 1940, a memory micro instruction queue 1942, an integer / floating point micro instruction queue 1944, a memory scheduler 1946, a fast scheduler 1902, a slow / general floating point scheduler (“slow / general FP scheduler”) 1904, and a simple floating point scheduler (“simple FP scheduler”) 1906. In at least one embodiment, fast scheduler 1902, slow / general floating point scheduler 1904, and simple floating point scheduler 1906 are also collectively referred to as “micro instruction schedulers 1902, 1904, 1906.” Allocator / register renamer 1940 allocates machine buffers and resources needed for each micro instruction to execute in order. In at least one embodiment, allocator / register renamer 1940 renames logical registers to entries in a register file. In at least one embodiment, allocator / register renamer 1940 also allocates entries for each micro instruction in one of two micro instruction queues, memory micro instruction queue 1942 for memory operations and integer / floating point micro instruction queue 1944 for non-memory operations, in front of memory scheduler 1946 and micro instruction schedulers 1902, 1904, 1906. In at least one embodiment, micro instruction schedulers 1902, 1904, 1906 determine when micro instructions are ready to execute based on readiness of their dependent input register operand sources and availability of execution resource micro instructions needed to complete. In at least one embodiment, fast scheduler 1902 of at least one embodiment can schedule on every half of a main clock cycle, while slow / general floating point scheduler 1904 and simple floating point scheduler 1906 can schedule once per main processor clock cycle. In at least one embodiment, micro instruction schedulers 1902, 1904, 1906 arbitrate for a dispatch port to dispatch micro instructions for execution.

[0209] In at least one embodiment, execution block 1911 includes, without limitation, an integer register file / bypass network 1908, a floating point register file / bypass network (“FP register file / bypass network”) 1910, address generation units (“AGUs”) 1912 and 1914, fast arithmetic logic units (“fast ALUs”) 1916 and 1918, a slow ALU 1920, a floating point ALU (“FP”) 1922, and a floating point move unit (“FP move”) 1924. In at least one embodiment, integer register file / bypass network 1908 and floating point register file / bypass network 1910 are also referred to herein as “register files 1908, 1910.” In at least one embodiment, AGUs 1912 and 1914, fast ALUs 1916 and 1918, slow ALU 1920, floating point ALU 1922, and floating point move unit 1924 are also referred to herein as “execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924.” In at least one embodiment, execution block can include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

[0210] In at least one embodiment, register files 1908, 1910 can be arranged between microinstruction decoders 1902, 1904, 1906 and execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924. In at least one embodiment, integer register file / bypass network 1908 performs integer operations. In at least one embodiment, floating point register file / bypass network 1910 performs floating point operations. In at least one embodiment, each of register files 1908, 1910 can include, without limitation, a bypass network that can bypass or forward a just-completed result that has not yet been written into a register file to a new dependee. In at least one embodiment, register files 1908, 1910 can communicate data with each other. In at least one embodiment, integer register file / bypass network 1908 can include, without limitation, two separate register files, one for lower 32 bits of data and a second for upper 32 bits of data. In at least one embodiment, floating point register file / bypass network 1910 can include, without limitation, 128 bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0211] In at least one embodiment, execution units 1912, 1914, 1916, 1918, 1920, 1922, 1924 can execute instructions. In at least one embodiment, register files 1908, 1910 store integer and floating point data operand values upon which microinstructions require execution. In at least one embodiment, processor 1900 can include, without limitation, any number of execution units 1912, 1914, 1916, 1918, 1920, 1922, 1924 and combinations thereof. In at least one embodiment, floating point ALU 1922 and floating point move unit 1924 can execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 1922 can include, without limitation, a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. In at least one embodiment, instructions for dealing with floating point values can be handled with floating point hardware. In at least one embodiment, ALU operations can be passed to fast ALUs 1916, 1918. In at least one embodiment, fast ALUS 1916, 1918 can execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALU 1920 as slow ALU 1920 can include, without limitation, integer execution hardware for long latency type operations such as multiplies, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be executed by AGUs 1912, 1914. In at least one embodiment, fast ALU 1916, fast ALU 1918, and slow ALU 1920 can execute integer operations on 64 bit data operands. In at least one embodiment, fast ALU 1916, fast ALU 1918, and slow ALU 1920 can be implemented to support a variety of data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, floating point ALU 1922 and floating point move unit 1924 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU 1922 and floating point move unit 1924 can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

[0212] In at least one embodiment, micro-instruction scheduler 1902, 1904, 1906 schedules dependent operations prior to completion of parent load execution. In at least one embodiment, because micro-instructions can be speculatively scheduled and executed in processor 1900, processor 1900 can also include logic to handle memory misses. In at least one embodiment, if a data load in a data cache misses, there can be dependent operations running in a pipeline that cause the scheduler to temporarily have incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations can need to be replayed and independent operations can be allowed to complete. In at least one embodiment, a scheduler and replay mechanism of at least one embodiment of a processor can also be designed to capture instruction sequences for text string compare operations.

[0213] In at least one embodiment, the term “register” can refer to an on-board processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register can be one that can be used from outside of a processor (from a programmer’s perspective). In at least one embodiment, a register can not be limited to a particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein can be implemented by circuitry within a processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data.

[0214] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 At least one component in the foregoing figures is utilized to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of a component described in relation to Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, such as in relation to Figures 1-5The described system and / or process, such as a processor including one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

[0215] Figure 20 A processor 2000 according to at least one embodiment is shown. In at least one embodiment, processor 2000 includes, without limitation, one or more processor cores (cores) 2002A-2002N, an integrated memory controller 2014, and an integrated graphics processor 2008. In at least one embodiment, processor 2000 can include additional cores up to and including an additional core 2002N represented by the dashed box. In at least one embodiment, each processor core 2002A-2002N includes one or more internal cache units 2004A-2004N. In at least one embodiment, each processor core can also access one or more shared cache units 2006. In at least one embodiment, one or more processor cores 2002A-2002N are referred to as one or more compute units or processing units.

[0216] In at least one embodiment, internal cache units 2004A-2004N and shared cache units 2006 represent a cache memory hierarchy within processor 2000. In at least one embodiment, cache memory units 2004A-2004N can include one or more levels of cache within each processor core, such as a level one or more cache, e.g., L2, L3, 4-way (L4), or other level cache, of instruction and data within each processor core and a shared level two cache, where a highest level of cache is categorized as an LLC prior to an external memory. In at least one embodiment, cache coherency logic maintains coherency between various cache units 2006 and 2004A-2004N.

[0217] In at least one embodiment, processor 2000 can also include a set of one or more bus controller units 2016 and a system agent core 2010. In at least one embodiment, one or more bus controller units 2016 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2010 provides management functionality for various processor components. In at least one embodiment, system agent core 2010 includes one or more integrated memory controllers 2014 to manage access to various external memory devices (not shown), including support for data bus protocols such as DDR DRAM.

[0218] In at least one embodiment, one or more processor cores 2002A-2002N include support for simultaneous multi-threading. In at least one embodiment, system agent core 2010 includes components for coordination and operation of processor cores 2002A-2002N during multi-threaded processing. In at least one embodiment, system agent core 2010 can additionally include a power control unit (PCU), including logic and components to regulate one or more power states of processor cores 2002A-2002N and graphics processor 2008.

[0219] In at least one embodiment, processor 2000 additionally includes a graphics processor 2008 to perform graphics processing operations. In at least one embodiment, graphics processor 2008 couples with shared cache unit 2006 and system agent core 2010, including one or more integrated memory controllers 2014. In at least one embodiment, system agent core 2010 also includes a display controller 2011 to drive output to one or more coupled displays. In at least one embodiment, display controller 2011 can also be a separate module coupled with graphics processor 2008 via at least one interconnect, or can be integrated within graphics processor 2008.

[0220] In at least one embodiment, ring based interconnect unit 2012 is used to couple the internal components of processor 2000. In at least one embodiment, an alternative interconnect unit can be used, such as a point-to-point interconnect, a switched interconnect, or other technology. In at least one embodiment, graphics processor 2008 couples with ring interconnect 2012 via I / O link 2013.

[0221] In at least one embodiment, I / O link 2013 represents at least one of a variety of I / O interconnects, including a package I / O interconnect facilitating communication between various processor components and a high performance embedded memory module 2018, such as an eDRAM module. In at least one embodiment, each of processor cores 2002A-2002N and graphics processor 2008 uses embedded memory module 2018 as a shared LLC.

[0222] In at least one embodiment, processor cores 2002A-2002N are homogenous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2002A-2002N are heterogeneous in terms of ISA, with one or more processor cores 2002A-2002N executing a common instruction set, while one or more other processor cores 2002A-2002N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2002A-2002N are heterogeneous in terms of microarchitecture, with one or more cores having a relatively higher power consumption coupled with one or more power cores having a lower power consumption. In at least one embodiment, processor 2000 can be implemented on one or more chips or as a SoC integrated circuit.

[0223] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is utilized to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of a component described in relation to Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, for example, in relation to systems and / or processes described in relation to Figures 1-5 In at least one embodiment, a processor comprises one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0224] Figure 21 A graphics processor core 2100 according to at least one embodiment described is shown. In at least one embodiment, graphics processor core 2100 is included within a graphics core array. In at least one embodiment, graphics processor core 2100 (sometimes called a core slice) can be one of one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2100 is an example of one graphics core slice, and a graphics processor described herein can include multiple graphics core slices based on a target power and performance envelope. In at least one embodiment, each graphics core 2100 can include fixed function and programmable function pipeline logic in a graphics processing pipeline 2130 that is coupled to a cache memory 2110 and that implements a graphics processing unit (GPU).

[0225] In at least one embodiment, fixed function block 2130 includes geometry / fixed function pipeline 2136, which can be shared by all of the sub-cores in graphics processor 2100, for example, in a lower performance and / or lower power graphics processor implementation. In at least one embodiment, geometry / fixed function pipeline 2136 includes a 3D fixed function pipeline, a video front-end unit, a thread generator and thread dispatcher, and a unified return buffer manager which manages a unified return buffer.

[0226] In at least one embodiment, fixed function block 2130 also includes a graphics SoC interface 2137, a graphics microcontroller 2138, and a media pipeline 2139. Graphics SoC interface 2137 provides an interface between graphics core 2100 and other processor cores within a SoC integrated circuit. In at least one embodiment, graphics microcontroller 2138 is a programmable sub-processor that is configurable to manage various functions of graphics processor 2100, including thread dispatch, scheduling, and pre-emption.

[0227] In at least one embodiment, SoC interface 2137 enables graphics core 2100 to communicate with general application processor cores within a SoC, including memory hierarchy elements such as a shared LLC cache, system RAM, and / or embedded on-chip or package DRAM. In at least one embodiment, SoC interface 2137 can also enable communication with fixed function devices within SoC, such as camera imaging pipelines, and enable use of and / or implementation of global memory atoms that can be shared between graphics core 2100 and a CPU within SoC. In at least one embodiment, SoC interface 2137 can also implement power management controls for graphics core 2100 and enable an interface between a clock domain of graphics core 2100 with other clock domains within SoC. In at least one embodiment, SoC interface 2137 enables receiving command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within graphics processor 2100. In at least one embodiment, commands and instructions can be dispatched from a command streamer and global thread dispatcher to media pipeline 2139 when media operations are to be performed, or to the geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2136, geometry and fixed function pipeline 2114) when graphics processing operations are to be performed.

[0228] In at least one embodiment, graphics microcontroller 2138 can be configured to perform various scheduling and management tasks for graphics core 2100. In at least one embodiment, graphics microcontroller 2138 can perform graphics and / or compute workload scheduling on various graphics processing engines within execution unit (EU) arrays 2102A-2102F, 2104A-2104F in sub-cores 2101A-2101F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core 2100 can submit workloads for one of a plurality of graphics processor rings, which invoke scheduling operations on appropriate graphics engines. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller 2138 can also facilitate low power or idle states for graphics core 2100, providing the ability to save and restore registers across low power state transitions independent of operating system and / or graphics driver software on the system.

[0229] In at least one embodiment, graphics core 2100 can have more or less than the illustrated sub-cores 2101A-2101F, up to N modular sub-cores. For each set of N sub-cores, graphics core 2100 can also include shared function logic 2110, shared and / or cache memory 2112, geometry / fixed function pipeline 2114, and additional fixed function logic 2116 to accelerate various graphics and compute processing tasks in at least one embodiment. In at least one embodiment, shared function logic 2110 can include logic units (e.g., samplers, math, and / or inter-thread communication logic) that are shared by each N sub-core within graphics core 2100. Shared and / or cache memory 2112 can be an LLC for N sub-cores 2101A-2101F within graphics core 2100, and can also serve as shared memory accessible by multiple sub-cores in at least one embodiment. In at least one embodiment, geometry / fixed function pipeline 2114 can be included in place of geometry / fixed function pipeline 2136 within fixed function block 2130, and can include the same or similar logic units.

[0230] In at least one embodiment, graphics core 2100 includes additional fixed function logic 2116 which can include various fixed function acceleration logic to be utilized by graphics core 2100. In at least one embodiment, additional fixed function logic 2116 includes additional geometry pipeline for use in position only shading. In position only shading, there are at least two geometry pipelines, a full geometry pipeline and a cull pipeline within geometry / fixed function pipeline 2116, 2136, which is an additional geometry pipeline that can be included in additional fixed function logic 2116. In at least one embodiment, cull pipeline is a trimmed down version of full geometry pipeline. In at least one embodiment, full pipeline and cull pipeline can execute different instances of an application, each with separate state. In at least one embodiment, position only shading can hide long cull runs of triangles that are discarded, which can complete shading earlier in some cases. For example, in at least one embodiment, cull pipeline logic in additional fixed function logic 2116 can execute position shaders in parallel with main application and often generate critical results faster than full pipeline because cull pipeline takes position attributes of vertices and shades them without needing to perform rasterization and render pixels to a frame buffer. In at least one embodiment, cull pipeline can use generated critical results to compute visibility information for all triangles regardless of whether these triangles are culled or not. In at least one embodiment, full pipeline, which can be referred to in this case as replay pipeline, can consume visibility information to skip culled triangles to only shade visible triangles that are finally passed to rasterization stage.

[0231] In at least one embodiment, additional fixed function logic 2116 can also include general-purpose processing acceleration logic, such as fixed function matrix multiplication logic for implementing a reduced CUAD program.

[0232] In at least one embodiment, each graphics sub-core 2101A-2101F includes a set of execution resources within each graphics sub-core 2101A-2101F that can be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader program. In at least one embodiment, graphics sub-cores 2101A-2101F include multiple arrays of EU’s 2102A-2102F, 2104A-2104F, thread dispatch and inter-thread communication (TD / IC) logic 2103A-2103F, 3D (e.g., texture) samplers 2105A-2105F, media samplers 2106A-2106F, shader processors 2107A-2107F, and shared local memory (SLM) 2108A-2108F. EU arrays 2102A-2102F, 2104A-2104F each include multiple execution units, which are GPGPU cores capable of performing floating-point and integer / fixed-point logic operations including graphics, media, and compute shader programs. In at least one embodiment, TD / IC logic 2103A-2103F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate

[0233] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in connection with Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is used to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs Figures 1-5at least one aspect of the middle component. In at least one embodiment, one or more systems and / or processes are implemented with one or more systems depicted in preceding figures, such as, for example Figures 1-5 A system and / or process described herein, such as, for example, a processor including one or more circuits for causing execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0234] Figure 22 A parallel processing unit (“PPU”) 2200, in accordance with at least one embodiment, is shown. In at least one embodiment, PPU 2200 is configured with machine-readable code that, if executed by PPU 2200, causes PPU 2200 to perform some or all of the processes and techniques described throughout this document. In at least one embodiment, PPU 2200 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) that are executed in parallel across multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a set of instructions configured to be executed by PPU 2200. In at least one embodiment, PPU 2200 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2200 is used to perform computations, such as linear algebraic operations and machine learning operations. Figure 22 Example parallel processors are shown for illustrative purposes only and should be interpreted as non-limiting examples of processor architectures implemented in at least one embodiment.

[0235] In at least one embodiment, PPU(s) 2200 are configured to accelerate high- performance computing (“HPC”), datacenter, and machine learning applications. In at least one embodiment, PPU(s) 2200 are configured to accelerate CUDA programs. In at least one embodiment, PPU 2200 includes, without limitation, I / O unit 2206, front-end unit 2210, scheduler unit 2212, work distribution unit 2214, hub 2216, crossbar (“Xbar”) 2220, one or more general processing clusters (“GPCs”) 2218, and one or more partition units (“memory partition units”) 2222. In at least one embodiment, PPU(s) 2200 are connected to a host processor or other PPU(s) 2200 by one or more high-speed GPU interconnects 2208. In at least one embodiment, PPU(s) 2200 are connected to a host processor or other peripheral devices by system bus 2202 or interconnect 2202. In at least one embodiment, PPU(s) 2200 are connected to a local memory comprising one or more memory devices (“memory”) 2204. In at least one embodiment, memory devices 2204 include, without limitation, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high-bandwidth memory (“HBM”) subsystems with multiple DRAM dies stacked

[0236] In at least one embodiment, high-speed GPU interconnect 2208 can refer to a link-based parallel computer bus that systems use to scale and includes one or more PPUs 2200 in conjunction with one or more CPUs (“CPUs”) that support cache coherency between PPUs 2200 and CPUs and CPU mastering. In at least one embodiment, high-speed GPU interconnect 2208 transports data and / or commands through hub 2216 to other units of PPU(s) 2200, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components not explicitly shown in Figure 22

[0237] In at least one embodiment, I / O unit 2206 is configured to facilitate communication between PPU(s) 2200 and a host processor (not shown), other PPU(s) 2200, and / or one or more Figure 22 ​The I / O units 2206 send and receive communications (e.g., commands, data) to and from the system bus 2202. In at least one embodiment, the I / O units 2206 communicate directly with the host processor(s) via the system bus 2202 or through one or more intermediate devices such as a memory hub. In at least one embodiment, the I / O units 2206 can communicate with one or more other processors, such as one or more PPUs 2200, via the system bus 2202. In at least one embodiment, the I / O units 2206 implement a PCIe interface for communications over a PCIe bus. In at least one embodiment, the I / O units 2206 implement interfaces for communicating with external devices.

[0238] In at least one embodiment, the I / O units 2206 decode packets received via the system bus 2202. In at least one embodiment, at least some packets represent commands configured to cause the PPUs 2200 to perform various operations. In at least one embodiment, the I / O units 2206 send decoded commands to various other units of the PPUs 2200 as specified by the commands. In at least one embodiment, commands are sent to the front-end unit 2210 and / or to the hub 2216 or other units of the PPUs 2200 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. Figure 22 In at least one embodiment, the I / O units 2206 are not explicitly shown in FIG. 22. In at least one embodiment, the I / O units 2206 are configured to route communications between various logical units of the PPUs 2200.

[0239] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPUs 2200 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory that is accessible (e.g., read / write) by both the host processor and the PPUs 2200 - the host interface unit can be configured to access memory requests transmitted via the I / O units 2206 over the system bus 2202 to the buffer in system memory connected to the system bus 2202. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPUs 2200, causing the front-end unit 2210 to receive the one or more command stream pointers and manage the one or more command streams, reading commands from the command stream and forwarding the commands to various units of the PPUs 2200.

[0240] In at least one embodiment, front-end unit 2210 is coupled to a scheduler unit 2212 which configures various GPCs 2218 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2212 is configured to track state information related to various tasks managed by scheduler unit 2212, where state information can indicate which task is assigned to which GPC 2218, whether a task is active or inactive, a priority associated with a task, and so forth. In at least one embodiment, scheduler unit 2212 manages multiple tasks that are executed on one or more GPCs 2218.

[0241] In at least one embodiment, scheduler unit 2212 is coupled to a work distribution unit 2214 which is configured to dispatch tasks for execution on GPCs 2218. In at least one embodiment, work distribution unit 2214 tracks a number of scheduled tasks received from scheduler unit 2212 and work distribution unit 2214 manages a pending task pool and an active task pool for each GPC 2218. In at least one embodiment, the pending task pool includes a number of slots (e.g., 32 slots) that hold tasks assigned to be processed by a particular GPC 2218; the active task pool can include a number of slots (e.g., 4 slots) for tasks that are actively being processed by a GPC 2218, such that as one task completes execution on a GPC 2218, that task is evicted from the GPC’s 2218 active task pool and another task from the pending task pool is selected for execution on the GPC 2218. In at least one embodiment, if an active task is idle, for example, while waiting for a data dependency to resolve, the active task is evicted from the GPC 2218 and returned to the pending task pool while another task is selected from the pending task pool and scheduled for execution on the GPC 2218.

[0242] In at least one embodiment, work distribution unit 2214 communicates with one or more GPCs 2218 via XBar 2220. In at least one embodiment, XBar 2220 is an interconnect network that couples many units of PPU 2200 to other units of PPU 2200 and can be configured to couple work distribution unit 2214 to a particular GPC 2218. In at least one embodiment, other units of one or more PPUs 2200 can also be connected to XBar 2220 via hub 2216.

[0243] In at least one embodiment, tasks are managed by a scheduler unit 2212 and dispatched to one of GPCs 2218 by a work distribution unit 2214. GPCs 2218 are configured to process tasks and generate results. In at least one embodiment, results can be consumed by other tasks within GPC 2218, routed to different GPCs 2218 via XBar 2220 or stored in memory 2204. In at least one embodiment, results can be written to memory 2204 via a partition unit 2222, which implements a memory interface for reading and writing data to memory 2204. In at least one embodiment, results can be transmitted to another PPU 2200 or CPU via a high-speed GPU interconnect 2208. In at least one embodiment, PPU 2200 includes, without limitation, U partition units 2222 equal to a number of separate and distinct memory devices 2204 coupled to PPU 2200.

[0244] In at least one embodiment, a host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on a host processor to schedule operations to be performed on PPU 2200. In one embodiment, multiple compute applications are executed simultaneously by PPU 2200 and PPU 2200 provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause a driver core to generate one or more tasks for execution by PPU 2200 and driver core outputs tasks to one or more streams processed by PPU 2200. In at least one embodiment, each task includes one or more related thread groups, which can be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread can refer to a plurality of threads including instructions for performing a task and exchanging data via shared memory.

[0245] In at least one embodiment, the techniques, functions, and / or processes described are implemented with one or more systems depicted in relation to the preceding figures. Figures 1-5 The described techniques, functions, and / or processes. In at least one embodiment, at least one component in the preceding figures is used to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the preceding figures performs Figures 1-5at least one embodiment, one or more systems and / or processes are implemented using the one or more systems depicted in the preceding figures, for example, in combination with Figures 1-5 A described system and / or process, such as one that includes one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one of the one or more threads encountering an error.

[0246] Figure 23 A GPC 2300 according to at least one embodiment is shown. In at least one embodiment, GPC 2300 is a GPC 2218 of FIG. 22. In at least one embodiment, each GPC 2300 includes, without limitation, a number of hardware units for processing tasks and each GPC 2300 includes, without limitation, a pipeline manager 2302, a pre-raster operations unit (“PROP”) 2304, a raster engine 2308, a work distribution crossbar (“WDX”) 2316, a memory management unit (“MMU”) 2318, one or more data processing clusters (“DPCs”) 2306, and any suitable combination of such components. Figure 22

[0247] In at least one embodiment, operation of GPC 2300 is controlled by pipeline manager 2302. In at least one embodiment, pipeline manager 2302 manages configuration of one or more DPCs 2306 to process tasks assigned to GPC 2300. In at least one embodiment, pipeline manager 2302 configures at least one of one or more DPCs 2306 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC 2306 is configured to execute vertex shader programs on a programmable streaming multi-processor (“SM”) 2314. In at least one embodiment, pipeline manager 2302 is configured to route packets received from a work distribution unit to appropriate logical units within GPC 2300, and in at least one embodiment, some packets can be routed to fixed function hardware units in PROP 2304 and / or raster engine 2308 while other packets can be routed to DPCs 2306 for processing by a primitive engine 2312 or SM 2314. In at least one embodiment, pipeline manager 2302 configures at least one of DPCs 2306 to implement a neural network model and / or compute pipeline. In at least one embodiment, pipeline manager 2302 configures at least one of DPCs 2306 to execute at least a portion of a CUDA program.

[0248] ​In at least one embodiment, PROP unit 2304 is configured to route data generated by raster engine 2308 and DPC 2306 to a raster operations (“ROP”) unit in a partition unit, such as partition unit 2202 described above in connection with FIG. 22, for example. Figure 22 In at least one embodiment, PROP unit 2304 is configured to perform optimizations for color blending, organize pixel data, perform address translations, and / or the like. In at least one embodiment, raster engine 2308 includes, without limitation, a number of fixed function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2308 includes, without limitation, a setup engine, a coarse raster engine, a cull engine, a clip engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, setup engine receives transformed vertices and generates plane equations associated with geometric primitives defined by the vertices; plane equations are passed to coarse raster engine to generate coverage information (e.g., x, y coverage masks for tiles) for the primitive; output from coarse raster engine is passed to cull engine where fragments associated with primitives that fail a z-test are culled, and to clip engine where fragments that are outside of a viewing frustum are clipped. In at least one embodiment, clipped and culled fragments are passed to fine raster engine to generate attributes of pixel fragments based on plane equations generated by setup engine. In at least one embodiment, output from raster engine 2308 includes fragments to be processed by any suitable entity, such as by a fragment shader implemented within DPC 2306.

[0249] In at least one embodiment, each DPC 2306 included in GPC 2300 includes, without limitation, a M-Pipe Controller (“MPC”) 2310; a primitive engine 2312; one or more SMs 2314; and any suitable combination thereof. In at least one embodiment, MPC 2310 controls operation of DPC 2306, routing received packets from pipeline manager 2302 to appropriate units in DPC 2306. In at least one embodiment, packets associated with vertices are routed to primitive engine 2312, which is configured to fetch vertex attributes associated with the vertices from memory; in contrast, packets associated with a shader program can be transmitted to SM 2314.

[0250] In at least one embodiment, SM 2314 comprises, without limitation, a programmable streaming processor configured to process tasks represented by a plurality of threads. In at least one embodiment, SM 2314 is multi-threaded and configured to execute a number of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a single-instruction, multiple-data (“SIMD”) architecture wherein each thread in group of threads is configured to process a different data set based on same set of instructions. In at least one embodiment, all threads in a group of threads execute same instructions. In at least one embodiment, SM 2314 implements a single-instruction, multiple-thread (“SIMT”) architecture wherein each thread in a group of threads is configured to process a different data set based on same set of instructions, but where individual threads in group of threads are allowed to diverge during execution. In at least one embodiment, program counter, call stack, and execution state are maintained for each thread block, enabling concurrency between thread blocks and serial execution within thread blocks as threads within a thread block diverge. In another embodiment, program counter, call stack, and execution state are maintained for each individual thread, enabling equal concurrency between all threads within and across thread blocks. In at least one embodiment, execution state is maintained for each individual thread and threads executing same instructions can be converged and executed in parallel for efficiency. Concurrency within a thread block and between thread blocks is managed and coordinated with one or more schedulers, in at least one embodiment. Figure 24 At least one embodiment of SM 2314 is described in greater detail below.

[0251] In at least one embodiment, MMU 2318 interfaces with GPC 2300 and a memory partition unit (e.g., partition unit 2222 of FIG. 22) and MMU 2318 provides translations of virtual addresses to physical addresses, memory protection, and demand paging. In at least one embodiment, MMU 2318 provides one or more translation lookaside buffers (TLBs) for Figure 22

[0252] In at least one embodiment, one or more systems depicted in relation to preceding figures are utilized to implement techniques, functions, and / or processes described in conjunction with Figures 1-5 preceding figures are utilized to implement at least one aspect of a component in Figures 1-5 preceding figures are utilized to implement one or more systems and / or processes, such as in conjunction with Figures 1-5 ​The described system and / or process, such as a processor including one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

[0253] Figure 24 A streaming multi-processor (“SM”) 2400 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2400 is a SM 2314 of FIG. 23. Figure 23 In at least one embodiment, SM 2400 includes, without limitation, an instruction cache 2402; one or more scheduler units 2404; a register file 2408; one or more processing cores (“cores”) 2410; one or more special function units (“SFUs”) 2412; one or more load / store units (“LSUs”) 2414; an interconnect network 2416; shared memory / level one (“LI”) cache 2418; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks to general processing clusters (“GPCs”) of parallel processing units (“PPUs”) for execution, and each task is assigned a specific data processing cluster (“DPC”) within a GPC and, if task is associated with a shader program, to one of SMs 2400. In at least one embodiment, scheduler unit 2404 receives tasks from work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2400. In at least one embodiment, scheduler unit 2404 schedules threads of a thread block to execute as warps of parallel threads, with each thread block allocated at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, scheduler unit 2404 manages a plurality of different thread blocks, allocating warps of threads to different thread blocks and then dispatching instructions from different ones of the plurality of different cooperative groups to various functional units (e.g., processing cores 2410, SFUs 2412, and LSUs 2414) during each clock cycle. In at least one embodiment, SM 2400 includes one or more clusters of thread blocks, where a cluster of thread blocks can enable programming control of locality at a greater granularity than a single thread block of a single streaming multi-processor (SM). In at least one embodiment, a cluster of thread blocks (also referred to as a “cluster”) enables multiple thread blocks running concurrently across streaming multi-processors to synchronize and cooperatively fetch, exchange, or otherwise use data.

[0254] In at least one embodiment, a “cooperative group” can refer to a programming model for organizing groups of communication threads that allows developers to express the granularity at which threads are communicating, enabling richer, more efficient parallel decomposition. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, an API of a conventional programming model provides a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., a syncthreads() function). However, in at least one embodiment, a programmer can define thread groups at less than a thread block granularity and synchronize within defined groups to achieve higher performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads in a cooperative group. In at least one embodiment, sub-block granularity is as small as a single thread. In at least one embodiment, a programming model supports clean composition across software boundaries, so that library and utility functions can safely synchronize in their local environment without having to make assumptions about convergence. In at least one embodiment, cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across a grid of thread blocks.

[0255] In at least one embodiment, dispatch unit 2406 is configured to send instructions to one or more of the functional units, and a scheduler unit 2404 includes, without limitation, two dispatch units 2406 that enable two different instructions from the same thread to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 2404 includes a single dispatch unit 2406 or an additional dispatch unit 2406.

[0256] In at least one embodiment, each SM 2400 includes, without limitation, a register file 2408 that provides a set of registers for functional units of the SM 2400. In at least one embodiment, register file 2408 is split between functional units as is needed to perform computational operations. In at least one embodiment, register file 2408 is partitioned between different threads executed by the SM 2400, and register file 2408 provides temporary storage for operands of the data paths connected to the functional units. In at least one embodiment, each SM 2400 includes, without limitation, a plurality L of processing cores 2410. In at least one embodiment, SM 2400 includes, without limitation, a large number (e.g., 128 or more) of different processing cores 2410. In at least one embodiment, each processing core 2410 includes, without limitation, a full-pipe, single precision, double precision, and / or mixed precision processing unit including, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic for the floating point arithmetic logic unit is implemented according to IEEE 754-2008 standard. In at least one embodiment, processing core 2410 includes, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0257] In at least one embodiment, tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing cores 2410. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on 4x4 matrices and performs matrix multiplication and accumulation operations D = A x B + C, where A, B, C, and D are 4x4 matrices.

[0258] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating point matrices, and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, a tensor core performs 32-bit floating point accumulation operations on 16-bit floating point input data. In at least one embodiment, 16-bit floating point multiplication uses 64 operations and results in a full precision product, which is then accumulated with other intermediate products using 32-bit floating point addition for 4x4x4 matrix multiplication. In at least one embodiment, tensor cores are used to perform larger two-dimensional or higher dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API such as a CUDA-C++ API exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at a CUDA level, a warp level interface assumes a 16x16 size matrix across all 32 warp threads.

[0259] In at least one embodiment, each SM 2400 includes, without limitation, M SFUs 2412 to perform special functions (e.g., certain math functions, atomics, bit endcomplement, etc.). In at least one embodiment, SFUs 2412 include, without limitation, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs 2412 include, without limitation, texture units configured to perform texture mapping filtering operations. In at least one embodiment, texture units are configured to load a texture map (e.g., a 2D array of texture pixels) from memory and sample the texture map to produce sampled texture values for use by a shader program executed by SM 2400. In at least one embodiment, texture maps are stored in shared memory / L1 cache 2418. In at least one embodiment, texture units use mip-maps (e.g., different levels of detail for a texture map) to perform texture operations such as filtering operations. In at least one embodiment, each SM 2400 includes, without limitation, two texture units.

[0260] In at least one embodiment, each SM 2400 includes, without limitation, N LSUs 2414 that implement load and store operations between shared memory / L1 cache 2418 and register file 2408. In at least one embodiment, each SM 2400 includes, without limitation, interconnect network 2416 that connects each of the functional units to register file 2408 and LSUs 2414 to register file 2408 and shared memory / L1 cache 2418. In at least one embodiment, interconnect network 2416 is a cross-bar switch that can be configured to connect any of the functional units to any of the registers in register file 2408, and to connect LSUs 2414 to registers in register file 2408 and to memory locations in shared memory / L1 cache 2418.

[0261] In at least one embodiment, shared memory / L1 cache 2418 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between SMs 2400 and graphics engines and between threads within SMs 2400. In at least one embodiment, shared memory / L1 cache 2418 includes, without limitation, 128 KB of storage and is located on a path from SM 2400 to partition units. In at least one embodiment, shared memory / L1 cache 2418 is used for caching reads and writes, in at least one embodiment. In at least one embodiment, one or more of shared memory / L1 cache 2418, L2 cache, and memory are backing stores.

[0262] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use shared memory or use it as a cache, e.g., if shared memory is configured to use half the capacity, then textures and load / store operations can use remaining capacity. According to at least one embodiment, integration within shared memory / L1 cache 2418 enables shared memory / L1 cache 2418 to be used as a high-throughput pipe for streaming data while also providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared to graphics processing. In at least one embodiment, fixed function GPU is bypassed, creating a more straightforward programming model. In at least one embodiment, in a general purpose parallel computation configuration, work assignment unit assigns and distributes blocks of threads directly to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in a computation to ensure that each thread generates unique results, use SM 2400 to execute the program and perform the computation, use shared memory / L1 cache 2418 to communicate between threads, and use LSUs 2414 to read and write to global memory through shared memory / L1 cache 2418 and memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM 2400 writes to scheduler unit 2404 commands that can be used to launch new work on DPCs. In at least one embodiment, SM 2400 includes one or more distributed shared memories (or distributed shared memories) that support direct SM to SM operations, such as loading, storing and executing atomic operations across multiple SMs sharing a memory block.

[0263] In at least one embodiment, the SM 2500 includes one or more asynchronous execution functions, including Tensor Memory Accelerator (TMA) units capable of transferring data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa. In at least one embodiment, the SM 2400 includes one or more TMAs for asynchronous copying between thread blocks in a cluster. In at least one embodiment, the SM 2400 includes one or more asynchronous transaction barriers for performing atomic data moves and synchronization. In at least one embodiment, the SM 2400 includes a Tensor Core Transformer Engine, comprising software and one or more cores for accelerating transformer model training and inference. In at least one embodiment, a transformer executing one or more processor cores of the Tensor Core Transformer Engine manages FP8 and 16-bit computations and dynamically selects between them by re-casting and scaling in each layer of one or more neural networks.

[0264] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices (e.g., additional PPUs, memory, RISC CPU, MMU, digital-to-analog converter (“DAC”), etc.).

[0265] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU (“iGPU”) included in the motherboard's chipset.

[0266] In at least one embodiment, the combination is achieved using one or more systems depicted in relation to the foregoing figures. Figures 1-5 The described techniques, functions, and / or processes. In at least one embodiment, at least one component of the foregoing figures is used to cause the execution of one or more threads corresponding to one or more corresponding kernels to selectively stop at least in part based on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of the foregoing figures performs... Figures 1-5at least one embodiment, one or more systems and / or processes are implemented using the one or more systems depicted in the preceding figures, such as the systems illustrated in Figures 1-5 A described system and / or process, such as a processor including one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

[0267] Software constructs for general purpose computing

[0268] The following figures set forth, without limitation, example software constructs for implementing at least one embodiment.

[0269] Figure 25 A software stack of a programming platform is shown, in accordance with at least one embodiment. In at least one embodiment, a programming platform is a platform for accelerating compute tasks with hardware on a computing system. In at least one embodiment, a software developer can access a programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, a programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL TM ), SYCL, or Intel One API.

[0270] In at least one embodiment, software stack 2500 of a programming platform provides an execution environment for application 2501. In at least one embodiment, application 2501 can include any computer software capable of launching on software stack 2500. In at least one embodiment, application 2501 can include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0271] In at least one embodiment, application 2501 and software stack 2500 run on hardware 2507. In at least one embodiment, hardware 2507 can include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, software stack 2500 can be vendor specific, and only compatible with devices from a particular vendor, e.g., with CUDA. In at least one embodiment, software stack 2500 can be used with devices from different vendors, e.g., with OpenCL. In at least one embodiment, hardware 2507 includes a host connected to one or more devices that can be accessed via an application programming interface (API) call to perform a computational task. In at least one embodiment, a device within hardware 2507 can include, without limitation, a GPU, FPGA, AI engine, or other computing device (but also can include a CPU) and its memory, as opposed to a host within hardware 2507, which can include, without limitation, a CPU (but also can include a computing device) and its memory.

[0272] In at least one embodiment, software stack 2500 of a programming platform includes, without limitation, a plurality of libraries 2503, a runtime 2505, and a device kernel driver 2506. In at least one embodiment, each of libraries 2503 can include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, libraries 2503 can include, without limitation, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, libraries 2503 include functions optimized for execution on one or more types of devices. In at least one embodiment, libraries 2503 can include, without limitation, functions for performing mathematical, deep learning, and / or other types of operations on a device. In at least one embodiment, libraries 2503 are associated with a corresponding API 2502, which can include one or more APIs that expose functions implemented in libraries 2503. In at least one embodiment, a processor (e.g., CPU, GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., a parent kernel) can launch a second kernel (e.g., a child kernel), and a processor can use the second kernel to launch an additional kernel (e.g., a grandchild kernel) independent of the first kernel. In at least one embodiment, a processor executes or calls an API from memory to support dynamic stream prioritization (e.g., updating a priority while using a stream to perform an operation). For example, when a processor executes the API, it allows a programmer to copy a stream priority from one stream to one or more other streams.

[0273] In at least one embodiment, software stack 2500 includes an API to support dynamic stream priority (e.g., priority is updated while a stream is being used to perform operations), which allows a programmer to set a priority of a stream at any time after creation. In at least one embodiment, software stack 2500 includes an API to support dynamic stream priority (e.g., priority is updated while a stream is being used to perform operations), which allows a programmer to get a current priority of a stream, where the priority is one of a plurality of attributes of a stream. In at least one embodiment, software stack 2500 includes an API to support dynamic stream priority (e.g., priority is updated while a stream is being used to perform operations), which allows a programmer to get a current priority of a stream as a single attribute. In at least one embodiment, software stack 2500 includes an API to support dynamic stream priority (e.g., priority is updated while a stream is being used to perform operations), which allows a programmer to launch a kernel so that an operation is performed on a stream with a set priority (which can be different from a stream priority). In at least one embodiment, software stack 2500 includes an API to indicate whether an object (e.g., a thread synchronization object such as a barrier) tracks whether all data movement operations for a set of threads operating on a GPU have completed with a specified status after a specified time period, where the specified status can be a status indicating that data has been moved and is ready for use, and uses an expected parity value as an input to the API to specify.

[0274] In at least one embodiment, software stack 2500 includes one or more APIs to update a kernel. In at least one embodiment, an execution API or an API to be executed to update a processor’s support for a contextless kernel from memory, which allows a programmer to add a kernel node to a graph without a graphics context, such that a graphics context can be dynamically associated with a kernel at runtime. In at least one embodiment, software stack 2500 includes one or more APIs that allow a programmer to get a kernel identifier and a graphics context from a kernel node as separate parameters, obtaining parameters from a kernel and a contextless kernel. In at least one embodiment, software stack 2500 includes one or more APIs to launch a task graph (e.g., a task graph) and execute one or more task graphs (e.g., including one or more programs) using a parallel processor (such as one or more graphics processing units).

[0275] In at least one embodiment, the software stack 2500 includes one or more APIs for associating one or more instructions with one or more memory sorting operations (e.g., fence or memory bar operations). In at least one embodiment, instructions are associated with one or more domains such that memory sorting operations are performed in association with one or more specific domains without interfering with instructions in other domains. In at least one embodiment, the software stack 2500 includes APIs for indicating that a thread has reached (e.g., at a thread synchronization barrier) or completed a phase of work associated with an asynchronous data movement operation on the GPU. In at least one embodiment, the software stack 2500 includes one or more APIs for allowing a programmer to manually indicate an expected transaction count when a thread completes a phase of work, the transaction count being used to update an object that tracks whether all data movement operations of a set of threads have completed.

[0276] In at least one embodiment, application 2501 is written as source code, which is compiled into executable code, as follows: Figures 30-32 This will be discussed in more detail. In at least one embodiment, the executable code of application 2501 may run at least partially on an execution environment provided by software stack 2500. In at least one embodiment, during the execution of application 2501, code that needs to run on the device (compared to the host) may be obtained. In this case, in at least one embodiment, runtime 2505 may be invoked to load and start the necessary code on the device. In at least one embodiment, runtime 2505 may include any technically feasible runtime system capable of supporting the execution of application 2501.

[0277] In at least one embodiment, runtime 2505 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 2504). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, etc. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, dealing with, and copying device memory, as well as functions for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the function is a global function that can be called from the host), and functions for setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0278] In at least one embodiment, runtime libraries and corresponding APIs 2504 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number) of APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number) of APIs can expose a higher-level set of functions. In at least one embodiment, high-level runtime APIs can be built on top of low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of language-independent runtime APIs.

[0279] In at least one embodiment, one or more processors disclosed in “processing systems” can execute, access, or otherwise use software stacks 2500. For example, APU 1200, CPU 1300, Figures 15A-15B In at least one embodiment, exemplary graphics processor, general purpose graphics processing unit (“GPGPU”) 1630, parallel processor 1700, processing cluster 1794, graphics multiprocessor 1734, graphics multiprocessor 1796, graphics processor 1800, processor 1900, processor 2000, parallel processing unit (“PPU”) 2200, GPC 2300, and / or streaming multiprocessor (“SM”) 2400 can execute, use, call, or otherwise implement one or more APIs included in software stack 2500, for example, by accessing memory.

[0280] In at least one embodiment, device kernel driver 2506 is configured to facilitate communication with underlying devices. In at least one embodiment, device kernel driver 2506 can provide low-level functions relied upon by APIs such as APIs 2504 and / or other software. In at least one embodiment, device kernel driver 2506 can be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 2506 can compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a particular target device at runtime (caching compiled binary code), which is sometimes also referred to as “final” code. In at least one embodiment, doing so can allow final code to run on a target device that can not have existed when source code was initially compiled into PTX code. Alternatively, in at least one embodiment, device source code can be compiled into binary code offline without requiring device kernel driver 2506 to compile IR code at runtime.

[0281] In at least one embodiment, one or more systems depicted in relation to preceding figures are utilized to implement the combination of Figures 1-5The described techniques, functions, and / or processes. In at least one embodiment, at least one component of the foregoing figures is used to cause the execution of one or more threads corresponding to one or more corresponding kernels to selectively stop at least in part based on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of the foregoing figures performs... Figures 1-5 At least one aspect of the components. In at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the foregoing figures, for example, in combination with Figures 1-5 The described system and / or process, such as a processor, includes one or more circuits for causing the execution of one or more threads corresponding to one or more respective cores to be selectively stopped at least in part based on at least one of the one or more threads encountering an error.

[0282] Figure 26 The illustration shows an embodiment according to at least one of the embodiments. Figure 25 The software stack 2500 is a CUDA implementation. In at least one embodiment, the CUDA software stack 2600 on which an application 2601 can be launched includes a CUDA library 2603, a CUDA runtime 2605, a CUDA driver 2607, and a device kernel driver 2608. In at least one embodiment, the CUDA software stack 2600 executes on hardware 2609, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0283] In at least one embodiment, application 2601, CUDA runtime 2605, and device kernel driver 2608 can respectively perform functions similar to those of application 2701, runtime 2705, and device kernel driver 2706, in combination with the above. Figure 25described. In at least one embodiment, CUDA driver 2607 includes a library (libcuda.so) that implements CUDA driver API 2606. In at least one embodiment, similar to CUDA runtime API 2604 implemented by CUDA runtime library (cudart), CUDA driver API 2606 can expose, without limitation, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability, among others. In at least one embodiment, CUDA driver API 2606 differs from CUDA runtime API 2604 in that CUDA runtime API 2604 simplifies device code management by providing implicit initialization, context (similar to a process) management, and module (similar to a dynamically loaded library) management. In contrast to high-level CUDA runtime API 2604, in at least one embodiment, CUDA driver API 2606 is a low-level API that provides more fine-grained control over a device, particularly with respect to contexts and module loading. In at least one embodiment, CUDA driver API 2606 can expose functions for context management that are not exposed by CUDA runtime API 2604. In at least one embodiment, CUDA driver API 2606 is also language agnostic and supports, for example, OpenCL in addition to CUDA runtime API 2604. Further, in at least one embodiment, development libraries including CUDA runtime 2605 can be considered separate from driver components, including user-mode CUDA driver 2607 and kernel-mode device driver 2608 (sometimes also referred to as a “display” driver).

[0284] In at least one embodiment, CUDA libraries 2603 can include, without limitation, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that can be utilized by parallel computing applications such as application 2601. In at least one embodiment, CUDA libraries 2603 can include mathematical libraries such as a cuBLAS library that is an implementation of basic linear algebra subprograms (“BLAS”) for performing linear algebra operations, a cuFFT library for computing fast Fourier transforms (“FFTs”), a cuRAND library for generating random numbers, and / or the like. In at least one embodiment, CUDA libraries 2603 can include deep learning libraries such as a cuDNN library for primitives of deep neural networks and a TensorRT platform for high-performance deep learning inference, among others.

[0285] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement the techniques described in connection with Figures 1-5The described techniques, functions, and / or processes. In at least one embodiment, at least one component of the foregoing figures is used to cause the execution of one or more threads corresponding to one or more corresponding kernels to selectively stop at least in part based on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of the foregoing figures performs... Figures 1-5 At least one aspect of the components. In at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the foregoing figures, for example, in combination with Figures 1-5 The described system and / or process, such as a processor, includes one or more circuits for causing the execution of one or more threads corresponding to one or more respective cores to be selectively stopped at least in part based on at least one of the one or more threads encountering an error.

[0286] Figure 27 The illustration shows an embodiment according to at least one of the embodiments. Figure 25 The software stack 2500 is a ROCm implementation. In at least one embodiment, the ROCm software stack 2700 on which application 2701 can be launched includes a language runtime 2703, a system runtime 2705, a thunk 2707, and a ROCm kernel driver 2708. In at least one embodiment, the ROCm software stack 2700 executes on hardware 2709, which may include a ROCm-enabled GPU developed by AMD Inc. of Santa Clara, California.

[0287] In at least one embodiment, application 2701 can perform the above-described combination. Figure 25 The discussed application 2501 has similar functionality. Additionally, in at least one embodiment, the language runtime 2703 and system runtime 2705 can perform functions combined with the above. Figure 25similar functions discussed above in connection with the CUDA runtime API 2604, such as functions for memory management, execution control, device management, error handling, and synchronization, etc. Figure 26 similar functions discussed above in connection with the CUDA runtime API 2604, such as functions for memory management, execution control, device management, error handling, and synchronization, etc.

[0288] In at least one embodiment, the thunk (ROCt) 2707 is an interface 2706 that can be used to interact with an underlying ROCm driver 2708. In at least one embodiment, the ROCm driver 2708 is a ROCk driver, which is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs similar functions discussed above in connection with the device kernel driver 2506. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to share system resources more efficiently via hardware features. Figure 25 similar functions discussed above in connection with the device kernel driver 2506. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to share system resources more efficiently via hardware features.

[0289] In at least one embodiment, various libraries (not shown) can be included in the ROCm software stack 2700 above the language runtime 2703 and provide similar functions discussed above in connection with the CUDA libraries 2603. In at least one embodiment, various libraries can include, without limitation, math, deep learning, and / or other libraries, such as a hipBLAS library that implements similar functions to CUDA cuBLAS, a rocFFT library that is similar to CUDA cuFFT for computing FFTs, etc. Figure 26 similar functions discussed above in connection with the CUDA runtime API 2604, such as functions for memory management, execution control, device management, error handling, and synchronization, etc.

[0290] In at least one embodiment, one or more systems depicted in relation to the aforementioned figures are utilized to implement systems and / or processes described in connection with Figures 1-5 technology, functions, and / or processes described. In at least one embodiment, at least one component in the aforementioned figures is used to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the aforementioned figures performs at least one aspect of a component described in connection with Figures 1-5 technology, functions, and / or processes described. In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the aforementioned figures, for example, a system and / or process described in connection with Figures 1-5 technology, functions, and / or processes described. In at least one embodiment, a processor comprises one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0291] Figure 28 An OpenCL implementation of a software stack 2500 of a Figure 25 device 2500 is shown in accordance with at least one embodiment. In at least one embodiment, an OpenCL software stack 2800 on which an application 2801 can be launched includes an OpenCL framework 2810, an OpenCL runtime 2806, and a driver 2807. In at least one embodiment, OpenCL software stack 2800 executes on hardware 2809 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers can be required to interoperate with hardware from such vendors.

[0292] In at least one embodiment, application 2801, OpenCL runtime 2806, device kernel driver 2807, and hardware 2808 can perform similar functions to application 2501, runtime 2505, device kernel driver 2506, and hardware 2507, respectively, discussed above in connection with Figure 25 In at least one embodiment, application 2801 also includes an OpenCL kernel 2802 with code to be executed on a device.

[0293] In at least one embodiment, OpenCL defines a “platform” that allows a host to control devices connected to that host. In at least one embodiment, OpenCL framework provides a platform layer API and a runtime API, shown as platform API 2803 and runtime API 2805. In at least one embodiment, runtime API 2805 uses a context to manage execution of kernels on a device. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 2805 can use to manage a command queue for that device, program and kernel objects, shared memory objects, etc. In at least one embodiment, platform API 2803 exposes functions that allow a device context to be used to select and initialize a device, submit work to a device via a command queue, enable data transfers to and from a device, etc. Additionally, in at least one embodiment, OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0294] In at least one embodiment, compiler 2804 is also included in OpenCL framework 2810. In at least one embodiment, source code can be compiled offline before an application is executed or online during execution of an application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 2804, which is included to represent any number of compilers that can be used to compile source and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before such applications are executed.

[0295] In at least one embodiment, one or more systems depicted in relation to the aforementioned figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 In at least one embodiment, at least one component in the aforementioned figures is utilized to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component in the aforementioned figures performs at least one aspect of a component described in relation to Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the aforementioned figures, such as in relation to Figures 1-5The described system and / or process, such as a processor, includes one or more circuits for causing the execution of one or more threads corresponding to one or more respective cores to be selectively stopped at least in part based on at least one of the one or more threads encountering an error.

[0296] Figure 29 Software supported by a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform 2904 is configured to support various programming models 2903, middleware and / or libraries 2902, and frameworks 2901 that an application 2900 may depend on. In at least one embodiment, the application 2900 may be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which may depend on libraries such as cuDNN, the NVIDIA Collective Communications Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computation on the underlying hardware.

[0297] In at least one embodiment, the programming platform 2904 can be a combination of the above-described components. Figure 26 , Figure 27 and Figure 28 One of the described CUDA, ROCm, or OpenCL platforms. In at least one embodiment, the programming platform 2904 supports multiple programming models 2903, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, the programming model 2903 may expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 2903 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multiprocessing (“OpenMP”), Open Accelerator (“OpenACC”), and / or Vulcan Compute.

[0298] In at least one embodiment, libraries and / or middleware 2902 provide implementations of abstractions of programming models 2904. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications in addition to those that can be obtained from programming platform 2904. In at least one embodiment, libraries and / or middleware 2902 can include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, libraries and / or middleware 2902 can include NCCL and ROCm Communication Collectives Library (“RCCL”) libraries, which provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and Eigen libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0299] In at least one embodiment, application frameworks 2901 rely on libraries and / or middleware 2902. In at least one embodiment, each application framework 2901 is a software framework used to implement a standard structure for application software. Returning to AI / ML example discussed above, in at least one embodiment, a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework can be used to implement an AI / ML application.

[0300] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is used to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of a component described in relation to Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, e.g., in relation to systems and / or processes described in relation to Figures 1-5 In at least one embodiment, a processor comprises one or more circuits to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0301] Figure 30 FIG. 1 illustrates a compiler 100 to compile code to run on a system 102 in accordance with at least one embodiment.Figures 25-28 one of the programming platforms. In at least one embodiment, compiler 3001 receives source code 3000, which includes both host code as well as device code. In at least one embodiment, compiler 3001 is configured to convert source code 3000 into host executable code 3002 for execution on a host and device executable code 3003 for execution on a device. In at least one embodiment, source code 3000 can be compiled offline prior to execution of an application, or online during execution of an application. In at least one embodiment, compiler 3001 includes or has access to one or more libraries to identify sequences of API calls for execution of a single fused API, where a single fused API is a combined API of two or more APIs.

[0302] In at least one embodiment, source code 3000 can include code in any programming language supported by compiler 3001, such as C++, C, Fortran, etc. In at least one embodiment, source code 3000 can include a single-source file with a mix of host code and device code, with locations of device code indicated therein. In at least one embodiment, a single-source file can be a.cu file including CUDA code or a.hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3000 can include multiple source code files, rather than a single-source file, with host code and device code separated.

[0303] In at least one embodiment, compiler 3001 is configured to compile source code 3000 into host executable code 3002 for execution on a host and device executable code 3003 for execution on a device. In at least one embodiment, compiler 3001 performs operations including parsing source code 3000 into an abstract syntax tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3000 includes a single-source file, compiler 3001 can separate device code from host code in such single-source file, compile device code and host code into device executable code 3003 and host executable code 3002, respectively, and link device executable code 3003 and host executable code 3002 together in a single file, as discussed in more detail below with respect to FIG. 3B. Figure 31

[0304] ​In at least one embodiment, host executable code 3002 and device executable code 3003 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3002 can comprise native object code, while device executable code 3003 can comprise PTX intermediate representation code. In the case of ROCm, in at least one embodiment, both host executable code 3002 and device executable code 3003 can comprise target binary code.

[0305] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is utilized to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of a component described in relation to Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, such as, for example, systems and / or processes described in relation to Figures 1-5 In at least one embodiment, a processor comprises one or more circuits to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0306] Figure 31 is a more detailed illustration of compiled code to execute on one of Figures 25-28 programming platforms in accordance with at least one embodiment. In at least one embodiment, compiler 3101 is configured to receive source code 3100, compile source code 3100, and output executable 3110. In at least one embodiment, source code 3100 is a single source file, such as a.cu file, a.hip.cpp file, or other format file, that includes both host code and device code. In at least one embodiment, compiler 3101 can be, without limitation, an NVIDI A CUDA compiler (“NVCC”) for compiling CUDA code in a.cu file, or an HCC compiler for compiling HIP code in a.hip.cpp file.

[0307] In at least one embodiment, compiler 3101 includes a compiler front end 3102, a host compiler 3105, a device compiler 3106, and a linker 3109. In at least one embodiment, compiler front end 3102 is configured to separate device code 3104 from host code 3103 in source code 3100. In at least one embodiment, device code 3104 is compiled by device compiler 3106 into device executable code 3108, which as described, can include binary code or IR code. In at least one embodiment, host code 3103 is separately compiled by host compiler 3105 into host executable code 3107. In at least one embodiment, for NVCC, host compiler 3105 can be, without limitation, a general C / C++ compiler that outputs native object code, while device compiler 3106 can be, without limitation, a low-level virtual machine (“LLVM”)-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 3105 and device compiler 3106 can be, without limitation, LLVM-based compilers that output target binary code.

[0308] In at least one embodiment, after source code 3100 is compiled into host executable code 3107 and device executable code 3108, linker 3109 links host and device executable code 3107 and 3108 together in executable file 3110. In at least one embodiment, native object code for a host and PTX or binary code for a device can be linked together in an executable and linkable format (“ELF”) file, which is a container format for storing object code.

[0309] In at least one embodiment, one or more systems depicted in relation to the aforementioned figures are utilized to implement techniques, functions, and / or processes described in relation to Figures 1-5 the aforementioned figures are utilized to enable execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component of the aforementioned figures performs at least one aspect of a component described in relation to Figures 1-5 the aforementioned figures are utilized to implement one or more systems and / or processes, e.g., in relation to systems and / or processes described in relation to Figures 1-5 a processor comprising one or more circuits to enable execution of one or more threads corresponding to one or more respective cores to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0310] Figure 32 Conversion of source code prior to compilation is shown in accordance with at least one embodiment. In at least one embodiment, source code 3200 is passed through a conversion tool 3201 that converts source code 3200 to converted source code 3202. In at least one embodiment, a compiler 3203 is used to compile converted source code 3202 to host executable code 3204 and device executable code 3205, a process similar to that of compiler 3001 compiling source code 3000 to host executable code 3002 and device executable code 3003, as described above in connection with Figure 30 .

[0311] In at least one embodiment, the conversion performed by conversion tool 3201 is used to port source code 3200 to execute in a different environment than originally intended. In at least one embodiment, conversion tool 3201 can include, without limitation, a HIP transpiler that is used to “hipify” CUDA code intended for a CUDA platform to HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, conversion of source code 3200 can include parsing source code 3200 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as discussed in more detail below in connection with Figure 33A and Figure 34 . Returning to the example of porting CUDA code, in at least one embodiment, calls to CUDA runtime APIs, CUDA driver APIs, and / or CUDA libraries can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by conversion tool 3201 can sometimes be incomplete, requiring additional human effort to fully port source code 3200.

[0312] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in connection with Figures 1-5 . In at least one embodiment, at least one component in the foregoing figures is used to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of the components in Figures 1-5 . In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, such as in connection with Figures 1-5The described system and / or process, such as a processor including one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

[0313] Configuring a GPU for general-purpose computing

[0314] The following figures illustrate, without limitation, exemplary architectures for compiling and executing compute source code, in accordance with at least one embodiment.

[0315] Figure 33A A system 3300 configured to compile and execute CUDA source code 3310 using different types of processing units is shown, in accordance with at least one embodiment. In at least one embodiment, system 3300 includes, without limitation, CUDA source code 3310, CUDA compiler 3350, host executable code 3370(1), host executable code 3370(2), CUDA device executable code 3384, CPU 3390, CUDA-enabled GPU 3394, GPU 3392, CUDA to HIP translation tool 3320, HIP source code 3330, HIP compiler driver 3340, HCC 3360, and HCC device executable code 3382.

[0316] In at least one embodiment, CUDA source code 3310 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, without limitation, mechanisms to define device code and to distinguish between device code and host code. In at least one embodiment, device code is source code that, after compilation, can be executed in parallel on a device. In at least one embodiment, a device can be a processor optimized for parallel instruction processing, such as CUDA-enabled GPU 3390, GPU 3392, or another GPGPU, etc. In at least one embodiment, host code is source code that, after compilation, can be executed on a host. In at least one embodiment, a host is a processor optimized for sequential instruction processing, such as CPU 3390.

[0317] In at least one embodiment, CUDA source code 3310 includes, without limitation, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, global functions 3312, device functions 3314, host functions 3316, and host / device functions 3318 can be intermingled in CUDA source code 3310. In at least one embodiment, each global function 3312 is executable on a device and is invocable from a host. In at least one embodiment, one or more of global functions 3312 can thus serve as an entry point to a device. In at least one embodiment, each global function 3312 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3312 define a kernel that is executable on a device and is invocable from such device. In at least one embodiment, a kernel is executed N times in parallel by N different threads on a device during execution (where N is any positive integer).

[0318] In at least one embodiment, each device function 3314 is executable on a device and is invocable only from such device. In at least one embodiment, each host function 3316 is executable on a host and is invocable only from such host. In at least one embodiment, each host / device function 3316 defines both a host version of a function that is executable on a host and is invocable only from such host, and a device version of a function that is executable on a device and is invocable only from such device.

[0319] In at least one embodiment, CUDA source code 3310 can also include, without limitation, any number of calls to any number of functions defined by a CUDA runtime API 3302. In at least one embodiment, CUDA runtime API 3302 can include, without limitation, any number of functions executing on a host that are used to allocate and de-allocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code 3310 can also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API can be any API designed to be used by CUDA code. In at least one embodiment, CUDA APIs include, without limitation, CUDA runtime API 3302, a CUDA driver API, APIs for any number of CUDA libraries, etc. In at least one embodiment and relative to CUDA runtime API 3302, a CUDA driver API is a lower-level API but can provide more fine-grained control over a device. In at least one embodiment, examples of CUDA libraries include, without limitation, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

[0320] In at least one embodiment, CUDA compiler 3350 compiles input CUDA code (e.g., CUDA source code 3310) to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, CUDA compiler 3350 is NVCC. In at least one embodiment, host executable code 3370(1) is a compiled version of host code included in input source code that is executable on CPU 3390. In at least one embodiment, CPU 3390 can be any processor optimized for sequential instruction processing.

[0321] In at least one embodiment, CUDA device executable code 3384 is a compiled version of device code included in input source code executable on a CUDA-enabled GPU 3394. In at least one embodiment, CUDA device executable code 3384 includes, without limitation, binary code. In at least one embodiment, CUDA device executable code 3384 includes, without limitation, IR code, such as PTX code, which is further compiled into binary code for a particular target device (e.g., CUDA-enabled GPU 3394) at runtime by a device driver. In at least one embodiment, CUDA-enabled GPU 3394 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, CUDA-enabled GPU 3394 is developed by NVIDIA Corporation of Santa Clara, CA.

[0322] In at least one embodiment, CUDA to HIP translation tool 3320 is configured to translate CUDA source code 3310 into functionally similar HIP source code 3330. In at least one embodiment, HIP source code 3330 is a collection of human-readable code in the HIP programming language. In at least one embodiment, HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language that includes, without limitation, functionally similar versions of CUDA mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, the HIP programming language can include a subset of functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, without limitation, mechanisms to define global functions 3312, but such a HIP programming language can lack support for dynamic parallelism, and thus global functions 3312 defined in HIP code are only callable from a host.

[0323] In at least one embodiment, HIP source code 3330 includes, without limitation, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, HIP source code 3330 can also include any number of calls to any number of functions specified in a HIP runtime API 3332. In one embodiment, HIP runtime API 3332 includes, without limitation, functionally similar versions of a subset of functions included in CUDA runtime API 3302. In at least one embodiment, HIP source code 3330 can also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API can be any API designed for use with HIP code and / or ROCm. In at least one embodiment, a HIP API includes, without limitation, HIP runtime API 3332, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0324] In at least one embodiment, CUDA to HIP translation tool 3320 translates each kernel call in CUDA code from CUDA syntax to HIP syntax, and translates any number of other CUDA calls in CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in a CUDA API, and a HIP call is a call to a function specified in a HIP API. In at least one embodiment, CUDA to HIP translation tool 3320 translates any number of calls to functions specified in CUDA runtime API 3302 to any number of calls to functions specified in HIP runtime API 3332.

[0325] In at least one embodiment, CUDA to HIP translation tool 3320 is a tool known as hipify-perl, which performs a text-based translation process. In at least one embodiment, CUDA to HIP translation tool 3320 is a tool known as hipify-clang, which performs a more complex and robust translation process relative to hipify-perl, involving parsing of CUDA code using clang (a compiler frontend), followed by translation of resulting symbols. In at least one embodiment, in addition to modifications performed by CUDA to HIP translation tool 3320, proper translation of CUDA code to HIP code can also require modifications (e.g., manual edits).

[0326] In at least one embodiment, HIP compiler driver 3340 is a front end that determines target device 3346 and then configures a compiler compatible with target device 3346 to compile HIP source code 3330. In at least one embodiment, target device 3346 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3340 can determine target device 3346 in any technically feasible manner.

[0327] In at least one embodiment, if target device 3346 is compatible with CUDA (e.g., a CUDA-enabled GPU 3394), then HIP compiler driver 3340 generates HIP / NVCC compilation commands 3342. In at least one embodiment and in conjunction with Figure 33B In more detail, HIP / NVCC compilation commands 3342 configure CUDA compiler 3350 to compile HIP source code 3330 using, without limitation, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP / NVCC compilation commands 3342, CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384.

[0328] In at least one embodiment, if target device 3346 is not compatible with CUDA, then HIP compiler driver 3340 generates HIP / HCC compilation commands 3344. In at least one embodiment and in conjunction with Figure 33C In more detail, HIP / HCC compilation commands 3344 configure HCC 3360 to compile HIP source code 3330 using a HCC header and a HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation commands 3344, HCC 3360 generates host executable code 3370(2) and HCC device executable code 3382. In at least one embodiment, HCC device executable code 3382 is a compiled version of device code contained in HIP source code 3330 that is executable on GPU 3392. In at least one embodiment, GPU 3392 can be any processor optimized for parallel instruction processing that is not compatible with CUDA and is compatible with HCC. In at least one embodiment, GPU 3392 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, GPU 3392 is a non-CUDA-enabled GPU 3392.

[0329] For illustrative purposes only, in Figure 33ACUDA source code 3310 to execute on CPU 3390 and a different device in at least one embodiment. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3310 to execute on CPU 3390 and a CUDA-enabled GPU 3394 without converting CUDA source code 3310 to HIP source code 3330. In at least one embodiment, an indirect CUDA flow converts CUDA source code 3310 to HIP source code 3330 and then compiles HIP source code 3330 to execute on CPU 3390 and a CUDA-enabled GPU 3394. In at least one embodiment, a CUDA / HCC flow converts CUDA source code 3310 to HIP source code 3330 and then compiles HIP source code 3330 to execute on CPU 3390 and a GPU 3392.

[0330] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and series of bubble annotations Al-A3. In at least one embodiment, and as shown by bubble annotation Al, CUDA compiler 3350 receives CUDA source code 3310 and a CUDA compile command 3348 that configures CUDA compiler 3350 to compile CUDA source code 3310. In at least one embodiment, CUDA source code 3310 used in a direct CUDA flow is written in a CUDA programming language that is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to CUDA compile command 3348, CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384 (denoted with bubble annotation A2). In at least one embodiment and as shown with bubble annotation A3, host executable code 3370(1) and CUDA device executable code 3384 can be executed on CPU 3390 and CUDA-enabled GPU 3394, respectively. In at least one embodiment, CUDA device executable code 3384 includes, without limitation, binary code. In at least one embodiment, CUDA device executable code 3384 includes, without limitation, PTX code and is further compiled into binary code for a particular target device at runtime.

[0331] The indirect CUDA flow that can be implemented in at least one embodiment can be described by the dashed line and series of bubble annotations Bl- B6. In at least one embodiment and as shown by bubble annotation Bl, CUDA to HIP translation tool 3320 receives CUDA source code 3310. In at least one embodiment and as shown by bubble annotation B2, CUDA to HIP translation tool 3320 translates CUDA source code 3310 to HIP source code 3330. In at least one embodiment and as shown by bubble annotation B3, HIP compiler driver 3340 receives HIP source code 3330 and determines whether target device 3346 has CUDA enabled.

[0332] In at least one embodiment and as shown by bubble annotation B4, HIP compiler driver 3340 generates HIP / NVCC compilation commands 3342 and sends both HIP / NVCC compilation commands 3342 and HIP source code 3330 to CUDA compiler 3350. In at least one embodiment and as described in greater detail below in connection with FIG. 3B, CUDA compiler 3350 is configured to compile HIP source code 3330 using, without limitation, a HIP to CUDA translation header and a CUDA runtime library in response to HIP / NVCC compilation commands 3342. Figure 33B In at least one embodiment and as shown by bubble annotation B4, HIP compiler driver 3340 generates HIP / NVCC compilation commands 3342 and sends both HIP / NVCC compilation commands 3342 and HIP source code 3330 to CUDA compiler 3350. In at least one embodiment and as described in greater detail below in connection with FIG. 3B, CUDA compiler 3350 is configured to compile HIP source code 3330 using, without limitation, a HIP to CUDA translation header and a CUDA runtime library in response to HIP / NVCC compilation commands 3342.

[0333] The CUDA / HCC flow that can be implemented in at least one embodiment can be described by the solid line and series of bubble annotations Cl- C6. In at least one embodiment and as shown by bubble annotation Cl, CUDA to HIP translation tool 3320 receives CUDA source code 3310. In at least one embodiment and as shown by bubble annotation C2, CUDA to HIP translation tool 3320 translates CUDA source code 3310 to HIP source code 3330. In at least one embodiment and as shown by bubble annotation C3, HIP compiler driver 3340 receives HIP source code 3330 and determines that target device 3346 does not have CUDA enabled.

[0334] In at least one embodiment, the HIP compiler driver 3340 generates HIP / HCC compilation commands 3344 and sends both the HIP / HCC compilation commands 3344 and the HIP source code 3330 to the HCC 3360 (indicated by bubble comment C4). In at least one embodiment and as in combination Figure 33C In more detail, HIP / HCC compilation command 3344 configures HCC 3360 to compile HIP source code 3330 using, but not limited to, the HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation command 3344, HCC 3360 generates host executable code 3370(2) and HCC device executable code 3382 (indicated by bubble comment C5). In at least one embodiment and as shown by bubble comment C6, host executable code 3370(2) and HCC device executable code 3382 can be executed on CPU 3390 and GPU 3392, respectively.

[0335] In at least one embodiment, after converting CUDA source code 3310 to HIP source code 3330, the HIP compiler driver 3340 can then be used to generate executable code for a CUDA-enabled GPU 3394 or GPU 3392 without re-executing CUDA to the HIP conversion tool 3320. In at least one embodiment, the CUDA to HIP conversion tool 3320 converts CUDA source code 3310 to HIP source code 3330 and then stores it in memory. In at least one embodiment, the HIP compiler driver 3340 then configures HCC 3360 to generate host executable code 3370(2) and HCC device executable code 3382 based on the HIP source code 3330. In at least one embodiment, the HIP compiler driver 3340 then configures CUDA compiler 3350 to generate host executable code 3370(1) and CUDA device executable code 3384 based on the stored HIP source code 3330.

[0336] Figure 33B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU 3390 and a CUDA-enabled GPU 3394. Figure 33A The system 3304 includes, but is not limited to, CUDA source code 3310, CUDA to HIP conversion tool 3320, HIP source code 3330, HIP compiler driver 3340, CUDA compiler 3350, host executable code 3370(1), CUDA device executable code 3384, CPU 3390, and CUDA-enabled GPU 3394.

[0337] In at least one embodiment and as previously described herein in connection with Figure 33A CUDA source code 3310 includes, without limitation, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, CUDA source code 3310 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.

[0338] In at least one embodiment, CUDA to HIP translation tool 3320 translates CUDA source code 3310 into HIP source code 3330. In at least one embodiment, CUDA to HIP translation tool 3320 translates each kernel call in CUDA source code 3310 from CUDA syntax to HIP syntax, and translates any number of other CUDA calls in CUDA source code 3310 to any number of other functionally similar HIP calls.

[0339] In at least one embodiment, HIP compiler driver 3340 determines that target device 3346 is CUDA-enabled, and generates a HIP / NVCC compilation command 3342. In at least one embodiment, HIP compiler driver 3340 then configures CUDA compiler 3350 via HIP / NVCC compilation command 3342 to compile HIP source code 3330. In at least one embodiment, as part of configuring CUDA compiler 3350, HIP compiler driver 3340 provides access to a HIP to CUDA translation header 3352. In at least one embodiment, HIP to CUDA translation header 3352 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler 3350 uses HIP to CUDA translation header 3352 in conjunction with a CUDA runtime library 3354 corresponding to CUDA runtime API 3302 to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, host executable code 3370(1) and CUDA device executable code 3384 can then be executed on CPU 3390 and CUDA-enabled GPU 3394, respectively. In at least one embodiment, CUDA device executable code 3384 includes, without limitation, binary code. In at least one embodiment, CUDA device executable code 3384 includes, without limitation, PTX code and is further compiled into binary code for a particular target device at runtime.

[0340] Figure 33C FIG. 33 shows a system 3306 configured to compile and execute CUDA source code 3310 using CPU 3390 and a GPU 3392 that is not CUDA-enabled, according to at least one embodiment. Figure 33A In at least one embodiment, system 3306 includes, without limitation, CUDA source code 3310, CUDA to HIP translation tool 3320, HIP source code 3330, HIP compiler driver 3340, HCC 3360, host executable code 3370(2), HCC device executable code 3382, CPU 3390, and GPU 3392.

[0341] In at least one embodiment, and as previously discussed herein in conjunction with Figure 33AAs described, the CUDA source code 3310 includes, without limitation, any number (including zero) of global functions 3312, any number (including zero) of device functions 3314, any number (including zero) of host functions 3316, and any number (including zero) of host / device functions 3318. In at least one embodiment, the CUDA source code 3310 also includes, without limitation, any number of calls to any number of functions specified in any number of CUDA APIs.

[0342] In at least one embodiment, the CUDA to HIP translation tool 3320 translates the CUDA source code 3310 into HIP source code 3330. In at least one embodiment, the CUDA to HIP translation tool 3320 translates each kernel call in the CUDA source code 3310 from CUDA syntax to HIP syntax, and translates any number of other CUDA calls in the source code 3310 to any number of other functionally similar HIP calls.

[0343] In at least one embodiment, the HIP compiler driver 3340 then determines that the target device 3346 is not CUDA-enabled, and generates a HIP / HCC compilation command 3344. In at least one embodiment, the HIP compiler driver 3340 then configures the HCC 3360 to execute the HIP / HCC compilation command 3344, thereby compiling the HIP source code 3330. In at least one embodiment, the HIP / HCC compilation command 3344 configures the HCC 3360 to use, without limitation, the HIP / HCC runtime library 3358 and the HCC header 3356 to generate host executable code 3370(2) and HCC device executable code 3382. In at least one embodiment, the HIP / HCC runtime library 3358 corresponds to the HIP runtime API 3332. In at least one embodiment, the HCC header 3356 includes, without limitation, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, the host executable code 3370(2) and the HCC device executable code 3382 can be executed on the CPU 3390 and the GPU 3392, respectively.

[0344] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in relation to the foregoing figures. Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is utilized to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs Figures 1-5at least one embodiment, one or more systems and / or processes are implemented using one or more systems depicted in the preceding figures, such as a system Figures 1-5 A described system and / or process, such as a processor including one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

[0345] Figure 34 An exemplary kernel converted by the CUDA to HIP translation tool 3320 of Figure 33C In at least one embodiment, CUDA source code 3310 divides the overall problem that a given kernel is designed to solve into relatively coarse sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each sub-problem is divided into relatively fine pieces that can be solved in parallel by threads in a thread block in collaboration. In at least one embodiment, threads within a thread block can collaborate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0346] In at least one embodiment, CUDA source code 3310 organizes thread blocks associated with a given kernel into a one-, two-, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads, and the grid includes, without limitation, any number of thread blocks.

[0347] In at least one embodiment, a kernel is a function in device code defined using a “__global__” declaration specifier. In at least one embodiment, CUDA kernel launch syntax 3410 is used to specify the size of a grid of kernels to execute for a given kernel invocation, as well as an associated stream. In at least one embodiment, CUDA kernel launch syntax 3410 is specified as “KernelName<<<GridSize, BlockSize, SharedMemorySize, Stream>>>(KernelArguments);”. In at least one embodiment, execution configuration syntax is the “<<<...>>>” construct, which is inserted between a kernel name (“KernelName”) and a parenthetical list of kernel arguments (“KernelArguments”). In at least one embodiment, CUDA kernel launch syntax 3410 includes, without limitation, CUDA launch function syntax instead of execution configuration syntax.

[0348] In at least one embodiment, “GridSize” is of type dim3 and specifies the size and dimensions of a grid. In at least one embodiment, type dim3 is a CUDA defined structure that includes, without limitation, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, it defaults to 1. In at least one embodiment, if y is not specified, it defaults to 1. In at least one embodiment, a number of thread blocks in a grid is equal to a product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, “BlockSize” is of type dim3 and specifies the size and dimensions of each thread block. In at least one embodiment, a number of threads per thread block is equal to a product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing a kernel is given a unique thread ID that is accessible within a kernel via a built-in variable, such as “threadIdx”.

[0349] In at least one embodiment, with respect to CUDA kernel launch syntax 3410, “SharedMemorySize” is an optional parameter that specifies a number of bytes of dynamic allocation of shared memory per thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 3410, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 3410, “stream” is an optional parameter that specifies an associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands (which can be issued by different host threads) that are executed in-order. In at least one embodiment, different streams can execute commands out-of-order or simultaneously with respect to each other.

[0350] In at least one embodiment, CUDA source code 3310 includes, without limitation, a kernel definition and a host function for an exemplary kernel “MatAdd”. In at least one embodiment, a host function is host code that executes on a host and includes, without limitation, a kernel call that causes kernel MatAdd to execute on a device. In at least one embodiment, as shown, kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores a result in matrix C. In at least one embodiment, a host function defines a threadsPerBlock variable to be 16x 16 and a numBlocks variable to be N / 16 x N / 16. In at least one embodiment, host function then specifies a kernel call “MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);”. In at least one embodiment, and in accordance with CUDA kernel launch syntax 3410, kernel MatAdd is executed using a thread block grid of size N / 16 x N / 16, where each thread block is of size 16 x 16. In at least one embodiment, each thread block includes 256 threads, a grid with enough blocks is created so that each matrix element has one thread, and each thread in that grid executes kernel MatAdd to perform one pairwise addition.

[0351] In at least one embodiment, while converting CUDA source code 3310 to HIP source code 3330, CUDA to HIP translation tool 3320 converts each kernel call in CUDA source code 3310 from CUDA kernel launch syntax 3410 to HIP kernel launch syntax 3420 and converts any number of other CUDA calls in source code 3310 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3420 is specified as “hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 3420 as in CUDA kernel launch syntax 3410 (described previously herein). In at least one embodiment, parameters SharedMemorySize and Stream are required in HIP kernel launch syntax 3420, but are optional in CUDA kernel launch syntax 3410.

[0352] In at least one embodiment, in addition to the kernel call to cause kernel MatAdd to execute on a device, Figure 34 A portion of HIP source code 3330 depicted in Figure 34 CUDA source code 3510 depicted in FIG. 35 is the same as a portion of In at least one embodiment, in addition to the kernel call to cause kernel MatAdd to execute on a device,

[0353] In at least one embodiment, one or more systems depicted in relation to the foregoing figures are utilized to implement techniques, functions, and / or processes described in conjunction with Figures 1-5 In at least one embodiment, at least one component in the foregoing figures is utilized to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error. In at least one embodiment, at least one component in the foregoing figures performs at least one aspect of a component in Figures 1-5 In at least one embodiment, one or more systems and / or processes are implemented utilizing one or more systems depicted in the foregoing figures, such as, for example, systems and / or processes described in conjunction with Figures 1-5 In at least one embodiment, a processor comprises one or more circuits to cause execution of one or more threads corresponding to one or more respective kernels to selectively stop based at least in part on at least one thread of the one or more threads encountering an error.

[0354] Figure 35 FIGS. 36-39 illustrate in further detail systems in accordance with at least one embodiment, Figure 33Ca CUDA-unenabled GPU 3392. In at least one embodiment, GPU 3392 is developed by AMD Corporation, Santa Clara, CA. In at least one embodiment, GPU 3392 can be configured to perform compute operations in a highly parallel manner. In at least one embodiment, GPU 3392 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering images to a display. In at least one embodiment, GPU 3392 is configured to perform operations that are not graphics-related. In at least one embodiment, GPU 3392 is configured to perform both graphics-related operations and operations that are not graphics-related. In at least one embodiment, GPU 3392 can be configured to execute device code included in HIP source code 3330.

[0355] In at least one embodiment, GPU 3392 includes, without limitation, any number of programmable processing units 3520, a command processor 3510, an L2 cache 3522, a memory controller 3570, a DMA engine 3580(1), a system memory controller 3582, a DMA engine 3580(2), and a GPU controller 3584. In at least one embodiment, each programmable processing unit 3520 includes, without limitation, a workload manager 3530 and any number of compute units 3540. In at least one embodiment, command processor 3510 reads commands from one or more command queues (not shown) and distributes commands to workload managers 3530. In at least one embodiment, for each programmable processing unit 3520, a relevant workload manager 3530 distributes work to compute units 3540 included in programmable processing unit 3520. In at least one embodiment, each compute unit 3540 can execute any number of thread blocks, but each thread block executes on a single compute unit 3540. In at least one embodiment, a workgroup is a thread block.

[0356] In at least one embodiment, each compute unit 3540 includes, without limitation, any number of SIMD units 3550 and a shared memory 3560. In at least one embodiment, each SIMD unit 3550 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each SIMD unit 3550 includes, without limitation, a vector ALU 3552 and a vector register file 3554. In at least one embodiment, each SIMD unit 3550 executes a different thread bundle. In at least one embodiment, a thread bundle is a group of threads (e.g., 16 threads), where each thread in a thread bundle belongs to a single thread block and is configured to process a different set of data based on a single instruction set. In at least one embodiment, one or more threads in a thread bundle can be disabled using predication. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread bundle. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3560. In at least one embodiment, compute units 3540 include one or more distributed shared memories (or distributed shared memory) that implement direct stream processor (SM) to stream processor (SM) for operations related to loading, storing, and performing atomic operations on blocks of memory shared across multiple SMs. Compute units 3540 include one or more cluster distributed shared memories (DSMEMs) that are blocks of shared memory that are able to directly access each other within a cluster.

[0357] In at least one embodiment, programmable processing units 3520 are referred to as “tessellation engines.” In at least one embodiment, each programmable processing unit 3520 includes, without limitation, any number of geometry processors, any number of rasterizers, any number of render back-ends, a work distribution manager 3530, and any number of compute units 3540, in addition to compute units 3540.

[0358] In at least one embodiment, compute units 3540 share an L2 cache 3522. In at least one embodiment, the L2 cache 3522 is partitioned. In at least one embodiment, all compute units 3540 in the GPU 3392 have access to the GPU memory 3590. In at least one embodiment, a memory controller 3570 and a system memory controller 3582 facilitate data transfer between the GPU 3392 and the host, and a DMA engine 3580(1) enables asynchronous memory transfers between the GPU 3392 and the host. In at least one embodiment, a memory controller 3570 and a GPU controller 3584 facilitate data transfers between the GPU 3392 and other GPUs 3392, and a DMA engine 3580(2) enables asynchronous memory transfers between the GPU 3392 and other GPUs 3392.

[0359] In at least one embodiment, GPU 3392 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components, either internally or externally to GPU 3392. In at least one embodiment, GPU 3392 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3392 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3392 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3570 and system memory controller 3582) and memory devices dedicated to a component or shared among multiple components (e.g., shared memory 3560). In at least one embodiment, GPU 3392 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3522), each cache memory being private or shared among any number of components (e.g., SIMD unit 3550, compute unit 3540, and programmable processing unit 3520).

[0360] In at least one embodiment, the combination is achieved using one or more systems depicted in relation to the foregoing figures. Figures 1-5 The described techniques, functions, and / or processes. In at least one embodiment, at least one component of the foregoing figures is used to cause the execution of one or more threads corresponding to one or more corresponding kernels to selectively stop at least in part based on at least one of the one or more threads encountering an error. In at least one embodiment, at least one component of the foregoing figures performs...Figures 1-5 at least one aspect of the middle component. In at least one embodiment, one or more systems and / or processes are implemented with one or more systems depicted in preceding figures, for example, in conjunction with Figures 1-5 A system and / or process are described, such as a processor including one or more circuits to cause execution of one or more threads corresponding to one or more respective cores to be selectively stopped based at least in part on at least one of the one or more threads encountering an error.

[0361] Figure 36 threads of an exemplary CUDA grid 3620 are mapped to different compute units 3540 of Figure 35 In at least one embodiment, and for illustration purposes only, grid 3620 has a GridSize of BX by BY by 1 and a BlockSize of TX by TY by 1. Thus, in at least one embodiment, grid 3620 includes, without limitation, (BX*BY) thread blocks 3630, each including, without limitation, (TX*TY) threads 3640. Threads 3640 are depicted as curved arrows. Figure 36

[0362] In at least one embodiment, grid 3620 is mapped to programmable processing unit 3520(1), which includes, without limitation, compute units 3540(1)-3540(C). In at least one embodiment and as shown, (BJ*BY) thread blocks 3630 are mapped to compute unit 3540(1), and the remaining thread blocks 3630 are mapped to compute unit 3540(2). In at least one embodiment, each thread block 363...

Claims

1. A processor, comprising: One or more circuits, said one or more circuits being configured to cause the execution of one or more threads corresponding to one or more respective kernels to be selectively stopped at least in part based on at least one of said one or more threads encountering an error.

2. The processor according to claim 1, wherein, The one or more threads that encounter the error will be exclusively assigned to the one or more corresponding kernels, at least in part, based on the principle of exclusive access to the one or more threads.

3. The processor according to claim 1, wherein, The one or more threads corresponding to the one or more corresponding kernels will be selectively stopped at least in part based on the identification of the one or more corresponding kernels, wherein the identification of the one or more corresponding kernels is at least in part based on information associated with the one or more threads.

4. The processor according to claim 3, wherein, The information associated with the one or more threads includes one or more thread names indicating the one or more threads.

5. The processor according to claim 1, wherein, The one or more threads execute the one or more kernels exclusively.

6. The processor according to claim 1, wherein, The one or more threads were executing the one or more kernels before at least one of the one or more threads encountered the error.

7. The processor according to claim 1, wherein, The one or more circuits are used to generate an indication of the error.

8. The processor according to claim 1, wherein, The execution of the one or more threads may be selectively stopped by terminating, pausing, or rescheduling the execution of the one or more threads.

9. A system comprising: One or more processors, said one or more processors being configured to cause the execution of one or more threads corresponding to one or more respective cores to be selectively stopped at least in part based on at least one of said one or more threads encountering an error.

10. The system according to claim 9, wherein, The one or more threads that encounter the error will be exclusively assigned to the one or more corresponding kernels, at least in part, based on the principle of exclusive access to the one or more threads.

11. The system according to claim 9, wherein, The one or more threads corresponding to the one or more corresponding kernels will be selectively stopped at least in part based on the identification of the one or more corresponding kernels, wherein the identification of the one or more corresponding kernels is at least in part based on information associated with the one or more threads.

12. The system according to claim 9, wherein, The one or more threads execute the one or more kernels exclusively.

13. The system according to claim 9, wherein, The one or more threads were executing the one or more kernels before at least one of the one or more threads encountered the error.

14. The system according to claim 9, wherein, The execution of the one or more threads may be selectively stopped by terminating, pausing, or rescheduling the execution of the one or more threads.

15. A method comprising: This causes the execution of one or more threads corresponding to one or more corresponding kernels to be selectively stopped, at least in part, based on at least one of the one or more threads encountering an error.

16. The method according to claim 15, wherein, The one or more threads that encounter the error will be exclusively assigned to the one or more corresponding kernels, at least in part, based on the principle of exclusive access to the one or more threads.

17. The method according to claim 15, wherein, The one or more threads corresponding to the one or more corresponding kernels will be selectively stopped at least in part based on the identification of the one or more corresponding kernels, wherein the identification of the one or more corresponding kernels is at least in part based on information associated with the one or more threads.

18. The method according to claim 15, wherein, The one or more threads execute the one or more kernels exclusively.

19. The method according to claim 15, wherein, The one or more threads were executing the one or more kernels before at least one of the one or more threads encountered the error.

20. The method of claim 15, wherein, The execution of the one or more threads may be selectively stopped by terminating, pausing, or rescheduling the execution of the one or more threads.

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