Logic redundancy detection method, electronic device and storage medium

Abstract

The application belongs to the technical field of electronic design automation, and proposes a logic redundancy detection method, an electronic device and a storage medium, the method comprising: acquiring a circuit design to be detected, setting a detection starting point and a detection ending point of the circuit design, and creating a mark and a polarity corresponding to the detection starting point; starting from the detection starting point, traversing the circuit design along the signal propagation direction, and propagating the mark and the polarity in the circuit design in the process of traversal, wherein, for a current instance of the circuit design, in the case that an input pin of the current instance is not the detection ending point, a variable corresponding to the input pin in a function expression of the current instance is replaced with a mark corresponding to the input pin or a constant value; the function expression after replacement is logically simplified, and in the case that the simplified result is a constant value, it is detected that there is logic redundancy at the current instance. The application can quickly and efficiently detect the logic redundancy part in the circuit design and clearly determine the source of the logic redundancy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to a logic redundancy detection method, an electronic device and a storage medium. BACKGROUND

[0002] With the progress of manufacturing technology and design technology, the design method of electronic systems has undergone profound changes, from computer aided design (CAD), computer aided engineering (CAE) to electronic design automation (EDA), the degree of automation of design is higher and higher, and the complexity of design is stronger and stronger.

[0003] Integrated circuit (IC) EDA refers to using electronic design automation software to complete the functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.) of super large scale integrated circuit chips and other processes. At present, EDA technology has become a powerful tool for modern electronic design. Without the support of EDA technology, it is impossible to complete the design and manufacturing of super large scale integrated circuits. IC designers need to use EDA tools to develop complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviation, improve the success rate of chip implementation and save chip implementation costs.

[0004] Design for testability (DFT) static detection EDA tool is mainly to detect whether the user's design has a bad influence on test efficiency and accuracy, and to provide improvement suggestions to reduce the time overhead of the user in simulation verification, and to find design problems more quickly. Among the many detection points, the logic redundancy (Logic Redundant) in the circuit is an important detection point, because meaningless or excessive logic redundancy will lead to an increase in the complexity of test vectors, an increase in test time, a decrease in test coverage, and even more untestable parts, resulting in a decrease in chip reliability. In addition, the detection of logic redundancy is also involved in other static detection EDA tools such as clock domain crossing (CDC).

[0005] However, with the continuous improvement of chip integration, the continuous improvement of circuit complexity and the increasingly common application of sequential circuits, the static detection EDA tool of the related technology needs to occupy a large amount of detection time and resources when detecting logic redundancy, so a more efficient and fast way is needed to find the logic redundant part in the circuit. SUMMARY

[0006] The present application provides a logic redundancy detection method, an electronic device and a storage medium to at least solve the problem that a large amount of detection time and resources are required in the related art. The technical solutions of the present application are as follows.

[0007] According to a first aspect of the present application, a logic redundancy detection method is provided, comprising: obtaining a circuit design to be detected, setting a detection starting point and a detection ending point of the circuit design, and creating a mark and a polarity corresponding to the detection starting point, wherein the mark is used to represent source information of a signal, and the polarity is used to represent flip information of the signal; starting from the detection starting point, traversing the circuit design along a signal propagation direction, and propagating the mark and the polarity in the circuit design in the process of traversal, wherein, for a current instance of the circuit design, if an input pin of the current instance is not the detection ending point, a variable corresponding to the input pin in a function expression of the current instance is replaced by a mark corresponding to the input pin or a constant value, and if the polarity corresponding to any input pin indicates that the signal has been flipped, the mark corresponding to the any input pin is replaced after a logical NOT operator is added; the function expression after replacement is logically simplified, and if the simplified result is a constant value, it is detected that there is logic redundancy at the current instance.

[0008] According to a second aspect of the present application, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions, wherein the processor-executable instructions, when executed by the processor, cause the processor to perform the logic redundancy detection method according to the present application.

[0009] According to a third aspect of the present application, a computer-readable storage medium is provided, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device can perform the logic redundancy detection method according to the present application.

[0010] The technical solutions provided by the present application at least bring the following beneficial effects:

[0011] The present application can quickly propagate the mark and the polarity to the instance concerned in the process of traversing the circuit design, and can quickly detect the logic redundancy part in the circuit design according to the simplified result by replacing the mark in the function expression of the instance and logically simplifying, and can also efficiently obtain the source information of the related logic redundancy according to the mark propagated to the input pin of the instance.

[0012] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application and, do not represent any improper limitation of the scope of the present application.

[0014] Figure 1 is a flow chart showing a logic redundancy detection method according to an exemplary embodiment of the present application;

[0015] Figure 2 is a circuit schematic diagram showing an exemplary embodiment of the present application;

[0016] Figure 3 is a block diagram showing an electronic device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0017] In order for those skilled in the art to better understand the technical solutions of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings.

[0018] It should be noted that the steps in the specification and drawings of the present application are not limited to the specific order or sequence described. It should be understood that the steps used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0019] As described previously, in the static detection EDA tool (such as spyglass of Synopsys) of the related art, the detection project explicitly indicates that a large amount of detection time and resources are required for the detection of logic redundancy, which has gradually failed to meet the increasingly agile development needs of today.

[0020] In view of the above problems, the exemplary embodiments of the present application propose a logic redundancy detection method, an electronic device and a computer readable storage medium, which can solve or at least alleviate the above problems.

[0021] In a first aspect of the exemplary embodiments of the present application, a logic redundancy detection method is provided, which will be described below with reference to Figure 1 and Figure 2 in detail.

[0022] The logic redundancy according to the exemplary embodiments of the present application can refer to a combinational logic path composed of combinational logic gates, whose output does not change with the input, and is always a constant value, i.e. logic value 1 or logic value 0. For example, if the same signal passes through a buffer and an inverter to reach a combinational logic AND gate as its input, the output of the AND gate is always logic value 0, and then the path composed of the above buffer, inverter and AND gate constitutes the logic redundancy in the circuit. It should be understood that the above example is not a restrictive illustration of the logic redundancy, and any combinational logic path whose output does not change with the input can be the logic redundancy according to the exemplary embodiments of the present application.

[0023] According to the exemplary embodiments of the present application, the logic redundancy detection method is applicable to electronic design automation (EDA) software, and a user terminal can load the EDA software, so that the user terminal can obtain a circuit design to be detected, set a detection starting point and a detection ending point of the circuit design, and create a symbol and a polarity corresponding to the detection starting point; starting from the detection starting point, the circuit design is traversed in a signal propagation direction, and the symbol and the polarity are propagated in the circuit design in the process of traversal. Here, for a current instance of the circuit design, if an input pin of the current instance is not the detection ending point, a variable corresponding to the input pin in a function expression of the current instance is replaced by a symbol corresponding to the input pin or a constant value. Further, if the polarity of any input pin indicates that the signal has been flipped, the symbol corresponding to the input pin is replaced after adding a logical NOT operator. The replaced function expression is logically simplified, and if the simplified result is a constant value, it is detected that there is logic redundancy at the current instance.

[0024] This method can quickly propagate the symbol and the polarity to each instance of interest in the circuit in the process of traversing the circuit design, and can quickly detect the logic redundancy in the circuit design according to the simplified result by replacing the symbol and logically simplifying the function expression of the instance. Meanwhile, according to the symbol propagated to the input pin of the instance, the source information of the related logic redundancy can also be efficiently obtained.

[0025] The user terminal can be a tablet computer, a notebook computer, a digital assistant, a wearable device, etc., however, the implementation scenario of the logic redundancy detection method described above is only an example scenario, and the logic redundancy detection method according to the example embodiment of the present application can also be applied to other application scenarios, for example, a user can also request to access relevant data from a server through a network by using a user terminal (for example, a mobile phone, a desktop computer, a tablet computer, etc.), and the server can access the data by executing the logic redundancy detection method according to the example embodiment of the present application and return the result to the user terminal, here, the server can be a standalone server, a server cluster, a cloud computing platform, a virtualization center, etc.

[0026] The specific steps of a logic redundancy detection method according to an example embodiment of the present application will be described below with reference to the accompanying drawings. Figure 1 The specific steps of a logic redundancy detection method according to an example embodiment of the present application will be described below with reference to the accompanying drawings. Figure 1 The logic redundancy detection method can include the following steps:

[0027] In step S110, the circuit design to be detected can be acquired, the detection starting point and the detection ending point of the circuit design are set, and the mark and the polarity corresponding to the detection starting point are created.

[0028] According to an example embodiment of the present application, a designer usually uses HDL (Hardware Description Language) to complete integrated circuit design, which describes the structure and behavior of digital system hardware in text form, can represent logic circuit diagrams, logic expressions, and logic functions completed by digital logic systems, etc., so as to model various abstract design levels such as algorithm level, register transfer level, gate level, switch level, etc.

[0029] Here, the detection start point can include a primary input port of the circuit design, which is used to receive a main input signal in the circuit, and is generally an interface of a module or a circuit unit, representing an input end of the entire circuit, which can be a signal from other circuit modules or a control signal from an external system. Further, due to different design stages, there can be some units in the circuit design that are not clearly defined by the designer, and the EDA tool will identify these units as black boxes when reading the circuit design. The function of the identified black box is unknown, so the detection start point can also include the output pin of the black box. Further, considering that the detection of logic redundancy is mainly for combinational logic paths, the detection start point can also include the output pin of the sequential logic unit, such as but not limited to the output pin of the flip-flop. In addition to the primary input, black box and sequential logic, the detection start point can also include the input / output end of other specified instances, etc., to detect the specified area of the circuit according to actual needs, which is not limited by the present application.

[0030] Correspondingly, the detection end point can include a primary output port of the circuit design, which is used to transmit a main output signal in the circuit. These output signals are the results or reactions directly generated from the function of the circuit after the completion of the circuit design, and are usually related to the logic operation or processing of the input signal. In addition to the primary output, the detection end point can also include the input pin of the black box or the sequential logic, or the input / output end of other specified instances, etc., to detect the specified area of the circuit according to actual needs, which is not limited by the present application.

[0031] According to the exemplary embodiments of the present application, the mark can be used to represent the source information of the signal, and the polarity can be used to represent the flip information of the signal. Further, the mark created at the detection start point can indicate that the source of the signal is the detection start point, and the created polarity can indicate that the signal has not been flipped. For example, when creating a mark and polarity corresponding to a certain primary input port, the name of the port can be used as its mark, and the symbol "+" can be used to represent its polarity to indicate that the signal has not been flipped. Conversely, the symbol "-" can be used to indicate that the signal has been flipped. In addition, other ways can be used to express the mark and polarity to meet the actual needs of those skilled in the art, which is not limited by the present application.

[0032] According to the exemplary embodiments of the present application, in order to facilitate subsequent search, the mark and the polarity can be recorded into the attribute of the corresponding pin or port. Alternatively, a mapping table can be created in advance, and then the mark and the polarity corresponding to the pin or port are recorded in the mapping table in the form of a key-value pair, the key is used to represent the mark, and the value is used to represent the polarity, so as to facilitate unified management of the marks and polarities corresponding to all pins or ports, and optimize storage. In addition, the person skilled in the art can record the mark and the polarity according to actual needs, and the present application does not limit this.

[0033] Next, in step S120, the circuit design can be traversed from the detection starting point along the signal propagation direction, and the mark and the polarity are propagated in the circuit design in the process of traversal, so as to detect the logic redundancy in the circuit design according to the propagation result of the mark and the polarity.

[0034] According to the exemplary embodiments of the present application, the circuit design can be traversed by DFS (Depth-First Search), which is a method for traversing or searching a tree or a graph, which traverses as deep as possible along the depth of the tree or the graph, and then backtracks to the previous node, finds the unexplored node and continues to search. However, in the traversal mode of DFS, nearly half of the paths will appear repeated traversal more than once, which will increase the calculation time and affect the detection efficiency.

[0035] In another implementation, the circuit design can be traversed by BFS (Breadth-First Search), which is also a method for traversing or searching a tree or a graph, which starts from a node of the tree or the graph, and then explores and traverses all adjacent nodes of the node, and then explores the adjacent nodes of these adjacent nodes, until all nodes are traversed. Compared with DFS, the advantage of BFS traversal is that all paths only need to be traversed once, so that the number of processed paths is significantly reduced, and the traversal speed can be improved.

[0036] According to an example embodiment of the present application, if the traversal mode of BFS is used, after obtaining the circuit design to be detected, the number of times to be visited of each instance of the circuit design can also be initialized. Here, the number of times to be visited can refer to the expected number of times to traverse to the input pin of the instance through the net, and during the traversal, the clock pin, the power ground pin, and / or the constant pin, etc. can usually be excluded, so that the initialized number of times to be visited can be determined based on the number of target input pins of each instance, which are connected to other pins or ports through the net and used to receive data signals.

[0037] For example, the number of times to be visited of a flip-flop can be initialized to 1, and the number of times to be visited of a combinational logic AND gate can be initialized to 2. For a black box, since the directions of its pins are not clearly defined in the circuit design, it is not possible to distinguish the directions of its pins, so when initializing the number of times to be visited of the black box, it can be determined whether each pin of the black box is an input pin. Here, for the multiple pins of the black box, if the net connected to any pin has a driver, the any pin can be defaulted as an input pin, otherwise, the any pin can be defaulted as an output pin. Further, if there is a floating pin in the multiple pins of the black box, the floating pin can be defaulted as an output pin, because the floating pin is equivalent to having no driver. Further, if one pin of the black box is connected to the input of one instance and the output of another instance through the net, the output of the another instance can be defaulted as the driver, so that the pin of the black box can be defaulted as an input pin.

[0038] In addition, if the instances at the detection start point and the detection end point are initialized differently from other instances, when initializing the number of times to be visited of each instance of the circuit design, in response to any instance in each instance not being the instance at the detection start point or the instance at the detection end point, the number of times to be visited of the any instance can be initialized to the number of target input pins of the any instance; in response to any instance in each instance being the instance at the detection start point or the instance at the detection end point, the number of times to be visited of the any instance can be initialized to 0, so that the number of times to be visited of the instance at the detection start point / end point is no longer calculated, to simplify the calculation and save the calculation resources.

[0039] Further, after obtaining the circuit design to be detected, the detection starting point can also be put into the pre-created element set, so that the detection starting point is stored as an element in the element set. Here, the data structure of the element set for storing the detection starting point can be set as a linear structure, such as a stack or a queue, i.e. the detection starting points need to be processed in a certain order, but this will cause the processing order between branch paths to be certain as well, so it is difficult to support multi-threaded processing. In another possible implementation, the data structure of the element set can be set as a non-linear structure, i.e. the data in the element set can be taken out in any order or randomly without affecting the detection result, to cooperate with multi-threaded use.

[0040] On this basis, when traversing the circuit design in the signal propagation direction from the detection starting point, at least one detection starting point can be taken out from the element set, a second input pin connected to the at least one detection starting point through the net is found, and the number of times to be visited of the instance where the second input pin is located is updated, and then at least one element is taken out from the element set again and the input pin is continuously searched until the element set is empty. Here, the number of elements taken out from the element set each time can be determined according to the allocation of computing resources, for example, if the computing resources are limited to single-threaded, one element is taken out from the element set each time for processing, if the computing resources provide multi-threaded capability, multiple elements can be taken out from the element set each time for parallel processing, but the present application does not limit this.

[0041] Further, the second input pin can include n input pins of the current instance, so that when updating the number of times to be visited of the instance where the second input pin is located, for the current instance, the number of times to be visited of the current instance can be reduced by n; in response to the number of times to be visited of the current instance being reduced to 0, the output pin of the current instance is put into the element set; in response to the number of times to be visited of the current instance not being reduced to 0, the element set is maintained unchanged. It should be understood that the value of n can be determined by the actual connection of the current instance and the net, and the present application does not limit this. As can be seen, in the traversal process, the element set can be constantly updated, and the number of elements in the element set will dynamically change, possibly decreasing or increasing, until the traversal process finally converges, and the element set remains empty.

[0042] According to the exemplary embodiments of the present application, the detection of logic redundancy in the circuit is performed mainly in a breadth-first search manner, which not only supports single-threaded computing, but also supports the synchronous operation of multi-threaded, compared with the depth-first search manner without any additional assistance, which not only improves the speed and efficiency, reduces the space occupation, but also has high expansibility.

[0043] It should be understood that, regardless of which traversal manner is adopted, the detection of the logic redundancy is determined according to the propagation result of the specific instance when the symbol and the polarity are propagated to the specific instance, which will be described below with reference to the following Figure 1

[0044] Next, in step S121, for the current instance of the circuit design, if the input pin of the current instance is not the detection end point, the variable corresponding to the input pin in the functional expression of the current instance can be replaced by the symbol or the constant value corresponding to the input pin.

[0045] Here, if the input pin of the current instance is the detection end point, it means that the current path has been traversed and the propagation result of the current instance does not need to be concerned, and thus the traversal can be ended or the symbol and the polarity can be propagated in the next path. Further, in some designs, some inputs of some instances can be directly designed as a constant value (i.e. a logic value 1 or 0) or a constant value propagated from the logic redundancy of a previous path, and thus the input pin does not have a corresponding symbol and polarity, and thus the constant value can be directly used for replacement.

[0046] According to the exemplary embodiments of the present application, the signal is flipped when passing through an instance such as an inverter, and the polarity is changed accordingly, and thus when the polarity corresponding to any input pin indicates that the signal has been flipped, the symbol corresponding to the input pin can be replaced after being added with a logical NOT operator.

[0047] As an example, it is assumed that the current instance is an AND gate including input pins A and B and an output pin Z, and the functional expression of the AND gate is Z=A&B, and if the symbol corresponding to the input pin A is "PI" and the polarity is "+", and the symbol corresponding to the input pin B is also "PI" and the polarity is "-", then for the input pin B, the symbol "PI" can be replaced after being added with a logical NOT operator "!", and thus the replaced functional expression is Z=PI & (!PI).

[0048] Next, in step S122, the replaced functional expression can be logically simplified, and if the simplified result is a constant value, it is detected that there is a logic redundancy at the current instance.

[0049] Still taking the above AND gate as an example, the replaced functional expression Z=PI & (!PI) is logically simplified to obtain Z=0, and the simplified result is a constant value, which indicates that the output of the AND gate does not change with the change of the signal source PI and is always a logic value 0, and thus it is detected that there is a logic redundancy at the AND gate, and the source of the logic redundancy is the place corresponding to the symbol PI.

[0050] ​According to the exemplary embodiments of the present application, in the case that logical redundancy is detected at the current instance, the current instance can be directly marked to indicate the presence of logical redundancy at the current instance, and the detection can continue until the entire circuit is detected, so that the designer can optimize the logical redundancy at the current instance according to the indication of the mark after the detection of the entire circuit, which can quickly complete the detection of the entire circuit and then optimize all logical redundancies, thereby improving the optimization efficiency of the circuit design. In addition, in another possible implementation, in response to the detection of the presence of logical redundancy at the current instance, the detection can be paused and the designer is reminded to optimize the logical redundancy at the current instance in time, and then the detection can continue in the case that the logical redundancy at the current instance is optimized, which can reduce the probability of negative optimization and improve the reliability of the circuit design as a whole.

[0051] In addition, in the case that logical redundancy is detected at the current instance, the constant obtained after simplification can also be recorded to the output pin of the current instance or the wire network connected to the output pin of the current instance, so as to continue to propagate the constant obtained after simplification.

[0052] According to the exemplary embodiments of the present application, in addition to the detection of logical redundancy by logic simplification, there can also be a case that the simplification result is not a constant, in which case the mark and polarity can continue to propagate in the current path. Specifically, after the logic simplification of the replaced functional expression, in the case that the simplification result is not a constant, the mark and polarity corresponding to the output pin of the current instance can be determined; a first input pin connected to the output pin of the current instance through the wire network is found, and the mark and polarity corresponding to the output pin of the current instance are recorded to the first input pin as the mark and polarity corresponding to the first input pin.

[0053] According to the exemplary embodiments of the present application, the mark and polarity corresponding to the output pin of the current instance can be determined according to the number of non-repeated marks in the simplification result. Here, in the case that the simplification result contains only one mark, only one mark and the polarity corresponding to only one mark can be recorded to the output pin of the current instance as the mark and polarity corresponding to the output pin of the current instance; in the case that the simplification result contains multiple marks, the mark and polarity corresponding to the output pin of the current instance can be recreated. Further, the recreated mark can indicate that the source of the signal is the output pin of the current instance, and the recreated polarity can indicate that the signal does not flip, for example, the name of the output pin of the current instance can be used as its mark, and the symbol "+" can be used to represent its polarity to indicate that the signal does not flip. It should be understood that the above-mentioned only one mark or multiple marks refer to the number of non-repeated marks, that is, in the case that the simplification result contains multiple identical marks, the number of identical marks is only considered as one.

[0054] According to the exemplary embodiments of the present application, the polarity can include a first polarity and a second polarity, the first polarity can indicate that the signal has not been flipped, and the second polarity can indicate that the signal has been flipped. Here, the symbol "+" can be used to represent the first polarity, and the symbol "-" can be used to represent the second polarity, without limitation, so as to intuitively distinguish the flipping condition of the polarity. Further, when only one symbol and the polarity corresponding to the only one symbol are recorded to the output pin of the current instance, in response to the simplification result not containing the logical NOT operator, only one symbol and the first polarity can be recorded to the output pin of the current instance; in response to the simplification result also containing the logical NOT operator, only one symbol and the second polarity can be recorded to the output pin of the current instance. Through the distinction between the first polarity and the second polarity, the propagation process of the symbol and the polarity can be made more accurate and reliable.

[0055] The following will refer to Figure 2 the description of the processing procedure of the logic redundancy detection in the circuit according to the BFS-based traversal manner of the exemplary embodiments of the present application. Figure 2 is a circuit schematic diagram according to the exemplary embodiments of the present application.

[0056] As Figure 2 shown, the example circuit includes main inputs PI1, PI2, PI3, PI4, PI5, PI6, main outputs PO1, PO2, PO3, PO4, AND gates AND1, AND2, AND3, AND4, AND5, AND6, a multiplexer MUX, in addition, there is a buffer and an inverter in parallel between the AND gate AND1 and the AND gate AND5, there is an inverter between the multiplexer MUX and the AND gate AND6, the input end of the AND gate AND4 has a constant pin, and the input signal of the constant pin is a constant value.

[0057] As an example, the logic redundancy of the example circuit can be detected through the following main steps.

[0058] Step 1 (initialization): initialize the number of times to be accessed of each instance. For example, the number of times to be accessed of the AND gates AND1, AND2, AND3, AND5, AND6 can be initialized to 2, the number of times to be accessed of the AND gate AND4 can be initialized to 1, the number of times to be accessed of the multiplexer MUX can be initialized to 3, and the number of times to be accessed of the buffer and the inverter can be initialized to 1.

[0059] Step 2 (selecting the detection starting point and the detection ending point): set the detection starting point and the detection ending point of the BFS traversal. For example, the detection starting point mainly consists of the main inputs PI1, PI2, PI3, PI4, PI5, PI6, and the detection ending point mainly consists of the main outputs PO1, PO2, PO3, PO4.

[0060] Step 3 (Start BFS traversal): Set all detected start points as pending pins / ports, find all connected input pins through the net connected by all pending pins / ports, and update the pending visit count of the instance where the input pin is located. For example, the pending visit count of AND1 is updated to 1, the pending visit count of AND2, AND3 is updated to 0, and the pending visit count of MUX is updated to 2.

[0061] Step 4 (Data record of input pins): Record data (notation and polarity) to input pins. For example, when accessing the input pin of AND1 from the primary input PI1, record the notation "PI1" and polarity "+" in the corresponding input pin of AND1.

[0062] Step 5 (Data record of output pins): Record data (notation and polarity) to output pins, which is determined by the data of the input pins in the instance after functional expression notation substitution and logical simplification. For example, when accessing AND2 from the primary inputs PI2, PI3, the data of the output pin and2 / out of AND2 depends on the result of functional expression notation substitution and logical simplification of the data of its two input pins. Since the simplification result contains two notations, "PI2" and "PI3", a new notation "and2 / out" and a new polarity "+" are created for the output pin of AND2.

[0063] Step 6 (Repeat steps): Repeat steps 3, 4, 5 until the detection endpoint. When processing the output data of multi-input combinational logic gates, if a constant value is obtained after functional expression notation substitution and logical simplification, it indicates that a logic redundancy point in the circuit has been found, as well as the source of the logic redundancy (i.e., the corresponding place of the related notation). For example, logic redundancies can be detected at both AND5 and AND6.

[0064] Step 7 (Final result): At the end of BFS traversal, the detection of the entire circuit is also completed, and the logic redundancies found during the BFS traversal process are the final result of this detection.

[0065] As can be seen, by using the BFS traversal method to detect logic redundancies in the circuit, all paths can be detected for logic redundancies in one traversal (without repeating paths), and the starting point and endpoint of logic redundancy can be quickly and clearly determined. Compared to the DFS traversal method, which involves repeating paths, the analysis efficiency and speed are significantly improved, and multi-threaded analysis is also supported.

[0066] According to the logic redundancy detection method of the exemplary embodiments of the present application, the mark and polarity can be propagated to the instance of interest in the circuit in a fast manner during the traversal of the circuit design, and the logic redundancy part in the circuit design can be detected in a fast manner according to the simplification result of the functional expression of the instance by the mark replacement and logic simplification of the functional expression of the instance, and meanwhile, the source information of the related logic redundancy occurrence can also be efficiently obtained according to the mark propagated to the input pin of the instance.

[0067] In a second aspect of the exemplary embodiments of the present application, an electronic device is provided, which includes a processor, and a memory for storing processor-executable instructions, wherein the processor-executable instructions, when executed by the processor, cause the processor to perform the logic redundancy detection method according to the exemplary embodiments of the present application.

[0068] Figure 3 is a block diagram illustrating an electronic device according to the exemplary embodiments of the present application. As shown in Figure 3 the electronic device 10 includes a processor 101 and a memory 102 for storing processor-executable instructions. Here, the processor-executable instructions, when executed by the processor, cause the processor to perform the logic redundancy detection method according to the exemplary embodiments of the present application.

[0069] By way of example, the electronic device 10 need not be a single device, but can be a collection of devices or circuits that individually or jointly execute the above instructions (or sets of instructions). The electronic device 10 can also be part of an integrated control system or system manager, or can be configured as a server that interfaces with a local or remote (e.g., via wireless transmission) interface.

[0070] In the electronic device 10, the processor 101 can include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, the processor 101 can also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0071] The processor 101 can execute instructions or codes stored in the memory 102, wherein the memory 102 can also store data. The instructions and data can also be sent and received through a network via a network interface device, wherein the network interface device can employ any known transmission protocol.

[0072] The memory 102 can be integrated with the processor 101, e.g., RAM or flash memory disposed within an integrated circuit microprocessor or the like. Further, the memory 102 can comprise a separate device, such as an external disk drive, memory array, or other storage device usable by any database system. The memory 102 and the processor 101 can be operatively coupled, or can communicate with each other, e.g., through I / O ports, network connections, or the like, such that the processor 101 can read files stored in the memory 102.

[0073] Further, the electronic device 10 can also include a video display, such as a liquid crystal display, and a user interaction interface, such as a keyboard, mouse, touch input device, or the like. All components of the electronic device 10 can be connected to each other via a bus and / or a network.

[0074] In an exemplary embodiment, a computer readable storage medium can also be provided, which, when instructions in the computer readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the logical redundancy detection method as described in the exemplary embodiments above. The computer readable storage medium can be, for example, a memory comprising instructions, and optionally, the computer readable storage medium can be: a read-only memory (ROM), a random access memory (RAM), a random access programmable read-only memory (PROM), an electrically erasable programmable read-only memory (EEPROM), a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a non-volatile memory, a CD-ROM, a CD-R, a CD+R, a CD-RW, a CD+RW, a DVD-ROM, a DVD-R, a DVD+R, a DVD-RW, a DVD+RW, a DVD-RAM, a BD-ROM, a BD-R, a BD-R LTH, a BD-RE, a Blu-ray or optical disc memory, a hard disk drive (HDD), a solid state drive (SSD), a card memory, such as a multimedia card, a secure digital (SD) card, or an extreme digital (XD) card, a magnetic tape, a floppy disk, a magneto-optical data storage device, an optical data storage device, a hard disk, a solid state disk, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and provide the computer program and any associated data, data files, and data structures to a processor or computer such that the processor or computer can execute the computer program. The computer program in the computer readable storage medium described above can be run in an environment deployed in a computer device, such as a client, a host, a proxy device, a server, or the like, and, in one example, the computer program and any associated data, data files, and data structures are distributed over a networked computer system such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0075] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0076] Furthermore, it is to be understood that, unless otherwise expressly specified, embodiments of the application are not limited to particular combinations of steps, nor to steps performed in any particular order. The steps of the embodiments of the application can be combined, omitted or performed in different order than presented herein.

[0077] It is to be understood that the application is not limited to particular details described herein and / or illustrated in the drawings. Rather, the application is intended to cover all modifications and variations of this application that are within the scope of the appended claims. It is intended that the application encompass all such modifications and variations as falling within the scope of the claims.

Claims

1. A logical redundancy detection method, characterized in that, include: Obtain the circuit design to be tested, set the detection start point and detection end point of the circuit design, and create a mark and polarity corresponding to the detection start point, wherein the mark is used to represent the source information of the signal, and the polarity is used to represent the reversal information of the signal; Starting from the detection origin, the circuit design is traversed along the signal propagation direction, and the symbols and polarities are propagated within the circuit design during the traversal. For the current instance of the circuit design, if the input pin of the current instance is not the detection endpoint, the variable corresponding to the input pin in the function expression of the current instance is replaced with the symbol or constant value corresponding to the input pin. If the polarity indicator signal corresponding to any input pin has been flipped, the symbol corresponding to any input pin is added with a logical NOT operator before being replaced. The replaced function expression is logically simplified. If the simplification result is a constant value, logical redundancy is detected at the current instance.

2. The logical redundancy detection method according to claim 1, characterized in that, After logically simplifying the replaced functional expression, the following is also included: If the simplification result is not a constant, determine the notation and polarity of the output pin of the current instance; Locate the first input pin that is connected to the output pin of the current instance via a wire mesh, and record the symbol and polarity corresponding to the output pin of the current instance onto the first input pin as the symbol and polarity corresponding to the first input pin.

3. The logical redundancy detection method according to claim 2, characterized in that, If the simplification result is not a constant, determine the notation and polarity corresponding to the output pin of the current instance, including: If the simplification result contains only one symbol, the only symbol and the polarity corresponding to the only symbol are recorded to the output pin of the current instance as the symbol and polarity corresponding to the output pin of the current instance. If the simplification result contains multiple symbols, the symbols and polarities corresponding to the output pins of the current instance are recreated. The recreated symbols indicate that the source of the signal is the output pin of the current instance, and the recreated polarity indicator signal does not flip.

4. The logical redundancy detection method according to claim 3, characterized in that, The polarity includes a first polarity and a second polarity. The first polarity indicator signal has not flipped, while the second polarity indicator signal has flipped. Specifically, recording the single symbol and its corresponding polarity to the output pin of the current instance includes: In response to the simplification result not containing a logical NOT operator, the single symbol and the first polarity are recorded to the output pin of the current instance; In response to the simplification result also including a logical NOT operator, the single token and the second polarity are recorded to the output pin of the current instance.

5. The logical redundancy detection method according to claim 1, characterized in that, After obtaining the circuit design to be tested, the following steps are also included: Initialize the number of times each instance of the circuit design will be accessed, wherein the number of times will be accessed is determined based on the number of target input pins of each instance, which are connected to other pins or ports via nets and used to receive data signals.

6. The logical redundancy detection method according to claim 5, characterized in that, Initialize the number of visits for each instance of the circuit design, including: In response to any instance being the instance where the detection start point or the detection end point is located, the number of visits to any instance is initialized to 0. In response to any instance in each instance not being the instance where the detection start point is located or the instance where the detection end point is located, the number of times any instance needs to be accessed is initialized to the number of target input pins of any instance.

7. The logical redundancy detection method according to claim 5, characterized in that, After obtaining the circuit design to be tested, the following steps are also included: Place the detection starting point into a pre-created set of elements. The circuit design is traversed along the signal propagation direction starting from the detection starting point, including: Take at least one detection start point from the element set, find the second input pin connected to the at least one detection start point through a wire mesh, update the number of visits to the instance where the second input pin is located, and then take at least one element from the element set again and continue to search for the input pin until the element set is empty.

8. The logical redundancy detection method according to claim 7, characterized in that, The second input pin includes the n input pins of the current instance, wherein updating the number of times the instance containing the second input pin is to be accessed includes: Subtract n from the number of times the current instance needs to be accessed; In response to the current instance's pending access count being reduced to 0, the output pin of the current instance is placed into the element set; In response to the fact that the number of visits to the current instance has not been reduced to 0, the set of elements remains unchanged.

9. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions. Wherein, when the processor-executable instructions are executed by the processor, they cause the processor to perform the logical redundancy detection method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the logical redundancy detection method according to any one of claims 1 to 8.

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