Terminal structure of semiconductor power device and preparation method thereof
By introducing doped regions into the terminal structure of semiconductor power devices, the problems of uneven electric field distribution and ion aggregation are solved, achieving higher reliability and stability.
Patent Information
- Application Number
- CN202510952801.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-10
- Publication Date
- 2025-11-18
AI Technical Summary
The current semiconductor power device termination structure has an uneven electric field distribution under reverse bias, which is prone to dynamic avalanche. Furthermore, ions accumulate to a high degree on the surface of the epitaxial layer away from the substrate, affecting reliability.
In the termination structure of semiconductor power devices, a doped region is introduced. The conductivity type of the doped region is the same as that of the epitaxial layer and opposite to that of the junction termination extension region. The doping concentration is lower than that of the epitaxial layer. The electric field is balanced by rapidly expanding the space charge region and reducing the electric field intensity on the side of the epitaxial layer away from the substrate.
This improves the reliability of semiconductor power devices under high dV/dt conditions, reduces ion migration on the side of the epitaxial layer away from the substrate, and enhances the reliability of the terminal structure.
Smart Images
Figure CN120980929A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a terminal structure of a semiconductor power device and a preparation method thereof. BACKGROUND
[0002] Wide band gap semiconductor silicon carbide has a wide band gap, high thermal conductivity, high breakdown field strength, high electron saturation velocity and strong radiation resistance, so that silicon carbide power semiconductor devices can be applied to high temperature, high pressure, high frequency and strong radiation working environment, and therefore silicon carbide becomes an ideal material for high temperature and high power semiconductor devices. Due to the limited size of the semiconductor device, in order to alleviate the problem of breakdown of the semiconductor device caused by the concentration of the edge electric field of the semiconductor device, a junction terminal structure for protecting the semiconductor device is usually arranged at the edge of the semiconductor device. Common semiconductor terminal structures mainly include field plates, field limiting rings, junction termination extensions (JTE) and the like, and these terminal structures have been widely used in various semiconductor devices. SUMMARY
[0003] The technical problems solved by the present application include how to alleviate dynamic avalanche and reduce the lateral migration of ions on the side surface of the epitaxial layer away from the substrate layer.
[0004] The present application provides a terminal structure of a semiconductor power device, comprising: a substrate layer; an epitaxial layer located on one side of the substrate layer, the epitaxial layer comprising an active region and a terminal region surrounding the active region; a main junction located in the terminal region; a field limiting ring located in the terminal region, a plurality of the field limiting rings being arranged at intervals in the direction from the active region to the terminal region; a junction termination extension region located in the terminal region between the main junction and the field limiting ring and between adjacent field limiting rings, the junction termination extension region being away from the substrate layer relative to the field limiting ring; and a doped region located in the terminal region on the side of the junction termination extension region towards the substrate layer and in contact with the junction termination extension region, wherein the conductivity type of the doped region is the same as that of the epitaxial layer and opposite to that of the junction termination extension region, and the doping concentration of the doped region is less than that of the epitaxial layer.
[0005] Optionally, the doping concentration of the doped region is 1 / 20 to 4 / 5 of the doping concentration of the epitaxial layer.
[0006] Optionally, the doped region further extends to part of the surface of the main junction on the side towards the substrate layer and the surface of the field limiting ring on the side towards the substrate layer.
[0007] Optionally, a distance between a side surface of the doped region facing the substrate layer and a side surface of the field limiting ring facing the substrate layer in a first direction is 0.1 microns to 1 micron, the first direction being a direction from the substrate layer to the epitaxial layer.
[0008] Optionally, the doped region facing the side surface of the substrate layer is flush with the side surface of the main junction facing the substrate layer.
[0009] Optionally, the doped region facing the side surface of the substrate layer is flush with the side surface of the main junction facing the substrate layer.
[0010] Optionally, the doped region facing the side surface of the substrate layer is flush with the side surface of the main junction facing the substrate layer.
[0011] Optionally, the doped region facing the side surface of the substrate layer is flush with the side surface of the main junction facing the substrate layer.
[0012] Optionally, the doped region facing the side surface of the substrate layer is flush with the side surface of the main junction facing the substrate layer.
[0013] The application further provides a preparation method of a terminal structure of a semiconductor power device, comprising: forming an epitaxial layer on one side of a substrate layer, the epitaxial layer comprising an active region and a terminal region surrounding the active region; forming a main junction and a field limiting ring in the terminal region, a plurality of the field limiting rings being arranged at intervals in a direction from the active region to the terminal region; forming a junction terminal extension region; and forming a doped region; wherein the junction terminal extension region is located in the terminal region between the main junction and the field limiting ring and between adjacent field limiting rings, and the junction terminal extension region is away from the substrate layer relative to the field limiting ring; the doped region is located in the terminal region on a side of the junction terminal extension region facing the substrate layer and in contact with the junction terminal extension region, the doped region having the same conductivity type as the epitaxial layer and opposite conductivity type to the junction terminal extension region, and the doped region having a doping concentration less than that of the epitaxial layer.
[0014] Optionally, the junction termination extension region is formed by a first ion implantation process, and the doped region is formed by a second ion implantation process; wherein the ion implantation process of the first ion implantation process is the same as the conductive type of the field limiting ring, and the ion implantation process of the second ion implantation process is the same as the conductive type of the field limiting ring, and the implantation dose of the second ion implantation process is less than the implantation dose of the first ion implantation process.
[0015] Optionally, the first ion implantation process is performed after the second ion implantation process, or the second ion implantation process is performed after the first ion implantation process.
[0016] Optionally, the doped region also extends to part of the surface of the main junction towards the substrate layer and the surface of the field limiting ring towards the substrate layer; or the surface of the doped region towards the substrate layer is flush with the surface of the field limiting ring towards the substrate layer.
[0017] Optionally, the surface of the doped region towards the substrate layer is flush with the surface of the main junction towards the substrate layer.
[0018] Optionally, it also includes: forming an additional junction termination extension region, the additional junction termination extension region is located on the side of the field limiting ring away from the main junction and is spaced apart from the doped region and the junction termination extension region; forming an additional doped region, the additional doped region is located on the side of the additional junction termination extension region towards the substrate layer and is in contact with the additional junction termination extension region; wherein the conductive type of the additional doped region and the epitaxial layer is the same and opposite to the conductive type of the additional junction termination extension region, and the doping concentration of the additional doped region is less than the doping concentration of the epitaxial layer.
[0019] Optionally, the surface of the additional doped region towards the substrate layer is flush with the surface of the field limiting ring towards the substrate layer; or the spacing distance between the additional doped region and the substrate layer is less than the spacing distance between the field limiting ring and the substrate layer.
[0020] Optionally, the surface of the additional doped region towards the substrate layer is flush with the surface of the main junction towards the substrate layer; or the spacing distance between the additional doped region and the substrate layer is less than the spacing distance between the main junction and the substrate layer.
[0021] The technical scheme of the present application has the following technical effects: The terminal structure of the semiconductor power device provided by the technical scheme has a doping region located in a terminal region on a side of the junction terminal extension region facing the substrate layer and in contact with the junction terminal extension region, the doping region has the same conductivity type as the epitaxial layer and the opposite conductivity type to the junction terminal extension region, and the doping concentration of the doping region is less than the doping concentration of the epitaxial layer. The junction terminal extension region is in contact with the low-doped doping region. In the reverse bias state of the terminal structure of the semiconductor power device, the space charge region formed by the junction terminal extension region and the doping region extends more and faster in the doping region, the space charge region bears voltage lifting faster, the electric field distribution is more balanced, the occurrence of dynamic avalanche is alleviated, and the reliability of the terminal structure of the semiconductor power device under high dV / dt working conditions is improved. Secondly, the electric field intensity of the side surface of the epitaxial layer away from the substrate layer is reduced, the degree of ion accumulation on the side surface of the epitaxial layer away from the substrate layer is reduced, the electric field of the side surface of the epitaxial layer away from the substrate layer is reduced, the lateral migration of ions on the side surface of the epitaxial layer away from the substrate layer is reduced, and the reliability of the terminal structure is improved. BRIEF DESCRIPTION OF DRAWINGS
[0022] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0023] Figure 1 It is a schematic diagram of a terminal structure of a semiconductor power device in the related art; Figure 2 It is a schematic diagram of a terminal structure of a semiconductor power device in an embodiment of the present application; Figure 3 It is a schematic diagram of a terminal structure of a semiconductor power device in another embodiment of the present application; Figure 4 It is a schematic diagram of a terminal structure of a semiconductor power device in still another embodiment of the present application; Figures 5 to 7 It is a schematic diagram of a preparation process of a terminal structure of a semiconductor power device in an embodiment of the present application; Figures 8 to 10 It is a schematic diagram of a preparation process of a terminal structure of a semiconductor power device in an embodiment of the present application; Figures 11 to 13 It is a schematic diagram of a preparation process of a terminal structure of a semiconductor power device in an embodiment of the present application. DETAILED DESCRIPTION
[0024] A terminal structure of a semiconductor power device in the related art, referring to Figure 1The semiconductor power device includes a substrate layer 100, an epitaxial layer 120 located on one side of the substrate layer 100, the epitaxial layer 120 including an active region and a termination region surrounding the active region, a main junction 140 located in the termination region, a field limiting ring 130 located in the termination region, a plurality of field limiting rings 130 being arranged at intervals in the direction from the active region to the termination region, a junction termination extension region 150 located in the termination region between the main junction 140 and the field limiting ring 130 and between adjacent field limiting rings 130, the junction termination extension region 150 being away from the substrate layer 100 relative to the field limiting ring 130, a side surface of the junction termination extension region 150 facing the substrate layer 100 being in contact with the epitaxial layer 120, a conductive lead-out piece 160, a potential on the conductive lead-out piece 160 being set to be equal to an applied potential on the source region, a drain metal layer 110 located on a side of the substrate layer 100 away from the epitaxial layer 120, and a field oxide layer 170.
[0025] However, the performance of the terminal structure of the semiconductor power device needs to be improved, and research has found that the reason is that: Under the reverse bias state of the terminal structure of the semiconductor power device, the space charge region formed by the junction termination extension region 150 and the epitaxial layer 120 bears a slow voltage rise, the electric field distribution is unbalanced, the reliability of the terminal structure of the semiconductor power device under high dV / dt working conditions needs to be improved, and dynamic avalanche is prone to occur. Secondly, in high humidity and high temperature reverse bias voltage reliability tests, the degree of ion accumulation on the side surface of the epitaxial layer away from the substrate layer needs to be reduced.
[0026] On this basis, the application provides a terminal structure of a semiconductor power device and a preparation method thereof, which alleviates dynamic avalanche and reduces the degree of ion accumulation on the side surface of the epitaxial layer away from the substrate layer, reduces the electric field on the side surface of the epitaxial layer away from the substrate layer, reduces the lateral migration of ions on the side surface of the epitaxial layer away from the substrate layer, and improves the reliability of the terminal structure.
[0027] The technical solutions of the present application will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0029] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements, it can be wireless connection, or it can be wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0030] In addition, the technical features involved in the different embodiments of the application described below can be combined with each other as long as there is no conflict between them.
[0031] An embodiment of the present application provides a terminal structure of a semiconductor power device, referring to Figure 2 , Figure 3 and Figure 4 , comprising: a substrate layer 200; an epitaxial layer 220 located on one side of the substrate layer 200, the epitaxial layer 220 comprising an active region and a terminal region surrounding the active region; a main junction 240 located in the terminal region; a field limiting ring 230 located in the terminal region, a plurality of field limiting rings 230 being arranged at intervals in the direction from the active region to the terminal region; a junction terminal extension region 250 located in the terminal region between the main junction 240 and the field limiting ring 230 and between adjacent field limiting rings 230, the junction terminal extension region 250 being away from the substrate layer 200 relative to the field limiting ring 230; a doped region 280 located in the terminal region on the side of the junction terminal extension region 250 facing the substrate layer 200 and in contact with the junction terminal extension region 250, wherein the doped region 280 has the same conductivity type as the epitaxial layer 220 and the opposite conductivity type to the junction terminal extension region 250, and the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220.
[0032] The terminal structure of the semiconductor power device of the embodiment includes a junction terminal extension region 250 and a low-doped doped region 280. The junction terminal extension region 250 is located in the terminal region of the junction terminal extension region 250 on the side of the substrate layer 200, and the doped region 280 is in contact with the junction terminal extension region 250. The doped region 280 is of the same conductivity type as the epitaxial layer 220 and opposite to the conductivity type of the junction terminal extension region 250. The doping concentration of the doped region 280 is lower than the doping concentration of the epitaxial layer 220. The junction terminal extension region 250 is in contact with the low-doped doped region 280. In the reverse bias state of the terminal structure of the semiconductor power device, the space charge region formed by the junction terminal extension region 250 and the doped region 280 extends more and faster in the doped region 280. The space charge region bears voltage rise faster, and the electric field distribution is more balanced. The occurrence of dynamic avalanche is alleviated, and the reliability of the terminal structure of the semiconductor power device under high dV / dt working condition is improved. Secondly, the electric field intensity of the side surface of the epitaxial layer 220 away from the substrate layer 200 is reduced, and the degree of ion accumulation on the side surface of the epitaxial layer 220 away from the substrate layer 200 is reduced, for example, the degree of ion accumulation on the side surface of the epitaxial layer 220 away from the substrate layer 200 in high humidity and high temperature reverse bias voltage reliability test is reduced. The electric field of the side surface of the epitaxial layer 220 away from the substrate layer 200 is reduced, the lateral migration of ions on the side surface of the epitaxial layer 220 away from the substrate layer 200 is reduced, and the reliability of the terminal structure is improved.
[0033] In the embodiment, the semiconductor power device further includes a device structure in the active region, for example, a silicon carbide (SiC) MOSFET. The device structure includes a well region in the active region, a source region in the well region, and a gate structure. The gate structure is a planar gate structure or a trench gate structure. When the gate structure is a planar gate structure, the gate structure covers the JFET region between adjacent well regions and a part of the source region. When the gate structure is a trench gate structure, the gate structure is located in the active region, and the well region is located on both sides of the gate structure.
[0034] In the embodiment, the substrate layer 200 is, for example, silicon carbide (SiC) doped with N-type conductive ions.
[0035] In the embodiment, the conductivity type of the epitaxial layer 220 is the same as that of the substrate layer 200, and the doping concentration of the epitaxial layer 220 is lower than that of the substrate layer 200. In one embodiment, the material of the epitaxial layer 220 is silicon carbide doped with N-type conductive ions. The N-type conductive ions can be phosphorus ions or nitrogen ions.
[0036] In the embodiment, the terminal region surrounds the active region. Figure 2 、 Figure 3 and Figure 4 The terminal region is shown, and the active region is not shown.
[0037] In the embodiment, reference is made to Figure 2 、 Figure 3 andFigure 4 The terminal structure of the semiconductor power device further comprises a drain metal layer 210 located on the side of the substrate layer 200 facing away from the epitaxial layer 220; a field oxide layer 270 located on the side of the field limiting ring 230 and the junction termination extension region 250 facing away from the substrate layer 200, the field oxide layer 270 further extending to part of the surface of the main junction 240. The material of the field oxide layer 270 comprises silicon oxide.
[0038] Wherein, dV / dt refers to the rate of change of voltage between the source region and the drain metal layer 210.
[0039] In this embodiment, with reference to Figure 2 , Figure 3 and Figure 4 The terminal structure of the semiconductor power device further comprises a conductive lead-out piece 260 connected with the main junction 240, the potential on the conductive lead-out piece 260 is used to be set equal to the potential applied on the source region when the terminal structure of the semiconductor power device is reverse biased, avoiding the potential on the main junction 240 floating, and improving the electrical stability.
[0040] In this embodiment, the terminal structure of the semiconductor power device further comprises an isolation dielectric layer (not shown) located on the side of the field oxide layer 270 facing away from the terminal region; a passivation layer (not shown) located on the side of the isolation dielectric layer facing away from the field oxide layer 270.
[0041] In one embodiment, the material of the isolation dielectric layer comprises boron phosphorus silicon glass.
[0042] In one embodiment, the material of the passivation layer comprises silicon oxide. The passivation layer is used to prevent water vapor.
[0043] In this embodiment, the junction termination extension region 250 is away from the substrate layer 200 relative to the field limiting ring 230, specifically, the side surface of the junction termination extension region 250 facing the substrate layer 200 is away from the substrate layer 200 relative to the side surface of the field limiting ring 230 facing the substrate layer 200.
[0044] In this embodiment, the conductivity type of the main junction 240 and the conductivity type of the field limiting ring 230 are the same, and the conductivity type of the field limiting ring 230 and the conductivity type of the epitaxial layer 220 are opposite. For example, the conductivity type of the main junction 240 and the conductivity type of the field limiting ring 230 are both P-type.
[0045] In this embodiment, the conductivity type of the junction termination extension region 250 and the conductivity type of the field limiting ring 230 are the same, for example, the conductivity type of the main junction termination extension region 250 is P-type. The doping concentration of the junction termination extension region 250 is less than the doping concentration of the field limiting ring 230.
[0046] In the embodiment, the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220, and specifically, the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220 between the doped region 280 and the substrate layer 200.
[0047] In one embodiment, the doping concentration of the doped region 280 is 1 / 20-4 / 5 of the doping concentration of the epitaxial layer 220, for example, 1 / 20, 1 / 15, 1 / 12, 1 / 10, 1 / 5 or 4 / 5. If the doping concentration of the doped region 280 is too small, it is not conducive to the improvement of the blocking voltage of the termination structure in the reverse bias state; if the doping concentration of the doped region 280 is too large, the degree of alleviating dynamic avalanche is small and the degree of reducing the lateral migration of ions on the side surface of the epitaxial layer 220 away from the substrate layer 200 is small.
[0048] In the embodiment, referring to Figure 2 , the doped region 280 is located in the termination region on the side of the junction termination extension region 250 facing the substrate layer 200 and in contact with the junction termination extension region 250, and the doped region 280 also extends to part of the surface of the main junction 240 on the side facing the substrate layer 200 and the surface of the field limiting ring 230 on the side facing the substrate layer 200.
[0049] Referring to Figure 2 , the spacing distance between the doped region 280 and the substrate layer 200 is less than the spacing distance between the field limiting ring 230 and the substrate layer 200. The spacing distance between the doped region 280 and the substrate layer 200 is less than the spacing distance between the main junction 240 and the substrate layer 200.
[0050] Referring to Figure 2 , the distance between the side surface of the doped region 280 facing the substrate layer 200 and the side surface of the field limiting ring 230 facing the substrate layer 200 in the first direction is 0.1-1 microns, for example, 0.1 microns, 0.2 microns, 0.5 microns, 0.8 microns or 1 micron. The first direction is the arrangement direction of the substrate layer to the epitaxial layer. If the distance between the side surface of the doped region 280 facing the substrate layer 200 and the side surface of the field limiting ring 230 facing the substrate layer 200 in the first direction is too large, it is not conducive to the improvement of the blocking voltage of the termination structure in the reverse bias state; if the distance between the side surface of the doped region 280 facing the substrate layer 200 and the side surface of the field limiting ring 230 facing the substrate layer 200 in the first direction is too small, the degree of alleviating dynamic avalanche is small and the degree of reducing the lateral migration of ions on the side surface of the epitaxial layer 220 away from the substrate layer 200 is small.
[0051] The doping concentration of the doping region 280 is within the range of the doping concentration of the epitaxial layer 220 and the distance between the side surface of the doping region 280 facing the substrate layer 200 and the side surface of the field limiting ring 230 facing the substrate layer 200 in the first direction, so that the effective dynamic avalanche mitigation and the effective ion lateral migration reduction on the side surface of the epitaxial layer 220 away from the substrate layer 200 can be achieved.
[0052] Further, referring to Figure 2 , the distance between the side surface of the doping region 280 facing the substrate layer 200 and the side surface of the main junction 240 facing the substrate layer 200 in the first direction is 0.1 microns to 1 micron.
[0053] Referring to Figure 3 , the doping region 280 is located in the terminal region of the junction terminal extension region 250 facing the substrate layer 200 and in contact with the junction terminal extension region 250, and the side surface of the doping region 280 facing the substrate layer 200 is flush with the side surface of the field limiting ring 230 facing the substrate layer 200. Further, the side surface of the doping region 280 facing the substrate layer 200 is flush with the side surface of the main junction 240 facing the substrate layer 200. That is, the doping region 280 does not extend to the side surface of the main junction 240 facing the substrate layer 200, and the doping region 280 does not extend to the side surface of the field limiting ring 230 facing the substrate layer 200. In this way, the doping region 280 reduces the impact on the topography of the side surface of the main junction 240 facing the substrate layer 200 and reduces the impact on the topography of the side surface of the field limiting ring 230 facing the substrate layer 200. The probability of the local regions of the field limiting ring 230 and the main junction 240 forming sharp corners is reduced, and the situation of a large electric field peak at the sharp corner position is avoided.
[0054] Referring to Figure 4 , the terminal structure of the semiconductor power device further includes: an additional junction terminal extension region 251 located on the side of the field limiting ring 230 away from the main junction 240 and spaced apart from the doping region 280 and the junction terminal extension region 250; and an additional doping region 290 located on the side of the additional junction terminal extension region 251 facing the substrate layer 200 and in contact with the additional junction terminal extension region 251; wherein the additional doping region 290 and the epitaxial layer 220 have the same conductivity type and the opposite conductivity type of the additional junction terminal extension region 251, and the doping concentration of the additional doping region 290 is less than the doping concentration of the epitaxial layer 220. The dynamic avalanche is further mitigated, and the ion accumulation on the side surface of the epitaxial layer 220 away from the substrate layer 200 is further reduced.
[0055] For example, the conductivity type of the additional junction terminal extension region 251 is P-type, and the conductivity type of the additional doping region 290 is N-type.
[0056] The doping concentration of the additional junction terminal extension region 251 is less than the doping concentration of the field limiting ring 230.
[0057] It should be noted that, Figure 4 The additional junction terminal extension region 251 and the additional doped region 290 are arranged on the basis of the Figure 2 In other embodiments, the additional junction terminal extension region 251 and the additional doped region 290 can also be arranged on the basis of the Figure 3
[0058] In one embodiment, the doping concentration of the additional doped region 290 is 1 / 20~4 / 5 of the doping concentration of the epitaxial layer 220, for example, 1 / 20, 1 / 15, 1 / 12, 1 / 10, 1 / 5 or 4 / 5.
[0059] In one embodiment, the side surface of the additional doped region 290 towards the substrate layer 200 is flush with the side surface of the field limiting ring 230 towards the substrate layer 200; further, the side surface of the additional doped region 290 towards the substrate layer 200 is flush with the side surface of the main junction 240 towards the substrate layer 200.
[0060] In another embodiment, the spacing distance between the additional doped region 290 and the substrate layer 200 is smaller than the spacing distance between the field limiting ring 230 and the substrate layer 200. Further, the distance between the side surface of the additional doped region 290 towards the substrate layer 200 and the side surface of the field limiting ring 230 towards the substrate layer 200 in the first direction is 0.1 microns~1 microns, for example, 0.1 microns, 0.2 microns, 0.5 microns, 0.8 microns or 1 microns. Further, the spacing distance between the additional doped region 290 and the substrate layer 200 is smaller than the spacing distance between the main junction 240 and the substrate layer 200. Further, the distance between the side surface of the additional doped region 290 towards the substrate layer 200 and the side surface of the main junction 240 towards the substrate layer 200 in the first direction is 0.1 microns~1 microns, for example, 0.1 microns, 0.2 microns, 0.5 microns, 0.8 microns or 1 microns.
[0061] The application also provides a preparation method of a terminal structure of a semiconductor power device, comprising: forming an epitaxial layer on one side of a substrate layer, the epitaxial layer comprising an active region and a terminal region surrounding the active region; forming a main junction and a field limiting ring in the terminal region, a plurality of field limiting rings being arranged at intervals along the direction from the active region to the terminal region; forming a junction terminal extension region; and forming a doped region; wherein the junction terminal extension region is located in the terminal region between the main junction and the field limiting ring and between adjacent field limiting rings, and the junction terminal extension region is away from the substrate layer relative to the field limiting ring; the doped region is located in the terminal region on the side of the junction terminal extension region towards the substrate layer and in contact with the junction terminal extension region, the doped region has the same conductivity type as the epitaxial layer and the opposite conductivity type to the junction terminal extension region, and the doping concentration of the doped region is smaller than the doping concentration of the epitaxial layer.
[0062] Figures 5 to 7 FIG. 2 is a schematic diagram of a process for manufacturing a termination structure of a semiconductor power device according to an embodiment of the present application.
[0063] Referring to FIG. 2, a substrate layer 200 is provided. The substrate layer 200 is formed of a semiconductor material, such as silicon carbide (SiC). The substrate layer 200 is doped with a first dopant of a first conductivity type. The substrate layer 200 is formed of a single crystal semiconductor material. Figure 5 An epitaxial layer 220 is formed on one side of the substrate layer 200. The epitaxial layer 220 includes an active region and a termination region surrounding the active region. A main junction 240 and field limiting rings 230 are formed in the termination region. The field limiting rings 230 are spaced apart along a direction from the active region to the termination region.
[0064] The process of forming the main junction 240 includes an ion implantation process. The process of forming the field limiting rings 230 includes an ion implantation process. In one embodiment, the field limiting rings 230 are formed during the process of forming the main junction 240.
[0065] In the embodiment, a device structure is formed in the active region. The device structure is, for example, a SiC MOSFET. The device structure includes a well region in the active region, a source region in the well region, and a gate structure. The gate structure is a planar gate structure or a trench gate structure. When the gate structure is the planar gate structure, the gate structure covers a JFET region between adjacent well regions and a portion of the source region. When the gate structure is the trench gate structure, the gate structure is located in the active region, and the well region is located on both sides of the gate structure.
[0066] The substrate layer 200, the epitaxial layer 220, the main junction 240, and the field limiting rings 230 are described with reference to the descriptions of the foregoing embodiments.
[0067] Referring to FIG. 3, a junction termination extension region 250 is formed. A doped region 280 is formed. The junction termination extension region 250 is located in the termination region between the main junction 240 and the field limiting rings 230 and between adjacent field limiting rings 230. The junction termination extension region 250 is away from the substrate layer 200 relative to the field limiting rings 230. The doped region 280 is located in the termination region on a side of the junction termination extension region 250 toward the substrate layer 200 and contacts the junction termination extension region 250. The doped region 280 has a same conductivity type as the epitaxial layer 220 and an opposite conductivity type to the junction termination extension region 250. The doped region 280 has a doping concentration less than a doping concentration of the epitaxial layer 220. Figure 6 The junction termination extension region 250 is formed by a first ion implantation process. The doped region 280 is formed by a second ion implantation process. The first ion implantation process implants ions of a same conductivity type as the field limiting rings 230. The second ion implantation process implants ions of a same conductivity type as the field limiting rings 230. The second ion implantation process has a smaller implantation dose than the first ion implantation process.
[0068]
[0069] After the first ion implantation process, the second ion implantation process is performed, or after the second ion implantation process, the first ion implantation process is performed.
[0070] In the embodiment, the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220, and specifically, the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220 between the doped region 280 and the substrate layer 200.
[0071] In one embodiment, the doping concentration of the doped region 280 is 1 / 20-4 / 5 of the doping concentration of the epitaxial layer 220.
[0072] In the embodiment, the doped region 280 is located in the terminal region of the junction terminal extension region 250 facing the substrate layer 200 and in contact with the junction terminal extension region 250, and the doped region 280 also extends to part of the surface of the main junction 240 facing the substrate layer 200 and the surface of the field limiting ring 230 facing the substrate layer 200.
[0073] The spacing distance between the doped region 280 and the substrate layer 200 is less than the spacing distance between the field limiting ring 230 and the substrate layer 200. The spacing distance between the doped region 280 and the substrate layer 200 is less than the spacing distance between the main junction 240 and the substrate layer 200.
[0074] In one embodiment, the distance between the surface of the doped region 280 facing the substrate layer 200 and the surface of the field limiting ring 230 facing the substrate layer 200 in the first direction is 0.1-1 microns, and the first direction is the arrangement direction of the substrate layer to the epitaxial layer.
[0075] In one embodiment, the distance between the surface of the doped region 280 facing the substrate layer 200 and the surface of the main junction 240 facing the substrate layer 200 in the first direction is 0.1-1 microns.
[0076] Reference Figure 7 The field oxide layer 270 is formed, the field oxide layer 270 is located on the side of the field limiting ring 230 and the junction terminal extension region 250 away from the substrate layer 200, and the field oxide layer 270 also extends to part of the surface of the main junction 240. The conductive lead-out piece 260 is formed, and the conductive lead-out piece 260 is connected with the main junction 240.
[0077] The potential on the conductive lead-out piece 260 is used to be set equal to the potential applied on the source region when the terminal structure of the semiconductor power device is reverse biased, avoiding the potential on the main junction 240 floating, and improving the electrical stability.
[0078] The embodiment further includes forming an isolation dielectric layer (not shown) on a side of the field oxide layer 270 facing away from the termination region; and forming a passivation layer (not shown) on a side of the isolation dielectric layer facing away from the field oxide layer 270.
[0079] Referring to Figure 7 forming a drain metal layer 210 on a side of the substrate layer 200 facing away from the epitaxial layer 220.
[0080] Figures 8 to 10 FIG. 1 is a schematic diagram of a process for manufacturing a termination structure of a semiconductor power device according to an embodiment of the present application.
[0081] Referring to Figure 8 forming an epitaxial layer 220 on a side of the substrate layer 200, the epitaxial layer 220 including an active region and a termination region surrounding the active region; forming a main junction 240 and field limiting rings 230 in the termination region, the field limiting rings 230 being spaced apart along a direction from the active region to the termination region.
[0082] The process of forming the main junction 240 includes an ion implantation process. The process of forming the field limiting rings 230 includes an ion implantation process. In one embodiment, the field limiting rings 230 are formed in the process of forming the main junction 240.
[0083] The embodiment further includes forming a device structure in the active region, the device structure being, for example, a silicon carbide (SiC) MOSFET. The device structure includes: a well region in the active region; a source region in the well region; and a gate structure. The gate structure is a planar gate structure or a trench gate structure. When the gate structure is the planar gate structure, the gate structure covers a JFET region between adjacent well regions and a portion of the source region. When the gate structure is the trench gate structure, the gate structure is in the active region, and the well region is on both sides of the gate structure.
[0084] The descriptions of the substrate layer 200, the epitaxial layer 220, the main junction 240, and the field limiting rings 230 refer to the descriptions of the foregoing embodiments.
[0085] Referring to Figure 9 forming a junction termination extension region 250 in the termination region between the main junction 240 and the field limiting rings 230 and between adjacent field limiting rings 230, the junction termination extension region 250 being farther away from the substrate layer 200 than the field limiting rings 230; and forming a doped region 280 in the termination region on a side of the junction termination extension region 250 facing the substrate layer 200 and in contact with the junction termination extension region 250, the doped region 280 being of the same conductivity type as the epitaxial layer 220 and opposite to a conductivity type of the junction termination extension region 250, and having a doping concentration less than a doping concentration of the epitaxial layer 220.
[0086] The junction terminal extension region 250 is formed by a first ion implantation process, and the doped region 280 is formed by a second ion implantation process; the ion implantation process of the first ion implantation process is of the same conductive type as the field limiting ring 230, and the ion implantation process of the second ion implantation process is of the same conductive type as the field limiting ring 230, and the ion implantation dose of the second ion implantation process is less than the ion implantation dose of the first ion implantation process.
[0087] The first ion implantation process is performed before the second ion implantation process, or the second ion implantation process is performed before the first ion implantation process.
[0088] In this embodiment, the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220, and specifically, the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220 between the doped region 280 and the substrate layer 200.
[0089] In one embodiment, the doping concentration of the doped region 280 is 1 / 20 to 4 / 5 of the doping concentration of the epitaxial layer 220.
[0090] In this embodiment, the doped region 280 is located in the terminal region of the side of the junction terminal extension region 250 facing the substrate layer 200 and in contact with the junction terminal extension region 250, and the side surface of the doped region 280 facing the substrate layer 200 is flush with the side surface of the field limiting ring 230 facing the substrate layer 200. Further, the side surface of the doped region 280 facing the substrate layer 200 is flush with the side surface of the main junction 240 facing the substrate layer 200.
[0091] Referring to Figure 10 , the field oxide layer 270 is formed, and the field oxide layer 270 is located on the side of the field limiting ring 230 and the junction terminal extension region 250 away from the substrate layer 200, and the field oxide layer 270 also extends to part of the surface of the main junction 240. The conductive lead-out piece 260 is formed and connected with the main junction 240.
[0092] The potential on the conductive lead-out piece 260 is used to be set equal to the potential applied on the source region when the terminal structure of the semiconductor power device is reverse biased, avoiding the potential on the main junction 240 floating, and improving the electrical stability.
[0093] This embodiment also includes forming an isolation dielectric layer (not shown) on the side of the field oxide layer 270 away from the terminal region, and forming a passivation layer (not shown) on the side of the isolation dielectric layer away from the field oxide layer 270.
[0094] Referring to Figure 10 , the drain metal layer 210 is formed on the side of the substrate layer 200 away from the epitaxial layer 220.
[0095] Figures 11 to 13 This is a schematic diagram illustrating the fabrication process of the terminal structure of a semiconductor power device in one embodiment of this application.
[0096] refer to Figure 11 An epitaxial layer 220 is formed on one side of the substrate 200. The epitaxial layer 220 includes an active region and a terminal region surrounding the active region. A main junction 240 and a field limiting ring 230 are formed in the terminal region. Multiple field limiting rings 230 are arranged at intervals along the direction from the active region to the terminal region.
[0097] The process for forming the main junction 240 includes an ion implantation process. The process for forming the field confinement ring 230 includes an ion implantation process. In one embodiment, the field confinement ring 230 is formed during the formation of the main junction 240.
[0098] This embodiment further includes: forming a device structure in the active region, such as a silicon carbide (SiC) MOSFET. The device structure includes: a well region located in the active region; a source region located in the well region; and a gate structure. The gate structure is either a planar gate structure or a trench gate structure. When the gate structure is a planar gate structure, the gate structure covers the JFET region between adjacent well regions and a portion of the source region. When the gate structure is a trench gate structure, the gate structure is located in the active region, and the well regions are located on both sides of the gate structure.
[0099] The description of the substrate layer 200, epitaxial layer 220, main junction 240 and field limiting ring 230 refers to the description of the foregoing embodiments.
[0100] refer to Figure 12 A junction termination extension region 250 is formed; a doped region 280 is formed; wherein, the junction termination extension region 250 is located in the termination region between the main junction 240 and the field limiting ring 230 and between adjacent field limiting rings 230, and the junction termination extension region 250 is far away from the substrate layer 200 relative to the field limiting ring 230; the doped region 280 is located in the termination region of the junction termination extension region 250 on the side facing the substrate layer 200 and is in contact with the junction termination extension region 250, the conductivity type of the doped region 280 is the same as the conductivity type of the epitaxial layer 220 and opposite to the conductivity type of the junction termination extension region 250, and the doping concentration of the doped region 280 is less than the doping concentration of the epitaxial layer 220.
[0101] The junction terminal extension region 250 is formed using a first ion implantation process, and the doped region 280 is formed using a second ion implantation process. The conductivity type of the ions implanted in the first ion implantation process is the same as that of the field confinement ring 230, and the conductivity type of the ions implanted in the second ion implantation process is the same as that of the field confinement ring 230. The implantation dose of the second ion implantation process is less than that of the first ion implantation process.
[0102] After the first ion implantation process, the second ion implantation process is performed, or after the second ion implantation process, the first ion implantation process is performed.
[0103] In this embodiment, the description of the doped region 280 refers to the doped region 280 in Figure 6 In other embodiments, the description of the doped region 280 can refer to the doped region 280 in Figure 9
[0104] In this embodiment, the method further comprises: forming an additional junction termination extension region 251, the additional junction termination extension region 251 being located on a side of the field limiting ring 230 facing away from the main junction 240 and being spaced apart from the doped region 280 and the junction termination extension region 250; and forming an additional doped region 290, the additional doped region 290 being located on a side of the additional junction termination extension region 251 facing the substrate layer 200 and being in contact with the additional junction termination extension region 251; wherein the additional doped region 290 and the epitaxial layer 220 are of the same conductivity type and opposite to the conductivity type of the additional junction termination extension region 251, and the doping concentration of the additional doped region 290 is less than the doping concentration of the epitaxial layer 220.
[0105] The doping concentration of the additional junction termination extension region 251 is less than the doping concentration of the field limiting ring 230.
[0106] It should be noted that, Figure 12 The additional junction termination extension region 251 and the additional doped region 290 are arranged on the basis of the field limiting ring 230 and the doped region 280. Figure 6 In other embodiments, the additional junction termination extension region 251 and the additional doped region 290 can also be arranged on the basis of the field limiting ring 230 and the doped region 280. Figure 9
[0107] In one embodiment, the doping concentration of the additional doped region 290 is 1 / 20~4 / 5 of the doping concentration of the epitaxial layer 220.
[0108] In one embodiment, the additional doped region 290 is formed in the process of forming the doped region 280.
[0109] In one embodiment, the additional junction termination extension region 251 is formed in the process of forming the junction termination extension region 250.
[0110] In one embodiment, referring to Figure 12 Further, the distance between the side surface of the additional doped region 290 facing the substrate layer 200 and the side surface of the field limiting ring 230 facing the substrate layer 200 in the first direction is 0.1 microns~1 micron, for example, 0.1 micron, 0.2 micron, 0.5 micron, 0.8 micron or 1 micron. Further, referring toFigure 12 The spacing distance between the additional doped region 290 and the substrate layer 200 is less than the spacing distance between the main junction 240 and the substrate layer 200. Further, the distance between the side surface of the additional doped region 290 facing the substrate layer 200 and the side surface of the main junction 240 facing the substrate layer 200 in the first direction is 0.1 micrometer to 1 micrometer, for example, 0.1 micrometer, 0.2 micrometer, 0.5 micrometer, 0.8 micrometer or 1 micrometer.
[0111] In other embodiments, the side surface of the additional doped region facing the substrate layer is flush with the side surface of the field limiting ring facing the substrate layer; further, the side surface of the additional doped region facing the substrate layer is flush with the side surface of the main junction facing the substrate layer.
[0112] Referring to Figure 13 The field oxide layer 270 is formed, the field oxide layer 270 is located at the side of the field limiting ring 230 and the junction termination extension region 250 facing away from the substrate layer 200, and the field oxide layer 270 further extends to part of the surface of the main junction 240. The conductive extraction 260 is formed, the conductive extraction 260 is connected with the main junction 240.
[0113] The potential on the conductive extraction 260 is used to be set equal to the potential applied on the source region when the termination structure of the semiconductor power device is reverse biased, avoiding the potential on the main junction 240 floating, and improving the electrical stability.
[0114] The embodiments also include: forming an isolation dielectric layer (not shown), the isolation dielectric layer is located at the side of the field oxide layer 270 facing away from the termination region; forming a passivation layer (not shown), the passivation layer is located at the side of the isolation dielectric layer facing away from the field oxide layer 270.
[0115] Referring to Figure 13 The drain metal layer 210 is formed, the drain metal layer 210 is located at the side of the substrate layer 200 facing away from the epitaxial layer 220.
[0116] Obviously, the above-described embodiments are only examples for clearly illustrating the present application, and are not intended to limit the present application. Based on the above description, other different forms of changes or modifications can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or modifications derived therefrom are still within the protection scope of the present application.
Claims
1. A termination structure for a semiconductor power device, characterized in that, include: Substrate layer; An epitaxial layer located on one side of the substrate layer, the epitaxial layer including an active region and a terminal region surrounding the active region; The main node is located in the terminal region; A field limiting loop is located in the terminal region, and multiple field limiting loops are arranged at intervals along the direction from the active region to the terminal region; A junction termination extension region is located in the termination region between the main junction and the field limiting ring and between adjacent field limiting rings, and the junction termination extension region is far away from the substrate layer relative to the field limiting ring; as well as A doped region is located in the terminal region on the side of the junction terminal extension region facing the substrate layer and is in contact with the junction terminal extension region. The conductivity type of the doped region is the same as that of the epitaxial layer and opposite to that of the junction terminal extension region. The doping concentration of the doped region is less than that of the epitaxial layer.
2. The termination structure of the semiconductor power device according to claim 1, characterized in that, The doping concentration of the doped region is 1 / 20 to 4 / 5 of the doping concentration of the epitaxial layer.
3. The termination structure of the semiconductor power device according to claim 1, characterized in that, The doped region also extends to a portion of the main junction surface facing the substrate and the surface of the field confinement ring facing the substrate. Preferably, the distance between the side surface of the doped region facing the substrate and the side surface of the field limiting ring facing the substrate in a first direction is 0.1 micrometer to 1 micrometer, where the first direction is the arrangement direction from the substrate to the epitaxial layer.
4. The termination structure of the semiconductor power device according to claim 1, characterized in that, The surface of the doped region facing the substrate is flush with the surface of the field limiting ring facing the substrate. Preferably, the side surface of the doped region facing the substrate is flush with the side surface of the main junction facing the substrate.
5. The termination structure of the semiconductor power device according to claim 1, characterized in that, Also includes: An additional junction termination extension region is located on the side of the field limiting ring away from the main junction and is spaced apart from the doped region and the junction termination extension region; as well as An additional doped region is located on the side of the additional junction terminal extension region facing the substrate and is in contact with the additional junction terminal extension region; Wherein, the additional doped region and the epitaxial layer have the same conductivity type but the opposite conductivity type to the additional junction terminal extension region, and the doping concentration of the additional doped region is less than the doping concentration of the epitaxial layer; Preferably, the side surface of the additional doped region facing the substrate is flush with the side surface of the field limiting ring facing the substrate; or, the spacing between the additional doped region and the substrate is smaller than the spacing between the field limiting ring and the substrate. Preferably, the side surface of the additional doped region facing the substrate is flush with the side surface of the main junction facing the substrate; or, the spacing between the additional doped region and the substrate is less than the spacing between the main junction and the substrate.
6. A method for fabricating a termination structure for a semiconductor power device, characterized in that, include: An epitaxial layer is formed on one side of the substrate layer, the epitaxial layer including an active region and a terminal region surrounding the active region; A main junction and a field limiting loop are formed in the terminal region, and a plurality of the field limiting loops are arranged at intervals along the direction from the active region to the terminal region; Forming a terminal extension region; Formation of doped regions; The junction termination extension region is located in the termination region between the main junction and the field limiting ring, and between adjacent field limiting rings, and the junction termination extension region is far away from the substrate layer relative to the field limiting ring; the doped region is located in the termination region on the side of the junction termination extension region facing the substrate layer and is in contact with the junction termination extension region, the conductivity type of the doped region is the same as the conductivity type of the epitaxial layer and opposite to the conductivity type of the junction termination extension region, and the doping concentration of the doped region is less than the doping concentration of the epitaxial layer.
7. The method for fabricating the termination structure of the semiconductor power device according to claim 6, characterized in that, The first ion implantation process is used to form the junction terminal extension region, and the second ion implantation process is used to form the doped region. In this process, the conductivity type of the ions implanted by the first ion implantation process is the same as that of the field confinement ring, the conductivity type of the ions implanted by the second ion implantation process is the same as that of the field confinement ring, and the implantation dose of the second ion implantation process is less than that of the first ion implantation process. Preferably, the second ion implantation process is performed after the first ion implantation process, or the first ion implantation process is performed after the second ion implantation process.
8. The method for fabricating the termination structure of the semiconductor power device according to claim 6, characterized in that, The doped region also extends to a portion of the main junction surface facing the substrate and the surface of the field confinement ring facing the substrate. Alternatively, the surface of the doped region facing the substrate is flush with the surface of the field limiting ring facing the substrate; preferably, the surface of the doped region facing the substrate is flush with the surface of the main junction facing the substrate.
9. The method for fabricating the terminal structure of the semiconductor power device according to claim 6, characterized in that, Also includes: An additional junction terminal extension region is formed, which is located on the side of the field limiting ring away from the main junction and is spaced apart from the doped region and the junction terminal extension region; An additional doped region is formed, which is located on the side of the additional junction terminal extension region facing the substrate and is in contact with the additional junction terminal extension region; Wherein, the additional doped region and the epitaxial layer have the same conductivity type but the opposite conductivity type to the additional junction terminal extension region, and the doping concentration of the additional doped region is less than the doping concentration of the epitaxial layer; Preferably, the side surface of the additional doped region facing the substrate is flush with the side surface of the field limiting ring facing the substrate; or, the spacing between the additional doped region and the substrate is smaller than the spacing between the field limiting ring and the substrate. Preferably, the side surface of the additional doped region facing the substrate is flush with the side surface of the main junction facing the substrate; or, the spacing between the additional doped region and the substrate is less than the spacing between the main junction and the substrate.