Super block pool extension for enhanced manufacturing

Abstract

The invention relates to super block pool extension for enhanced manufacturing. Techniques are presented for partitions for borrowing portions of other partitions, for example during a manufacturing phase. In some examples, different partitions (e.g., enhanced memory partitions and normal partitions) may be configured to original sizes. A portion of the enhanced memory partition may be borrowed by a normal partition for use during a fabrication phase. The borrowed portion may be returned to the enhanced memory partition after the manufacturing stage for later use by the enhanced memory partition. By borrowing a portion of the enhanced memory partition, a larger portion of the normal partition may be used to store information during the manufacturing stage, thereby shortening program time.

Description

[0001] Cross reference

[0002] The present patent application claims priority to U.S. Patent Application No. 19 / 205,803, titled “SUPERBLOCK POOL EXPANSION FOR ENHANCED MANUFACTURING,” filed May 12, 2025, to Cariello et al., and U.S. Provisional Patent Application No. 63 / 649,898, titled “SUPERBLOCK POOL EXPANSION FOR ENHANCED MANUFACTURING,” filed May 20, 2024, to Cariello et al., each of which is assigned to the assignee hereof, and each of which is expressly incorporated herein in its entirety by this reference thereto. TECHNICAL FIELD

[0003] The technical field relates to superblock pool expansion for enhanced manufacturing. BACKGROUND

[0004] Memory devices are widely used in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and other to store information. Information is stored by programming memory cells within the memory devices into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, the memory devices can read (e.g., sense, detect, retrieve, determine) the state from the memory cells. To store information, the memory devices can write (e.g., program, set, assign) a state to the memory cells.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic DRAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, chalcogenide memory technology, or non-volatile (NOR) and negative- and (NAND) memory devices, among others. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a prolonged period of time even in the absence of an external power source. When disconnected from an external power source, memory cells configured in a volatile configuration can lose stored state. SUMMARY

[0006] A memory system is described. The memory system can include one or more memories that store processor-executable code and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the memory system to configure the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters, assign a first portion of the second partition to the first partition after configuring the first partition and the second partition, store data to the first partition after assigning the first portion to the first partition and as part of a manufacturing process, and assign the first portion to the second partition after an event experienced during the manufacturing process.

[0007] A non-transitory computer-readable medium storing code is described. The non-transitory computer-readable medium can include the code comprising executable by one or more processors to configure the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters, assign a first portion of the second partition to the first partition after configuring the first partition and the second partition, store data to the first partition after assigning the first portion to the first partition and as part of a manufacturing process, and assign the first portion to the second partition after an event experienced during the manufacturing process.

[0008] A method at a memory system is described. The method can include configuring the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters; after configuring the first partition and the second partition, assigning a first portion of the second partition to the first partition; after assigning the first portion to the first partition and as part of a manufacturing process, storing data to the first partition; and after an event of the manufacturing process, assigning the first portion to the second partition. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system supporting superblock pool extension for enhanced manufacturing is shown in accordance with the examples disclosed herein.

[0010] Figure 2 An example of a memory system supporting superblock pool extension for enhanced manufacturing is shown in accordance with the examples disclosed herein.

[0011] Figure 3 An example of a memory system supporting superblock pool extension for enhanced manufacturing is shown in accordance with the examples disclosed herein.

[0012] Figure 4 A block diagram of a memory system supporting superblock pool extension for enhanced manufacturing is shown in accordance with the examples disclosed herein.

[0013] Figure 5 A flow diagram illustrating a method or methods supporting superblock pool extension for enhanced manufacturing is shown in accordance with the examples disclosed herein. DETAILED DESCRIPTION

[0014] Memory arrays are often divided into a number of partitions, such as normal partitions and enhanced memory (EM) partitions. Some normal partitions can be used to store information. In some cases, data can be temporarily stored in single-level cells, referred to as write boosters, during a manufacturing process (e.g., to make it more resistant to errors and speed up the process), and later transferred to triple-level cells after the manufacturing process is complete. In some applications, the size of the EM partitions can be large, such that the size of the normal partitions is reduced. The normal partitions can be used to store information during the manufacturing process. Preferably, this information is stored in single-level cells. However, if the normal partitions are too small, the manufacturing process can be adjusted to store the information in triple-level cells (or some other higher density storage) to account for the reduced size. This can result in longer programming times and / or more data errors during the manufacturing phase.

[0015] To allow for more single-level cells during the manufacturing phase, the EM partition can initially be configured to be smaller, and then reconfigured to be larger after the manufacturing phase. While the total partition size can be reconfigured after the manufacturing phase, this can cause other problems, such as data written in memory from one partition being reconfigured to another partition not being guaranteed to be preserved, and can be lost, for example, in FTL structure reset.

[0016] Techniques are presented for partitioning to borrow portions of other partitions, for example, during the manufacturing phase. In some examples, both the EM partition and the normal partition can be configured to the desired size for use. A portion of the EM partition can be "borrowed" by the normal partition for use during the manufacturing phase. The borrowed portion can be returned to the EM partition for use by the EM partition after the manufacturing phase.

[0017] By borrowing a portion of the EM partition, the total size of the normal partition for storing information during the manufacturing phase can be increased. With the larger size, more information can be configured to be stored in single-level cells, shortening programming time and reducing errors. Furthermore, once the partition size is configured, it cannot be changed during or after the manufacturing phase, alleviating associated problems. Also, using this borrowing technique, data loss can be reduced or avoided by using garbage collection on the borrowed portion of the partition after the manufacturing phase. For example, if garbage collection is performed to reclaim a portion of the EM partition that was borrowed, the garbage collection can be configured to transfer the information to the normal partition.

[0018] In addition to applicability in memory systems as described herein, techniques for borrowing portions of a partition during manufacturing of a memory device can generally be implemented to improve sustainability of various electronic devices and systems. As use of electronic devices has become more widespread, the amount of energy usage and harmful emissions associated with electronic device production and device operation has increased. Furthermore, the amount of waste associated with disposal of electronic devices (e.g., e-waste) can also contribute to environmental problems. Implementing the techniques described herein can improve the impacts associated with electronic devices by allowing a larger portion of a normal partition to be used to store information during the manufacturing phase, which can improve programming time and speed up manufacturing of memory devices, among other benefits.

[0019] Features of the disclosure are illustrated and described in the context of systems, devices, and circuits. Features of the disclosure are further illustrated and described in the context of block diagrams and flowcharts.

[0020] Figure 1An example of a system 100 supporting superblock pool extension for enhanced manufacturing is shown in accordance with the examples disclosed herein. The system 100 includes a host system 105 coupled with a memory system 110. The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle, an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0021] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other devices.

[0022] The system 100 can include a host system 105, which can be coupled with a memory system 110. In some examples, this coupling can include an interface with a host system controller 106, which can be an example of a controller or control component configured to cause the host system 105 to perform various operations in accordance with examples as described herein. The host system 105 can include one or more devices, and in some cases, can include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 can include an application configured for communication with the memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 can use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in the middle, but the host system 105 can be coupled with any number of memory systems 110.

[0023] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR- supported DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in, or otherwise supported between, the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0024] The memory system 110 can include a memory system controller 115 and one or more memory devices 130. The memory devices 130 can include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices 130-a and 130-b are shown in the example of FIG. 1, the memory system 110 can include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 can include the same or different types of memory cells. Figure 1

[0025] ​The memory system controller 115 can be coupled with and in communication with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations in accordance with examples as described herein. The memory system controller 115 can also be coupled with and in communication with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130, among other such operations, which can be collectively referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with the one or more memory devices 130 to perform such commands (e.g., at memory arrays within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effectuate desired accesses to the memory devices 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and the one or more memory devices 130 (e.g., in response to or otherwise in association with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory devices 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130. In some examples, the memory system controller 115 can be configured to perform or manage operations associated with partitioning of memory and borrowing of portions of a partition by other partitions, as discussed herein.

[0027] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry having specialized (e.g., hard-coded) logic for performing the operations attributed herein to the memory system controller 115. The memory system controller 115 can be or include a microcontroller, specialized logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, for example, in connection with the functions attributed herein to the memory system controller 115.

[0029] The memory devices 130 can include one or more arrays of non-volatile memory cells. For example, the memory devices 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), resistive memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally, or alternatively, the memory devices 130 can include one or more arrays of volatile memory cells. For example, the memory devices 130 can include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, the memory devices 130 can include (e.g., on the same die, within the same package) a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 can operate in conjunction with the memory system controller 115, or can perform one or more functions attributed herein to the memory system controller 115. For example, as explained in Figure 1 The memory device 130-a can include a local controller 135-a, and the memory device 130-b can include a local controller 135-b, as explained in

[0031] In some cases, the memory device 130 can be or include a NAND device (e.g., a NAND flash device). The memory device 130 can be or include a die 160 (e.g., a memory die). For example, in some cases, the memory device 130 can be a package that includes one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) that is cut from a wafer. Each die 160 can include one or more planes 165, and each plane 165 can include a respective set of blocks 170, where each block 170 can include a respective set of pages 175, and each page 175 can include a set of memory cells.

[0032] In some cases, the NAND memory device 130 can include memory cells configured to each store one bit of information, which can be referred to as single-level cells (SLCs). Additionally, or alternatively, the NAND memory device 130 can include memory cells configured to each store multiple bits of information, which can be referred to as multi-level cells (MLCs) if the memory cells are configured to each store two bits of information, as triple-level cells (TLCs) if the memory cells are configured to each store three bits of information, as quad-level cells (QLCs) if the memory cells are configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but can involve narrower read or write margins or greater complexity of supporting circuitry in some cases. In some examples, the NAND memory device 130 can include memory cells that are configurable between two or more levels (e.g., between two or more of SLC, MLC, TLC, QLC, etc.).

[0033] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, concurrent operations can be performed on different planes 165. For example, as long as different blocks 170 are in different planes 165, concurrent operations can be performed on memory cells within different blocks 170. In some cases, an individual block 170 can be referred to as a physical block. A virtual block 180 (which can also be referred to as a super block) can refer to a group of blocks 170 within which concurrent operations can occur. For example, concurrent operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d located within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d can collectively be referred to as a virtual block 180. In some cases, a virtual block can include blocks 170 from different memory devices 130 (e.g., include blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block can have the same block address within their respective planes 165 (e.g., block 170-a can be “block 0” of plane 165-a, block 170-b can be “block 0” of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 can be subject to one or more limitations, such as performing concurrent operations on memory cells within different pages 175 that have the same page address in their respective planes 165 (e.g., in relation to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., be coupled to) and memory cells in the same string can share a common digit line (which can alternatively be referred to as a bit line) (e.g., be coupled to).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page granularity level or a portion thereof), but erased at a second granularity level (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., group of memory cells) that can be programmed or read independently (e.g., concurrently as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., group of memory cells) that can be erased independently (e.g., concurrently as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be overwritten with new data. Thus, for example, in some cases, a used page 175 cannot be updated until the entire block 170 that includes the page 175 is erased.

[0036] In some cases, the memory system controller 115 or local controller 135 can perform operations on the memory devices 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or others, or any combination thereof. For example, within the memory device 130, a block 170 can have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in the block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called “garbage collection” can be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Garbage collection can refer to a set of media management operations including, for example: selecting a block 170 containing valid and invalid data; selecting pages 175 in the block containing valid data; copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected pages 175 as invalid; and erasing the selected block 170. Thus, the number of blocks 170 that have been erased can increase so that more blocks 170 are available for storing subsequent data (e.g., data received from the host system 105 subsequently). In some examples, garbage collection can be performed on a portion of a partition that is borrowed by another partition to move valid data to its original partition and release the block to its original partition, as discussed herein.

[0037] Techniques are presented for a partition to borrow portions of other partitions for use, for example, during a manufacturing phase. In some examples, both EM partitions and normal partitions can be configured to a desired size for use. A portion of an EM partition can be “borrowed” by a normal partition for use during a manufacturing phase. The borrowed portion can be returned to the EM partition after the manufacturing phase for use by the EM partition thereafter. By borrowing a portion of an EM partition, the total size of a normal partition for storing information during a manufacturing phase can be increased. With a larger size, more information can be configured to be stored in single level cells, shortening programming time and reducing errors.

[0038] The system 100 can include any number of non-transitory computer- readable media that support superblock pool extensions for enhanced manufacturing. For example, the host system 105 (e.g., the host system controller 106), the memory system 110 (e.g., the memory system controller 115), or the memory device 130 (e.g., the local controller 135) can include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., by the host system controller 106), the memory system 110 (e.g., by the memory system controller 115), or the memory device 130 (e.g., by the local controller 135), can cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions as described herein.

[0039] Figure 2 An example of a memory system 200 that supports superblock pool extensions for enhanced manufacturing in accordance with the examples disclosed herein is shown. The memory system 200 can be an example of or aspect of the memory system 110 described with reference to Figure 1 The memory system 200 can include one or more memory cell arrays (e.g., the memory array 205) divided into blocks and / or superblocks 210. In some cases, a superblock can be referred to as a virtual block, and vice versa. The superblocks 210 can be examples of the virtual blocks 180 described with reference to Figure 1

[0040] The memory array 205 can include one or more partitions (e.g., a first partition 220 and a second partition 225), each partition including a different portion of memory. The partitions can be separate entities or portions of the same memory. Each partition can include memory cells in one or more zones (e.g., one or more blocks 170, pages 175, or other zones of memory cells of the memory system 200), each zone configured to store data. For example, a manufacturer can configure a product (e.g., a UFS) with a first partition 220 and a second partition 225 each including different zones of memory (e.g., superblocks 210).

[0041] ​In some examples, the partitions can include different sets of operating parameters. In some examples, the partitions can have separate pools of addressing space for different usage modes. In some examples, at least one of the partitions can include some memory cells configured as SLC and other memory cells configured as multi-level cells. For example, in the depicted example, first partition 220 can include super blocks 1-3 with memory configured as SLC and super blocks 4-6 with memory configured as TLC; and second partition 225 can include super blocks 7-9 with memory configured as SLC. In some examples, the first partition can be configured to store information sequentially, and the second partition can be configured for random access. In some examples, one partition can be a secure partition, while another partition can be a non-secure partition. Other ways of dividing the partitions are also possible.

[0042] For purposes of this application, the partitions can be used in a first operating state and a second operating state. During the first operating state, the partitions can be used in a conventional manner without any partition borrowing any portion of another partition. Thus, the first operating state can be referred to herein as a "non-borrowing state." In the non-borrowing state, one of the partitions (e.g., first partition 220) can be used, for example, to store applications and their static data, such as navigation applications and corresponding maps, etc., and another partition (e.g., second partition 225) can be used, for example, to write temporary data, such as logs, black box data, or the like.

[0043] In some examples, second memory partition 225 can use single-level cells (e.g., SLC) to achieve faster access and better reliability. In some examples, first memory partition 220 can use triple-level cells (e.g., TLC) to store information more densely in the same memory space. A number of logical addresses can be associated with first partition 220 for reading and writing data. In some examples, a portion or all of the memory cells of a partition can be configurable between different cell types (e.g., between SLC and TLC). In some examples, one or more memory cells of a partition can be configured as SLC and used as a write accelerator to buffer data for writing to the TLC memory cells of the partition. Data buffering can allow for faster overall writing to the TLC memory cells, for example, during data bursts. Reads from logical addresses can cause data to be retrieved from first partition 220.

[0044] During the second operational state, a portion of a partition can be selectively used (borrowed) by another partition. Thus, the second operational state can be referred to herein as a "borrow state." The portion of a partition can include any subset of the memory associated with the partition. In some examples, the portion can comprise one or more superblocks 210. In the borrow state, the partition from which a portion is borrowed can be referred to herein as a "lender partition," and the partition that borrows the portion can be referred to herein as a "borrower partition." For example, if a portion of the second partition 225 is borrowed by the first partition 220, the second partition 225 can be referred to as the lender partition 225, and the first partition 220 can be referred to as the borrower partition 220.

[0045] The selective borrowing can be accomplished by assigning a portion of a lender partition to a borrower partition. For example, the borrowed portion 260 (e.g., superblocks 7 and 8) of the lender partition 225 can be assigned (e.g., by a controller) to the borrower partition 220 for use by the borrower partition during the borrow state. For example, the borrower partition 220 can use superblocks 7 and 8 of the second partition 225 during the borrow state. In some examples, during the borrow state, the memory cells of the borrowed portion 260 can be configured as SLC and used as a write accelerator. This can be beneficial in setting up the memory system while in the borrow state (e.g., as part of a manufacturing process).

[0046] The borrowed portion 260 can be returned (e.g., reassigned) to the lender partition at the end of the borrow state, e.g., after experiencing an event (e.g., based on a completion of a manufacturing process or after a completion of a manufacturing process). In some examples, the event can include a passage of a period of time since a start of a manufacturing process. In some examples, the event can include a start of one or more processes or a completion of one or more processes, e.g., associated with a manufacturing process. For example, superblocks 7 and 8 can be returned to the second partition 225 when a thermal event occurs (e.g., heat is applied to the memory system to solder components together).

[0047] In some examples, a portion of the borrowed partition 220 (e.g., the auxiliary portion 265) can be used in conjunction with the borrowed portion 260 of the lending partition 225 during the borrowed state. The auxiliary portion 265 can include a subset of the memory associated with the borrowed partition 220. In some examples, the auxiliary portion 265 can comprise one or more super blocks (e.g., super block 6). In some examples, the memory cells of the auxiliary portion 265 can be configured to a different cell type in the borrowed state than in the non-borrowed state. For example, the memory cells of the auxiliary portion 265 can be configured (e.g., by the controller) to TLC in the non-borrowed state and to SLC in the borrowed state. Using the memory cells as SLC during the borrowed state can allow data to be moved in and out of those memory cells faster during the borrowed state, while allowing the memory cells to retain more information during the non-borrowed state. In some examples, the memory cells of the auxiliary portion 265 can be used as write accelerators during the borrowed state.

[0048] Another advantage can be that, in some cases, the amount of addressable memory used by the borrowed partition 220 during the borrowed state and during the non-borrowed state can be the same. Memory configured as a TLC memory cell can store three bits per memory cell, while memory configured as an SLC memory cell can store 1 bit per memory cell. Thus, a TLC memory cell can store three times as much data as an SLC memory cell. Thus, three SLCs can provide the same addressable memory as one TLC. Some examples of the present disclosure take advantage of this difference.

[0049] The memory system can use TLC addressing techniques to address a series of SLC memory cells in the borrowed state. This can enable the addressing scheme to be the same for the borrowed partition 220, and the borrowed partition 220 can take advantage of the speed and reliability of SLC memory cells. For example, during the non-borrowed state, the borrowed partition 220 can use the helper portion 265 (e.g., super block 6) configured as TLC memory. Then, during the borrowed state, the borrowed partition 220 can continue to use the helper portion 265 (e.g., super block 6), but it is configured as SLC. Also, during the borrowed state, the borrowed partition 220 can use the borrowed portion 260 (e.g., super blocks 7 and 8 from the borrowed partition 225) from the lending partition 225, which is configured as SLC. That is, during the borrowed state, the borrowed partition can use three super blocks configured as SLC (e.g., super blocks 6, 7, and 8) instead of one super block configured as TLC (e.g., super block 6). Thus, the borrowed partition 220 can have the same total addressable memory in the borrowed state as in the non-borrowed state. In some examples, during the borrowed state, the helper portion 265 can be linked with the borrowed portion 260. For example, super block 6 can be linked with super blocks 7 and 8 to form a super block of three single-level cells. In some examples, the linked super blocks can be assigned to the data structures of the borrowed partition that are configured to track a single super block of three-level cells. By doing so, storing data to the borrowed portion can be based on assigning the linked super blocks to the data structures.

[0050] To replace a single TLC super block with three SLC super blocks in the borrowed state, the zones associated with the borrowed portion 260 can be more than twice the zones associated with the helper portion 265. In some examples, the number of blocks or super blocks in the borrowed portion 260 of the lending partition 225 can be twice the number of blocks or super blocks in the helper portion 265 of the borrowed partition 220. For example, when the number of super blocks in the helper portion 265 is 1, 2, 3, 4, and 5, respectively, the number of super blocks in the borrowed portion 260 can be 2, 4, 6, 8, and 10.

[0051] To help with selective borrowing, one or more flags can be used. In some examples, a first flag 230 can reflect which state the partition is in. When set, the first flag can reflect that the partition is in a borrowed state, and when cleared, the first flag can reflect that the partition is in a non-borrowed state. For example, when set (e.g., by a controller), the first flag 230 can indicate that the borrowed portion 260 of the lend-out partition 225 is assigned to the lend-in partition 220 (i.e., is borrowed), and can indicate that the memory cell type of the helper portion 265 of the lend-in partition 220 is configured to be a second cell type (e.g., SLC). Conversely, when cleared (e.g., by a controller), the first flag 230 can indicate that the borrowed portion 260 of the lend-out partition 225 is assigned to the lend-out partition 225 (i.e., is no longer borrowed), and can indicate that the memory cell type of the helper portion 265 of the lend-in partition 220 is configured to be a first cell type (e.g., TLC).

[0052] In some examples, a set of flags can be used to reflect which regions of the lend-out and lend-in partitions constitute the borrowed portion 260 and the helper portion 265 associated with the borrowed state. For example, each of a set of borrow flags 240 can reflect a respective region (e.g., superblock) of the lend-in partition 220 or the lend-out partition 225. A borrow flag 240 that is set can reflect a region of the lend-out and lend-in partitions that is used as the borrowed portion or the helper portion. For example, in the example shown in Figure 2

[0053] In some examples, the borrow flags 240 can be used in conjunction with the first flag 230. In that case, the borrow flags 240 can indicate which regions of the partition are to be used as the borrowed portion or the helper portion during both the borrowed state and the non-borrowed state. As such, when used in conjunction with the first flag 230, the borrow flags 240 corresponding to the borrowed portion or the helper portion can remain set during both the borrowed state and the non-borrowed state.

[0054] In other examples, the borrow flags 240 can be used in place of the first flag 230. In that case, the borrow flags 240 can be cleared in the non-borrowed state (when no borrowing is occurring). That is, when no borrowing is occurring, all of the borrow flags 240 can be cleared.

[0055] ​In some examples, a set of flags can be used to reflect which regions associated with the borrowed and helper portions contain valid data associated with the borrowed state. For example, each of a set of valid data flags 250 can reflect a respective region (e.g., superblock) of the borrowed portion or helper portion on which valid data associated with the borrowed state is stored. A set valid data flag 250 can reflect a region of the borrowed portion and helper portion on which valid data is present. For example, in the example shown in Figure 2 the valid data flags 250 corresponding to superblocks 6 and 7 are set, indicating that superblocks 6 and 7 have valid data associated with the borrowed state present thereon. In some examples, a valid data flag can correspond to a valid data counter that indicates a number of valid units (e.g., associated with an LBA). For example, a value of zero can indicate no valid data, and other values can indicate a number of blocks containing valid data.

[0056] When valid data is moved to another portion of the borrowed partition 220 (e.g., during a garbage collection activity), the valid data flags can be cleared (e.g., by the controller). Because such data movement can not occur until the borrowed portion 260 is reassigned back to the original (lent) partition 225, valid data can remain in the borrowed portion and helper portion after the manufacturing procedure has completed. To reflect this, the valid data flags 250 can remain set. Once valid data is moved to the borrowed partition 220, the respective valid data flag 250 can be cleared (e.g., by the controller), and the portion can be used by its original partition. For the helper portion 265, reconfiguration of the memory cells of the helper portion (e.g., from SLC to TLC) can not be performed until the respective valid data flag is cleared. Other flags can also be used.

[0057] In some examples, the borrowed flags 240 and / or the valid data flags 250 can be stored in one or more registers. For example, bits of a borrowed block register 245 can represent respective borrowed flags 240, and bits of a valid data register 255 can represent respective valid data flags 250. A first logic value (e.g., a logic "1" or "0") in a bit can indicate that the respective flag is set, and a second logic value (e.g., a logic value "0" or "1") in a bit can indicate that the respective flag is clear. For example, in the example shown in Figure 2 the logic value "1" indicates a set value, and the bits of the borrowed block register 245 match respective borrowed flags 240, and the bits of the valid data register 255 match respective valid data flags 250.

[0058] Reference will now be made to Figure 2Examples of methods of operation are given. During manufacturing, the memory system 200 can be configured to include multiple partitions having different regions of memory. For example, the memory array can be configured (e.g., by the controller) to include a normal partition 220 having a first set of super blocks (e.g., super blocks 1-6) and an enhanced memory (EM) partition 225 having a second set of super blocks (e.g., super blocks 7-9). The first set of super blocks can include a first subset (e.g., super blocks 1-3) configured as SLC and a second subset (e.g., super blocks 4-6) configured as TLC. The second set of super blocks (e.g., super blocks 7-9) can be configured as SLC. In some examples, the partitions can include different sets of operating parameters.

[0059] After the memory system is configured as the normal partition 220 and the EM partition 225, a borrowed state can be initialized for borrowing a portion 260 of the EM partition 225 for use by the normal partition 220. The borrowed state can be initialized, for example, as part of the manufacturing process. By borrowing a portion of the EM partition, a larger portion of the normal partition can be used to store information during the manufacturing phase, thereby shortening the programming time. For example, a first flag 230 can be set (e.g., by the controller) to indicate a borrowed state of operation for use during the setting up of the system 200 by the manufacturer. During the borrowed state, the borrowed portion 260 of the lending partition 225 can be assigned to the borrowing partition 220, and the memory cells of the helper portion 265 of the borrowing partition can be reconfigured. In the depicted example, the normal partition 220 and the EM partition 225 can correspond to the borrowing partition and the lending partition, respectively.

[0060] The borrowed portion 260 can be determined by a set of borrowed block flags 240, which can be set (e.g., by the controller) before or after the first flag 230 is set. For example, in the depicted example, super blocks 7 and 8 of the EM partition 225 can correspond to the borrowed portion 260, and super block 6 of the normal partition 220 can correspond to the helper portion 265, as reflected by the set of borrowed block flags 240. Thus, during the borrowed state, super blocks 7 and 8 can be assigned to the normal partition 220, and the memory cells of super block 6 can be reconfigured to SLC.

[0061] When in the borrowed state, the borrowed portion 260 can be considered to belong to the borrowed partition. For example, during the manufacturing process, super blocks 7 and 8 can be used by the normal partition 220 as if they had been configured to originally belong to the normal partition 220. That is, data can be stored and read from super blocks 7 and 8 during memory access operations (e.g., read, write, etc.) associated with the normal partition 220. In some examples, during the borrowed state, the memory cells of the borrowed portion 260 can be configured as SLC and used as write accelerators. Using more write accelerators can reduce the amount of time taken to complete operations (e.g., storing information during the manufacturing phase). Alternatively, to keep the number of super blocks associated with the borrowed partition 220 constant, and to avoid reshaping the corresponding data structures, the borrowed super blocks can be associated with "auxiliary super blocks" 265.

[0062] The memory system can remain in the borrowed state until an event occurs to trigger its end, which can be associated with, for example, the end of the manufacturing process. In some examples, the event can include: i) a threshold amount of time elapsing, for example, from the beginning of the borrowed state, ii) the end of one or more processes, iii) the beginning of one or more processes, or a combination thereof. Other change events can also be used. In one example, the change event can be a thermal event, such as applying heat to the memory system to solder components together.

[0063] In response to the event, the borrowed state can end and a non-borrowed state can be initiated. After the borrowed state has ended, the borrowed portion 260 can be returned (assigned) back to the lending partition (e.g., by the controller), and the first flag 230 can be cleared. For example, after experiencing a thermal event, super blocks 7 and 8 can be reassigned from the normal partition 220 back to the EM partition 225, and the first flag 230 can be cleared (e.g., by the controller). As discussed herein, one or more regions of the borrowed portion 260 and / or the auxiliary portion 265 can still contain valid data associated with the borrowed state before the borrowed state ends, as reflected by the valid data flag 250.

[0064] A garbage collection operation can be performed on one or more of these zones to move valid data to other zones of the borrowed (e.g., normal) partition before clearing the borrowed state. For example, a garbage collection operation can be performed to move valid data from a zone of superblock 6, 7, or 8 to a zone of any of superblocks 1-5. Once all valid data of a borrowed zone of borrowed portion 260 is moved to another zone of borrowed (e.g., normal) partition 220, the lending partition 225 (e.g., EM partition) can use the borrowed zone normally. Once valid data of a zone of auxiliary portion 265 is moved to another zone of borrowed (normal) partition 220, the memory cells of the zone can be reconfigured (e.g., by the controller) back to their original memory cell type (e.g., from SLC to TLC).

[0065] During the non-borrowed state, each partition can be used by the controller separately from the other partitions as known in the art. For example, in a normal operating state, superblocks 1-6 of normal partition 220 can be used, e.g., to store application programs and their static data, e.g., navigation application programs and corresponding maps, etc., and superblocks 7-9 of EM partition 225 can be used, e.g., to write temporary data, e.g., logs, black box data, or the like. Also during the non-borrowed state, garbage collection operations can be performed on each partition in a normal manner. For example, valid data can be moved from zones of superblocks 1-6 to zones of superblocks 1-6 and valid data can be moved from zones of superblocks 7-9 to zones of superblocks 7-9. In some examples, during the non-borrowed state, valid data flags 250 can be used to identify zones (e.g., superblocks) containing valid data to be moved.

[0066] Generally, during the non-borrowed and borrowed states, each partition can be used separately from the other partitions, except that the borrowed portion of the lending partition can be considered to belong to the borrowed partition during the borrowed state.

[0067] Figure 3 An example of a memory system 300 that supports superblock pool extension for enhanced manufacturing is shown in accordance with the examples disclosed herein. Memory system 300 can be an example of memory system 110 or 200 or aspects thereof described with reference to Figure 1 and 2 described. Memory system 300 can include one or more arrays of memory cells that are divided into blocks 315 and / or superblocks 320. Blocks 315 and superblocks 320 can be examples of blocks 170 and virtual blocks 180 described with reference to Figure 1 described.

[0068] In some examples, a subset of the regions of memory can be reserved and used as a replacement for regions that can experience errors. The first table 310 represents physical blocks associated with two dies. Each cell of the table represents a physical block 315 of a plane of a die. All of the blocks in a row of the table can form a superblock 320. For example, the system represented by the first table 310 can have 10 superblocks 320 labeled 0 through 9. The second table 325 shows a mapping of the physical blocks 315 that can be used (e.g., instead of the physical block that is addressed) when a physical block is addressed. For example, when a physical block associated with superblock 0 and plane P0 of die 0 is addressed, the second table 325 indicates that a physical block associated with superblock 0 and plane P0 of die 0 can be used. As reflected by the second table 325, most (or all) of the blocks can be mapped to the same physical block that is addressed.

[0069] In some examples, the addressable amount of memory can be less than the total amount of memory in the system, such that some of the memory can be used as a replacement for bad memory. For example, as shown in the second table 325, the blocks associated with physical superblocks 0 through 8 can generally map to blocks associated with physical superblocks 0 through 5 and 7 through 9, respectively, such that one physical superblock (e.g., superblock 6) can be unmapped. By doing so, the physical blocks associated with superblock 6 can be used in place of bad blocks.

[0070] For example, as shown in the first table 310, several physical blocks (denoted as “BB”) can be exhibiting errors and thus considered bad blocks. To mitigate faulty memory, those physical blocks can be remapped to blocks in unused superblock 6, as reflected in the second table 325. If any of the blocks in superblock 6 are considered bad blocks (as in the first table 310), that block can not be remapped because it is already in superblock 6 and thus not used.

[0071] Figure 4 A block diagram 400 showing a memory system 420 that supports superblock pool extension for enhanced manufacturing in accordance with examples as disclosed herein is shown. The memory system 420 can be an example of aspects of the memory system described. The memory system 420, or various components thereof, can be examples of means for performing various aspects of superblock pool extension for enhanced manufacturing as described herein. For example, the memory system 420 can include a configuration manager 425, an assigner 430, a data manager 435, a flag manager 440, a scrap collection manager 445, a linker 450, or any combination thereof. Each of these components, or components of subcomponents thereof (e.g., one or more processors, one or more memories), can communicate, directly or indirectly, with one another (e.g., via one or more buses). Figures 1 to 3

[0072] ​The configuration manager 425 can be configured as or otherwise support means for configuring the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters. The assigner 430 can be configured as or otherwise support means for assigning a first portion of the second partition to the first partition after configuring the first partition and the second partition. The data manager 435 can be configured as or otherwise support means for storing data to the first partition after assigning the first portion to the first partition and as part of a manufacturing process. In some examples, the assigner 430 can be configured as or otherwise support means for assigning the first portion to the second partition after an event that experiences the manufacturing process.

[0073] In some examples, the first partition and the second partition have separate block pools for different usage modes.

[0074] In some examples, the first partition includes blocks having memory cells configured as single-level cells and blocks having memory cells configured as triple-level cells. In some examples, the second partition includes blocks having memory cells configured as single-level cells.

[0075] In some examples, the event includes an elapse of a period of time, a start of one or more processes, a completion of one or more processes, or a combination thereof.

[0076] In some examples, the flag manager 440 can be configured as or otherwise support means for setting a flag indicating that the first portion of the second partition is assigned to the first partition after assigning the first portion to the first partition, where storing the data is based at least in part on setting the flag.

[0077] In some examples, the first portion includes a plurality of superblocks and the flag includes a plurality of flags, where each flag of the plurality of flags is associated with a respective superblock of the plurality of superblocks.

[0078] In some examples, the flag manager 440 can be configured as or otherwise support means for clearing the flag corresponding to the first portion after assigning the first portion to the first partition.

[0079] In some examples, the garbage collection manager 445 can be configured as or otherwise support means for performing a garbage collection operation on the first portion after assigning the first portion back to the second partition. In some examples, the data manager 435 can be configured as or otherwise support means for transferring valid data stored in the first portion to the first partition based at least in part on performing the garbage collection operation.

[0080] In some examples, the configuration manager 425 can be configured as or otherwise support means for configuring memory cells of the first portion of the second partition as single-level cells based at least in part on assigning the first portion to the first partition. In some examples, the configuration manager 425 can be configured as or otherwise support means for configuring memory cells of a second portion of the first partition as single-level cells based at least in part on assigning the first portion to the first partition.

[0081] In some examples, the linker 450 can be configured as or otherwise support means for linking the first portion and the second portion into super-blocks to form three super-blocks of single-level cells based at least in part on configuring the first portion. The device can configure a memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters. The device can assign a first portion of the second partition to the first partition after configuring the first partition and the second partition. The device can store data to the first partition after assigning the first portion to the first partition and as part of a manufacturing process. The device can assign the first portion to the second partition after experiencing an event of the manufacturing process. In some examples, the assigner 430 can be configured as or otherwise support means for assigning the linked super-blocks to a data structure configured to track a single super-block of three-level cells for the first partition, where storing data to the first portion is based at least in part on assigning the linked super-blocks to the data structure.

[0082] In some examples, the described functionality of the memory system 420, or various components thereof, can be supported by, or can involve, at least a portion of at least one processor, where such at least one processor can include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination thereof). In some examples, the described functionality of the memory system 420, or various components thereof, can be implemented, at least in part, by instructions executable by such at least one processor (e.g., stored in memory, non-transitory computer-readable media).

[0083] Figure 5 A flow diagram illustrating a method 500 that supports super-block pool extension for enhanced manufacturing in accordance with examples as disclosed herein is shown. The operations of method 500 can be implemented by a memory system or its components as described herein. For example, the operations of method 500 can be performed by a memory system as described with reference to FIGS. 1-4. Figures 1 to 4 In some examples, a memory system can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the described functions using special-purpose hardware.

[0084] At 505, the method can include configuring the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters. In some examples, aspects of the operation 505 can be performed by a configuration manager 425 as described with reference to FIG. 4. Figure 4

[0085] At 510, the method can include assigning a first portion of the second partition to the first partition after configuring the first partition and the second partition. In some examples, aspects of the operation 510 can be performed by an assigner 430 as described with reference to FIG. 4. Figure 4

[0086] At 515, the method can include storing data to the first partition after assigning the first portion to the first partition and as part of a manufacturing process. In some examples, aspects of the operation 515 can be performed by a data manager 435 as described with reference to FIG. 4. Figure 4

[0087] At 520, the method can include assigning the first portion to the second partition after an event of the manufacturing process. In some examples, aspects of the operation 520 can be performed by an assigner 430 as described with reference to FIG. 4. Figure 4

[0088] In some examples, an apparatus as described herein can perform one or more methods, such as method 500. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing aspects of the disclosure, or any combination thereof:

[0089] Aspect 1 : A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions for, or any combination thereof: configuring the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters; after configuring the first partition and the second partition, assigning a first portion of the second partition to the first partition; after assigning the first portion to the first partition and as part of a manufacturing process, storing data to the first partition; and after an event of the manufacturing process, assigning the first portion to the second partition.

[0090] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, wherein the first partition and the second partition have separate block pools for different usage modes.

[0091] ​​​​Aspect 3: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-2, wherein the first partition includes a block having memory cells configured as single-level cells and a block having memory cells configured as triple-level cells, and the second partition includes a block having memory cells configured as single-level cells.

[0092] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-3, wherein the event includes a passage of time, a start of one or more processes, a completion of one or more processes, or a combination thereof.

[0093] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for setting a flag indicating that the first portion of the second partition is assigned to the first partition after assigning the first portion to the first partition, wherein storing the data is based at least in part on setting the flag.

[0094] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of aspect 5, wherein the first portion includes a plurality of superblocks, and the flag includes a plurality of flags, wherein each flag of the plurality of flags is associated with a respective superblock of the plurality of superblocks.

[0095] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 5-6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for clearing the flag corresponding to the first portion after assigning the first portion to the first partition.

[0096] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1-7, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for performing a garbage collection operation on the first portion after assigning the first portion back to the second partition, and transferring valid data stored in the first portion to the first partition based at least in part on performing the garbage collection operation.

[0097] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for configuring memory cells of the first portion of the second partition as single-level cells based at least in part on assigning the first portion to the first partition, and configuring memory cells of a second portion of the first partition as single-level cells based at least in part on assigning the first portion to the first partition.

[0098] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of Aspect 9, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof, for linking the first portion and the second portion to form three superblocks of single-level cells based at least in part on configuring the first portion and the second portion, and assigning the linked superblocks to a data structure configured to track a single superblock of three-level cells for the first partition, wherein storing the data to the first portion is based at least in part on assigning the linked superblocks to the data structure.

[0099] It should be noted that the described techniques include possible implementation manners, and that the operations and steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods can be combined.

[0100] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or symbols, which can be referenced throughout the above description, can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; this is for convenience only and should not be construed as limiting. For example, a signal can be represented by a bus or a wire, which can comprise any combination of wires, conductive lines, and / or other transmission mediums.

[0101] The terms“electronic communication,”“electrically conductive contact,”“connected,” and“coupled” can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or electrically conductive contact or connected or coupled with each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or electrically conductive contact or connected or coupled with each other) can be an open or closed circuit based on the operation of the device that includes the connected components at any given time. The conductive path between connected components can be a direct conductive path between the components or the conductive path between connected components can be an indirect conductive path that can include intervening components (such as switches, transistors, or other components). In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intervening components (such as switches or transistors).

[0102] The term "coupled" (e.g., "electrically coupled") can refer to a condition of components moving from an open relationship between the components, where a signal is currently not able to pass between the components through a conductive path, to a closed relationship between the components, where a signal is able to pass between the components through a conductive path. If a component (e.g., a controller) couples other components together, the component initiates a change that allows a signal to flow between the other components through a conductive path that previously did not allow the signal to flow.

[0103] The term "isolated" refers to a relationship between components where a signal is currently not able to flow between the components. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch that is open are isolated from each other. If a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0104] The terms "if," "when," "based on," or "based at least in part on" can be used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" can be used to describe a conditional relationship, a causal relationship, or a partial connection between

[0105] The term "in response to" can refer to at least in part (if not entirely) a condition or action occurring as a result of a prior condition or action. For example, a first condition or action can be performed, and a second condition or action can occur at least in part as a result of the prior condition or action occurring (whether immediately following the first condition or action or following one or more other intervening conditions or actions).

[0106] Additionally, the term "directly in response to" or "in direct response to" can refer to a condition or action that occurs as a direct result of a prior condition or action. In some examples, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the prior condition or action, independent of whether other conditions or actions occur. In some examples, a first condition or action can be performed, and a second condition or action can occur directly as a result of the occurrence of the prior condition or action, such that no other intervening conditions or actions occur between the prior condition or action and the second condition or action, or a limited number of one or more intervening steps or actions occur between the prior condition or action and the second condition or action. Any condition or action described herein as being performed "based on," "at least in part on," or "in response to" some other step, action, event, or condition can additionally or alternatively (e.g., in alternative examples) be performed "in direct response to" or "directly in response to" this other condition or action, unless otherwise noted.

[0107] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation or any other means of doping during initial formation or growth of the substrate.

[0108] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials (e.g., metal). The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be“turned on” or“activated” if a voltage greater than or equal to the transistor’s threshold voltage is applied to the transistor gate. A transistor can be“turned off’ or“deactivated” if a voltage less than the transistor’s threshold voltage is applied to the transistor gate.

[0109] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the instances that can be implemented or that are within the scope of the claims. The term“exemplary” used herein means“serving as an example, instance, or illustration,” and not“preferred” over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0110] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by adding a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0111] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored on or transmitted over as one or more instructions (e.g., code) on a computer-readable medium. Due to the nature of software, changes to the functions described herein can be made by a software implementation in response to changes in the software. The functions described herein can be implemented by software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing functions can be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0112] For example, illustrative blocks and modules described herein can be implemented or performed with one or more processors (e.g., DSPs, ASICs, FPGAs, discrete logic, discrete hardware components, other programmable logic devices, or any combination thereof designed to perform the functions described herein). A processor can be an example of a microprocessor, a controller, a microcontroller, a state machine, or other

[0113] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0114] As used herein, including in the claims, the article “a” preceding a noun is an open- ended article and should be interpreted to mean “at least one” or “one or more” of the noun. Thus, the terms “a,” “at least one,” “one or more,” and “at least one of’ can be interchangeable. For example, if a claim recites “a component” that performs one or more functions, then each individual function can be performed by a single component or by any combination of components. Thus, the term “component” having a particular characteristic or performing a particular function can refer to “at least one of’ or “one or more of’ the “component” having the particular characteristic or performing the particular function. Subsequent references to “the component” in the claims can refer to any one of or all of the “component” introduced by the indefinite article “a” or “an.” For example, a component introduced by the indefinite article “a” can be understood to mean “one or more components,” and a subsequent reference to “the component” in the claims can be understood as equivalent to a reference to “at least one of’ or “one or more of’ the “component.” Similarly, subsequent references to a component introduced by the indefinite article “a” or “an” can refer to any one of or all of the “component.” For example, a subsequent reference to “one or more components” in the claims can be understood as equivalent to a reference to “at least one of’ or “one or more of’ the “component.”

[0115] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0116] The description is presented to enable any person skilled in the art to make and use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: one or more memories that store processor-executable code; and one or more processors coupled with the one or more memories and capable individually or collectively operating to execute the code to cause the memory system to: configure the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters; after configuring the first partition and the second partition, assign a first portion of the second partition to the first partition; after assigning the first portion to the first partition and as part of a manufacturing process, store data to the first partition; and after an event of experiencing the manufacturing process, assign the first portion to the second partition.

2. The memory system of claim 1, wherein: the first partition and the second partition have separate block pools for different usage modes.

3. The memory system of claim 1, wherein: the first partition includes blocks having memory cells configured as single-level cells and blocks having memory cells configured as triple-level cells, and the second partition includes blocks having memory cells configured as single-level cells.

4. The memory system of claim 1, wherein the event comprises a passage of time, a start of one or more processes, a completion of one or more processes, or a combination thereof.

5. The memory system of claim 1, wherein the one or more processors are further capable individually or collectively operating to execute the code to cause the memory system to: set a flag indicating the first portion is assigned to a first partition after assigning the first portion of the second partition to the first partition, wherein storing the data is based at least in part on setting the flag.

6. The memory system of claim 5, wherein the first portion includes a plurality of superblocks and the flag includes a plurality of flags, wherein each flag of the plurality of flags is associated with a respective superblock of the plurality of superblocks.

7. The memory system of claim 5, wherein the one or more processors are further capable individually or collectively operating to execute the code to cause the memory system to: after assigning the first portion to the first partition, clear the flag corresponding to the first portion.

8. The memory system of claim 1, wherein the one or more processors are further capable individually or collectively operating to execute the code to cause the memory system to: before assigning the first portion back to the second partition, perform a garbage collection operation on the first portion; and based at least in part on performing the garbage collection operation, transfer valid data stored in the first portion to the first partition.

9. The memory system of claim 1, wherein the one or more processors are further capable individually or collectively operating to execute the code to cause the memory system to: configuring memory cells of a second portion of the first partition as single-level cells based at least in part on assigning the first portion to the first partition. configuring memory cells of a second portion of the first partition as single-level cells based at least in part on assigning the first portion to the first partition.

10. The memory system of claim 9, wherein the one or more processors, individually or collectively, are further operable to execute the code to cause the memory system to: based at least in part on configuring the first portion and the second portion, link superblocks of the first portion and the second portion to form three superblocks of single-level cells; and assign the linked superblocks to a data structure configured to track a single superblock of triple-level cells for the first partition, wherein storing the data to the first portion is based at least in part on assigning the linked superblocks to the data structure.

11. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: configure a memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters; after configuring the first partition and the second partition, assign a first portion of the second partition to the first partition; after assigning the first portion to the first partition and as part of a manufacturing process, store data to the first partition; and after an event of the manufacturing process, assign the first portion to the second partition.

12. The non-transitory computer-readable medium of claim 11, wherein: the first partition and the second partition have separate block pools for different usage modes.

13. The non-transitory computer-readable medium of claim 11, wherein the instructions are further executable by the one or more processors to: set a flag indicating that the first portion is assigned to a first partition after assigning the first portion of the second partition to the first partition, wherein storing the data is based at least in part on setting the flag.

14. The non-transitory computer-readable medium of claim 13, wherein the first portion comprises a plurality of superblocks and the flag comprises a plurality of flags, wherein each flag of the plurality of flags is associated with a respective superblock of the plurality of superblocks.

15. The non-transitory computer-readable medium of claim 11, wherein the instructions are further executable by the one or more processors to: configure memory cells of the first portion as single-level cells based at least in part on assigning the first portion of the second partition to the first partition; and configure memory cells of a second portion of the first partition as single-level cells based at least in part on assigning the first portion to the first partition.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions are further executable by the one or more processors to: linking superblocks of the first portion and the second portion to form three superblocks of a single level cell based at least in part on configuring the first portion and the second portion; and assigning the linked superblocks to a data structure configured to track a single superblock of a three level cell for the first partition, wherein storing the data to the first portion is based at least in part on assigning the linked superblocks to the data structure.

17. A method at a memory system, comprising: configuring the memory system to include a first partition and a second partition, the first partition configured with a first set of operating parameters and the second partition configured with a second set of operating parameters; after configuring the first partition and the second partition, assigning a first portion of the second partition to the first partition; after assigning the first portion to the first partition and as part of a manufacturing process, storing data to the first partition; and after an event of the manufacturing process, assigning the first portion to the second partition.

18. The method of claim 17, further comprising: setting a flag indicating that the first portion is assigned to a first partition after assigning the first portion of the second partition to the first partition, wherein storing the data is based at least in part on setting the flag.

19. The method of claim 17, further comprising: configuring memory cells of the first portion as single level cells based at least in part on assigning the first portion of the second partition to the first partition; and configuring memory cells of a second portion of the first partition as single level cells based at least in part on assigning the first portion to the first partition.

20. The method of claim 19, further comprising: linking superblocks of the first portion and the second portion to form three superblocks of a single level cell based at least in part on configuring the first portion and the second portion; and assigning the linked superblocks to a data structure configured to track a single superblock of a three level cell for the first partition, wherein storing the data to the first portion is based at least in part on assigning the linked superblocks to the data structure. ​

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