Decoding method and device, electronic equipment and storage medium

Abstract

The invention discloses a decoding method and device, electronic equipment and a storage medium, and relates to the technical field of data storage, and the method comprises the steps: splitting a to-be-decoded codeword and a check matrix, and distributing the to-be-decoded codeword and the check matrix to a plurality of decoding cores for parallel iterative decoding; in the process that the decoding core performs iterative decoding on the target code word distributed to the decoding core based on the target check matrix distributed to the decoding core, when an updated target code word is decoded, the variable quantity of the decision value of the updated target code word is determined; updating an incremental verification result matrix based on the variable quantity of the decision value of the updated target code word; and if each row of data of the incremental verification result matrix is a preset value, stopping executing the iterative decoding process of each decoding core to obtain a decoding result. According to the invention, the technical problems of long decoding time and low decoding performance are solved through parallel iterative decoding and incremental verification of the plurality of decoding cores, and the technical effect of improving the decoding efficiency and the decoding performance is achieved.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a decoding method, apparatus, electronic device and storage medium. Background Technology

[0002] With the development of information technology, NAND flash memory has become the mainstream data storage medium, and its reliability issues have become increasingly prominent. To improve the reliability of data storage, Low-Density Parity-Check (LDPC) codes are widely used in NAND storage. LDPC decoders gradually correct errors in the data through iterative decoding algorithms.

[0003] This method of gradually correcting errors in the data through iterative decoding algorithms requires multiple iterations, and each iteration requires updating the entire parity check matrix, resulting in long decoding time and low decoding performance. Summary of the Invention

[0004] This application provides a decoding method, apparatus, electronic device, and storage medium to at least solve the problems of long decoding time and low decoding performance in related technologies.

[0005] This application provides a decoding method, including:

[0006] Obtain the codeword to be decoded;

[0007] The codewords to be decoded and the parity check matrix are split and distributed to multiple decoding cores for parallel iterative decoding;

[0008] In the process of iteratively decoding the target codewords assigned to it based on the target parity matrix assigned to it, the change in the decision value of the updated target codeword is determined each time an updated target codeword is decoded.

[0009] Based on the change in the decision value of the updated target codeword, update the incremental verification result matrix;

[0010] If each row of data in the incremental verification result matrix is ​​a preset value, stop executing the iterative decoding process of each decoding core and obtain the decoding result.

[0011] This application also provides a decoding device, including:

[0012] The first acquisition module is used to acquire the codeword to be decoded;

[0013] The splitting module is used to split the codewords to be decoded and the parity check matrix, so that they can be distributed to multiple decoding cores for parallel iterative decoding;

[0014] The determination module is used to determine the change in the decision value of each updated target codeword during the iterative decoding process of the decoding core based on the target parity matrix assigned thereto.

[0015] The update module is used to update the incremental verification result matrix based on the change in the decision value of the updated target codeword;

[0016] The second acquisition module is used to stop the iterative decoding process of each decoding core and obtain the decoding result when each row of data in the incremental verification result matrix is ​​a preset value.

[0017] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described decoding methods when executing the computer program.

[0018] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described decoding methods.

[0019] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described decoding methods.

[0020] This application achieves the following: First, the codeword to be decoded is obtained. Then, the codeword and parity check matrix are split and distributed among multiple decoding cores for parallel iterative decoding. During the iterative decoding process of the target codewords assigned to each core based on its assigned parity check matrix, the change in the decision value of each updated target codeword is determined. Based on this change in decision value, the incremental parity check result matrix is ​​updated. If each row of the incremental parity check result matrix contains a preset value, the iterative decoding process of each decoding core is stopped, and the decoding result is obtained. By using multiple decoding cores for parallel iterative decoding and incremental parity check, the iterative decoding process can be terminated early. Therefore, this solves the technical problems of long decoding time and low decoding performance in related technologies, achieving the technical effect of improving decoding efficiency and performance. Attached Figure Description

[0021] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A flowchart illustrating a decoding method provided in an embodiment of this application;

[0023] Figure 2 A flowchart illustrating yet another decoding method provided in an embodiment of this application;

[0024] Figure 3 This is a schematic diagram illustrating the change in the calculated decision value provided in an embodiment of this application;

[0025] Figure 4 A schematic diagram illustrating the updating of the intermediate verification result matrix provided in an embodiment of this application;

[0026] Figure 5 A schematic diagram of the updated incremental verification result matrix provided in an embodiment of this application;

[0027] Figure 6 An architecture diagram of another decoding method provided in the embodiments of this application;

[0028] Figure 7 This is a schematic diagram of the structure of a decoding device provided in an embodiment of this application;

[0029] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] With the rapid development of information technology, the demand for data storage is constantly increasing. NAND flash memory, with its high-density storage and low cost, has become the main storage medium used in solid-state drives, USB drives, smartphones, and other electronic devices. However, as the storage density and capacity of NAND flash memory continue to increase, its reliability and data integrity issues are becoming increasingly prominent. In particular, under the influence of factors such as noise, external interference, and aging of storage cells, the probability of data errors increases significantly.

[0034] To enhance the reliability of NAND flash memory, Error Correction Codes (ECC) are widely used in the NAND storage field to ensure data accuracy during transmission and storage. Among various ECC technologies, Low-Density Parity-Check (LDPC) codes perform exceptionally well, especially suitable for scenarios with high performance and latency requirements. With the continuous development of NAND flash memory technology and the increasing demands for data transmission, LDPC codes are widely used in various storage and communication devices. LDPC codes are an encoding technique that uses a sparse parity-check matrix for error detection and correction. LDPC decoders typically employ iterative decoding algorithms (such as the Belief Propagation algorithm) to gradually correct errors in the data through multiple iterations.

[0035] However, LDPC decoders need to perform a large number of matrix operations and multiple iterations during the decoding process. These calculations and iterations are very complex, especially in NAND flash memory with large storage capacity. The amount of calculation and the number of iterations will increase significantly. Moreover, each iteration requires updating the entire parity matrix, which places high demands on hardware resources and computing power. In particular, in power-sensitive systems, excessive calculations lead to excessive overall power consumption.

[0036] Furthermore, LDPC decoding requires multiple iterations, resulting in long decoding times and low decoding performance. This situation is even more pronounced in large-scale data transmission.

[0037] To address the issues of complex decoding and verification processes, high power consumption, and low performance in LDPC decoders, this application provides a decoding method, apparatus, electronic device, and storage medium. The method includes: acquiring a codeword to be decoded; splitting the codeword and a parity check matrix and distributing them to multiple decoding cores for parallel iterative decoding; during the iterative decoding process of the decoding cores on the target codewords assigned to them based on the assigned target parity check matrix, determining the change in the decision value of each updated target codeword after decoding; updating the incremental parity check result matrix based on the change in the decision value of the updated target codeword; and stopping the iterative decoding process of each decoding core when each row of the incremental parity check result matrix contains a preset value, thereby obtaining the decoding result. The method provided above, through parallel iterative decoding and incremental verification by multiple decoding cores, can achieve early termination of the iterative decoding process, reduce redundant calculations, significantly improve decoding efficiency, reduce computational overhead, thereby reducing power consumption and improving overall decoding performance. It is particularly suitable for high-efficiency storage systems and high-speed data transmission scenarios.

[0038] Embodiments of this application provide a decoding method applied to an LDPC decoder. Figure 1 This is a flowchart illustrating the decoding method provided in the embodiments of this application, as shown below. Figure 1 As shown, the decoding method includes:

[0039] Step S101: Obtain the codeword to be decoded.

[0040] The codeword to be decoded is a potentially erroneous codeword received from the storage medium or communication channel. The codeword is typically a binary sequence encoded using LDPC, containing the original data bits and parity bits. In NAND flash memory scenarios, errors may be introduced into the codeword due to factors such as flash cell aging and interference.

[0041] Step S102: The codeword to be decoded and the parity check matrix are split and distributed to multiple decoding cores for parallel iterative decoding.

[0042] The parity check matrix is ​​the LDPC parity check matrix (H matrix).

[0043] In step S103, during the process of the decoding core iteratively decoding the target codewords assigned to it based on the target parity matrix assigned to it, the change in the decision value of the updated target codeword is determined each time an updated target codeword is decoded.

[0044] The decision value is the hard decision result of the received updated target codeword in LDPC decoding, used to verify its correctness.

[0045] Step S104: Update the incremental verification result matrix based on the change in the decision value of the updated target codeword.

[0046] In the initial state, each row of the incremental verification result matrix contains 0 data.

[0047] Step S105: If each row of data in the incremental verification result matrix is ​​a preset value, stop executing the iterative decoding process of each decoding core and obtain the decoding result.

[0048] The preset value is 0. If each row of the incremental verification result matrix is ​​0, the verification passes, the iterative decoding process of each decoding core stops, and the decoding result is obtained. The decoding result includes the decision value of each codeword to be decoded and the original data corresponding to the codeword to be decoded.

[0049] The decoding method provided in this application involves: acquiring the codeword to be decoded; splitting the codeword and the parity check matrix and distributing them to multiple decoding cores for parallel iterative decoding; during the iterative decoding process of the decoding cores on the target codewords assigned to them based on the target parity check matrix, determining the change in the decision value of each updated target codeword after decoding; updating the incremental parity check result matrix based on the change in the decision value of the updated target codeword; and stopping the iterative decoding process of each decoding core when each row of the incremental parity check result matrix contains a preset value, thereby obtaining the decoding result. By incrementally updating the parity check matrix, only updating the changed parts, instead of recalculating the entire parity check matrix in each iterative decoding, the incremental update effectively reduces the amount of computation and avoids unnecessary redundant calculations. By distributing the computational tasks in the LDPC decoding process to multiple decoding cores to achieve parallel iterative decoding, the allocation and utilization of computing resources are optimized. Each decoding core only needs to be responsible for updating a portion of the data blocks and the parity check matrix, thereby improving the decoding speed. By introducing a real-time monitoring mechanism during the decoding process, the system can determine whether to terminate decoding based on the current decoding status. If each row of the incremental verification result matrix contains a preset value, the subsequent iterative decoding process is immediately terminated, avoiding unnecessary calculations, reducing decoding time and power consumption, and improving the system's real-time performance and energy efficiency. The introduction of incremental verification will further drive NAND flash memory technology towards greater efficiency and reliability.

[0050] Embodiments of this application provide a decoding method applied to an LDPC decoder. Figure 2 This is a flowchart illustrating the decoding method provided in the embodiments of this application, as shown below. Figure 2 As shown, the decoding method includes:

[0051] Step S201: Obtain the codeword to be decoded. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0052] Step S202: The codeword to be decoded and the parity check matrix are split and distributed to multiple decoding cores for parallel iterative decoding.

[0053] Specifically, step S202 includes:

[0054] Step S2021: Divide the codewords to be decoded into timing units based on each clock cycle, and sequentially allocate codewords with consecutive sequence numbers to each decoding core.

[0055] In this process, the codewords are allocated in units of each clock cycle, i.e., per clock tick. For example, if there are four decoding cores, the codewords with column numbers n, n+1, n+2, and n+3 are assigned to the first, second, third, and fourth decoding cores respectively for computation, so as to achieve parallel iterative decoding of multiple codewords by multiple decoding cores.

[0056] Step S2022: Based on the column information of the target codewords allocated to multiple decoding cores, the parity check matrix is ​​split to obtain the target parity check matrix allocated to each decoding core.

[0057] In this algorithm, the LDPC parity-check matrix is ​​divided into columns, and each decoding core is responsible for updating a portion of the variable nodes (columns). Since the variable node update operations in the normalized minimum sum algorithm are local and independent, multiple columns can be processed in parallel simultaneously.

[0058] In step S203, during the process of the decoding core iteratively decoding the target codewords assigned to it based on the target parity matrix assigned to it, the change in the decision value of the updated target codeword is determined each time an updated target codeword is decoded.

[0059] Specifically, step S203 includes:

[0060] Step S2031: Obtain the target storage address of the decision value of the updated target codeword.

[0061] Understandably, each decoding core independently stores the decision value of the updated target codeword it has calculated.

[0062] Step S2032: Based on the write flag corresponding to the target storage address, determine whether there is a write decision value at the target storage address.

[0063] Step S2033: If a written decision value exists at the target storage address, the written decision value is read, and an XOR operation is performed between the written decision value and the decision value of the updated target codeword to obtain the change in the decision value of the updated target codeword. Based on the decision value of the updated target codeword, the storage data at the target storage address is updated.

[0064] Specifically, based on the decision value of the updated target codeword, the storage data at the target storage address is updated, that is, the storage data at the target storage address is updated with the decision value of the updated target codeword.

[0065] If no written decision value exists at the target storage address, the default written decision value for the target storage address is 0. An XOR operation is performed between the written decision value and the decision value of the updated target codeword to obtain the change in the decision value of the updated target codeword. Based on this updated decision value, the stored data at the target storage address is updated. By defaulting to a written decision value of 0 if no written decision value exists at the target storage address, uninitialized or empty values ​​at the target storage address are avoided, ensuring data consistency and correctness. This default value also helps with subsequent incremental verification and calculation, ensuring that erroneous values ​​are not introduced when calculating the change in decision value.

[0066] It is understandable that if the target storage address does not have a written judgment value, the default written judgment value of the target storage address is 0. Therefore, the target storage address does not need to be initialized, which can reduce the power consumption of the initialization part.

[0067] Figure 3 This is a schematic diagram illustrating the change in the calculated decision value as provided in an embodiment of this application. Figure 3 As shown, the updated decision value is XORed with the old value (i.e., the written decision value) at the target storage address to obtain the change in the decision value. The written decision value is determined based on the target storage address and its corresponding write tag. If the write tag indicates that a written decision value exists at the target storage address, the written decision value stored at the target storage address is retrieved. If the write tag indicates that no written decision value exists at the target storage address, the written decision value at the target storage address is determined to be 0.

[0068] Step S204: Update the incremental check result matrix based on the change in the decision value of the updated target codeword. See details below. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0069] Step S205: If each row of the incremental verification result matrix contains a preset value, stop the iterative decoding process for each decoding core and obtain the decoding result. For details, please refer to [link to details]. Figure 1Step S105 of the illustrated embodiment will not be described again here.

[0070] The decoding method provided in this application divides the codeword to be decoded into time sequences, and distributes consecutively numbered codewords to each decoding core in one go. Based on the column information of the target codewords distributed to multiple decoding cores, the parity check matrix is ​​split to obtain the target parity check matrix distributed to each decoding core. This enables multiple decoding cores to perform iterative decoding of the target codewords in parallel, thereby improving the decoding speed, optimizing the overall system performance, and supporting higher data transmission rates.

[0071] By comparing the difference (change) between the current decision value and the historical value, only the affected part of the check matrix is ​​updated, instead of recalculating the entire data in each iteration. This incremental update method greatly reduces the amount of computation, avoids unnecessary redundant calculations, reduces power consumption, and improves decoding speed.

[0072] In some optional implementations, step S204 above includes:

[0073] Step a1: Based on the updated target codeword and the corresponding target parity check matrix, determine the target column matrix corresponding to the updated target codeword.

[0074] In LDPC decoding, updates to changes only affect the rows associated with them. Therefore, when calculating the checksum, the increment of the change only needs to be multiplied by the associated submatrix, without needing to perform a full calculation on the entire checksum matrix. This significantly reduces computational load and improves decoding efficiency.

[0075] Based on the column number of the updated target codeword, the target column matrix is ​​determined from the target check matrix in the decoding core where the target codeword is located.

[0076] Step a2: Update the incremental verification result matrix based on the change in the target column matrix and the decision value of the updated target codeword.

[0077] The decoding method provided in this application reduces the scope of the verification calculation from the entire matrix to a local submatrix by extracting the target column matrix, thereby avoiding unnecessary redundant calculations, reducing power consumption, and improving decoding speed.

[0078] In some alternative implementations, step a2 above includes:

[0079] Step a21: Based on the target column matrix, determine multiple column submatrices corresponding to the target column matrix.

[0080] Step a22: For any column submatrix, determine whether the column submatrix is ​​a shift matrix of the identity matrix.

[0081] Since LDPC decoding typically uses sparse matrices (most elements are 0, with only a few being 1), the relationship between the relevant rows and columns of the parity check matrix H can be optimized using these sparsities.

[0082] In other words, multiple column submatrices in the target column matrix are either shift matrices of the identity matrix or matrices with all elements equal to 0.

[0083] As mentioned above, the increment calculation of the change only requires multiplication with the associated submatrix. Since the associated submatrix is ​​either a shifted matrix of the identity matrix or a matrix with all elements equal to 0, and the change multiplied by a matrix with all elements equal to 0, the increment calculation of the change only needs to be achieved by multiplying with the column submatrix of the shifted matrix of the identity matrix. That is, the increment calculation of the change can be achieved by shifting the change.

[0084] Specifically, the change is multiplied by the shift matrix of the identity matrix. The change will move in the relevant rows of the parity check matrix according to certain rules and affect the calculation result of the parity check matrix.

[0085] Step a23: If the submatrix in this column is a shift matrix of the identity matrix, then determine the shift amount of the submatrix in this column relative to the identity matrix.

[0086] Step a24: Based on the shift amount of the submatrix relative to the identity matrix, perform a shift operation on the change in the decision value of the updated target codeword to obtain the shift result.

[0087] Step a25: Based on the position information of the target column matrix in the verification matrix and the position information of the submatrix of that column in the target column matrix, determine the position information of the shift result in the intermediate verification result matrix.

[0088] Specifically, based on the position information of the target column matrix in the verification matrix, the column in the intermediate verification result matrix is ​​determined, and based on the position information of the submatrix of that column in the target column matrix, the row in the intermediate verification result matrix is ​​determined.

[0089] Assuming the column weight is w, meaning the number of column submatrices of the shift matrix that is the identity matrix in the target column matrix is ​​w, then each change will have w shift forms. For parallel processing, w sets of shifters can be used to calculate these shift operations in parallel. Each shifter is responsible for the shift result of one change and outputs w related submatrix calculation results, i.e., the shift results.

[0090] For each change, w sets of shifters are used to calculate the shift result of that change in parallel. Specifically, each change is processed by its corresponding shifter, which calculates the impact of the change on the relevant rows in the parity check matrix. The output of each shifter is a shift result, representing the change brought about by the change in the corresponding row and column.

[0091] In order to correctly map the w shifted values ​​to the intermediate verification result matrix, a data mapping structure is needed. The function of this structure is to map the w shifted values ​​to r rows of the intermediate verification structure matrix according to a predetermined rule, where r is usually much larger than w, that is, the number of rows in the verification matrix is ​​much larger than the number of columns.

[0092] By using data selection mapping, the w shift results are mapped to their corresponding positions in the r-row intermediate check matrix according to their row positions. This step ensures that the intermediate check matrix reflects the impact of each change on the relevant row. This mapping method effectively limits the contribution of each change to the check matrix to the relevant submatrix, thus avoiding the need for full matrix calculation.

[0093] Figure 4 This is a schematic diagram illustrating the updating of the intermediate verification result matrix provided in an embodiment of this application. For example... Figure 4 As shown, the change is input into w groups of shifters to obtain w shift results, and the w shift results are mapped to row r of the intermediate verification result matrix.

[0094] Step a26: Update the intermediate verification result matrix based on the position information of the shift result in the intermediate verification result matrix.

[0095] Step a27: Update the incremental verification result matrix based on the updated intermediate verification result matrix.

[0096] The decoding method provided in this application significantly reduces hardware resource consumption and power consumption by replacing multiplication operations with shift operations.

[0097] The decoding method provided in this application reduces the use of the parity check matrix register by mapping each decoding core to the intermediate parity check result matrix. It eliminates the need for a parity check matrix register in each decoding core. After updating the intermediate parity check result matrix, the data in each row of the updated intermediate parity check result matrix is ​​summed, allowing the parity information from different decoding cores to be superimposed without repeated verification. The decoding method provided in this application verifies the data at each step. Upon successful verification, subsequent iterations are immediately terminated, avoiding unnecessary computation and reducing decoding time and power consumption. This mechanism significantly improves the system's real-time performance and energy efficiency, making it suitable for applications sensitive to decoding speed and power consumption.

[0098] In some alternative implementations, step a27 above includes:

[0099] Step a271: Based on the updated intermediate verification result matrix, sum the data in each row of the updated intermediate verification result matrix to obtain the incremental change result of each row of the updated intermediate verification result matrix.

[0100] Step a272: Add the incremental change result of each row of the updated intermediate verification result matrix to the incremental verification result of the corresponding row of the original incremental verification result matrix to update the incremental verification result matrix.

[0101] Figure 5 This is a schematic diagram of the updated incremental verification result matrix provided in an embodiment of this application, as shown below. Figure 5 As shown, since multiple decoding cores perform iterative decoding in parallel, each iteration yields multiple shift results corresponding to the changes in the decision values ​​output by the multiple decoding cores. The shift results of each row in the intermediate verification result matrix are summed to obtain the incremental change result of each row. Specifically, the shift result of row 1 of decoding core 0 is the shift result of the first row of the intermediate verification result matrix output by decoding core 0.

[0102] The incremental change result of each row is added to the incremental verification result of the corresponding row in the original incremental verification result matrix to update the incremental verification matrix. The original incremental verification result matrix is ​​the same as the incremental verification result matrix obtained in the previous iteration. Initially, each row in the incremental verification result matrix contains only 0 data.

[0103] The decoding method provided in this application reduces unnecessary computational workload by calculating only the sum of changes instead of recalculating the entire amount. This helps to reduce computational complexity, save system resources, and improve decoding efficiency.

[0104] In some optional implementations, the above decoding method further includes:

[0105] Step b1: If at least one row of data in the incremental verification result matrix is ​​not a preset value, continue to execute the iterative decoding process of each decoding core until the maximum number of iterations is reached or the decoding result is obtained.

[0106] It is understood that the decoding method provided in this application performs independent incremental verification in each step, so the incremental verification result matrix can be updated in each step, and the iteration can be stopped at any time when the verification passes.

[0107] The decoding method provided in this application continues the iterative decoding process even when at least one row of data in the incremental verification result matrix is ​​not a preset value. This avoids premature termination of the decoding process before it is completed or when the decoding result does not meet the requirements. This ensures that the decoder can make full use of the information obtained in each iteration, thereby improving the success rate and efficiency of decoding. By terminating unnecessary iterations before reaching the maximum number of iterations (when the incremental verification result matrix meets the preset conditions), the consumption of computing resources can be reduced, power consumption can be lowered, and time can be avoided on invalid iterations.

[0108] In some optional implementations, the above decoding method further includes:

[0109] Step c1: During the process of iteratively decoding the target codewords assigned to the decoding core based on the target parity matrix assigned to it, if at least one decoding core fails, then based on the number of failed decoding cores, a corresponding number of target decoding cores are selected from the normal decoding cores, and the iterative decoding tasks on the failed decoding cores are evenly distributed to the target decoding cores.

[0110] The decoding method provided in this application improves the reliability and resource utilization efficiency of LDPC decoding by promptly migrating the iterative decoding tasks on a certain decoding core to other decoding cores when a failure occurs, thus preventing the failure from spreading and affecting the entire system.

[0111] The embodiments of this application provide a decoding method. Figure 6 An architecture diagram of the decoding method provided in the embodiments of this application is shown below. Figure 6 As shown, the decoding method includes:

[0112] Obtain the codeword to be decoded. Split the codeword and parity check matrix and distribute them to multiple decoding cores for parallel iterative decoding.

[0113] Each decoding core calculates the change in the decision value of the updated target codeword after decoding it. After obtaining the change in the decision value of the updated target codeword, the change in the decision value is multiplied by the parity check matrix.

[0114] Specifically, multiplying the change in the decision value with the verification matrix involves shifting the change in the decision value to obtain multiple shift results. For details, please refer to steps a21 to a27 above, which will not be repeated here.

[0115] Each decoding core outputs multiple shift results, which are then verified using a common incremental check matrix to obtain the verification result, ensuring efficient parallel decoding. Understandably, if every row of the incremental check matrix is ​​0, decoding is successful, the decoding process terminates, and the decoding result is obtained. If the incremental check matrix contains non-zero values, decoding fails, requiring another iteration. In this case, the codeword to be decoded continues to be updated and judged until decoding is successful.

[0116] In related technologies, during LDPC decoding, to improve data throughput, the decoding module is often configured with multiple decoding cores arranged in a column-parallel manner. For the verification module, a copy is typically used in each decoding core to observe whether the verification was successful. The decoding method provided in this application, by judging the new and old values ​​of the decision value obtained from each decoding core, calculates the change in the decision value, and then uses a common incremental verification result matrix for verification, ensuring efficient execution of the decoding process.

[0117] The decoding method provided in this application performs incremental verification after each target codeword update. The verification process is based on the current decision value and the corresponding parity check matrix data, updating the verification result according to the non-zero positions of the parity check matrix. By using incremental verification, only the changed parts are updated, avoiding unnecessary redundant calculations and improving decoding efficiency.

[0118] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0119] Embodiments of this application also provide a decoding device, such as... Figure 7 As shown, the decoding device includes:

[0120] The first acquisition module 701 is used to acquire the codeword to be decoded.

[0121] The splitting module 702 is used to split the codeword to be decoded and the parity check matrix, so as to distribute them to multiple decoding cores for parallel iterative decoding.

[0122] The determination module 703 is used to determine the change in the decision value of the updated target codeword each time it is decoded, during the iterative decoding process of the target codeword assigned to the decoding core based on the target parity matrix assigned thereto.

[0123] The update module 704 is used to update the incremental verification result matrix based on the change in the decision value of the updated target codeword.

[0124] The second acquisition module 705 is used to stop the iterative decoding process of each decoding core and obtain the decoding result when each row of data in the incremental verification result matrix is ​​a preset value.

[0125] In some alternative implementations, the splitting module 702 includes:

[0126] The allocation unit is used to divide the codewords to be decoded into timing units on a clock cycle basis, and to allocate codewords with consecutive sequence numbers to each decoding core in sequence.

[0127] The first acquisition unit is used to split the parity check matrix based on the column information of the target codewords allocated to multiple decoding cores, and obtain the target parity check matrix allocated to each decoding core.

[0128] In some alternative implementations, the determining module 703 includes:

[0129] The second acquisition unit is used to acquire the target storage address of the decision value of the updated target codeword.

[0130] The first determining unit is used to determine whether a write decision value exists at the target storage address based on the write flag corresponding to the target storage address.

[0131] The third acquisition unit is used to read the written decision value if the target storage address has a written decision value, perform an XOR operation on the written decision value and the decision value of the updated target codeword to obtain the change in the decision value of the updated target codeword, and update the storage data of the target storage address based on the decision value of the updated target codeword.

[0132] In some alternative implementations, the update module 704 includes:

[0133] The second determining unit is used to determine the target column matrix corresponding to the updated target codeword based on the updated target codeword and the corresponding target parity check matrix.

[0134] The first update unit is used to update the incremental verification result matrix based on the change in the decision value of the target column matrix and the updated target codeword.

[0135] In some optional implementations, the first update unit includes:

[0136] The third determining unit is used to determine multiple column submatrices corresponding to the target column matrix based on the target column matrix.

[0137] The judgment unit is used to determine whether any given submatrix is ​​a shift matrix of the identity matrix.

[0138] The fourth determining unit is used to determine the shift amount of the submatrix relative to the identity matrix if the submatrix is ​​a shift matrix of the identity matrix.

[0139] The fourth acquisition unit is used to perform a shift operation on the change in the decision value of the updated target codeword based on the shift amount of the submatrix relative to the identity matrix, and obtain the shift result.

[0140] The fifth determining unit is used to determine the position information of the shift result in the intermediate verification result matrix based on the position information of the target column matrix in the verification matrix and the position information of the submatrix in the target column matrix.

[0141] The second update unit is used to update the intermediate verification result matrix based on the position information of the shift result in the intermediate verification result matrix.

[0142] The third update unit is used to update the incremental verification result matrix based on the updated intermediate verification result matrix.

[0143] In some optional implementations, the third update unit includes:

[0144] The fifth acquisition unit is used to sum the data in each row of the updated intermediate verification result matrix based on the updated intermediate verification result matrix, so as to obtain the incremental change result of each row of the updated intermediate verification result matrix.

[0145] The sixth acquisition unit is used to add the incremental change result of each row of the updated intermediate verification result matrix to the incremental verification result of the corresponding row of the original incremental verification result matrix in order to update the incremental verification result matrix.

[0146] In some alternative implementations, the decoding device further includes:

[0147] The continuation execution unit is used to continue the iterative decoding process of each decoding core when there is at least one row of data in the incremental verification result matrix that is not a preset value, until the maximum number of iterations is reached or the decoding result is obtained.

[0148] For a description of the features in the corresponding embodiment of the decoding device, please refer to the relevant description of the corresponding embodiment of the decoding method, which will not be repeated here.

[0149] Embodiments of this application also provide an electronic device, such as... Figure 8 As shown, it includes a processor 801 and a memory 802, in which a computer program is stored. The processor 801 is configured to run the computer program to perform the steps in any of the above-described decoding method embodiments.

[0150] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described decoding method embodiments at runtime.

[0151] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0152] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described decoding method embodiments.

[0153] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described decoding method embodiments.

[0154] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0155] The decoding method, apparatus, electronic device, and storage medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A decoding method, characterized in that, include: Obtain the codeword to be decoded; The codewords to be decoded and the parity check matrix are split and distributed to multiple decoding cores for parallel iterative decoding; During the process of iteratively decoding the target codewords assigned to it based on the target parity matrix assigned to it in the decoding core, the change in the decision value of the updated target codeword is determined each time an updated target codeword is decoded. Based on the change in the decision value of the updated target codeword, update the incremental verification result matrix; If each row of data in the incremental verification result matrix is ​​a preset value, the iterative decoding process of each decoding core is stopped, and the decoding result is obtained.

2. The method according to claim 1, characterized in that, The step of splitting the codeword to be decoded and the parity check matrix and distributing them to multiple decoding cores for parallel iterative decoding includes: The codewords to be decoded are divided into time sequences in units of each clock cycle, and the codewords with consecutive sequence numbers are sequentially assigned to each decoding core. Based on the column information of the target codewords assigned to the multiple decoding cores, the verification matrix is ​​split to obtain the target verification matrix assigned to each of the decoding cores.

3. The method according to claim 1, characterized in that, The determination of the change in the decision value of the updated target codeword includes: Obtain the target storage address of the decision value of the updated target codeword; Based on the write flag corresponding to the target storage address, determine whether the target storage address has a write decision value; If the target storage address has a written decision value, then the written decision value is read, and an XOR operation is performed between the written decision value and the decision value of the updated target codeword to obtain the change in the decision value of the updated target codeword. Based on the decision value of the updated target codeword, the storage data of the target storage address is updated.

4. The method according to claim 1, characterized in that, The step of updating the incremental verification result matrix based on the change in the decision value of the updated target codeword includes: Based on the updated target codeword and the corresponding target parity check matrix, determine the target column matrix corresponding to the updated target codeword; The incremental verification result matrix is ​​updated based on the change in the target column matrix and the decision value of the updated target codeword.

5. The method according to claim 4, characterized in that, The step of updating the incremental verification result matrix based on the change in the decision value of the target column matrix and the updated target codeword includes: Based on the target column matrix, determine multiple column submatrices corresponding to the target column matrix; For any given submatrix, determine whether the submatrix is ​​a shift matrix of the identity matrix; If the submatrix in this column is a shift matrix of the identity matrix, then determine the shift amount of the submatrix relative to the identity matrix; Based on the shift amount of this submatrix relative to the identity matrix, the change in the decision value of the updated target codeword is shifted to obtain the shift result; Based on the position information of the target column matrix in the verification matrix and the position information of the column submatrix in the target column matrix, the position information of the shift result in the intermediate verification result matrix is ​​determined; The intermediate verification result matrix is ​​updated based on the position information of the shift result in the intermediate verification result matrix. The incremental verification result matrix is ​​updated based on the updated intermediate verification result matrix.

6. The method according to claim 5, characterized in that, The step of updating the incremental verification result matrix based on the updated intermediate verification result matrix includes: Based on the updated intermediate verification result matrix, the data in each row of the updated intermediate verification result matrix is ​​summed to obtain the incremental change result of each row of the updated intermediate verification result matrix; The incremental change result of each row of the updated intermediate verification result matrix is ​​added to the incremental verification result of the corresponding row of the original incremental verification result matrix to update the incremental verification result matrix.

7. The method according to claim 1, characterized in that, The method further includes: If at least one row of data in the incremental verification result matrix is ​​not a preset value, the iterative decoding process of each decoding core continues to be executed until the maximum number of iterations is reached or the decoding result is obtained.

8. A decoding device, characterized in that, include: The first acquisition module is used to acquire the codeword to be decoded; The splitting module is used to split the codeword to be decoded and the check matrix, so as to distribute them to multiple decoding cores for parallel iterative decoding; The determination module is used to determine the change in the decision value of the updated target codeword each time the updated target codeword is decoded during the iterative decoding process of the decoding core based on the target parity matrix assigned thereto. The update module is used to update the incremental verification result matrix based on the change in the decision value of the updated target codeword; The second acquisition module is used to stop the iterative decoding process of each decoding core and obtain the decoding result when each row of data in the incremental verification result matrix is ​​a preset value.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the decoding method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the decoding method as described in any one of claims 1 to 7.

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