Data transmission method based on cloud service system and cloud service system

Abstract

The invention discloses a data transmission method based on a cloud service system and the cloud service system, which can improve the data transmission speed and further improve the processing efficiency of tasks associated with data. The method comprises the following steps: when a first processor of a first computing node needs to send data to a second processor of a second computing node, the first processor of the first computing node can directly write the data into a first memory area distributed to the first processor in a first host machine; and writing the first instruction into a second memory area of the first host machine. The first host opportunity polls the second memory area, so that the first host opportunity can determine that the data is stored in the first memory area based on the polled second instruction. If so, the first host machine may notify a first SDI card of the first computing node to read the data from the allocated first memory region to send the data to a second processor of the second computing node.

Description

[0001] This application claims priority to Chinese Patent Application No. 202410650705.1, filed on May 21, 2024, entitled "A Computing Cluster and a Model Training Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of cloud technology, and in particular to a data transmission method and a cloud service system based on a cloud service system. Background Technology

[0003] With the rapid development of cloud technology, cloud providers have launched hypernode products to provide tenants with better cloud services. A hypernode typically consists of multiple compute nodes, each of which can contain a host machine and multiple processors connected to the host machine. The processors of different compute nodes are connected to each other via a high-speed bus, so the hypernode has high-performance computing capabilities and network communication capabilities, and can perform complex computing tasks.

[0004] In cloud service systems based on related technologies, a source computing node may include a source host, a source processor, and a source network interface card (NIC), while a destination computing node may include a target host, a target processor, and a target NIC. When the source processor needs to send data to the destination processor, it first writes the data to the source host's memory. Next, the source host's central processing unit (CPU) writes the data to its communication buffer. Then, the source NIC reads the data from the communication buffer and sends it to the destination NIC, which in turn sends it to the destination processor, allowing the destination processor to process the data and complete the task.

[0005] During the aforementioned data transmission process, multiple data writes are involved, and the source host's CPU is also required. This consumes CPU resources, which can affect the data transmission speed and consequently lead to lower task processing efficiency. Summary of the Invention

[0006] This application provides a data transmission method and a cloud service system based on a cloud service system, which can improve the speed of data transmission and thus improve the processing efficiency of data-related tasks.

[0007] A first aspect of this application provides a data transmission method based on a cloud service system. The cloud service system includes infrastructure providing cloud services, including a first computing node and a second computing node. The first computing node includes a first host, a first processor, and a first software-defined infrastructure (SDI) card. The method includes:

[0008] In the first computing node, when the first processor has data to be transmitted, the first processor can directly write the data into the first memory area allocated to the first processor by the first host machine, and directly write the first instruction into the second memory area of ​​the first host machine.

[0009] Since the first host machine polls the second memory region, it can determine the role of the first instruction in the second memory region after polling is completed, and thus determine that the first memory region stores the data based on the role.

[0010] After confirming that the data is stored in the first memory region, the first host machine can instruct the first SDI card to read the data from the first memory region. The first SDI card can then send the data to the second computing node. This completes the data transmission.

[0011] As can be seen from the above method, when the first processor of the first computing node needs to send data to the second processor of the second computing node, the first processor of the first computing node can directly write the data into the first memory area allocated to the first processor in the first host machine, and write the first instruction into the second memory area of ​​the first host machine. Since the first host machine polls the second memory area, it can determine that the first memory area stores the data based on the second instruction obtained from the polling. Then, the first host machine can notify the first SDI card of the first computing node to read the data from the allocated first memory area, so as to send the data to the second processor of the second computing node. It can be seen that during the data transmission process, after the first processor writes the data into the first host machine, the first host machine does not need to participate in any write operation. The first host machine only needs to detect the arrival of the data and notify the first SDI card to read the data directly from the first host machine, and then complete the data transmission. This can reduce the excessive consumption of the first host machine's resources, improve the data transmission speed, and thus improve the processing efficiency of data-related tasks.

[0012] In one possible implementation, the first processor writing the data to be transmitted into the first memory region of the first host machine includes: the first processor generating the data to be transmitted and storing the data in a third memory region of the first processor; and the first processor copying the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host machine. In the aforementioned implementation, after the first processor generates the data to be transmitted, it can first store the data in its third memory region. Since the first processor has determined the address of the first memory region, it can directly copy the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host machine. Therefore, the first processor can directly copy data to the first memory region of the first host machine without the involvement of the first host machine's CPU and without consuming CPU resources in the first host machine.

[0013] In one possible implementation, the second computing node includes a second host, a second processor, and a second SDI card. The first host notifies the first SDI card to read data from a first memory region. The first SDI card sending data to the second computing node includes: the first host obtaining the addresses of mutually bound third memory regions, the address of the first memory region, the address of the first SDI card, the address of the second SDI card, and the address of a fourth memory region of the second host from a first mapping table, wherein the fourth memory region is a memory region allocated by the second host to the second processor; the first host providing the first SDI card with the addresses of the first memory region, the second SDI card, and the fourth memory region based on the address of the first SDI card; the first SDI card reading data from the first memory region based on the address of the first memory region; and the first SDI card sending the data and the address of the fourth memory region to the second SDI card based on the address of the second SDI card, wherein the address of the fourth memory region is used by the second SDI card to write data into the fourth memory region. In the aforementioned implementation, after determining that the data is stored in the first memory region, the first host machine can first obtain the addresses of the mutually bound third memory region, the first memory region, the first SDI card, the second SDI card, and the fourth memory region of the second host machine from its own first mapping table. Then, based on these mutually bound addresses, the first host machine can determine that the first SDI card is an SDI card bound to the first memory region. Therefore, the first host machine can provide the addresses of the first memory region, the second SDI card, and the fourth memory region to the first SDI card based on the first SDI card's address. This allows the first SDI card to read the data from the first memory region based on the first memory region's address, and then send the data, along with the address of the fourth memory region in the first task, to the second SDI card based on the second SDI card's address. Thus, the first host machine only needs to query the first mapping table to determine which processor the data originates from and which processor it is destined for. Therefore, the first host machine does not need to query multiple tables, reducing its resource overhead.

[0014] In one possible implementation, the first host provides the addresses of a first memory region, a second SDI card, and a fourth memory region to the first SDI card based on the address of the first SDI card. This includes: the first host writing a second instruction into the first register of the first SDI card based on the address of the first SDI card; and the first SDI card polling the first register to obtain the addresses of the first memory region, the second SDI card, and the fourth memory region provided by the first host based on the polled second instruction. In the aforementioned implementation, the first host can write the second instruction into the first register of the first SDI card based on the address of the first SDI card. Since the first SDI card polls the first register, it can obtain the addresses of the first memory region, the second SDI card, and the fourth memory region provided by the first host based on the polled second instruction. Therefore, the first host can quickly trigger the first SDI card to perform data transmission tasks by directly writing to the first register of the first SDI card.

[0015] In one possible implementation, the first and second instructions are store instructions.

[0016] In one possible implementation, the method further includes: the second SDI card writing data from the first SDI card into the fourth memory region of the second host machine, and instructing the second host machine to determine that the data has arrived in the fourth memory region; the second host machine writing the data from the fourth memory region into the second processor; and the second processor processing the data to obtain the processing result. In the aforementioned implementation, after receiving the data from the first SDI card, the second SDI card can write the data into the fourth memory region of the second host machine, and instruct the second host machine to detect that the data has arrived in the fourth memory region. After the second host machine detects that the data has arrived in the fourth memory region, since the fourth memory region is the memory region allocated to the second processor of the second computing node, the second host machine can directly write the data from the fourth memory region into the second processor, so that the second processor can process the data to obtain the processing result, thereby meeting the tenant's data processing needs.

[0017] In one possible implementation, the second SDI card writing data from the first SDI card into a fourth memory region and instructing the second host machine to determine that the data has been stored in the fourth memory region includes: the second SDI card writing the data into the fourth memory region based on the address of the fourth memory region, and providing the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card to the second host machine, so that the second host machine can determine that the data has arrived in the fourth memory region of the second host machine. In the aforementioned implementation, after receiving the data from the first SDI card and the address of the fourth memory region of the second host machine, the second SDI card can write the data into the fourth memory region based on the address of the fourth memory region. Then, the second SDI card can provide the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card to the second host machine, so that the second host machine can determine that the data has been stored in the fourth memory region based on this information.

[0018] In one possible implementation, the second host machine writing data from the fourth memory region to the second processor includes: the second host machine obtaining the address of the fifth memory region of the second processor bound to the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card from a second mapping table; and the second host machine copying the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region. In the aforementioned implementation, the second host machine determines that the data has arrived in the fourth memory region, so it obtains the address of the fifth memory region of the second processor bound to the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card from the second mapping table. Therefore, the second host machine can directly copy the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region. Thus, the second host machine only needs to query the second mapping table to determine which processor the data comes from and which processor it is destined for, thereby reducing the resource overhead of the second host machine by not needing to query multiple tables.

[0019] In one possible implementation, the second processor processes the data to obtain the processing result, including: polling its second register to determine that the data is stored in a fifth memory region based on a third instruction obtained from the polling; the third instruction is written to the second register by the second host machine; and retrieving the data from the fifth memory region based on its address, processing the data, and obtaining the processing result. In the aforementioned implementation, after the second host machine writes the data to the fifth memory region, it can also write the third instruction to the second processor's second register. Since the second processor polls its second register, it can determine that the data is stored in the fifth memory region based on the third instruction obtained from the polling. Therefore, the second processor can retrieve the data from the fifth memory region based on its address, process the data, and obtain the processing result. Thus, the second host machine or the second SDI card can quickly notify the second processor that data has arrived by directly writing to the second processor's second register, without kernel-mode switching overhead or queueing overhead.

[0020] A second aspect of this application provides a cloud service system. The cloud service system includes infrastructure for providing cloud services. The infrastructure includes a first computing node and a second computing node. The first computing node includes a first host machine, a first processor, and a first SDI card. The first processor is configured to write data to be transmitted into a first memory area of ​​the first host machine and write a first instruction into a second memory area of ​​the first host machine. The first memory area is a memory area allocated by the first host machine to the first processor. The first host machine is configured to poll the second memory area to determine that the first memory area stores data based on the first instruction obtained from the polling. The first host machine is also configured to notify the first SDI card to read data from the first memory area. The first SDI card is configured to send the data to the second computing node.

[0021] In one possible implementation, the first processor is configured to: generate data to be transmitted and store the data in a third memory region of the first processor; and copy the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host machine.

[0022] In one possible implementation, the second computing node includes a second host, a second processor, and a second SDI card; the first host is configured to: obtain from a first mapping table the addresses of mutually bound third memory regions, the first memory region, the first SDI card, the second SDI card, and the fourth memory region of the second host, wherein the fourth memory region is a memory region allocated by the second host to the second processor; and provide the first SDI card with the addresses of the first memory region, the second SDI card, and the fourth memory region based on the address of the first SDI card; the first SDI card is configured to: read data from the first memory region based on the address of the first memory region; and send the data and the address of the fourth memory region to the second SDI card based on the address of the second SDI card, wherein the address of the fourth memory region is used by the second SDI card to write data into the fourth memory region.

[0023] In one possible implementation, a first host machine is used to write a second instruction into a first register of the first SDI card based on the address of the first SDI card; the first SDI is used to poll the first register to obtain the address of a first memory region, the address of the second SDI card, and the address of a fourth memory region provided by the first host machine based on the polled second instruction.

[0024] In one possible implementation, the first and second instructions are store instructions.

[0025] In one possible implementation, a second SDI card is used to write data from the first SDI card into the fourth memory region of the second host machine, and to enable the second host machine to determine that the data has arrived in the fourth memory region; the second host machine is used to write data from the fourth memory region into the second processor; the second processor is used to process the data to obtain the data processing result.

[0026] In one possible implementation, a second SDI card is used to write data to the fourth memory region based on the address of the fourth memory region, and to provide the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card to the second host machine so that the second host machine can determine that the data has arrived in the fourth memory region of the second host machine.

[0027] In one possible implementation, the second host machine is configured to: obtain from a second mapping table the address of the fifth memory region of the second processor, which is bound to the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card; and copy data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region.

[0028] In one possible implementation, the second processor is configured to: poll the second register of the second processor to determine, based on a third instruction obtained from the polling, that the data is stored in the fifth memory region, the third instruction being written into the second register by the second host machine; retrieve data from the fifth memory region based on the address of the fifth memory region, process the data, and obtain the data processing result.

[0029] A third aspect of this application provides a computing device cluster, which includes at least one computing device, each computing device including a processor and a memory: the memory is used to store instructions; the processor is used to cause the computing device cluster to perform the method described in the first aspect or any possible implementation of the first aspect according to the instructions.

[0030] A fourth aspect of this application provides a computer storage medium storing one or more instructions that, when executed by one or more computers, cause the one or more computers to perform the method described in the first aspect or any possible implementation of the first aspect.

[0031] A fifth aspect of this application provides a computer program product storing instructions that, when executed by a computer, cause the computer to perform the method described in the first aspect or any possible implementation of the first aspect.

[0032] In this embodiment, when the first processor of the first computing node needs to send data to the second processor of the second computing node, the first processor of the first computing node can directly write the data into the first memory area allocated to the first processor in the first host machine, and write the first instruction into the second memory area of ​​the first host machine. Since the first host machine polls the second memory area, it can determine that the first memory area stores the data based on the second instruction obtained from the polling. Then, the first host machine can notify the first SDI card of the first computing node to read the data from the allocated first memory area, so as to send the data to the second processor of the second computing node. It can be seen that during the data transmission process, after the first processor writes the data into the first host machine, the first host machine does not need to participate in any write operation. The first host machine only needs to detect the arrival of the data and notify the first SDI card to read the data directly from the first host machine, and then complete the data transmission. This can reduce the excessive occupation of the resources of the first host machine, improve the data transmission speed, and thus improve the processing efficiency of data-related tasks. Attached Figure Description

[0033] Figure 1 A schematic diagram of the structure of the cloud service system provided in the embodiments of this application;

[0034] Figure 2a A schematic diagram of the structure of a supercluster provided in an embodiment of this application;

[0035] Figure 2b A schematic diagram of the structure of a computing node provided in an embodiment of this application;

[0036] Figure 3 A schematic diagram of a mapping table provided in an embodiment of this application;

[0037] Figure 4 A flowchart illustrating a data transmission method based on a cloud service system provided in this application embodiment;

[0038] Figure 5a A schematic diagram illustrating data transmission provided in an embodiment of this application;

[0039] Figure 5b Another schematic diagram illustrating data transmission provided in an embodiment of this application;

[0040] Figure 6 Another schematic diagram illustrating data transmission provided in an embodiment of this application;

[0041] Figure 7 This is another schematic diagram of the cloud service system provided in the embodiments of this application;

[0042] Figure 8 A schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0043] Figure 9 A schematic diagram of the structure of a computing device cluster provided in an embodiment of this application;

[0044] Figure 10 This is a schematic diagram illustrating the network connection of computer devices in a computer cluster provided in an embodiment of this application. Detailed Implementation

[0045] This application provides a data transmission method and a cloud service system based on a cloud service system, which can improve the speed of data transmission and thus improve the processing efficiency of data-related tasks.

[0046] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0047] With the rapid development of cloud technology, cloud providers have launched supernode products to offer tenants better cloud services. A supernode typically consists of multiple compute nodes, each containing a host machine and multiple processors connected to the host machine (e.g., graphics processing units (GPUs) or neural network processing units (NPUs)). The processors on different compute nodes are connected via a high-speed bus, thus enabling supernodes to possess high-performance computing and network communication capabilities, allowing them to perform complex computational tasks (e.g., model training tasks in the field of artificial intelligence (AI)).

[0048] In cloud service systems based on related technologies, a source computing node may include a source host, a source processor, and a source network interface card (NIC), while a destination computing node may include a target host, a target processor, and a target NIC. When the source processor needs to send data to the destination processor, it first writes the data into the source host's memory. Then, the source host's CPU writes the data into its communication buffer. Next, the source NIC reads the data from the communication buffer and sends it to the destination NIC, which then forwards it to the destination processor via the destination host. The destination processor then processes the data to complete the task.

[0049] During the aforementioned data transmission process, multiple data writes are involved, and the source host's CPU is also required. This consumes CPU resources, which can affect the data transmission speed and consequently lead to lower task processing efficiency.

[0050] To address the aforementioned problems, embodiments of this application provide a data transmission method based on a cloud service system. This method can be implemented through a cloud service system (e.g., a public cloud system, etc.). Figure 1 A schematic diagram of the cloud service system provided in the embodiments of this application is shown below. Figure 1As shown, a cloud service system includes the infrastructure that provides cloud services and a cloud management platform that manages this infrastructure. The cloud management platform and the infrastructure are described separately below:

[0051] A cloud management platform can centrally manage the infrastructure of the entire cloud service system. (For example, within the infrastructure, it can create hyperclusters for tenants according to their instructions. These hyperclusters can contain multiple hypernodes that can communicate and connect to collectively process tenant tasks, such as model training tasks in the AI ​​field.) The cloud management platform can also be open to tenants outside the cloud service system and respond to their requests. For example, the cloud management platform can provide various interfaces, such as login and task processing interfaces, for tenant clients (e.g., the terminal devices used by the tenant or the browsers on those devices) to access. The cloud management platform can authenticate tenant clients through the login interface, allowing them to log in after successful authentication. Similarly, the cloud management platform can allow tenant clients to send pending tasks to the platform through the task processing interface. The platform can then invoke the serving hyperclusters to process the tenant's tasks and return the processing results to the tenant.

[0052] The infrastructure includes a hypercluster that serves tenants, such as Figure 2a As shown, ( Figure 2a (This is a schematic diagram of a supercluster provided in an embodiment of this application). The supercluster contains multiple supernodes, and each supernode can contain multiple compute nodes. The multiple compute nodes are described below from both hardware and software perspectives:

[0053] From a hardware perspective, any one of these computing nodes comprises a host, multiple processors connected to the host, and multiple software-defined infrastructure (SDI) cards. The host of this computing node connects to the multiple processors and SDI cards via a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interface. Each of the host, processors, and SDI cards has its own independent CPU and memory. The host, processors, and SDI cards can work collaboratively. The processors can read and write to the host's memory without the host's CPU's involvement. Once the host submits a data transfer task, subsequent data interfaces and transmissions do not require the host's participation. The SDI card of this compute node includes a CPU, memory, and a doorbell (DB) register. The DB register triggers the SDI card to perform data transmission tasks, and it can be directly written in user space by the host machine's forwarding module without kernel-mode switching overhead. The processor of this compute node mainly includes a compute processor (e.g., when the processor is an NPU, the compute processor of the NPU can be an AI CORE, etc.), high-bandwidth memory (HBM), and a notification register. The notification register can also be directly written in user space by the host machine's forwarding module or the TA module of the SDI card, without kernel-mode switching or enqueue / dequeue overhead.

[0054] like Figure 2b As shown, ( Figure 2b(This is a schematic diagram of a computing node provided in an embodiment of this application). From a software perspective, for any one of these computing nodes, the host machine, multiple processors, and multiple SDI cards of the computing node each have an independent operating system (running on the CPU of the host machine, multiple processors, and multiple SDI cards of the computing node). The operating system of the host machine includes a forwarding module, which manages the reception and transmission of data between the processors, the host machine, and the SDI cards of the computing node. The operating system of the processors includes a scheduler, which manages the reception and transmission of data between the processors and the host machine. The operating system of the SDI cards includes a transaction (TA) module, which manages the reception and transmission of data between the computing node and the other computing nodes. It should be noted that the relevant descriptions of data reception and transmission will not be elaborated here.

[0055] It is worth noting that for any one of these computing nodes, the processor's memory can contain a special memory region called Segment1. Segment1 is used to store the data that the processor of this computing node needs to send or interface. The host machine's memory can contain four special memory regions: Segment2, Trigger, Mapping Table, and Communication Queue. These four memory regions are described in detail below:

[0056] (1) Segment2 can also be called a communication buffer. Multiple processors of the computing node and multiple SDI cards of the computing node can directly read and write to Segment2. It is worth noting that since the host machine of the computing node is connected to multiple processors, the host machine of the computing node will allocate a corresponding Segment2 to each of its connected processors. That is to say, for the multiple processors of the computing node, each processor has its own dedicated Segment2 in the host machine of the computing node.

[0057] (2) Triggers are used by multiple processors of the computing node to notify the host machine's forwarding module whether the data to be transmitted is ready. Triggers can also be written directly by multiple processors of the computing node in user space, and can quickly detect the arrival of data in user space.

[0058] (3) The mapping table is used to store information related to the transmission channel. The forwarding module of the host machine of the computing node can query the mapping table to determine which processor of the computing node or which processor of other computing nodes the data is sent to. For example Figure 3 As shown ( Figure 3 (This is a schematic diagram of a mapping table provided in an embodiment of this application). When a processor of a computing node needs to establish a transmission channel with a processor of another computing node, the forwarding module of the host machine of the computing node can add an entry (tag) to the mapping table. The entry records mutually bound d transmission channels (dChannel) and n transmission channels (nChannel). dChannel is the channel between a processor of the computing node and the host machine of the computing node, and nChannel is the channel between the host machine of the computing node and the host machine of another computing node. Then, dChannel and nChannel can be combined to form a transmission channel built between a processor of the computing node and a processor of another computing node. The information contained in dChannel and nChannel varies depending on the transport protocol on which they are built. For example, when dChannel and nChannel use the Remote Direct Memory Access (RDMA) protocol, dChannel includes the (memory) address of Segment1 of a processor on the compute node and the (memory) address of Segment2 of the host machine on the compute node (this Segment2 is the one allocated to the processor). nChannel includes the (network) address of an SDI card on the compute node and the (network) address of an SDI card on another compute node, and may even include the address of Segment2 of the host machine on another compute node (this Segment2 is the one allocated to a processor on another compute node). Therefore, the pair of bound dChannels and nChannels recorded in the compute node's mapping table describes a transport channel built between a processor on the compute node and a processor on another compute node.

[0059] To further understand mapping tables, a specific application example will be used as an example below. Figure 3As shown, a tenant's supernode includes compute node 1, compute node 2, ..., compute node n. For compute node 1, its host1 is connected to multiple NPUs and multiple SDI cards. Host1 maintains a mapping table containing multiple entries. Entrance 1 records the mutually bound dChannel1 and nChannel2. dChannel1 contains the address of Segment1 of NPU1 and the address of Segment2-1 of host1. Segment2-1 is the Segment2 assigned by host1 to NPU1. nChannel2 contains the address of SDI card 1, the address of SDI card 3 of compute node 2, and the address of Segment2-9 of host2 of compute node 2. Segment2-9 is the Segment2 assigned by host2 to NPU9 of compute node 2.

[0060] Therefore, it can be seen that dChannel1 (between Segment 1 of NPU1 and Segment 2-1 of host1) and nChannel2 (between Segment 2-1 of host1 and Segment 2-9 of host2) form a transmission channel built between NPU1 and NPU9. This transmission channel indicates that host1 is bound to Segment 1 of NPU1, Segment 2-1 of host1, SDI card 1, SDI card 3, Segment 2-9 of host2, and NPU9. Data can be transmitted from Segment 1 of NPU1 to Segment 1 of NPU9 along this transmission channel. The other dChannels and nChannels in the mapping table are similar, and will not be elaborated here.

[0061] (4) The communication queue includes a work queue (WQ) and a completion queue (CQ). The WQ is used to submit data transmission tasks, and the CQ is used to submit task completion notifications. The description information of the data transmission task can be stored in the work queue element (WQE). When the forwarding module of the host machine of the computing node determines that the data has arrived, it can generate a WQE and submit the WQE to the WQ, so that the SDI card of the computing node can retrieve the WQE from the WQ, read the data from the host machine of the computing node based on the WQE, and send the data to the SDI card of another computing node, thereby completing the data transmission. The completion information of the data transmission task is stored in the completion queue element (CQE). After receiving the data, the SDI card of another computing node can generate a CQE and submit it to the CQ to notify the forwarding module of the host machine of the other computing node that the data transmission is complete.

[0062] Furthermore, in the embodiments of this application, any two computing nodes that communicate can be located either within the same supernode or in two different supernodes; no restrictions are imposed here.

[0063] Furthermore, in the embodiments of this application, the computing nodes in the supernode can be cloud instances in the infrastructure. These cloud instances can be presented in various ways. For example, these cloud instances can be physical servers selected by the cloud management platform, or bare metal servers selected by the cloud management platform, etc.

[0064] Furthermore, in the embodiments of this application, for a tenant's multiple supernodes, these multiple supernodes can be deployed in the same site or different sites. The site can be presented in various forms. For example, the site can be a region in the infrastructure, or an availability zone in the infrastructure, or a data center (DC) in the infrastructure, or a room in the infrastructure, or a rack in the infrastructure, etc.

[0065] Based on the aforementioned cloud service system, when a source processor (one of the multiple processors of a source compute node, i.e., a compute node within a supernode) needs to send data to the destination processor (one of the multiple processors of the destination compute node, i.e., another compute node of the same supernode or a compute node of another supernode), the source processor of the source compute node can directly write the data to the memory area allocated to the source processor in the source host machine, and write a certain instruction to another memory area of ​​the source host machine. Since the source host machine polls the other memory area, it can determine that the memory area allocated to the source processor stores data based on the instruction obtained from the polling. Then, the source host machine can instruct the source SDI card (one of the multiple SDI cards of the source compute node) to read the data from the memory area allocated to the source processor, so as to send the data to the destination processor of the destination compute node. Therefore, during data transmission, after the source processor writes data to the source host, the source host does not need to participate in any write operations. The source host only needs to detect the arrival of data and notify the source SDI card to read the data directly from the source host before completing the data transmission. This reduces the resource consumption of the source host, improves the data transmission speed, and thus improves the processing efficiency of data-related tasks. To further understand the workflow of the aforementioned cloud service system, the following section combines... Figure 4 This workflow will be described in further detail. Figure 4 This is a flowchart illustrating a data transmission method based on a cloud service system provided in an embodiment of this application. The method can be achieved through, for example... Figure 1 The cloud service system implementation shown includes infrastructure providing cloud services. This infrastructure comprises a first computing node (also called a source computing node) and a second computing node (also called a destination computing node). The first computing node includes a first host machine (also called a source host machine), a first processor (also called a source processor), and a first SDI card (also called a source SDI card). The second computing node includes a second host machine (also called a destination host machine), a second processor (also called a destination processor), and a second SDI card (also called a destination SDI card). The method includes:

[0066] 401. The first processor writes the data to be transmitted into the first memory area of ​​the first host machine and writes the first instruction into the second memory area of ​​the first host machine. The first memory area is the memory area allocated by the first host machine to the first processor.

[0067] In this embodiment, when the first processor of the first computing node has data to be transmitted, the first processor can directly write the data into the first memory area of ​​the first host machine of the first computing node, and directly write the first instruction into the second memory area of ​​the first host machine. It should be noted that the first memory area is the memory area allocated by the first host machine to the first processor, and the second instruction is used to make the first host machine aware that the first memory area stores the data.

[0068] Specifically, the first processor can write the data to the first memory region in the following manner:

[0069] After the first processor generates the data to be transmitted, it can first store the data in its third memory region. Since the first processor has already obtained the address of the first memory region allocated to it by the first host machine, it can directly copy the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host machine (these two addresses constitute the dChannel between the first processor and the first host machine).

[0070] For example, such as Figure 5a and Figure 5b As shown ( Figure 5a A schematic diagram illustrating data transmission provided in an embodiment of this application. Figure 5b (This is another schematic diagram of data transmission provided in the embodiments of this application. For ease of explanation, it will be...) Figure 5a and Figure 5b The example shown is explained in several steps.

[0071] Step 1: After the AI ​​core of NPU1 on compute node 1 generates the data to be transmitted, the AI ​​core of NPU1 can first write the data into segment1 of NPU1 (i.e. the aforementioned third memory area), and let the scheduler of NPU1 know that segment1 of NPU1 stores the data, and can start the data copying.

[0072] Step 2: Since the scheduler of NPU1 has determined the dChannel between segment2-1 of host1 (i.e. the aforementioned second memory region) and segment1 of NPU1 (this dChannel contains the address of segment1 of NPU1 and the address of segment2-1 of host1), let this dChannel be dChannel1, the scheduler of NPU1 can copy the data from segment1 of NPU1 to segment2-1 of host1 through dChannel1.

[0073] Step 3: When the data copy is completed, the scheduler of NPU1 can write the store instruction (i.e. the first instruction mentioned above) into the Trigger (i.e. the second memory area mentioned above). The store instruction can set the flag bit associated with segment2-1 in the Trigger. Therefore, when the forwarding module of host1 polls the Trigger, it can find that the flag bit has been set, so it can be determined that segment2-1 stores the data.

[0074] 402. The first host machine polls the second memory region to determine, based on the first instruction obtained from the polling, that the first memory region stores data.

[0075] Since the first host machine polls the second memory region, it can determine that the first memory region stores the data based on the first instruction obtained from the polling (i.e., the effect of the first instruction in the second memory region).

[0076] As in the example above, in step 4: the forwarding module of host1 polls the Trigger and finds that the flag associated with segment2-1 in the Trigger has been set, so it can be determined that segment2-1 stores the data.

[0077] 403. The first host notifies the first SDI card to read data from the first memory area, and the first SDI card sends the data to the second SDI card.

[0078] After confirming that the data is stored in the first memory region, the first host machine can instruct the first SDI card of the first compute node to read the data from the first memory region. Therefore, the first SDI card can send the data to the second SDI card of the second compute node. It should be noted that the first SDI card is an SDI card bound to the first host machine, and the second SDI card is an SDI card bound to the first SDI card.

[0079] Specifically, the first host machine can instruct the first SDI card to acquire and send the data in the following manner:

[0080] After determining that the data is stored in the first memory region, the first host machine can first obtain the dchannel between the third memory region of the first processor and the first memory region of the first host machine from its own first mapping table (the dchannel contains the address of the third memory region and the address of the first memory region). Since the dchannel is bound to an nchannel, the nchannel is the nchannel between the first memory region of the first host machine and the fourth memory region of the second host machine (the nchannel contains the address of the first SDI card, the address of the second SDI card, and the address of the fourth memory region of the second host machine). The fourth memory region is the memory region allocated by the second host machine to the second processor.

[0081] Next, based on the mutually bound dchannel and nchannel, the first host machine can determine that the first SDI card is an SDI card bound to the first memory region. Therefore, the first host machine can use the address of the first memory region in the dchannel, the address of the second SDI card in the nchannel, and the address of the fourth memory region as the first task and submit the first task to the first task queue.

[0082] Then, the first host can, based on the address of the first SDI card in the nchannel, notify the first SDI to retrieve the first task from the first task queue. After obtaining the first task, the first SDI card can read the data from the first memory region based on the address of the first memory region in the first task. Subsequently, the first SDI card can, based on the address of the second SDI card in the first task, send the data and the address of the fourth memory region in the first task to the second SDI card.

[0083] More specifically, the first host can notify the first SDI card in the following ways:

[0084] The first host machine can write the second instruction into the first register of the first SDI card based on the address of the first SDI card in the nchannel. Since the first SDI card polls the first register, it can determine that there is a first task to be processed in the first task queue based on the second instruction obtained from the polling (i.e., the effect of the second instruction in the first register). Therefore, the first SDI card can obtain the first task from the first task queue, which is equivalent to obtaining the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region.

[0085] Continuing with the example above, in step 5: after confirming that segment2-1 stores the data, the forwarding module of host1 can find dChannel1 between NPU1's Segment1 and host1's Segment2-1 from the mapping table (i.e., the aforementioned first mapping table). Then, the forwarding module of host1 can further find nChannel2 bound to dChannel1 from the mapping table. nChannel2 is the nChannel between host1's Segment2-1 and host2's Segment2-9.

[0086] Step 6: The forwarding module of host1 can use the address of Segment2-1 of host1 in dChannel1, the address of SDI card 2 in nChannel and the address of Segment2-9 of host2 to generate WQE (i.e. the first task mentioned above) and submit WQE to WQ (i.e. the first task queue mentioned above).

[0087] Step 7: The forwarding module of host1 writes a store instruction (i.e., the aforementioned second instruction) to the DB register (i.e., the aforementioned first register) of SDI card 1 based on the address of SDI card 1 in nChannel, so as to set the DB register.

[0088] Step 8: Since the TA module of SDI card 1 polls the DB register, the TA module of SDI card 1 will detect that the DB register is set, thereby determining that there is a WQE to be processed in WQ.

[0089] Step 9: The TA module of SDI card 1 obtains WQE from WQ.

[0090] Step 10: The TA module of SDI card 1 can extract the address of Segment 2-1 of host1, the address of SDI card 2, and the address of Segment 2-9 of host2 from WQE. First, based on the address of Segment 2-1 of host1, it reads the data from Segment 2-1 of host1, and based on the address of SDI card 2, it sends the data and the address of Segment 2-9 of host2 to SDI card 2.

[0091] 404. The second SDI card writes data to the fourth memory area of ​​the second host machine and instructs the second host machine to confirm that the data has arrived in the fourth memory area.

[0092] After receiving the data from the first SDI card, the second SDI card of the second computing node can write the data into the fourth memory area of ​​the second host machine of the second computing node, and enable the second host machine to detect that the data has arrived in the fourth memory area.

[0093] Specifically, the first SDI card can make the second host aware that the data has arrived in the following way:

[0094] Upon receiving the data from the first SDI card and the address of the fourth memory region of the second host machine, the second SDI card can write the data into the fourth memory region based on the address of the fourth memory region. Next, the second SDI card can use the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card as a second task, and submit the second task to the second task queue of the second host machine. Since the second host machine polls the second task queue, it can retrieve the second task from the queue to determine that the data has been stored in the fourth memory region.

[0095] As in the example above, steps 11 to 12: Since SDI card 1 and SDI card 2 communicate through a virtual private cloud (VPC), the TA module of SDI card 1 can send the data and the address of Segment2-9 of host2 to the TA module of SDI card 2 through the VPC.

[0096] Step 13: The TA module of SDI card 2 can write the data to Segment 2-9 of host2 (i.e., the aforementioned fourth memory area) based on the address of Segment 2-9 of host2.

[0097] Step 14: The TA module of SDI card 2 can use the address of Segment2-9 of host2, the address of SDI card 1 and the address of SDI card 2 as CQE (i.e. the aforementioned second task), that is, use nChannel2 as CQE and add it to the CQ of host2 (i.e. the aforementioned second task queue).

[0098] Step 15: The forwarding module of host2 will poll the CQ, obtain the CQE from the CQ, and determine that the data has reached Segment2-9 of host2 based on the CQE.

[0099] 405. The second host writes data from the fourth memory area to the second processor.

[0100] 406. The second processor processes the data to obtain the processing result.

[0101] After the second host machine detects that the data has arrived in the fourth memory region, since the fourth memory region is the memory region allocated to the second processor of the second computing node, the second host machine can directly write the data from the fourth memory region to the second processor, so that the second processor can process the data and obtain the processing result. At this point, the data transmission and data processing are completed, satisfying the tenant's task processing requirements associated with the data.

[0102] Specifically, the second host machine can write this data to the second processor in the following way:

[0103] The second host machine has acquired the second task, which includes the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card. That is, the second task includes the nchannel between the first host machine's first memory region and the second host machine's fourth memory region. Therefore, the second host machine retrieves the dchannel bound to this nchannel from the second mapping table. This dchannel is the dchannel between the second processor's fifth memory region and the second host machine's fourth memory region; that is, this dchannel includes the address of the second host machine's fourth memory region and the address of the second processor's fifth memory region. Then, the second host machine can directly copy the data from the fourth memory region to the fifth memory region based on the addresses of the fourth and fifth memory regions.

[0104] As in the example above, step 16: Since CQE includes nChannel2, the forwarding module of host2 can obtain dchannel21 bound to nChannel2 from its own mapping table (i.e. the second mapping table mentioned above). dchannel21 contains the addresses of Segment2-9 of host2 and the address of Segment1 of NPU9.

[0105] Step 17: Since dchannel21 contains the addresses of Segment2-9 of host2 and Segment1 of NPU9, the forwarding module of host2 can copy the data directly from Segment2-9 of host2 to Segment1 of NPU9 (i.e. the aforementioned fifth memory area) based on these two addresses, that is, based on dchannel21.

[0106] More specifically, the second processor can process the data in the following ways:

[0107] After the second host machine writes the data into the fifth memory region, it can also write the third instruction into the second register of the second processor. Since the second processor polls the second register, it can determine that the data is stored in the fifth memory region based on the polled third instruction (i.e., the function of the third instruction in the second register). Then, the second processor can retrieve the data from the fifth memory region based on its address and process the data to obtain the processing result.

[0108] As in the example above, in step 18: after the data copy is completed, the forwarding module of host2 can use the store instruction (i.e. the third instruction mentioned above) to directly write the Notify register of NPU9 (i.e. the second register mentioned above) to set the Notify register.

[0109] Step 19: The NPU9 scheduler polls the Notify register. Once it finds that the Notify register is set, it can be determined that the NPU9's Segment1 stores the data. Therefore, the NPU9 scheduler notifies the NPU9's AI core to read the data from the NPU9's Segment1 and process the data.

[0110] It should be understood that in this embodiment, the first SDI card may send the data only to the second SDI card without sending the address of the fourth memory region, or even the first mapping table may not contain the address of any destination memory region (e.g., the address of the fourth memory region). In this case, after receiving the data, the second SDI card will randomly write the data into any memory region in the second host machine and inform the second host machine that the data is stored in that memory region. Therefore, the second host machine can subsequently write the data from that memory region to the second processor. This writing process is the same as the process of writing the data from the fourth memory region to the second processor, and will not be described again here. It should be noted that this memory region is no longer the memory region allocated by the second host machine to the second processor.

[0111] It should also be understood that, in this embodiment, after the second SDI card receives the data and writes it into the fourth memory region of the second host machine, since the second SDI card has already determined the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card (i.e., the nchannel between the first memory region of the first host machine and the fourth memory region of the second host machine), the second SDI card can also directly query the second mapping table of the second host machine to obtain the dchannel bound to the nchannel. Since the dchannel contains the address of the fourth memory region of the second host machine and the address of the fifth memory region of the second processor, the second SDI card can copy the data from the fourth memory region to the fifth memory region, and the second SDI card can notify the second processor to read and process the data from the fifth memory region.

[0112] For example, such as Figure 6 As shown ( Figure 6 (This is another schematic diagram of data transmission provided in the embodiment of this application). Steps 1 to 2: After the TA module of SDI card 2 receives the data and the address of Segment2-9 of host2, it can write the data into Segment2-9 of host2 based on the address of Segment2-9 of host2.

[0113] Step 3: Since the TA module of SDI card 2 has determined nChannel2, the TA module of SDI card 2 can obtain dchannel21 bound to nChannel2 from the mapping table of host2. dchannel21 contains the addresses of Segment2-9 of host2 and the address of Segment1 of NPU9.

[0114] Step 4: The TA module of SDI card 2 can copy the data directly from Segment 2-9 of host2 to Segment 1 of NPU9 based on dchannel21.

[0115] Steps 5 and 6: After copying the data, the TA module of SDI card 2 can use the store instruction to directly write to the Notify register of NPU9 to set the Notify register. The NPU9 scheduler will poll the Notify register. After finding that it is set, it can determine that the data is stored in Segment 1 of NPU9. Therefore, the NPU9 scheduler notifies the AI ​​core of NPU9 to read the data from Segment 1 of NPU9 and process the data.

[0116] In this embodiment, when the first processor of the first computing node needs to send data to the second processor of the second computing node, the first processor of the first computing node can directly write the data into the first memory area allocated to the first processor in the first host machine, and write the first instruction into the second memory area of ​​the first host machine. Since the first host machine polls the second memory area, it can determine that the first memory area stores the data based on the second instruction obtained from the polling. Then, the first host machine can notify the first SDI card of the first computing node to read the data from the allocated first memory area, so as to send the data to the second processor of the second computing node. It can be seen that during the data transmission process, after the first processor writes the data into the first host machine, the first host machine does not need to participate in any write operation. The first host machine only needs to detect the arrival of the data and notify the first SDI card to read the data directly from the first host machine, and then complete the data transmission. This can reduce the excessive occupation of the resources of the first host machine, improve the data transmission speed, and thus improve the processing efficiency of data-related tasks.

[0117] Furthermore, in this embodiment, the first processor can directly copy data to the first memory region of the first host machine using synchronous direct memory access (SDMA) technology (of course, this embodiment is not limited to this technology; the first processor can also perform data copying using other technologies, which are not specifically limited here), without occupying CPU resources in the first host machine. Moreover, the first processor can complete the data copying in user mode, without kernel mode switching overhead. Furthermore, the first processor can directly write to the second memory region, enabling the first host machine to quickly detect that data has arrived in the first memory region, a process without interruption overhead.

[0118] Furthermore, in this embodiment, the first host machine and the second host machine can quickly query the first mapping table and the second mapping table respectively. Since both the first mapping table and the second mapping table contain mutually bound dChannel and nChannel, the first host machine and the second host machine can quickly determine which processor the data comes from and which processor it is sent to. For the first host machine and the second host machine, only one mapping table needs to be queried, without having to query multiple tables, which is beneficial to improving the efficiency of data transmission.

[0119] Furthermore, in this embodiment, the first host machine can quickly trigger the first SDI card to execute data transmission tasks by directly writing to the first register of the first SDI card. Moreover, the first host machine submits the first task in user mode, and the first SDI card can read the first task in user mode without kernel mode switching overhead. Furthermore, data transmission between the first host machine, the first processor, and the first SDI card uses the RDMA protocol, eliminating the need for a kernel protocol stack.

[0120] Furthermore, in this embodiment of the application, the second host or the second SDI card can quickly notify the second processor that data has arrived by directly writing to the second register of the second processor, without kernel mode switching overhead or queue entry / exit overhead.

[0121] The above is a detailed description of the data transmission method based on a cloud service system provided in the embodiments of this application. The cloud service system provided in the embodiments of this application will be described below. Figure 7 Another schematic diagram of the cloud service system provided in the embodiments of this application is shown below. Figure 7 As shown, the cloud service system includes infrastructure for providing cloud services. This infrastructure includes a first computing node and a second computing node. The first computing node includes a first host 701, a first processor 702, and a first SDI card 703. The second computing node includes a second host 704, a second processor 705, and a second SDI card 706. Notably, the first host 701 includes a first forwarding module, the first processor 702 includes a first scheduler, the first SDI card 703 includes a first TA module, the second host 704 includes a second forwarding module, the second processor 705 includes a second scheduler, and the second SDI card 706 includes a second TA module.

[0122] The first processor 702 is configured to write data to be transmitted into a first memory region of the first host machine 701 and write a first instruction into a second memory region of the first host machine 701. The first memory region is the memory region allocated by the first host machine 701 to the first processor 702. For example, the first processor 702 is configured to execute the aforementioned... Figure 4 Step 401 in the illustrated embodiment.

[0123] The first host machine 701 is used to poll the second memory region to determine that the first memory region stores data based on the first instruction obtained from the polling; for example, the first host machine 701 is used to execute the aforementioned Figure 4 Step 402 in the illustrated embodiment.

[0124] The first host machine 701 is also used to notify the first SDI card 703 to read data from the first memory area; for example, the first host machine 701 is used to perform the aforementioned Figure 4 Step 403 in the illustrated embodiment.

[0125] The first SDI card 703 is used to send data to the second computing node. For example, the first SDI card 703 is used to perform the aforementioned... Figure 4 Step 403 in the illustrated embodiment.

[0126] In one possible implementation, the first processor 702 is configured to: generate data to be transmitted and store the data in a third memory region of the first processor 702; and copy the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host machine 701.

[0127] In one possible implementation, the first host 701 is configured to: obtain from a first mapping table the addresses of mutually bound third memory regions, the first memory region, the first SDI card 703, the second SDI card 706, and the fourth memory region of the second host 704, wherein the fourth memory region is a memory region allocated by the second host 704 to the second processor 705; and provide the first SDI card 703 with the addresses of the first memory region, the second SDI card 706, and the fourth memory region based on the address of the first SDI card 703; the first SDI card 703 is configured to: read data from the first memory region based on the address of the first memory region; and send the data and the address of the fourth memory region to the second SDI card 706 based on the address of the second SDI card 706, wherein the address of the fourth memory region is used by the second SDI card 706 to write data into the fourth memory region.

[0128] In one possible implementation, a first host 701 is used to write a second instruction into a first register of the first SDI card 703 based on the address of the first SDI card 703; the first SDI is used to poll the first register to obtain the address of a first memory region, the address of a second SDI card 706, and the address of a fourth memory region provided by the first host 701 based on the polled second instruction.

[0129] In one possible implementation, the first and second instructions are store instructions.

[0130] In one possible implementation, the second SDI card 706 is used to write data from the first SDI card 703 into the fourth memory region of the second host 704, and to enable the second host 704 to determine that the data has arrived in the fourth memory region; the second host 704 is used to write data from the fourth memory region into the second processor 705; the second processor 705 is used to process the data to obtain the data processing result.

[0131] In one possible implementation, the second SDI card 706 is used to write data to the fourth memory region based on the address of the fourth memory region, and to provide the address of the fourth memory region, the address of the first SDI card 703, and the address of the second SDI card 706 to the second host 704 so that the second host 704 can determine that the data has arrived in the fourth memory region of the second host 704.

[0132] In one possible implementation, the second host 704 is configured to: obtain from the second mapping table the address of the fifth memory region of the second processor 705, which is bound to the address of the fourth memory region, the address of the first SDI card 703, and the address of the second SDI card 706; and copy data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region.

[0133] In one possible implementation, the second processor 705 is configured to: poll the second register of the second processor 705 to determine, based on a third instruction obtained from the polling, that the data is stored in the fifth memory region, the third instruction being written into the second register by the second host 704; retrieve data from the fifth memory region based on the address of the fifth memory region, process the data, and obtain the data processing result.

[0134] It should be noted that the information interaction and implementation process between the modules / units of the above-mentioned device are based on the same concept as the method embodiments of this application, and the resulting technical effects are the same as those of the method embodiments of this application. For details, please refer to the description in the method embodiments shown above in the embodiments of this application, and will not be repeated here.

[0135] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 8 As shown, the computing device 800 (which can be used to present the aforementioned first computing node or second computing node; for ease of explanation, the following description uses the computing device 800 to represent the aforementioned first computing node) includes: a processor 801, a memory 802, a communication interface 803, and a bus 804. The processor 801, memory 802, and communication interface 803 are coupled via the bus (not shown in the figure). The memory 802 stores instructions. When the execution instructions in the memory 802 are executed, the computing device 800 executes the method performed by the first computing node or the second computing node in the above method embodiments.

[0136] The computing device 800 may be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. Furthermore, when the units in the device can be implemented in the form of a processing element scheduler, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling programs. Alternatively, these units may be integrated together to implement a system-on-a-chip (SOC).

[0137] The processor 801 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0138] The memory 802 can be volatile memory or non-volatile memory, or it can include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0139] The memory 802 stores executable program code, and the processor 801 executes this executable program code to implement the functions of the aforementioned first forwarding module, first scheduler, and first TA module, thereby realizing the aforementioned data transmission method based on the cloud service system. That is, the memory 802 stores instructions for executing the aforementioned data transmission method based on the cloud service system.

[0140] The communication interface 803 uses transceiver modules, such as, but not limited to, network interface cards and transceivers, to enable communication between the computing device 800 and other devices or communication networks.

[0141] In addition to the data bus, the 804 bus can also include a power bus, a control bus, and a status signal bus. The bus can be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. The bus can be divided into address bus, data bus, and control bus.

[0142] Please see Figure 9 , Figure 9 This is a schematic diagram of a computing device cluster provided in an embodiment of this application. Figure 9 As shown, the computing device cluster 900 includes at least one computing device 800.

[0143] like Figure 9 As shown, the computing device cluster 900 includes at least one computing device 800. The memory 802 of one or more computing devices 800 in the computing device cluster 900 may store the same instructions for executing the data transmission method described above for the cloud service system.

[0144] In some possible implementations, the memory 802 of one or more computing devices 800 in the computing device cluster 900 may also store partial instructions for executing the data transmission method of the cloud service-based system described above. In other words, a combination of one or more computing devices 800 can jointly execute the data transmission method of the cloud service-based system described above.

[0145] It should be noted that the memory 802 in different computing devices 800 within the computing device cluster 900 can store different instructions, which are used to execute certain functions of the aforementioned cloud management platform. That is, the instructions stored in the memory 802 of different computing devices 800 can implement the functions of one or more modules, such as the first forwarding module, the first scheduler, and the first TA module.

[0146] In some possible implementations, one or more computing devices 800 in the computing device cluster 900 can be connected via a network. This network can be a wide area network (WAN) or a local area network (LAN), etc.

[0147] Please see Figure 10 , Figure 10 This is a schematic diagram illustrating the network connection of computer devices in a computer cluster provided in an embodiment of this application. Figure 10 As shown, the two computing devices 800A and 800B are connected via a network. Specifically, they are connected to the network through the communication interfaces in each computing device.

[0148] In one possible implementation, the memory in computing device 800A stores instructions for performing the functions of modules such as the first forwarding module. Meanwhile, the memory in computing device 800B stores instructions for performing the functions of modules such as the first scheduler and the first TA module.

[0149] It should be understood that Figure 10 The functions of computing device 800A shown can also be performed by multiple computing devices. Similarly, the functions of computing device 800B can also be performed by multiple computing devices.

[0150] This application also relates to a computer storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform actions such as... Figure 4 The steps performed by the first computing node or the second computing node in the illustrated embodiment.

[0151] This application also relates to a computer program product that stores instructions that, when executed by a computer, cause the computer to perform actions such as... Figure 4 The steps performed by the first computing node or the second computing node in the illustrated embodiment.

[0152] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0153] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0154] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0155] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0156] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A data transmission method based on a cloud service system, characterized in that, The cloud service system includes infrastructure for providing cloud services. The infrastructure includes a first computing node and a second computing node. The first computing node includes a first host, a first processor, and a first software-defined infrastructure (SDI) card. The method includes: The first processor writes the data to be transmitted into the first memory area of ​​the first host machine and writes the first instruction into the second memory area of ​​the first host machine. The first memory area is the memory area allocated by the first host machine to the first processor. The first host machine polls the second memory region to determine, based on the first instruction obtained from the polling, that the first memory region stores the data; The first host machine notifies the first SDI card to read the data from the first memory region; The first SDI card sends the data to the second computing node.

2. The method according to claim 1, characterized in that, The first processor writes the data to be transmitted into the first memory area of ​​the first host machine, including: The first processor generates data to be transmitted and stores the data in the third memory area of ​​the first processor; The first processor copies the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host machine.

3. The method according to claim 1 or 2, characterized in that, The second computing node includes a second host, a second processor, and a second SDI card. The first host notifies the first SDI card to read the data from the first memory region, and the first SDI card sends the data to the second computing node, including: The first host machine obtains from the first mapping table the address of the mutually bound third memory region, the address of the first memory region, the address of the first SDI card, the address of the second SDI card, and the address of the fourth memory region of the second host machine, wherein the fourth memory region is the memory region allocated by the second host machine to the second processor; The first host machine provides the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region to the first SDI card based on the address of the first SDI card; The first SDI card reads the data from the first memory region based on the address of the first memory region; The first SDI card sends the data and the address of the fourth memory region to the second SDI card based on the address of the second SDI card. The address of the fourth memory region is used by the second SDI card to write the data into the fourth memory region.

4. The method according to claim 3, characterized in that, The first host machine provides the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region to the first SDI card based on the address of the first SDI card, including: The first host machine writes the second instruction into the first register of the first SDI card based on the address of the first SDI card; The first SDI polls the first register to obtain the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region provided by the first host machine based on the second instruction obtained from the polling.

5. The method according to claim 4, characterized in that, The first instruction and the second instruction are store instructions.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: The second SDI card writes the data from the first SDI card into the fourth memory area of ​​the second host machine, and instructs the second host machine to determine that the data has arrived in the fourth memory area; The second host writes the data from the fourth memory region to the second processor; The second processor processes the data to obtain the processing result.

7. The method according to claim 6, characterized in that, The second SDI card writes the data from the first SDI card into the fourth memory region, and the second host machine determines that the data has been stored in the fourth memory region, including: The second SDI card writes the data into the fourth memory region based on the address of the fourth memory region, and provides the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card to the second host machine, so that the second host machine can determine that the data has arrived in the fourth memory region of the second host machine.

8. The method according to claim 7, characterized in that, The second host machine writes the data from the fourth memory region to the second processor in the following ways: The second host machine obtains from the second mapping table the address of the fifth memory region of the second processor, which is bound to the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card; The second host machine copies the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region.

9. The method according to claim 8, characterized in that, The second processor processes the data to obtain the processing result, including: The second processor polls the second register of the second processor to determine, based on the third instruction obtained from the polling, that the data is stored in the fifth memory region, and the third instruction is written into the second register by the second host machine; The second processor retrieves the data from the fifth memory region based on the address of the fifth memory region, processes the data, and obtains the processing result of the data.

10. A cloud service system, characterized in that, The cloud service system includes infrastructure for providing cloud services. The infrastructure includes a first computing node and a second computing node. The first computing node includes a first host, a first processor, and a first SDI card. The first processor is configured to write the data to be transmitted into a first memory area of ​​the first host machine and write the first instruction into a second memory area of ​​the first host machine, wherein the first memory area is the memory area allocated by the first host machine to the first processor; The first host machine is configured to poll the second memory region to determine, based on the first instruction obtained from the polling, that the first memory region stores the data; The first host machine is also configured to notify the first SDI card to read the data from the first memory region; The first SDI card is used to send the data to the second computing node.

11. The cloud service system according to claim 10, characterized in that, The first processor is configured to: Generate the data to be transmitted and store the data in the third memory area of ​​the first processor; Based on the address of the third memory region and the address of the first memory region of the first host machine, the data is copied from the third memory region to the first memory region.

12. The cloud service system according to claim 10 or 11, characterized in that, The second computing node includes a second host, a second processor, and a second SDI card; The first host machine is used for: From the first mapping table, obtain the addresses of the mutually bound third memory region, the first memory region, the first SDI card, the second SDI card, and the fourth memory region of the second host machine, wherein the fourth memory region is the memory region allocated by the second host machine to the second processor; Based on the address of the first SDI card, the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region are provided to the first SDI card; The first SDI card is used for: Based on the address of the first memory region, read the data from the first memory region; Based on the address of the second SDI card, the data and the address of the fourth memory region are sent to the second SDI card, and the address of the fourth memory region is used by the second SDI card to write the data into the fourth memory region.

13. The cloud service system according to claim 12, characterized in that, The first host machine is configured to write a second instruction into the first register of the first SDI card based on the address of the first SDI card; The first SDI is used to poll the first register to obtain the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region provided by the first host machine based on the second instruction obtained from the polling.

14. The cloud service system according to claim 13, characterized in that, The first instruction and the second instruction are store instructions.

15. The cloud service system according to any one of claims 10 to 14, characterized in that, The second SDI card is used to write the data from the first SDI card into the fourth memory area of ​​the second host machine, and to enable the second host machine to determine that the data has arrived in the fourth memory area; The second host machine is used to write the data from the fourth memory region to the second processor; The second processor is used to process the data to obtain the processing result of the data.

16. The cloud service system according to claim 15, characterized in that, The second SDI card is used to write the data into the fourth memory region based on the address of the fourth memory region, and to provide the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card to the second host machine so that the second host machine can determine that the data has arrived in the fourth memory region of the second host machine.

17. The cloud service system according to claim 16, characterized in that, The second host machine is used for: From the second mapping table, obtain the address of the fifth memory region of the second processor, which is bound to the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card; Based on the address of the fourth memory region and the address of the fifth memory region, the data is copied from the fourth memory region to the fifth memory region.

18. The cloud service system according to claim 17, characterized in that, The second processor is used for: The second register of the second processor is polled to determine, based on the third instruction obtained from the polling, that the data is stored in the fifth memory region, and the third instruction is written into the second register by the second host machine; Based on the address of the fifth memory region, the data is obtained from the fifth memory region, and the data is processed to obtain the processing result of the data.

19. A computing device cluster, characterized in that, The computing device cluster includes at least one computing device, each computing device including a processor and memory: The memory is used to store instructions; The processor is configured to, according to the instructions, cause the computing device cluster to perform the method of any one of claims 1 to 9.

20. A computer storage medium, characterized in that, The computer storage medium stores one or more instructions that, when executed by one or more computers, cause the one or more computers to perform the method of any one of claims 1 to 9.

21. A computer program product, characterized in that, The computer program product stores instructions that, when executed by a computer, cause the computer to perform the method described in any one of claims 1 to 9.

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