Data hashing method, hardware accelerator, electronic equipment and storage medium
By receiving processor instructions and performing data filling processing, the high power consumption and limited applicability of hash algorithm hardware accelerators are solved, achieving efficient and flexible data hashing processing suitable for various application needs.
Patent Information
- Application Number
- CN202511071676.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-21
AI Technical Summary
Existing hash algorithm hardware accelerators have high power consumption and limited applicability, and cannot be compatible with different data hashing modes, resulting in high hardware costs and poor flexibility.
By receiving data hashing instructions from the processor, determining the completion of data reception based on the end marker, filling in the data and performing data hashing, it supports multiple data hashing modes and enables logical sharing.
It saves power consumption of hardware accelerators, improves data processing efficiency and smoothness, enhances versatility and flexibility, reduces hardware costs, and is suitable for a variety of application scenarios.
Smart Images
Figure CN120995506A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of data processing, and in particular to a data hashing method, a hardware accelerator, an electronic device and a storage medium. BACKGROUND
[0002] In today's digital age, information security and integrity are of great importance. Whether it is network communication, cloud computing services, or data interaction of Internet of Things devices, various security threats such as data tampering, forgery, and malicious attacks are faced, so it is of great significance to improve the ability to protect information security. Among them, the hash algorithm is one of the basic tools for protecting information security. The hash algorithm is a one-way function that converts input data of arbitrary length into a fixed-length hash value, and the hardware accelerator becomes an important solution to improve the computing efficiency of the hash algorithm.
[0003] The existing hardware accelerator of the hash algorithm usually needs to use a large number of internal counters to count the data amount of the data to be hashed, resulting in large power consumption of the hardware accelerator. In addition, the hardware accelerator can only receive data to be hashed in a format length required by the hash algorithm, making the applicable scenarios of the hardware accelerator have limitations. SUMMARY
[0004] The present application provides a data hashing method, a hardware accelerator, an electronic device and a storage medium to at least solve the problems of large power consumption and limited applicable scenarios of the hardware accelerator in the related art.
[0005] The present application provides a data hashing method, which comprises: receiving a data hashing instruction issued by a processor, the data hashing instruction carrying data identification information of data to be hashed, data length of the data to be hashed, data hashing mode corresponding to the data to be hashed and hash value output length; requesting to obtain the data to be hashed from a target hardware device according to the data identification information, wherein the data to be hashed is sent to the hardware accelerator in the form of a plurality of messages to be hashed; receiving each message to be hashed and performing data hashing processing on each message to be hashed; when it is determined that the data to be hashed is received completely after receiving a message to be hashed carrying an end identifier issued by the target hardware device, performing data padding on the data to be hashed according to the data length and the data hashing mode to obtain target data; performing data hashing processing on the target data based on the data hashing mode to obtain a target hash value corresponding to the data to be hashed, the length of the target hash value being consistent with the hash value output length.
[0006] The application further provides a hardware accelerator, comprising: a transceiver module, configured to receive a data hash instruction issued by a processor, the data hash instruction carrying data identification information of to-be-hashed data, a data length of the to-be-hashed data, a data hash mode corresponding to the to-be-hashed data, and a hash value output length; and the to-be-hashed data is requested from a target hardware device according to the data identification information, wherein the to-be-hashed data is sent to the hardware accelerator in the form of a plurality of to-be-hashed messages; a processing module, configured to receive each to-be-hashed message and perform data hash processing on each to-be-hashed message; when it is determined that the to-be-hashed data is received completely by receiving a to-be-hashed message issued by the target hardware device and carrying an end identifier, the to-be-hashed data is filled according to the data length and the data hash mode to obtain target data; and the target data is processed according to the data hash mode to obtain a target hash value corresponding to the to-be-hashed data, and the length of the target hash value is consistent with the hash value output length.
[0007] The application further provides an electronic device, comprising: a memory, configured to store a computer program; and a processor, configured to execute the computer program to implement the steps of any of the data hash methods.
[0008] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the data hash methods.
[0009] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the data hash methods.
[0010] According to the application, the hardware accelerator can determine that the to-be-hashed data is received completely based on the to-be-hashed message carrying the end identifier, without using a large number of internal counters to count the data amount of the to-be-hashed data to determine that the to-be-hashed data is received completely, thereby saving the power consumption of the hardware accelerator and synchronously completing the filling in the data end period without affecting the performance of the hardware accelerator. In addition, the hardware accelerator can fill the to-be-hashed data to obtain target data with a format length required by a hash algorithm, so that the hardware accelerator maintains high efficiency and smoothness of data processing, avoids performance bottlenecks caused by the data filling link, and improves the versatility of the hardware accelerator. The hardware accelerator can also be compatible with different data hash modes, implement logical sharing of the data hash modes, enhance the versatility and flexibility of the hardware accelerator, reduce the complexity and cost of developing different hardware structures for different modes, so that the hardware accelerator can be applied to various application requirements and scenarios, and enhance its competitiveness in the market. BRIEF DESCRIPTION OF DRAWINGS
[0011] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.
[0012] Figure 1 A topological structure diagram of a data hash system provided for the embodiments of the present application;
[0013] Figure 2 A schematic diagram of an internal state machine of a control module provided for the embodiments of the present application;
[0014] Figure 3 A structural block diagram of a core operation module provided for the embodiments of the present application;
[0015] Figure 4 A flowchart of a data hash method provided for the embodiments of the present application;
[0016] Figure 5 A flowchart of another data hash method provided for the embodiments of the present application;
[0017] Figure 6 A flowchart of still another data hash method provided for the embodiments of the present application;
[0018] Figure 7 A flowchart of yet another data hash method provided for the embodiments of the present application;
[0019] Figure 8 A structural block diagram of a hardware accelerator provided for the embodiments of the present application;
[0020] Figure 9 A hardware structure schematic diagram of an electronic device provided for the embodiments of the present application. DETAILED DESCRIPTION
[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.
[0022] It should be noted that in the description of the present application, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent to such processes, methods, articles or devices. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.
[0023] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.
[0024] The embodiments of the present application are applied to the scene of data hashing based on secure hash algorithm 2 (SHA2). The secure hash algorithm is also called hash algorithm.
[0025] Hash algorithm is a one-way function that converts input data of arbitrary length into a fixed length hash value. Its main features include: determinism, i.e. the same input always produces the same output; high efficiency, which can quickly calculate the hash value; collision resistance, i.e. it is difficult to find two different inputs that produce the same hash value. These features make hash algorithm one of the basic tools to protect information security. Among them, SHA2 algorithm is widely used in data integrity verification, digital signature, certificate generation and other fields. The SHA2 family includes SHA-224, SHA-256, SHA-384, SHA-512, SHA-512 / 224 and SHA-512 / 256 variants, and the variant is also called data hashing mode.
[0026] The hash calculation of SHA2 algorithm includes the following steps: padding the data to be hashed to a specific length, so that the length of the padded data meets the algorithm requirements; dividing the padded message into fixed-size data blocks; determining the initial value of each algorithm; applying the compression function to each data block in turn to calculate the hash value of each data block; after the iteration and compression calculation of all data blocks, the final hash value obtained is the target hash value.
[0027] The calculation process of SHA2 algorithm is relatively complex, involving a large number of bit operations, circular shifts and logical operations. In software implementation, these complex calculations will consume a large amount of processor resources and time, resulting in slow processing speed, which cannot meet some application scenarios with high real-time requirements, such as real-time data verification in high-speed network data transmission, fast data processing in large-scale data centers, etc. With the continuous development of technology, hardware accelerator has become an important solution to improve the calculation efficiency of SHA2 algorithm.
[0028] In the related art, the performance and efficiency of the SHA2 algorithm hardware accelerator are improved by optimizing the circuit structure, using advanced semiconductor processes and other methods. For example, using a parallel computing structure can process multiple data blocks simultaneously, reducing the computation time; using low-power circuit design techniques can reduce the power consumption of the hardware accelerator. However, some hardware accelerators can only receive data to be hashed that conforms to the required format length of the hash algorithm, and do not implement the data padding function in the algorithm, so the data padding function is still implemented in software, making the application scenarios of the hardware accelerator have limitations. In addition, the hardware accelerator can only adapt to one mode of the SHA2 algorithm, and has poor flexibility and universality, and different modes require the development of hardware accelerators with different hardware structures, thus increasing the hardware cost of the hardware accelerator.
[0029] To solve the above technical problems, the embodiments of the present application provide a data hashing method, which comprises: receiving a data hashing instruction issued by a processor, and requesting a target hardware device to obtain to-be-hashed data according to data identification information in the data hashing instruction; receiving each to-be-hashed message and performing data hashing processing on each to-be-hashed message; when a to-be-hashed message carrying an end identifier issued by the hardware device is received, determining that the to-be-hashed data reception is complete, and performing data padding on the to-be-hashed data to obtain target data; and performing data hashing processing on the target data based on a data hashing mode to obtain a target hash value corresponding to the to-be-hashed data. In this method, the hardware accelerator can determine that the to-be-hashed data reception is complete based on the to-be-hashed message carrying the end identifier, without using a large number of internal counters to count the amount of to-be-hashed data to determine that the to-be-hashed data reception is complete, thereby reducing the power consumption of the hardware accelerator. In addition, the hardware accelerator can also perform data padding on the to-be-hashed data to obtain target data that conforms to the required format length of the hash algorithm, thereby improving the universality of the hardware accelerator. The hardware accelerator can also adapt to different data hashing modes, thereby improving the flexibility of the hardware accelerator and reducing the hardware cost of the hardware accelerator.
[0030] The following describes the method provided by the embodiments of the present application by taking the data hashing system shown in Figure 1 as an example.
[0031] As shown in Figure 1 , a topology structure diagram of a data hashing system provided by the embodiments of the present application is shown in Figure 1 .In the embodiments of the present application, the data hashing system 100 comprises a hardware accelerator 101, a target hardware device 102 and a processor 103. Figure 1
[0032] The hardware accelerator 101 is based on the Federal Information Processing Standard Publication 180-4 Secure Hash Standard definition, and is used to implement the SHA2 algorithm. The hardware accelerator 101 includes a configuration module (SHA2_CFG), a control module (SHA2_CTRL), and a core operation module (SHA2_CORE).
[0033] The control module internal state machine is as shown in Figure 2 Figure 2 The control module internal state machine is as shown in Figure 2 The standby state (IDLE): after the reset (RESET) and the core operation module completes the hash value calculation, the state enters this state, and in this state, the data is waited to enter the core operation module. The padding state (PADDING): after the standby state obtains the data to be hashed, the state enters this state, and in this state, the received data to be hashed is filled to meet the SHA2 algorithm requirement, and after the data filling is completed, the data is transmitted to the core operation module, and the state machine enters the iteration state. The iteration state (ROUND): in this state, the data to be hashed and the filled data are obtained again according to the working state of the core operation module, and the filled data of the received data to be hashed is transmitted to the core operation module. The completion state (DONE): after the ROUND state completes the iteration calculation of all received data, the state enters this state, and in this state, whether an additional data needs to be sent to ensure that the filled data meets the SHA2 algorithm filling rule is determined according to the data length of the data to be hashed. Finally, when the core operation module completes the calculation of all filled data, the target hash value of this hash calculation is output, and the state machine enters the standby state.
[0034] The core operation module can include hash values of two different bit widths. The core operation module will complete the data hashing processing of the data to be hashed according to the corresponding data hashing mode, for example, message expansion and message iteration of the data to be hashed, so as to complete the calculation of the hash value. Different data hashing modes correspond to different bit widths. For example, the data hashing mode SHA-224 / 256 and SHA-256 correspond to the bit width of 256 bits of the core operation module; the data hashing mode SHA-384 / 512, SHA-512, and SHA-t / 512 correspond to the bit width of 512 bits of the core operation module. In order to ensure the logical multiplicity, the internal signal bit width of the core operation module is expanded to 512 bits.
[0035] The core operation module is as shown in Figure 3 Figure 3 The core operation module is as shown in Figure 3 In this module, the internal signal width of the core arithmetic module is 256 bits. A 512-bit data block enters the data expansion module to expand the data block into 64 32-bit message words (W). t The iterative module will use the initial hash value H. (0) and iteration constant (K) 256 The data is hashed, and the intermediate hash value H is obtained through iterative calculation. (i) This continues until the final 256-bit target hash value is output.
[0036] Understandably, hardware accelerators achieve logical sharing of multiple SHA2 modes by adjusting the parameterized bit width.
[0037] The target hardware device 102 can be any device with communication capabilities. For example, the target hardware device 102 can be a terminal device, a transmission device, a storage device, etc. The target hardware device is used to transmit the data to be hashed to the hardware accelerator 101.
[0038] Processor 103 may be a central processing unit. Processor 103 is used to issue data hash instructions to hardware accelerator 101.
[0039] Figure 1 The data hashing system illustrated is for illustrative purposes only and is not intended to limit the technical solutions of this application. Those skilled in the art should understand that, in specific implementations, the data hashing system may include more devices, without limitation.
[0040] Embodiments of this application provide a data hashing method, applied to... Figure 1 The hardware accelerator shown, such as Figure 4 As shown, Figure 4 The following is a flowchart illustrating a data hashing method provided in an embodiment of this application. The data hashing method includes the following steps:
[0041] S401 receives data hash instructions from the processor.
[0042] The data hashing instruction carries the data identifier information of the data to be hashed, the data length of the data to be hashed (data_lenth), the data hashing mode (mode) corresponding to the data to be hashed, and the output length of the hash value.
[0043] The hash pattern can be the hash pattern corresponding to the SHA2 algorithm. A hash pattern can also be called a variant of the SHA2 algorithm. For example, the hash pattern can be SHA-224 / 256, SHA-256, SHA-384 / 512, SHA-512, or SHA-t / 512, where t is commonly 224 or 256.
[0044] Different data hash modes correspond to different hash value output lengths, data block sizes, message word lengths, or iteration rounds. For example, as shown in Table 1 below.
[0045] Table 1
[0046]
[0047]
[0048] For example, in the data hash system in Figure 1 The processor 103 sends a data hash instruction to the configuration module in the hardware accelerator 101; the configuration module parses the data hash instruction to obtain data identification information of the data to be hashed, data length of the data to be hashed, data hash mode corresponding to the data to be hashed, and hash value output length.
[0049] S402, according to the data identification information, request the target hardware device to obtain the data to be hashed.
[0050] The data to be hashed is sent to the hardware accelerator in the form of multiple pieces of data to be hashed.
[0051] For example, in the data hash system in Figure 1 The control module requests the target hardware device 102 to obtain the data to be hashed based on the data identification information of the data to be hashed; the target hardware device 102 sends the control module of the hardware accelerator 101 in the form of multiple pieces of data to be hashed.
[0052] S403, receive each piece of data to be hashed and perform data hash processing on each piece of data to be hashed.
[0053] In an example, when the control module of the hardware accelerator 101 receives each piece of data to be hashed issued by the target hardware device 102, it transmits a calculation control signal to the core operation module, and the core operation module performs data hash processing on each piece of data to be hashed. S404, when receiving the data to be hashed issued by the target hardware device and carrying an end identifier, it is determined that the data to be hashed is received, and according to the data length and the data hash mode, the data to be hashed is filled to obtain target data.
[0054] The target data includes multiple data blocks. Each data block occupies K bits. K matches the data hash mode. For example, for SHA-224 / 256, SHA-256, K is 512; for SHA-384 / 512, SHA-512, SHA-t / 512, K is 1024.
[0055] The data length of the target data needs to meet the requirements of the SHA2 algorithm. The data length of the target data matches the data hash mode. The number of bits occupied by the data length of the target data is an integer multiple of K.
[0056] For example, for SHA-224 / 256, SHA-256, the number of bits occupied by the data length of the target data required by the SHA2 algorithm is an integer multiple of 512. For example, for SHA-384 / 512, SHA-512, SHA-t / 512, the number of bits occupied by the data length of the target data required by the SHA2 algorithm is an integer multiple of 1024.
[0057] The corresponding padding rule of the data padding can be adding a binary number "first preset value" at the end of the data to be hashed, and then adding a number of binary numbers "second preset value", so that the data length after padding is less than an integer multiple of K Q bits. Finally, a binary number of Q bits is added at the end of the padded data to obtain the target data.
[0058] The Q bits represent the data length of the data to be hashed. Q has a one-to-one correspondence with the data hash mode. Wherein, when K is 512, Q is 64; when K is 1024, Q is 128.
[0059] The first preset value can be 1. The second preset value can be 0.
[0060] For example, when the control module of the hardware accelerator 101 receives the last message to be hashed carrying the end identifier issued by the target hardware device 102, it is determined that the data to be hashed is received, and according to the configuration of the data length and the data hash mode in the configuration module, the data to be hashed is padded according to the corresponding padding rule of the data padding to obtain the target data, and the target data is grouped to obtain multiple data blocks, and each data block is transmitted to the core operation module through the calculation control signal, and the block-msg signal is set to the value corresponding to the data hash mode.
[0061] The calculation control signal includes a first control signal (init_cmd signal) and a second control signal (next_cmd signal). The init_cmd signal and the next_cmd signal are used to inform the core operation module whether each data block is the first iteration round. If the init_cmd signal is high, it indicates that each data block is the first iteration round; if the init_cmd signal is high, it indicates that each data block is not the first iteration round.
[0062] S405, based on the data hash mode, the target data is hashed to obtain the target hash value corresponding to the data to be hashed.
[0063] The length of the target hash value is the same as the length of the hash value output.
[0064] Each data block corresponds to one iteration loop; each iteration loop corresponds to multiple iteration rounds.
[0065] In one example, the core computing module obtains the target initial value corresponding to the first iteration round of each data block based on the data hash pattern. Based on each data block and the target initial value corresponding to the first iteration round, the module performs data hashing on each data block to obtain the intermediate hash value corresponding to each data block, and then obtains the target hash value corresponding to the data to be hashed.
[0066] In this process, each time the core computing module obtains an intermediate hash value, it sends the `ready` and `digest_vld` signals to the control module, and simultaneously outputs the `digest` value as the intermediate hash value. This process continues until all data included in the target data has undergone hash processing. The control module then outputs the `sha2_rsl` signal as the final target hash value corresponding to the data to be hashed, and simultaneously sends the `sha2_rsl_vld` signal.
[0067] The sha2_rsl_vld signal is used to indicate whether the calculated target hash value is valid.
[0068] The ready signal is used to indicate that the calculation of the intermediate hash value for each data block has ended.
[0069] The digest_vld signal is used to indicate whether the calculated intermediate hash value is valid.
[0070] Optionally, the control module can simultaneously transmit the messages to be hashed to the core computing module while receiving multiple messages to be hashed from the target hardware device, so that the core computing module can perform data hashing processing simultaneously.
[0071] based on Figure 4 The method shown allows the hardware accelerator to receive a data hashing instruction from the processor and request the data to be hashed from the target hardware device based on the data identification information in the data hashing instruction. When the hardware device sends a hashing message carrying an end identifier to confirm that the data to be hashed has been received, the data to be hashed is filled to obtain the target data. Based on the data hashing mode, the target data is hashed to obtain the target hash value corresponding to the data to be hashed.
[0072] Since the hardware accelerator can determine that the to-be-hashed data receiving is completed based on the to-be-hashed message carrying the end identifier, it is not necessary to count the data amount of the to-be-hashed data by using a large number of internal counters to determine that the to-be-hashed data receiving is completed, thereby saving the power consumption of the hardware accelerator and enabling the filling to be completed synchronously in the data end period without affecting the performance of the hardware accelerator. In addition, the hardware accelerator can also perform data filling on the to-be-hashed data to obtain target data in a format length required by the hash algorithm, so that the hardware accelerator maintains high efficiency and smoothness of data processing, avoids performance bottlenecks caused by the data filling link, and improves the versatility of the hardware accelerator. The hardware accelerator can also be compatible with different data hashing modes to realize logical sharing of the data hashing modes, thereby enhancing the versatility and flexibility of the hardware accelerator, reducing the complexity and cost of developing different hardware structures for different modes, and enabling the hardware accelerator to be applicable to various application requirements and scenarios, thereby enhancing its competitiveness in the market.
[0073] In some optional examples, on the basis of the foregoing embodiments, when the data length is equal to n times of K, the target data is obtained by performing data filling on the to-be-hashed data according to the data length and the data hashing mode, n is a positive integer, and the following method steps are used, which are specifically shown in Figure 5 Figure 5 Another flowchart of a data hashing method provided in the embodiments of the present application is shown in
[0074] S501, the first preset number of first preset values, the second preset number of second preset values, and the length value are combined to obtain the filling data.
[0075] The number of bit positions occupied by the filling data is K.
[0076] The first preset value is 1, and the second preset value is 0.
[0077] The length value (datalenth) is a binary string corresponding to the data length, and the number of bit positions occupied by the binary string is Q.
[0078] The first preset number can be 1. The second preset number can be K-Q-1.
[0079] For example, when K is 512 and the data length of the to-be-hashed data is K*n, the control module combines 1 of 1, 447 of 0, and the length value after transmitting the last 512-bit data in the to-be-hashed data to the core operation module to obtain the filling data, which is {1’d1, 447’d0, datalenth}.
[0080] S502, performing data padding on the data to be hashed based on the padding data to obtain target data.
[0081] In some optional examples, on the basis of the foregoing embodiments, when the data length is greater than n times of K, the data to be hashed is padded according to the data length and the data hashing mode to obtain target data, as shown in the following method steps, for details, refer to Figure 6 , Figure 6 Another data hashing method provided by the embodiments of the present application is shown in the flowchart, which includes:
[0082] S601, generating a first mask according to K and the data length.
[0083] In one example, the first quantity of the first preset value is determined according to the data length, the second quantity of the second preset value is determined according to the first quantity and K, and the first mask is generated according to the first quantity of the first preset value and the second quantity of the second preset value.
[0084] The second quantity is the difference between the first quantity and K.
[0085] When K is 512, the first mask occupies 512 bits; when K is 1024, the first mask occupies 1024 bits.
[0086] For example, taking the data length of 100 and K of 512 as an example, the first mask (data_strob) is: "111111111…0000…", which is composed of 100 1s and 412 0s, and a total of 512 binary bits.
[0087] S602, determining a second mask according to the first mask.
[0088] In one example, the second mask is obtained by modifying "1" to "0" in the first mask and modifying the first "0" to "1".
[0089] S603, performing AND operation on the last data block in the data to be hashed and the first mask to obtain a first calculation result.
[0090] The last data block in the data to be hashed is the last piece of data remaining in the data to be hashed except for n times of K.
[0091] S604, performing OR operation on the first calculation result and the second mask to obtain a second calculation result.
[0092] S605, obtaining padding data according to the data length and the second calculation result.
[0093] In an example, when the data length is greater than n times of K and less than the sum of n times of K and K-Q, the Q low bits included in the second calculation result are replaced by the length value.
[0094] In another example, when the data length is greater than or equal to the sum of n times of K and K-Q and less than (n+1) times of K, the second calculation result is combined with a third number of second preset values to obtain first padding data; a fourth number of second preset values is combined with the length value to obtain second padding data; and the padding data is obtained according to the first padding data and the second padding data.
[0095] The fourth number is K-Q.
[0096] The number of bits occupied by the first padding data is K.
[0097] The number of bits occupied by the second padding data is K.
[0098] It can be understood that the first padding data and the second padding data constitute the final padding data, and the final padding data is still an integer multiple of K.
[0099] S606, based on the padding data, data padding is performed on the to-be-hashed data to obtain target message.
[0100] In an example, based on the padding data, the padding data is added after the to-be-hashed data to obtain target data.
[0101] It can be understood that the data length of the target data is an integer multiple of K, which meets the requirements of the SHA2 algorithm.
[0102] In some optional examples, on the basis of the foregoing embodiments, as introduced in the foregoing, based on the data hash mode, data hash processing is performed on the target data to obtain a target hash value corresponding to the data hash mode, such as the following method steps, which are specifically described with reference to Figure 7 shown in Figure 7 is a flowchart of another data hash method provided by the embodiments of the present application, which includes:
[0103] S701, in the first iteration round in each iteration cycle, determining that the target initial value corresponding to the first iteration round is an initial value matched with the data hash mode, and in the non-first iteration round in each iteration cycle, determining that the target initial value corresponding to the non-first iteration round is an iteration calculation result of the last round of the non-first iteration round.
[0104] In an example, the core operation module receives the init_cmd signal and the next_cmd signal sent by the control module, and determines the target initial value used in each iteration round according to the init_cmd signal and the next_cmd signal. If the init_cmd signal is high, it means the first iteration round. In the first iteration round in each iteration loop, the target initial value corresponding to the first iteration round is determined to be the initial value matched with the data hash mode. At this time, the initial value matched with the data hash mode is used as the target initial value to participate in the first iteration round.
[0105] If the next_cmd signal is high, it means a non-first iteration round. In the non-first iteration round in each iteration loop, the target initial value corresponding to the non-first iteration round is determined to be the iteration calculation result of the last round of the non-first iteration round. At this time, the last iteration calculation result is used as the target initial value to participate in the iteration round.
[0106] Optionally, for the data hash mode SHA-t / 512, the initial value matched with the data hash mode can be obtained through the following calculation logic:
[0107]
[0108] H (0) = SHA-512 (“SHA-t / 512”)
[0109] is the initial value matched with the data hash mode SHA-512. H (0) is the initial value matched with the data hash mode SHA-t / 512 calculated according to different t values. a5a5a5a5a5a5a5a5 is a constant. is an intermediate value of the exclusive or calculation, which is used to substitute H (0) in the corresponding calculation logic to obtain H (0) .
[0110] S702, according to the target initial value, each data block, and the plurality of compression function calculation paths corresponding to the data hash mode, performing data hash processing on each data block included in the target data to obtain a hash value corresponding to the data hash mode.
[0111] S703, determining the target hash value based on the hash value and the hash value output length.
[0112] For example, when the data hash mode is SHA2-512, the number of bits occupied by the hash value is 512, the output length of the hash value is 512 bits, and the target hash value is determined as the hash value corresponding to the data hash mode. When the data hash mode is SHA2-t / 512, the number of bits occupied by the hash value is 512, the output length of the hash value is t bits, and the target hash value is determined as the hash value truncated to the leftmost t bits of the hash value corresponding to the data hash mode.
[0113] Optionally, the data hash modes supported by the hardware accelerator include a first data hash mode and a second data hash mode. The first data hash mode corresponds to the first type of compression function calculation path and the second type of compression function calculation path, and the second data hash mode corresponds to the first type of compression function calculation path and the third type of compression function calculation path. The first data hash mode and the second data hash mode share the hardware logic circuit corresponding to the first type of compression function calculation path.
[0114] It can be understood that the hardware logic circuit of the first type of compression function calculation path is shared by the two data hash modes, avoiding repeated design and layout of the same function circuit, significantly reducing the chip area occupation and manufacturing complexity. Supporting multiple hash modes on the same hardware basis enables the accelerator to adapt to the needs of different application scenarios, improving the versatility and flexibility of the hardware.
[0115] In summary, the control module is configured to perform message padding on the to-be-hashed data according to the data hash mode signal and the data length signal of the to-be-hashed data, and to transmit the padded data to the core module through the calculation control signal. After all data is received, the calculation process is controlled according to the end identification signal, and the calculation result and the result validity signal are output. In the SHA2-t / 512 mode, the target initial value of the iteration round can be pre-calculated and transmitted to the core module.
[0116] The core operation module includes two different bit-width hash value outputs, which are combined by sub-modules supporting different SHA2 data hash modes, and is responsible for data block expansion and data block iteration calculation to complete data hash processing. The initial value used for each iteration round is determined according to the init_cmd and next_cmd signals from the control module for iteration calculation. The core operation module supports SHA-224 / 256, SHA-256, SHA-384 / 512, SHA-512, and SHA-t / 512 modes, and implements SHA2 algorithm processing for different input data blocks through internal logic while ensuring logic reusability. By adjusting the parameterized bit width and the multi-mode control signal (data hash mode information), compatibility with different data hash modes is achieved, and all modes are logically shared at the hardware level, improving the versatility and flexibility of the hardware accelerator.
[0117] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software on a general hardware platform as necessary, and of course can also be implemented by hardware, but in many cases the former is a better embodiment.
[0118] The embodiments of the present application also provide a hardware accelerator, as shown in Figure 8 Figure 8 The hardware accelerator provided by the embodiments of the present application has the structure diagram as shown in the figure.
[0119] The hardware accelerator comprises a transceiving module 801 configured to receive a data hash instruction issued by a processor, the data hash instruction carrying data identification information of to-be-hashed data, a data length of the to-be-hashed data, a data hash mode corresponding to the to-be-hashed data, and a hash value output length; and the transceiving module 801 is configured to request a target hardware device to obtain the to-be-hashed data according to the data identification information, wherein the to-be-hashed data is sent to the hardware accelerator in the form of a plurality of to-be-hashed messages.
[0120] A processing module 802 is configured to receive each to-be-hashed message and perform data hash processing on each to-be-hashed message; when it is determined that the to-be-hashed data reception is completed after receiving a to-be-hashed message carrying an end identifier issued by the target hardware device, the processing module 802 is configured to perform data padding on the to-be-hashed data according to the data length and the data hash mode to obtain target data; and the processing module 802 is configured to perform data hash processing on the target data based on the data hash mode to obtain a target hash value corresponding to the to-be-hashed data, the length of the target hash value being consistent with the hash value output length.
[0121] In some optional embodiments, in the data hash mode, the target data comprises a plurality of data blocks, and each data block comprises a plurality of data segments; when the data length is equal to n times of K, the processing module 802 is specifically configured to combine a first preset number of first preset values, a second preset number of second preset values, and a length value to obtain padding data, the number of bits occupied by the padding data being K, the length value being a binary string corresponding to the data length, and the number of bits occupied by the binary string being Q, Q having a one-to-one correspondence with the data hash mode, and n being a positive integer; and the processing module 802 is configured to perform data padding on the to-be-hashed data based on the padding data to obtain the target data.
[0122] In some optional embodiments, when the data length is greater than n times of K, the processing module 802 is specifically configured to generate a first mask according to K and the data length; determine a second mask according to the first mask; perform an AND operation on the last data block in the to-be-hashed data and the first mask to obtain a first calculation result; perform an OR operation on the first calculation result and the second mask to obtain a second calculation result; obtain padding data according to the data length and the second calculation result; and perform data padding on the to-be-hashed data based on the padding data to obtain the target message.
[0123] In some optional embodiments, when the data length is greater than n times of K and less than a sum of n times of K and K-Q, the processing module 802 is specifically configured to replace Q low bits included in the second calculation result with a length value.
[0124] In some optional embodiments, when the data length is greater than or equal to a sum of n times of K and K-Q and less than n+1 times of K, the processing module 802 is specifically configured to combine the second calculation result and a third number of second preset values to obtain first padding data; combine a fourth number of second preset values and the length value to obtain second padding data, the fourth number being K-Q; and obtain the padding data according to the first padding data and the second padding data.
[0125] In some optional embodiments, each data block corresponds to an iteration cycle, and each iteration cycle corresponds to a plurality of iteration rounds; the processing module 802 is specifically configured to, in a first iteration round in each iteration cycle, determine a target initial value corresponding to the first iteration round as an initial value matched with the data hashing mode, and in a non-first iteration round in each iteration cycle, determine a target initial value corresponding to the non-first iteration round as an iteration calculation result of a previous round of the non-first iteration round; perform data hashing processing on each data block included in the target data according to the target initial value, each data block, and a plurality of compression function calculation paths corresponding to the data hashing mode, to obtain a hash value corresponding to the data hashing mode; and determine a target hash value based on the hash value and a hash value output length.
[0126] In some optional embodiments, the data hashing mode includes a first data hashing mode and a second data hashing mode; the first data hashing mode corresponds to a first type of compression function calculation path and a second type of compression function calculation path, and the second data hashing mode corresponds to the first type of compression function calculation path and a third type of compression function calculation path; the first data hashing mode and the second data hashing mode share a hardware logic circuit corresponding to the first type of compression function calculation path.
[0127] The features of the embodiments corresponding to the hardware accelerator can be referred to the related descriptions of the embodiments corresponding to the data hashing method, which will not be repeated here.
[0128] Embodiments of the present application also provide an electronic device, such as Figure 9 as shown, Figure 9 A hardware structure schematic diagram of an electronic device provided by embodiments of the present application is shown in FIG. 1. The electronic device includes a processor 10 and a memory 20, wherein the memory 20 stores a computer program, and the processor 10 is configured to execute the computer program to perform the steps in any of the above data hashing method embodiments.
[0129] Embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above data hashing method embodiments when executed.
[0130] In an exemplary embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.
[0131] Embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is executed by a processor to implement the steps in any of the above data hashing method embodiments.
[0132] Embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above data hashing method embodiments.
[0133] Those skilled in the art can further appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.
[0134] The above describes in detail the data hashing method, the hardware accelerator, the electronic device and the storage medium provided by the present application. The principles and implementation manners of the present application are described by using specific examples, and the above description of the embodiments is only used to help understand the method of the present application and the core idea thereof. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.
Claims
1. A method of data hashing, characterized by, The method is executed by a hardware accelerator, and the method comprises: receiving a data hash instruction issued by a processor, the data hash instruction carrying data identification information of to-be-hashed data, data length of the to-be-hashed data, a data hash mode corresponding to the to-be-hashed data, and a hash value output length; requesting the to-be-hashed data from a target hardware device according to the data identification information, wherein the to-be-hashed data is sent to the hardware accelerator in the form of a plurality of to-be-hashed messages; receiving each of the to-be-hashed messages and performing data hash processing on each of the to-be-hashed messages; when it is determined that the to-be-hashed data is received completely after receiving the to-be-hashed message carrying an end identifier issued by the target hardware device, performing data padding on the to-be-hashed data according to the data length and the data hash mode to obtain target data; performing data hash processing on the target data based on the data hash mode to obtain a target hash value corresponding to the to-be-hashed data, the length of the target hash value being consistent with the hash value output length.
2. The method of claim 1, wherein, In the data hash mode, the target data comprises a plurality of data blocks, and each of the data blocks occupies K bits. When the data length is equal to n times of the K, the performing data padding on the to-be-hashed data according to the data length and the data hash mode to obtain target data comprises: combining a first preset number of first preset values, a second preset number of second preset values, and a length value to obtain padding data, the padding data occupying K bits, the length value being a binary string corresponding to the data length, and the binary string occupying Q bits, the Q having a one-to-one correspondence with the data hash mode, and n being a positive integer; performing data padding on the to-be-hashed data based on the padding data to obtain the target data.
3. The method of claim 2, wherein, When the data length is greater than n times of the K, the performing data padding on the to-be-hashed data according to the data length and the data hash mode to obtain target data comprises: generating a first mask according to the K and the data length; determining a second mask according to the first mask; performing AND operation on a last data block in the to-be-hashed data and the first mask to obtain a first calculation result; performing OR operation on the first calculation result and the second mask to obtain a second calculation result; obtaining the padding data according to the data length and the second calculation result; performing data padding on the to-be-hashed data based on the padding data to obtain the target data.
4. The method of claim 3, wherein, The obtaining the padding data according to the data length and the second calculation result comprises: when the data length is greater than n times of the K and less than a sum of n times of the K and K-Q, replacing Q low bits included in the second calculation result with the length value.
5. The method of claim 3, wherein, The obtaining the padding data according to the data length and the second calculation result comprises: when the data length is greater than or equal to the sum of n times of the K and K-Q, and less than (n+1) times of the K, the second calculation result and the second preset value of the third quantity are combined to obtain first padding data; the second preset value of the fourth quantity and the length value are combined to obtain second padding data, and the fourth quantity is K-Q; the padding data is obtained according to the first padding data and the second padding data.
6. The method according to any one of claims 2-5, characterized in that, Each of the data blocks corresponds to an iteration cycle; each of the iteration cycles corresponds to multiple iteration rounds; and the data hash processing of the target data based on the data hash mode to obtain the target hash value corresponding to the data hash mode comprises: in the first iteration round in each iteration cycle, the target initial value corresponding to the first iteration round is determined as an initial value matched with the data hash mode, and in the non-first iteration round in each iteration cycle, the target initial value corresponding to the non-first iteration round is determined as the iteration calculation result of the last round of the non-first iteration round; the data hash processing of each of the data blocks included in the target data is performed according to the target initial value, each of the data blocks, and the multiple compression function calculation paths corresponding to the data hash mode, to obtain the hash value corresponding to the data hash mode; the target hash value is determined based on the hash value and the hash value output length.
7. The method of claim 6, wherein, The data hash mode comprises a first data hash mode and a second data hash mode. The first data hash mode corresponds to a first type of compression function calculation path and a second type of compression function calculation path, the second data hash mode corresponds to the first type of compression function calculation path and a third type of compression function calculation path, and the first data hash mode and the second data hash mode share the hardware logic circuit corresponding to the first type of compression function calculation path.
8. A hardware accelerator, characterized by The hardware accelerator comprises: a transceiver module configured to receive a data hash instruction issued by a processor, the data hash instruction carrying data identification information of to-be-hashed data, a data length of the to-be-hashed data, a data hash mode corresponding to the to-be-hashed data, and a hash value output length; and request the to-be-hashed data from a target hardware device according to the data identification information, wherein the to-be-hashed data is sent to the hardware accelerator in the form of multiple to-be-hashed messages; a processing module configured to receive each of the to-be-hashed messages and perform data hash processing on each of the to-be-hashed messages; when it is determined that the to-be-hashed data is received completely after receiving the to-be-hashed message carrying an end identifier issued by the target hardware device, perform data padding on the to-be-hashed data according to the data length and the data hash mode to obtain target data; and perform data hash processing on the target data based on the data hash mode to obtain a target hash value corresponding to the to-be-hashed data, the length of the target hash value being consistent with the hash value output length.
9. An electronic device, comprising: a memory configured to store a computer program; A processor for implementing the steps of the data hashing method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, A computer readable storage medium having stored therein a computer program, wherein the computer program, when executed by a processor, implements the steps of the data hashing method according to any one of claims 1 to 7.