Test method, control device and test equipment of DRAM (Dynamic Random Access Memory)
By detecting changes in neighboring memory cells under initial voltage and frequency settings in DRAM, it is possible to confirm whether the tested memory cell is a faulty cell. Furthermore, by adjusting the voltage and frequency, the detection accuracy is improved, thus resolving the write failure and data reversal issues caused by interference between adjacent memory cells in DRAM.
Patent Information
- Application Number
- CN202511106956.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2025-11-21
AI Technical Summary
Interference between adjacent memory cells in DRAM can cause memory cell write failures or data reversals, and existing technologies make it difficult to accurately detect faulty memory cells.
By setting the operating voltage and frequency of the DRAM to different preset values for the tested memory cell and neighboring memory cells, and observing the changes in the neighboring memory cell values, it is possible to confirm whether the tested memory cell is a faulty cell. Further adjustments to the voltage and frequency can then be made to improve the accuracy of the detection.
It effectively detects and confirms faulty memory cells in DRAM, improving the accuracy of detection.
Smart Images
Figure CN120998285A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of DRAM testing technology, and in particular to a DRAM testing method, control device, and testing equipment. Background Technology
[0002] DRAM (Dynamic Random Access Memory) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. The memory cells within DRAM exhibit some variation in quality and reliability. This variation is caused by a combination of factors, including the randomness of the manufacturing process, material defects, thermal stress, and design tolerances.
[0003] Among the many types of DRAM failures, one is particularly unique: interference can occur between adjacent memory cells, affecting one of them. When a neighboring memory cell of the affected cell is written with a "1" or "0", the write operation fails. Alternatively, in certain modes, the written data value may be "perturbed" or "inverted," causing the system to encounter errors when reading data from that memory cell. Summary of the Invention
[0004] The main objective of this invention is to provide a DRAM testing method, control device, and testing equipment, aiming to improve the accuracy of DRAM testing.
[0005] To achieve the above objectives, the present invention proposes a DRAM testing method, the DRAM testing method comprising:
[0006] With the DRAM operating voltage and operating frequency being the initial operating voltage and initial operating frequency, the value of the tested memory cell is set to the first preset value, and the value of the neighboring memory cell is set to the second preset value.
[0007] When the value of the tested storage cell is set to a first preset value and the value of the neighboring storage cell is set to a second preset value, the value of the neighboring storage cell is adjusted from the second preset value to the first preset value.
[0008] When the value of the neighboring storage unit changes, the test storage unit is determined to be a faulty storage unit based on the change status of the value in the test storage unit.
[0009] The neighboring storage unit is the adjacent storage unit of the tested storage unit, and one of the first preset value and the second preset value is 0 and the other is 1.
[0010] In one embodiment, the step of determining whether the tested storage unit is a faulty storage unit based on the change in the value of the neighboring storage unit when the value of the neighboring storage unit changes specifically includes:
[0011] If the value of the tested storage unit is inconsistent with the first preset value when the state of the neighboring storage unit changes, the tested storage unit is confirmed as a faulty storage unit, and the physical address of the tested storage unit is fed back.
[0012] If the value of the tested storage unit is consistent with the first preset value when the state of the neighboring storage unit changes, then the tested storage unit is confirmed not to be a faulty storage unit.
[0013] In one embodiment, after the step of confirming that the tested storage unit is not a faulty storage unit when the value of the tested storage unit is consistent with a first preset value in the event of a state change in the neighboring storage unit, the method further includes:
[0014] If the tested memory cell is not a faulty memory cell, adjust the operating voltage and operating frequency of the DRAM and repeat the above steps.
[0015] In one embodiment, the step of adjusting the operating voltage and operating frequency of the DRAM when the tested memory cell is not a faulty memory cell specifically includes:
[0016] If the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the initial operating voltage and initial operating frequency to the first preset voltage and first preset frequency, respectively.
[0017] When the operating voltage and operating frequency of the DRAM are adjusted from the initial operating voltage and initial operating frequency to the first preset voltage and first preset frequency, and the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the first preset voltage and the second preset frequency to the third preset voltage and the third preset frequency, respectively.
[0018] When the operating voltage and operating frequency of the DRAM are adjusted from a first preset voltage and a second preset frequency to a third preset voltage and a third preset frequency, respectively, and the tested memory cell is not a faulty memory cell, the operating voltage of the DRAM is adjusted to the first preset voltage.
[0019] When the operating voltage of the DRAM is adjusted from the third preset voltage to the first preset voltage, and the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the first preset voltage and the third preset frequency to the third preset voltage and the first preset frequency, respectively.
[0020] Wherein, the initial operating voltage is a second preset voltage, and the initial operating frequency is a second preset frequency.
[0021] In one embodiment, after adjusting the operating voltage and frequency of the DRAM and repeating the above steps when the tested memory cell is not a faulty memory cell, the method further includes:
[0022] After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, adjust the value of the neighboring memory cells and repeat the above steps.
[0023] In one embodiment, the step of adjusting the value of the neighboring memory cell after adjusting the operating voltage and frequency of the DRAM, repeating the above steps, and ensuring that none of the tested memory cells are faulty memory cells, specifically involves:
[0024] After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, the value of the neighboring memory cell is adjusted from the second preset value to the first preset value, and the above steps are repeated.
[0025] In one embodiment, after adjusting the value of the neighboring storage unit from a second preset value to a first preset value and repeating the above steps, the method further includes:
[0026] After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, the value of the neighboring memory cell is alternately adjusted from the second preset value and the first preset value within a first preset time period, and the above steps are repeated.
[0027] The present invention also proposes a control device comprising a memory, a processor, and a DRAM test program stored in the memory and executable on the processor, the DRAM test program being configured to implement the steps of the DRAM test method as described in any of the preceding claims.
[0028] The present invention also proposes a testing device, which includes the control device as described above.
[0029] This invention proposes a DRAM testing method that can specifically improve the accuracy of DRAM detection. By setting the DRAM's operating voltage and frequency to initial operating voltage and frequency, respectively, the value of the tested memory cell is set to a first preset value, and the values of neighboring memory cells are set to a second preset value. When the tested memory cell's value is set to the first preset value and the neighboring memory cells' values are set to the second preset value, the values of the neighboring memory cells are adjusted from the second preset value to the first preset value. Based on the changes in the values of the neighboring memory cells, it is determined whether the tested memory cell is a faulty memory cell. Specifically, if the value of the tested memory cell also changes when the state of the neighboring memory cells changes, then the tested memory cell can be confirmed as a faulty memory cell. This method can effectively detect faulty memory cells. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0031] Figure 1 This is a flowchart illustrating the DRAM testing method of the present invention;
[0032] Figure 2 This is a flowchart illustrating an embodiment of the DRAM testing method of the present invention;
[0033] Figure 3 This is a flowchart illustrating another embodiment of the DRAM testing method of the present invention;
[0034] Figure 4 This is an embodiment of the adjacent memory cell model structure in the DRAM testing method of the present invention;
[0035] Figure 5 This is yet another embodiment of the adjacent memory cell model structure in the DRAM testing method of the present invention;
[0036] Figure 6 This is yet another embodiment of the adjacent memory cell model structure in the DRAM testing method of the present invention.
[0037] Explanation of icon numbers:
[0038] 10. The storage unit under test; 20. The neighboring storage unit.
[0039] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0041] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.
[0042] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.
[0043] DRAM (Dynamic Random Access Memory) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. The memory cells within DRAM exhibit some variation in quality and reliability. This variation is caused by a combination of factors, including the randomness of the manufacturing process, material defects, thermal stress, and design tolerances.
[0044] Among the many types of DRAM failures, one is particularly unique: interference can occur between adjacent memory cells, affecting one of them. When a neighboring memory cell of the affected cell is written with a "1" or "0", the write operation fails. Alternatively, in certain modes, the written data value may be "perturbed" or "inverted," causing the system to encounter errors when reading data from that memory cell.
[0045] To solve the above problems, refer to Figure 1 and Figures 4 to 5This invention proposes a DRAM testing method, which includes:
[0046] Step S100: With the DRAM operating voltage and operating frequency being the initial operating voltage and initial operating frequency respectively, the value of the tested memory cell is set to a first preset value, and the value of the neighboring memory cell is set to a second preset value;
[0047] Step S200: When the value of the tested storage cell is set to a first preset value and the value of the neighboring storage cell is set to a second preset value, the value of the neighboring storage cell is adjusted from the second preset value to the first preset value.
[0048] Step S300: When the value of the neighboring storage cell changes, the test storage cell is confirmed as a faulty storage cell based on the change status of the value in the test storage cell.
[0049] The neighboring storage unit 20 is the adjacent storage unit of the tested storage unit 10, and one of the first preset value and the second preset value is 0 and the other is 1.
[0050] Understandably, there are three types of adjacent memory cell structures in DRAM: cross-shaped, 3x3 grid, and strip-shaped. However, the aforementioned disturbed memory cells are not in an unstable state; the data they store can be disturbed at certain times or under certain conditions, resulting in the stored data being sometimes accurate and sometimes incorrect.
[0051] In this embodiment, the DRAM is powered to operate. It is understood that the DRAM requires continuous power to maintain the charge in the memory cells, thereby ensuring data integrity. Since the DRAM uses capacitors to store each bit of information, and these capacitors can leak current, causing the charge to gradually dissipate, periodic data refresh is necessary, a process that also requires power. Secondly, the DRAM needs energy to perform various operations, such as reading, writing, and refreshing. Each operation requires specific voltage levels and currents to correctly control the state changes of the internal circuitry. Furthermore, appropriately increasing the operating voltage can increase the switching speed of transistors in the DRAM, potentially improving the data transfer rate of the memory module. However, excessively high voltage can cause signal interference and other electrical problems, thus degrading performance. Therefore, the DRAM operating voltage needs to be set within a suitable range. It is understood that the DRAM operating frequency directly affects the data transfer rate; a higher operating frequency allows for the transfer of more data per unit time, thereby improving the overall system performance. While higher frequencies theoretically offer faster speeds, they may also be accompanied by higher latency because control signals require more time to stabilize. Therefore, the DRAM operating frequency needs to be set within a suitable frequency range. To ensure the stability and accuracy of DRAM testing, the DRAM's operating voltage and frequency were set as initial operating voltage and frequency, respectively. These initial operating voltage and frequency were determined by the R&D personnel after multiple tests to ensure stable and accurate DRAM testing.
[0052] In this embodiment, one of the first preset value and the second preset value is 0, and the other is 1. It can be understood that in a DRAM memory cell, "1" indicates that the capacitor in the memory cell is charged to a higher voltage level, while "0" indicates that the capacitor in the memory cell is at a lower voltage level or is almost uncharged. By setting the value in the tested memory cell 10 to the first preset value and the value in the neighboring memory cell 20 to the second preset value, with the first and second preset values being 0 or 1 respectively, the value of the tested memory cell 10 is made different from the value of the neighboring memory cell 20. As can be seen from the above, some memory cells are easily affected by interference from neighboring cells, causing the written value to be "perturbed" or "reversed." Therefore, by setting the value in the tested memory cell 10 to the first preset value, setting the value in the neighboring memory cell 20 to the second preset value, and then adjusting the value of the neighboring memory cell 20 from the second preset value to the first preset value, the value of the neighboring memory cell 20 is changed. By checking whether the value in the tested storage cell 10 has changed in the case of a change in the value of the neighboring storage cell 20, it can be confirmed whether the tested storage cell 10 is a faulty storage cell.
[0053] refer to Figure 2 The specific steps for determining whether a tested storage unit is a faulty storage unit based on the value change status in the tested storage unit when the value of the neighboring storage unit changes are as follows:
[0054] Step S310: If the value of the tested storage unit is inconsistent with the first preset value when the state of the neighboring storage unit changes, the tested storage unit is confirmed to be a faulty storage unit, and the physical address of the tested storage unit is fed back.
[0055] Step S320: If the value of the tested storage unit is consistent with the first preset value when the state of the neighboring storage unit changes, then the tested storage unit is confirmed to be a faulty storage unit.
[0056] In this embodiment, when the value of the tested storage unit 10 is a first preset value, the value of the neighboring storage unit 20 is adjusted from a second preset value to the first preset value. The neighboring storage unit 20 is the adjacent storage unit of the tested storage unit 10. Therefore, the sudden change in the value of the adjacent storage units of the tested storage unit 10 strengthens the interference experienced by the tested storage unit 10. By detecting whether the value of the tested storage unit 10 at this time corresponds to the first preset value, it is confirmed whether the tested storage unit 10 is stable, and thus whether it is a faulty storage unit. For example, the value of the tested storage unit 10 is set to 1, and the value of the neighboring storage unit 20 is set to 0. After the tested storage unit 10 and the neighboring storage unit 20 stabilize, the value of the neighboring storage unit 20 is adjusted from 0 to 1. By detecting whether the value of the tested storage unit 10 remains at 1, it is confirmed whether the tested storage unit 10 is a faulty storage unit. If the value of the neighboring storage unit 20 is adjusted from 0 to 1, and the value of the tested storage unit 10 remains 1, then the tested storage unit 10 is not a faulty storage unit. If the value of the neighboring storage unit 20 is adjusted from 0 to 1, and the value of the tested storage unit 10 is not 1, then the tested storage unit 10 is a faulty storage unit.
[0057] By setting the DRAM's operating voltage and frequency to initial operating voltage and frequency, respectively, the value of the tested memory cell 10 is set to a first preset value, and the value of the neighboring memory cell 20 is set to a second preset value. When the value of the tested memory cell 10 is set to the first preset value and the value of the neighboring memory cell 20 is set to the second preset value, the value of the neighboring memory cell 20 is adjusted from the second preset value to the first preset value. When the value of the neighboring memory cell 20 changes, the state of the value change in the tested memory cell 10 is used to determine whether the tested memory cell 10 is a faulty memory cell. Specifically, if the value of the tested memory cell 10 also changes when the state of the neighboring memory cell 20 changes, then the tested memory cell 10 can be confirmed as a faulty memory cell. This method can effectively detect faulty memory cells.
[0058] In one embodiment of the present invention, after the step of confirming that the tested storage unit is not a faulty storage unit when the value of the tested storage unit is consistent with a first preset value in the event of a state change in the neighboring storage unit, the method further includes:
[0059] If the tested memory cell is not a faulty memory cell, adjust the operating voltage and operating frequency of the DRAM and repeat the above steps.
[0060] It is important to understand that the impact of the surrounding memory cells on the tested memory cell 10 varies depending on the operating voltage and frequency. The charge storage capacity of capacitors within a memory cell is directly related to voltage. When the operating voltage decreases, the amount of charge stored in the capacitors decreases, resulting in a smaller voltage difference between logic "1" and "0". This makes capacitive coupling in the surrounding memory cells more likely to cause voltage fluctuations in the tested memory cell 10 to exceed the threshold, thus increasing the likelihood of bit flips. Furthermore, an increase in the DRAM operating frequency increases the number of accesses to a specific row per unit time. Shorter cycle times lead to a relatively longer refresh interval, resulting in faster accumulation of electrical stress in adjacent rows, making interference errors easier to trigger. However, memory cells without potential faults are not affected by these voltage changes. Therefore, to further confirm that the tested memory cell 10 is without potential faults, it is necessary to adjust the DRAM's operating voltage and frequency.
[0061] Optionally, refer to Figure 3 The step of adjusting the operating voltage and operating frequency of the DRAM when the tested memory cell is not a faulty memory cell specifically includes:
[0062] Step S321: If the tested memory cell is not a faulty memory cell, adjust the operating voltage and operating frequency of the DRAM from the initial operating voltage and initial operating frequency to the first preset voltage and first preset frequency, respectively.
[0063] Step S322: When the operating voltage and operating frequency of the DRAM are adjusted from the initial operating voltage and initial operating frequency to the first preset voltage and first preset frequency, and the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the first preset voltage and the second preset frequency to the third preset voltage and the third preset frequency, respectively.
[0064] Step S323: When the operating voltage and operating frequency of the DRAM are adjusted from the first preset voltage and the second preset frequency to the third preset voltage and the third preset frequency respectively, and the tested memory cell is not a faulty memory cell, the operating voltage of the DRAM is adjusted to the first preset voltage.
[0065] Step S324: When the operating voltage of the DRAM is adjusted from the third preset voltage to the first preset voltage, and the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the first preset voltage and the third preset frequency to the third preset voltage and the first preset frequency, respectively.
[0066] Wherein, the initial operating voltage is a second preset voltage, and the initial operating frequency is a second preset frequency.
[0067] In this embodiment, during the initial testing of the tested memory cell, the DRAM's operating voltage and frequency are set to initial operating voltage and frequency, respectively. The initial operating voltage is a second preset voltage, and the initial operating frequency is a second preset frequency. A first preset voltage is lower than the second preset voltage, and the second preset voltage is lower than a third preset voltage; that is, the first, second, and third preset voltages represent low, medium, and high gradient operating voltages, respectively. Similarly, a first preset frequency is lower than the second preset frequency, and the second preset frequency is lower than the third preset frequency; that is, the first, second, and third preset frequencies represent low, medium, and high gradient operating frequencies, respectively. It is understood that the DRAM's operating voltage and frequency can be set to three different values. The initial test uses the second preset voltage and the second preset frequency. Therefore, to further confirm whether the tested memory cell is faulty, different operating voltages and frequencies are adjusted to more accurately determine whether the tested memory cell is faulty. Specifically, the operating voltage and frequency are set to a first preset voltage and a first preset frequency; the operating voltage and frequency are set to a first preset voltage and a third preset frequency; the operating voltage and frequency are set to a third preset voltage and a first preset frequency; and the operating voltage and frequency are set to a third preset voltage and a third preset frequency. The operating voltage and frequency can also be set to a first preset voltage and a second preset frequency, a second preset voltage and a first preset frequency, a third preset voltage and a second preset frequency, or a second preset voltage and a third preset frequency. By subjecting the DRAM to different operating voltages and frequencies, the potential for faults in the tested cell can be more comprehensively detected. It is important to note that after each adjustment of the DRAM's operating voltage and frequency, steps S100, S200, and S300 must be repeated to confirm whether the tested memory cell has any potential faults.
[0068] Optionally, after adjusting the operating voltage and frequency of the DRAM and repeating the above steps when the tested memory cell is not a faulty memory cell, the method further includes:
[0069] After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, adjust the value of the neighboring memory cells and repeat the above steps.
[0070] Understandably, by changing the value in the neighboring storage unit 20, the value in the neighboring storage unit 20 is made to fluctuate, while the tested storage unit 10 maintains its original value, thereby increasing the degree of interference experienced by the tested storage unit 10. This method can also more accurately confirm whether the tested storage unit 10 has potential faults. It should be noted that after adjusting the value of each tested storage unit, steps S100, S200, and S300 need to be repeated to confirm whether the tested storage unit 10 has potential faults.
[0071] Optionally, the step of adjusting the value of the neighboring memory cell after adjusting the operating voltage and frequency of the DRAM, repeating the above steps, and ensuring that none of the tested memory cells are faulty memory cells, specifically involves:
[0072] After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, the value of the neighboring memory cell is adjusted from the second preset value to the first preset value, and the above steps are repeated.
[0073] In this embodiment, the operating voltage and frequency of the DRAM are set to initial operating voltage and frequency, respectively. The value of the tested memory cell 10 is set to a first preset value, and the value of the neighboring memory cell 20 is set to a second preset value. After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty, the value of the neighboring memory cell 20 is adjusted from the second preset value to the first preset value. At this time, the value of the tested memory cell 10 is set to the first preset value, and the value of the neighboring memory cell 20 is also set to the first preset value. Therefore, when repeating the above steps, step S200 needs to be adjusted as follows: when the value of the tested memory cell 10 is set to the first preset value, and the value of the neighboring memory cell 20 is set to the first preset value, the value of the neighboring memory cell 20 is adjusted from the first preset value to the second preset value, thereby causing a change in the values of the neighboring memory cells of the tested memory cell 10, and thus increasing the interference level of the neighboring memory cells on the tested memory cell 10.
[0074] Optionally, after adjusting the value of the neighboring storage unit from the second preset value to the first preset value and repeating the above steps, the method further includes:
[0075] After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, the value of the neighboring memory cell is alternately adjusted from the second preset value and the first preset value within a first preset time period, and the above steps are repeated.
[0076] In this embodiment, the operating voltage and frequency of the DRAM are set to initial operating voltage and frequency, respectively. The value of the tested memory cell 10 is set to a first preset value, and the value of the neighboring memory cell 20 is set to a second preset value. While adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty, the value of the neighboring memory cell 20 is alternately adjusted between the second preset value and the first preset value within a first preset time period, and the above steps are repeated. At this time, step S200 needs to be repeated several times, that is, the value in the neighboring memory cell 20 is adjusted from the second preset value to the first preset value, and then from the first preset value to the second preset value. The number of repetitions of step S200 can be determined based on actual verification. This method can further increase the interference level of adjacent memory cells on the tested memory cell 10, making the values of memory cells with potential faults more prone to change.
[0077] The present invention also proposes a control device comprising a memory, a processor, and a DRAM test program stored in the memory and executable on the processor, the DRAM test program being configured to implement the steps of the DRAM test method as described in any of the preceding claims.
[0078] It is worth noting that since the control device of the present invention is based on the above-mentioned DRAM test program, the embodiments of the control device of the present invention include all the technical solutions of all embodiments of the above-mentioned DRAM test program, and the technical effects achieved are exactly the same, so they will not be repeated here.
[0079] The present invention also proposes a testing device, which includes the control device as described above. It is worth noting that, since the testing device of the present invention is based on the aforementioned control device, the embodiments of the testing device of the present invention include all the technical solutions of all embodiments of the aforementioned control device, and the achieved technical effects are completely identical, and will not be repeated here.
[0080] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. A method for testing DRAM, characterized in that, The DRAM testing method includes: With the DRAM operating voltage and operating frequency being the initial operating voltage and initial operating frequency, the value of the tested memory cell is set to the first preset value, and the value of the neighboring memory cell is set to the second preset value. When the value of the tested storage cell is set to a first preset value and the value of the neighboring storage cell is set to a second preset value, the value of the neighboring storage cell is adjusted from the second preset value to the first preset value. When the value of the neighboring storage unit changes, the test storage unit is determined to be a faulty storage unit based on the change status of the value in the test storage unit. The neighboring storage unit is the adjacent storage unit of the tested storage unit, and one of the first preset value and the second preset value is 0 and the other is 1.
2. The DRAM testing method as described in claim 1, characterized in that, The step of determining whether the tested storage unit is a faulty storage unit based on the change in the value of the neighboring storage unit when the value of the neighboring storage unit changes is specifically as follows: If the value of the tested storage unit is inconsistent with the first preset value when the state of the neighboring storage unit changes, the tested storage unit is confirmed as a faulty storage unit, and the physical address of the tested storage unit is fed back. If the value of the tested storage unit is consistent with the first preset value when the state of the neighboring storage unit changes, then the tested storage unit is confirmed not to be a faulty storage unit.
3. The DRAM testing method as described in claim 2, characterized in that, After the step of confirming that the tested storage unit is not a faulty storage unit when the value of the tested storage unit is consistent with the first preset value in the case of a change in the state of the neighboring storage unit, the method further includes: If the tested memory cell is not a faulty memory cell, adjust the operating voltage and operating frequency of the DRAM and repeat the above steps.
4. The DRAM testing method as described in claim 3, characterized in that, The steps for adjusting the operating voltage and frequency of the DRAM when the tested memory cell is not a faulty memory cell are as follows: If the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the initial operating voltage and initial operating frequency to the first preset voltage and first preset frequency, respectively. When the operating voltage and operating frequency of the DRAM are adjusted from the initial operating voltage and initial operating frequency to the first preset voltage and first preset frequency, and the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the first preset voltage and the second preset frequency to the third preset voltage and the third preset frequency, respectively. When the operating voltage and operating frequency of the DRAM are adjusted from a first preset voltage and a second preset frequency to a third preset voltage and a third preset frequency, respectively, and the tested memory cell is not a faulty memory cell, the operating voltage of the DRAM is adjusted to the first preset voltage. When the operating voltage of the DRAM is adjusted from the third preset voltage to the first preset voltage, and the tested memory cell is not a faulty memory cell, the operating voltage and operating frequency of the DRAM are adjusted from the first preset voltage and the third preset frequency to the third preset voltage and the first preset frequency, respectively. Wherein, the initial operating voltage is a second preset voltage, and the initial operating frequency is a second preset frequency.
5. The DRAM testing method as described in claim 3, characterized in that, After adjusting the operating voltage and frequency of the DRAM and repeating the above steps when the tested memory cell is not a faulty memory cell, the method further includes: After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, adjust the value of the neighboring memory cells and repeat the above steps.
6. The DRAM testing method as described in claim 5, characterized in that, The step of adjusting the value of the neighboring memory cell after adjusting the operating voltage and frequency of the DRAM, repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, specifically involves: After adjusting the operating voltage and frequency of the DRAM and repeating the above steps, and assuming that none of the tested memory cells are faulty memory cells, the value of the neighboring memory cell is adjusted from the second preset value to the first preset value, and the above steps are repeated.
7. The DRAM testing method as described in claim 6, characterized in that, After adjusting the value of the neighboring storage unit from the second preset value to the first preset value and repeating the above steps, the method further includes: If the operating voltage and frequency of the DRAM are adjusted and the above steps are repeated, and if none of the tested memory cells are faulty memory cells, the value of the neighboring memory cells is adjusted alternately from the second preset value and the first preset value within a first preset time period, and the above steps are repeated.
8. A control device, characterized in that, The control device includes a memory, a processor, and a DRAM test program stored in the memory and executable on the processor, the DRAM test program being configured to implement the steps of the DRAM test method as described in any one of claims 1 to 7.
9. A testing device, characterized in that, The testing equipment includes the control device as described in claim 8.