Epitaxial substrate and wafer with thermal cycle stress loading layer

Abstract

The present application relates to the technical field of epitaxy, and provides an epitaxial substrate with a thermal cycle stress loading layer and an epitaxial wafer, which comprises an original substrate and a thermal cycle stress loading layer arranged on the back surface of the original substrate; the front surface of the original substrate is arranged as a growth surface, and the back surface of the original substrate is arranged as a non-growth surface; the thermal cycle stress loading layer is used for changing the initial stress-free state of the thermal cycle stress loading layer by using a stress loading mechanism in a thermal cycle process when the thermal cycle process ends and returns to the same temperature condition, so that the warping degree of the epitaxial wafer is changed. The epitaxial wafer is formed by growing an epitaxial layer on the epitaxial substrate, and the epitaxial wafer comprises an original substrate, an epitaxial layer arranged on the front surface of the epitaxial substrate, and a thermal cycle stress loading layer arranged on the back surface of the original substrate. The present application can regulate the warping degree of the epitaxial wafer, effectively solves the problem of large warping of the epitaxial wafer, and the thermal cycle stress loading layer has simple preparation process, good compatibility and low cost.

Description

Technical Field

[0001] This invention relates to the field of epitaxial technology, and in particular to an epitaxial substrate and epitaxial wafer having a thermal cycling stress loading layer. Background Technology

[0002] Nitride semiconductor materials possess excellent properties such as wide bandgap, high breakdown electric field, high thermal conductivity, and high electron mobility, enabling them to operate stably in high-temperature, high-power, and high-frequency environments. They have broad application prospects in fields such as solid-state lighting, novel displays, power electronic devices, and radio frequency communications, and are crucial supporting materials for optoelectronics and microelectronics technologies.

[0003] However, there is a significant mismatch in the coefficient of thermal expansion between nitride semiconductor materials and commonly used epitaxial substrates, which easily leads to stress accumulation during high-temperature growth and cooling, resulting in significant wafer warpage. This not only affects the thickness and emission wavelength uniformity of the epitaxial layer, but also reduces the precision of processes such as photolithography, bonding, and packaging, thereby reducing chip yield. Existing solutions mainly suppress warpage by thickening the substrate, but thicker substrates significantly increase material and processing costs, and further substrate thinning is required in subsequent processes, increasing process complexity. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide an epitaxial substrate and epitaxial wafer with a thermal cycling stress loading layer, which can control the warpage of the epitaxial wafer, effectively solve the problem of large warpage of the epitaxial wafer, and the thermal cycling stress loading layer has a simple preparation process, good compatibility and low cost.

[0005] To achieve the above objectives, the present invention provides the following solution: an epitaxial substrate having a thermal cycling stress loading layer, comprising: a raw substrate and a thermal cycling stress loading layer disposed on the back side of the raw substrate;

[0006] The front side of the original substrate is set as the growth surface, and the back side of the original substrate is set as the non-growth surface;

[0007] The thermal cycling stress loading layer is used to change its initial stress state by utilizing the stress loading mechanism during the thermal cycling process after the thermal cycling process ends and the temperature is restored to the same condition, thereby realizing the warpage change of the epitaxial substrate.

[0008] Optionally, the stress loading mechanism includes thin film cracking, crack propagation, material phase transformation, amorphous-crystalline transformation, interfacial reaction, interfacial diffusion, interfacial slip, interfacial debonding, plastic deformation, microstructure evolution, gas release, porosity evolution, density change, chemical reaction, stoichiometric ratio change, and thermal expansion coefficient change.

[0009] Optionally, the original substrate is set to any one of sapphire substrate, patterned sapphire substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, aluminum nitride substrate, gallium oxide substrate, and diamond substrate.

[0010] Optionally, the thermal cycling stress loading layer is configured as a high-hydrogen-content SiO2 layer prepared by plasma-enhanced chemical vapor deposition. During the heating process, the high-hydrogen-content SiO2 layer undergoes dehydrogenation reaction and amorphous structure rearrangement, resulting in increased film density and decreased coefficient of thermal expansion. This ensures that the thermal expansion mismatch stress accumulation of the high-hydrogen-content SiO2 layer during the heating process is less than the thermal expansion mismatch stress release during the cooling process, resulting in additional stress loading.

[0011] Optionally, the thermal cycling stress loading layer is further configured as a dielectric film with a thermal expansion coefficient less than that of the original substrate. The back side of the dielectric film is provided with a plurality of uniformly arranged trenches. During the heating process, as the tensile stress accumulates, the dielectric film cracks along the trenches and guides the crack propagation to achieve tensile stress release, so as to generate additional stress loading during the heating and cooling thermal cycling process.

[0012] The present invention also provides an epitaxial wafer having a thermal cycling stress loading layer, wherein the epitaxial wafer having the thermal cycling stress loading layer is formed by growing an epitaxial layer on an epitaxial substrate having a thermal cycling stress loading layer as described in any one of the present invention, the epitaxial wafer comprising the original substrate, an epitaxial layer disposed on the front side of the epitaxial substrate, and a thermal cycling stress loading layer disposed on the back side of the original substrate.

[0013] This invention discloses the following technical effects by providing an epitaxial substrate and an epitaxial wafer with a thermal cycling stress loading layer:

[0014] 1. This invention forms a thermal cycling stress loading layer on the non-growth surface of the original substrate, and changes the stress state of this layer during the thermal cycling process of epitaxial growth, thereby controlling the warpage of the epitaxial wafer and effectively solving the problem of large warpage of epitaxial wafers.

[0015] 2. The thermal cycling stress loading layer preparation process of the present invention is simple and has good compatibility, overcoming the problem of high cost of traditional epitaxial wafer warpage control methods.

[0016] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the epitaxial wafer provided in Embodiment 1 of the present invention;

[0019] Figure 2 This is a cross-sectional schematic diagram of the epitaxial substrate provided in Embodiment 1 of the present invention;

[0020] Figure 3 This is a schematic cross-sectional view of the epitaxial substrate after a thermal cycling process, as provided in Embodiment 2 of the present invention.

[0021] Figure 4 This is a schematic diagram of the wafer curvature change during thermal cycling and GaN layer epitaxial growth provided in Embodiment 3 of the present invention.

[0022] Figure reference numerals: 1. Original substrate; 2. Thermal cycling stress loading layer; 3. Growth surface; 4. Non-growth surface; 401. Wafer curvature variation curve of patterned sapphire substrate with PECVD SiO2 layer; 402. Wafer curvature variation curve of control group patterned sapphire substrate without PECVD SiO2 layer; 403. Wafer curvature difference curve of patterned sapphire substrate with / without PECVD SiO2 layer; 5. Trench; 6. Epitaxial layer. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] Example 1

[0026] like Figure 1 , Figure 2 As shown, the present invention provides an epitaxial substrate having a thermal cycling stress loading layer, comprising: a raw substrate 1 and a thermal cycling stress loading layer 2 disposed on the back side of the raw substrate 1.

[0027] 1. Original substrate

[0028] The thickness of the original substrate 1 is set to 650 μm. The front side of the original substrate 1 is designated as the growth surface 3, and the back side of the original substrate 1 is designated as the non-growth surface 4.

[0029] The original substrate 1 is set to any one of the following: sapphire substrate, patterned sapphire substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, aluminum nitride substrate, gallium oxide substrate, and diamond substrate.

[0030] 2. Thermal Cyclic Stress Loading Layer

[0031] The thickness of the thermal cycling stress loading layer 2 is set to 3 μm. The thermal cycling stress loading layer 2 is used to change its initial stress-free state by utilizing the stress loading mechanism during the thermal cycling process after the thermal cycling process ends and the temperature is restored to the same condition, thereby realizing the warpage change of the epitaxial substrate.

[0032] The thermal cycling stress loading layer 2 is a high-hydrogen-content SiO2 layer prepared by plasma-enhanced chemical vapor deposition. During the heating process, the high-hydrogen-content SiO2 layer undergoes dehydrogenation reaction and amorphous structure rearrangement, which increases the film density and reduces the coefficient of thermal expansion. This makes the tensile stress accumulation of the high-hydrogen-content SiO2 layer during the heating process less than the tensile stress release during the cooling process, resulting in additional stress loading.

[0033] The thermal cycling stress loading layer 2 is further configured as a dielectric thin film with a thermal expansion coefficient smaller than that of the original substrate 1. The back side of the dielectric thin film is provided with a plurality of uniformly arranged trenches 5. During the heating process, as the tensile stress accumulates, the dielectric thin film cracks along the trenches 5 and guides the crack propagation to achieve tensile stress release, so as to generate additional stress loading during the thermal cycling process of heating and cooling.

[0034] The groove 5 is used to promote cracking of the thermal cycling stress loading layer 2. The depth of the groove 5 is set to 2μm, and the spacing between the grooves 5 is set to 5μm.

[0035] 3. Stress loading mechanism

[0036] The stress loading mechanisms include thin film cracking, crack propagation, material phase transformation, amorphous-crystalline transition, interfacial reaction, interfacial diffusion, interfacial slip, interfacial debonding, plastic deformation, microstructure evolution, gas release, porosity evolution, density change, chemical reaction, stoichiometric ratio change, and thermal expansion coefficient change.

[0037] like Figure 1As shown, the present invention also provides an epitaxial wafer with a thermal cycling stress loading layer, the epitaxial wafer being formed by growing an epitaxial layer 6 on an epitaxial substrate having a thermal cycling stress loading layer. The epitaxial wafer includes the original substrate, an epitaxial layer disposed on the front side of the epitaxial substrate, and a thermal cycling stress loading layer disposed on the back side of the original substrate.

[0038] Example 2

[0039] Embodiment 2 of the present invention provides an epitaxial substrate with a thermal cycling stress loading layer. The original substrate 1 is a sapphire substrate with a thickness of 650 μm. The thermal cycling stress loading layer 2 is a Si3N4 thin film with a total thickness of 3 μm. The Si3N4 thin film has trenches 5 on its surface to promote cracking. The trenches 5 have a depth of 2 μm and a spacing of 5 μm. The Si3N4 thin film is in a stress-free initial state at room temperature.

[0040] Figure 3 This invention provides a cross-sectional schematic diagram of an epitaxial substrate after a thermal cycling process, as shown below. Figure 3 As shown, after the epitaxial substrate undergoes thermal cycling, since the coefficient of thermal expansion of the Si3N4 thin film is smaller than that of the sapphire substrate, tensile stress gradually accumulates in the Si3N4 thin film during the heating process of thermal cycling. When the accumulated tensile stress exceeds the critical value for the Si3N4 thin film to resist cracking, cracks first appear at trench 5 of the Si3N4 thin film and propagate along trench 5, thereby releasing the tensile stress generated during the heating process. During the cooling process of thermal cycling, compressive stress gradually accumulates in the Si3N4 thin film. However, when the epitaxial substrate returns to room temperature after thermal cycling, residual compressive stress appears in the Si3N4 thin film, and the epitaxial substrate exhibits a concave warped state.

[0041] Example 3

[0042] The epitaxial wafer provided in Embodiment 3 of this invention has a primary substrate 1, which is a patterned sapphire substrate with a total thickness of 650 μm, and a thermal cycling stress loading layer 2, which is a SiO2 thin film deposited by PECVD with a total thickness of 3 μm. The initial hydrogen content of the film is 10 at.%, and the coefficient of thermal expansion is approximately 1.5 × 10⁻⁶. -6 / K, the SiO2 film is in its initial stress-free state at room temperature; the epitaxial layer 6 is a GaN layer with a thickness of 4μm grown by MOCVD after heating the epitaxial substrate with thermal cycling stress loading layer 2 to 1050℃.

[0043] Figure 4 This is a schematic diagram illustrating the wafer curvature change during thermal cycling and GaN layer epitaxial growth, as provided by the present invention. Figure 4As shown, curve 401 is the wafer curvature variation curve of the patterned sapphire substrate with PECVD SiO2 layer, curve 402 is the wafer curvature variation curve of the control group patterned sapphire substrate without PECVD SiO2 layer, and curve 403 is the wafer curvature difference between the patterned sapphire substrate with and without PECVD SiO2 layer.

[0044] During the heating process of patterned sapphire substrate to 1050℃, due to the temperature difference between the front and back sides of the patterned sapphire substrate, both the patterned sapphire substrate with and without the PECVD SiO2 layer exhibit an upward concave state, and the wafer curvature gradually increases with increasing temperature. Since the thermal expansion coefficient of PECVD SiO2 is smaller than that of the patterned sapphire substrate, the PECVD SiO2 layer accumulates tensile stress, which partially offsets the upward concave trend of the patterned sapphire substrate.

[0045] During GaN epitaxy, due to the lattice mismatch between GaN and the patterned sapphire substrate, compressive stress accumulates in the GaN epitaxial layer 6, causing the wafer curvature on the epitaxial substrate to gradually decrease. Simultaneously, at high temperatures, the PECVD SiO2 layer undergoes a dehydrogenation reaction, reducing the hydrogen content to 0.5 at.% and the coefficient of thermal expansion to approximately 0.5 × 10⁻⁶. -6 / K.

[0046] During the cooling process to room temperature, because the coefficient of thermal expansion of the GaN layer is smaller than that of the patterned sapphire substrate, compressive stress further accumulates in the GaN layer, and the wafer curvature gradually decreases from concave to convex. Meanwhile, the coefficient of thermal expansion of the PECVD SiO2 layer is smaller than that of the patterned sapphire substrate, and compressive stress accumulates during the cooling process, which partially offsets the convex trend of the patterned sapphire substrate.

[0047] Because the coefficient of thermal expansion of the PECVD SiO2 layer is lower during cooling than during heating, it retains net compressive stress after the entire thermal cycle, thus producing a net effect on the wafer curvature of the patterned sapphire substrate. Ultimately, the absolute value of the wafer curvature of the epitaxial wafer with the PECVD SiO2 layer is smaller than that of the epitaxial wafer without the PECVD SiO2 layer.

[0048] Therefore, by providing an epitaxial substrate and epitaxial wafer with a thermal cycling stress loading layer, the present invention can control the warpage of the epitaxial wafer, effectively solving the problem of large warpage of the epitaxial wafer. Furthermore, the thermal cycling stress loading layer is simple to prepare, has good compatibility, and is low in cost.

[0049] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0050] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An epitaxial substrate having a thermal cycling stress loading layer, characterized in that, include: The original substrate and the thermal cycling stress loading layer disposed on the back side of the original substrate; The front side of the original substrate is set as the growth surface, and the back side of the original substrate is set as the non-growth surface; The thermal cycling stress loading layer is used to change its initial stress state by utilizing the stress loading mechanism during the thermal cycling process after the thermal cycling process ends and the temperature is restored to the same condition, thereby realizing the warpage change of the epitaxial substrate. The thermal cycling stress loading layer is a high-hydrogen-content SiO2 layer prepared by plasma-enhanced chemical vapor deposition. During the heating process, the high-hydrogen-content SiO2 layer undergoes dehydrogenation reaction and amorphous structure rearrangement, which increases the film density and reduces the coefficient of thermal expansion. This makes the thermal expansion mismatch stress accumulation of the high-hydrogen-content SiO2 layer during the heating process less than the thermal expansion mismatch stress release during the cooling process, resulting in additional stress loading. The thermal cycling stress loading layer is further configured as a dielectric thin film with a thermal expansion coefficient smaller than that of the original substrate. The back side of the dielectric thin film is provided with multiple uniformly arranged trenches. During the heating process, as tensile stress accumulates, the dielectric thin film cracks along the trenches and guides crack propagation to achieve tensile stress release, thereby generating additional stress loading during the heating and cooling thermal cycling process.

2. The epitaxial substrate with a thermal cycling stress loading layer according to claim 1, characterized in that, The stress loading mechanisms include thin film cracking, crack propagation, material phase transformation, amorphous-crystalline transition, interfacial reaction, interfacial diffusion, interfacial slip, interfacial debonding, plastic deformation, microstructure evolution, gas release, porosity evolution, density change, chemical reaction, stoichiometric ratio change, and thermal expansion coefficient change.

3. The epitaxial substrate with a thermal cycling stress loading layer according to claim 2, characterized in that, The original substrate is set to any one of the following: sapphire substrate, patterned sapphire substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, aluminum nitride substrate, gallium oxide substrate, and diamond substrate.

4. An epitaxial wafer with a thermal cycling stress loading layer, characterized in that, The epitaxial wafer having a thermally cyclic stress loading layer is formed by growing an epitaxial layer on an epitaxial substrate having a thermally cyclic stress loading layer as described in any one of claims 1 to 3, the epitaxial wafer comprising the original substrate, an epitaxial layer disposed on the front side of the epitaxial substrate, and a thermally cyclic stress loading layer disposed on the back side of the original substrate.

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