ESD power clamp

Abstract

The present disclosure relates to an electrostatic discharge (ESD) power clamp including apparatuses and methods related to split placement of pre-drivers to provide unified turn-on of the power clamp when shunting ESD current. An example method includes detecting an ESD event and in response to the detected ESD event, the method includes segmenting a pre-driver output to send a trigger signal to a plurality of large field effect transistor (BigFET) gate fingers via different feed points on a gate finger manifold that interconnects the BigFET gate fingers. The method further includes shunting an ESD current using the activated bigFET.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to electronic devices, and more particularly to devices and methods for providing electrostatic discharge (ESD) protection for integrated circuit (IC) devices. BACKGROUND

[0002] ESD protection circuits or power clamps are important components in electronic systems to protect integrated circuits (ICs) and other sensitive electronic devices from damage caused by ESD events. ESD protection circuits can be integrated into IC chips to provide a low impedance path to ground. For example, all input / output (I / O) pads of an IC are typically protected via an ESD network that can include a power clamp on the supply pad. SUMMARY

[0003] In one aspect, the present disclosure provides a method associated with an ESD power clamp, comprising: detecting an electrostatic discharge (ESD) event; in response to the detected ESD event, sending a plurality of trigger signals to a plurality of big field effect transistor (FET) gate fingers via different feed points on a big FET gate finger manifold via a physically split pre-driver layout, the big FET gate finger manifold interconnecting the big FET gate fingers in parallel; and shunting ESD current using activated big FETs.

[0004] In another aspect, the present disclosure provides an electrostatic discharge (ESD) power clamp, comprising: a slew rate detector generating an ESD detection signal in response to a detected ESD event; a pre-driver configured to receive and condition the ESD detection signal to generate a plurality of trigger signals; and a big field effect transistor (FET) having a plurality of gate fingers connected by a gate finger manifold, wherein the generated trigger signals are fed to different feed points on the gate finger manifold to activate the big FET as an ESD power clamp.

[0005] In another aspect, the present disclosure provides an apparatus having an ESD power clamp, the apparatus comprising: a slew rate detector detecting an electrostatic discharge (ESD) event and generating an ESD detection signal in response to the detected ESD event; a pre-driver having a physical layout split into pre-driver portions to condition the ESD detection signal, wherein the pre-driver portions send trigger signals to a plurality of big field effect transistor (FET) gate fingers via different feed points on a gate finger manifold, the gate finger manifold interconnecting the big FET gate fingers in parallel; and a big FET having the plurality of big FET gate fingers connected in parallel by the gate finger manifold, wherein the trigger signals activate the big FET to shunt ESD current. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a block diagram of an integrated circuit (IC) device with a pre-driver with split circuit layout to generate multiple trigger signals according to embodiments of the present disclosure.

[0007] Figure 2 is a block diagram illustrating a more detailed example of an ESD power clamp with a pre-driver with split circuit physical layout placement for activating a bigFET power clamp according to embodiments of the present disclosure.

[0008] Figure 3 illustrates a method for activating a bigFET using a pre-driver with split circuit physical layout placement according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0009] The present disclosure includes apparatuses and methods related to providing ESD protection for IC devices and, in particular, IC devices that support high speed and / or high / low power applications. For example, circuits that operate at high power and high frequency can require a corresponding IC device with transistors of the metal-oxide-semiconductor field-effect transistor (MOSFET) type that are capable of reliably operating at this high frequency while still being able to handle high power loads. In this example, an ESD power clamp can be integrated into the IC device to provide circuit protection in the event of an ESD event (e.g., a strike). For example, the ESD power clamp can implement the ESD power clamp using a bigFET and protect the IC device from damage. For example, a bigFET includes, for example, an array of MOSFETs arranged in rows and columns with corresponding parallel connected segments (referred to herein as bigFET gate fingers) to increase its current carrying capacity and reduce the on-resistance. The bigFET (referred to herein interchangeably as an array of MOSFETs) can comprise n-channel MOSFET (NMOS) transistors or p-channel MOSFET (PMOS) transistors with multiple fingers and large channel width to enhance high current capability and reduce clamping voltage.

[0010] To support high voltage discharges, the size of the bigFET can be further increased. For example, the number of parallel connected MOSFETs arranged in rows and columns on the transistor semiconductor substrate can be increased. By increasing the size of the MOSFETs, and by extending the number of parallel connected bigFET gate fingers, the effective width of the bigFET is also increased. The increased number of bigFET gate fingers collectively increases the current carrying capacity of the bigFET. However, the disadvantage of increasing the number of bigFET gate fingers and thus the effective width will result in a variation of resistance along the transistor semiconductor substrate. This variation of resistance creates a signal phase variation, and thus a delay in activation of the MOSFET array along the portion of the transistor semiconductor substrate having a high resistance. The activation delay or non-uniform turn-on of the bigFET will not effectively facilitate clamping suppression of the circuit, which can cause damage to the IC device.

[0011] Aspects of the present disclosure address the above and other deficiencies by having a pre-driver with split circuit physical layout placement to provide a uniform turn-on time activation of the bigFET (or MOSFET array) during an ESD event. For example, embodiments can utilize a split physical circuit layout of the pre-driver to generate separate firing signals to different groups of bigFET gate fingers. The groups of bigFET gate fingers can be formed from a group of parallel connected MOSFETs. In this example, the bigFET gate fingers receive the firing signals via different feed points to compensate for different net resistances across the bigFET. The different feed points include, for example, opposite ends or edges of an elongated gate finger manifold that interconnects the bigFET gate fingers. The elongated gate finger manifold can include conductive substrate lines that physically interconnect the different bigFET gate fingers formed from parallel connected MOSFETs. Thus, embodiments can result in a higher net resistance being shifted to a central portion of the bigFET (corresponding to a central portion of the gate finger manifold), thereby enabling improved performance.

[0012] As used herein, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. Furthermore, the word "may" is used throughout this application in a permissive sense (i.e., having the potential to), not a mandatory sense (i.e., must). The term "include" and its derivatives mean "including, but not limited to." The term "coupled" means directly or indirectly connected.

[0013] The drawings herein generally follow the numbering convention in which the first or few digits correspond to the figure number and the remaining digits identify an element or component in the figure. Similar elements or components between different figures can be identified by the use of similar digits. For example, 110 can designate element "10" in Figure 1 , and similar elements in Figure 2Similar elements within the drawings can be designated by like reference numerals. It will be appreciated that elements shown as being incorporated into one embodiment can be added to or swapped out with similar elements in order to provide a number of additional embodiments of the present disclosure. In addition, it should be noted that the proportions and relative dimensions of the components provided in the drawings are intended to illustrate certain embodiments of the application and should not be taken in a limiting sense.

[0014] Figure 1 is a block diagram of an IC device 100 having a pre-driver 120 with split circuit layout placement to provide uniform turn-on of a bigFET 130 in accordance with embodiments of the present disclosure. In embodiments, the bigFET 130 is implemented by an array of MOSFETs 140 having multiple parallel connected segments (e.g., bigFET gate fingers 142) to enhance bigFET current carrying capability. The array of MOSFETs 140 can be arranged in rows and columns and further connected in parallel to increase the effective width (or current carrying capacity) of the bigFET 130. In this embodiment, the bigFET 130 is configured to implement voltage clamping in an ESD power clamer 102 that includes a device or system protected by the IC device 100. The bigFET 130 includes bigFET gate fingers 142 that can be connected in parallel, for example, through a gate finger manifold 148 that is a semiconductor structure or a physical conductive wire substrate in the bigFET 130. The number of bigFET gate fingers 142 can depend on the number of parallel connected MOSFETs 140 grouped into the array of MOSFETs 140. For example, a group of 3 parallel connected transistors in MOSFET 140-1 can form three bigFET gate fingers 142. In this example, the three bigFET gate fingers 142 are interconnected in parallel with other bigFET gate fingers from another group of MOSFETs through the gate finger manifold 148. Further, the three bigFET gate fingers 142 correspond to an increase in the effective width of the bigFET 130.

[0015] In some embodiments, the pre-driver 120 feeds the trigger signal to different feed points (e.g., a first feed point 144 and a second feed point 146) on the gate finger manifold 148 to eliminate or at least reduce the delay in transmitting the trigger signal to the respective gates of the array of MOSFETs 140. For example, the delay can be enhanced by the length of the column and / or row arrangement of MOSFETs. The reduction or elimination of the delay will provide uniform turn-on of the MOSFETs 140 and thus the bigFET 130 in the IC device 100. The IC device 100 can be, for example, a system, a device, or a system on chip (SoC); however, embodiments are not limited to a particular type of electronic system.

[0016] As shown, IC device 100 can include ESD power clamps 102 and core circuitry 104 connected to a power rail - Vdd 106 and a lower voltage rail Vss 108 (e.g., ground). ESD power clamps 102 can further include a slew rate detector 110; a predriver 120 having a circuit layout separating a first set of PMOS predrivers 122 from a second set of PMOS predrivers 124; and a bigFET 130 implemented by an array of MOSFETs 140. For example, bigFET gate fingers 142 of MOSFETs 140 can include interconnecting gate electrodes connecting MOSFETs 140-1 through 140-40 in parallel. For illustrative purposes, to simplify the illustration, the interconnecting drain electrodes, source electrodes, and / or bias voltages of MOSFETs 140-1 through 140-40 are not shown.

[0017] Figure 1 Further illustrating ESD detection signal 112 generated by slew rate detector 110 upon detection of an ESD event; first trigger signal 126 and second trigger signal 128 generated by first set of PMOS predrivers 122 and second set of PMOS predrivers 124, respectively; and first feed point 144 and second feed point 146 at opposite ends of bigFET 130.

[0018] As Figure 1 As an overview of operation of ESD power clamps 102, slew rate detector 110 is used to detect an ESD event (not shown) and then predriver 120 activates bigFET 130 to shunt high transient current resulting from the ESD event. BigFET 130 is an example protective or clamping circuitry that shunts high current and thus limits excessive power that can cause damage to core circuitry 104. Shunting of high transient current provides protection to core circuitry 104. Predriver 120 is not limited to having PMOS transistors, but can also be configured to include NMOS transistors. Further, the circuit layout of predriver 120 is not limited to being split into two parts, but predriver 120 can be split into more than two parts to support triggering of bigFET 130 via different feed points on gate finger manifold 148.

[0019] For example, additional pre-drivers can be added to supply trigger current at the same or different feed points on the gate finger manifold 148 depending on how the total gate charge is handled by the assigned pre-drivers 120 to activate the current capability of a group or set of specific parallel connected MOSFETs. In this example, the feed points provide less resistance to the trigger current to avoid delay in turn-on of the associated MOSFETs 140. In alternative or additional embodiments, a separate gate finger manifold is dedicated to connecting the bigFET gate fingers associated with the MOSFETs of a specific column (not shown). In this embodiment, trigger current is supplied at opposite edges of the dedicated gate finger manifold to provide low resistance to the trigger current that will activate the MOSFETs of the specific column.

[0020] The IC device 100 can be used in various applications, such as high power automotive applications, communication applications, industrial applications, medical applications, computer applications, and / or consumer or appliance applications. The IC device 100 can be implemented in a substrate, such as a semiconductor wafer or a printed circuit board (PCB). In embodiments, the IC device 100 is packaged as a semiconductor IC chip. The IC device 100 can be included in a microcontroller, which can be used, for example, for in-vehicle control or communication, identification, wireless communication, and / or lighting control. In some embodiments, the IC device 100 utilizes the ESD power clamps 102 to avoid potential ESD events from occurring during the shipping and handling of the packaged device. For example, a human touch can cause a sudden flow of electricity between objects with different static electric potentials.

[0021] The core circuit 104 can include a device that is protected by the ESD power clamps 102 in the event of an ESD strike or event. The core circuit 104 can include one or more internal circuit components that are susceptible to ESD strikes. Examples of the core circuit 104 include, but are not limited to, microcontrollers, transceivers, and high power switching circuits. In embodiments, the core circuit 104 includes a power domain of the IC device 100, which is a specific region or section of the IC device 100 that applies a specific power or voltage level. In multifunctional devices, different sections of the core circuit 104 can require different power supply voltages to optimize performance, power consumption, and overall functionality.

[0022] The ESD power clamps 102 can include components to control spikes in current and / or surges in voltage during ESD events or strikes. The ESD power clamps 102 can be configured to include a specific circuit layout to protect the power domain of the IC device 100. For example, the ESD power clamps 102 can use the bigFETs 130 to shunt high currents during ESD events and thereby prevent damage to the core circuit 104. In this example, the ESD power clamps 102 can include a split placement of circuitry, such as the pre-drivers 120, to provide uniform turn-on of the MOSFETs 140 that implement the bigFETs 130.

[0023] ESD power clamps 102 are implemented by suitable semiconductor devices having MOSFETs and corresponding plurality of bigFET gate fingers 142 to enhance the current carrying capability of the bigFETs. In embodiments, the bigFET gate fingers 142 can include separate feed points when receiving the first and second trigger signals 126, 128 from the predriver 120. The first or second trigger information can include an amplified, filtered, and / or conditioned ESD detection signal 112. The use of separate feed points (first and second feed points 144, 146) reduces or eliminates delay in transmission of the trigger signals and, in effect, provides a uniform turn-on of the MOSFETs 140 associated with the bigFET gate fingers 142. In some embodiments, the first trigger signal 126 can be different from the second trigger signal 128.

[0024] The bigFET 130 includes an array of gate fingers 142 of MOSFETs 140 that collectively contribute to increasing the current carrying capacity of the bigFET 130. The size of the bigFET 130 can be widened in the x- and / or y-directions to effectively scale and increase the current carrying capability of the associated MOSFETs. Effective scaling is proportional to the number of parallel connected MOSFETs 140 that implement the bigFET 130. By increasing the size of the bigFET 130 in the x- and / or y-directions, the bigFET can protect the power domain of the IC device 100 from overvoltage during an ESD event by shunting ESD current from the power domain (Vdd 106) to the ground domain (or power ground). In some embodiments, the channel width of the bigFET gate fingers 142 can be selected to ensure that the voltage drop across the bigFET 130 does not exceed a predetermined voltage during an ESD event, which is considered detrimental to internal circuit components (e.g., core circuit 104) of the IC device 100. The predetermined voltage is typically set to be equal to or close to the power voltage of the IC device 100.

[0025] In some embodiments, the number of MOSFETs 140 and, therefore, the number of bigFET gate fingers 142 can be increased to ensure that the voltage drop across the bigFET does not exceed a predetermined voltage during an ESD event. Increasing the size of the MOSFETs 140 in the row and / or column direction can correspond to increasing the effective width of the bigFET 130. For example, an increase in the number of rows of bigFET gate fingers 142 correspondingly increases the physical length of the bigFET and, therefore, the length of the gate finger manifold 148 in the y-direction. In this regard, the use of separate feed points can be utilized to eliminate delay in transmission of the trigger signals from one end of the gate finger manifold 148 to the bigFET gate fingers 142, which typically occurs when only one feed point is utilized, such as only one opposite end or edge of the gate finger manifold 148 is receiving the trigger signal.

[0026] As described herein, the first feed point 144 is located at one end or edge of the bigFET 130, and in particular, at one end or edge of the length of the gate finger manifold 148. On the other hand, the second feed point 146 is located at the other end or edge of the length of the gate finger manifold 148. For a particular number of bigFET gate fingers 142 corresponding to the number of parallel connected MOSFETs 140, the gate finger manifold 148 includes a conductive semiconductor substrate that extends along the y-direction and interconnects the bigFET gate fingers 142 in parallel.

[0027] The gate finger manifold 148 is a semiconductor structure or a physically conductive substrate line that connects the plurality of bigFET gate fingers 142 in the ESD power clamps 102. As the number of rows and / or columns of parallel connected MOSFETs 140 increases, the physical length (e.g., y-direction) of the gate finger manifold conductive substrate line also increases. Thus, the physical bigFET package can impose a constraint on the number of bigFET gate fingers 142 to be included in the IC device 100 due to the non-uniform signal phase distribution that can occur along the length of the gate finger manifold 148. In this regard, the physical split circuit layout placement of the pre-driver 120 can be utilized to transmit the trigger signal to the MOSFETs 140 via different placement of the feed points in the gate finger manifold 148. Only 40 MOSFETs 140 or groups of MOSFETs 140 are shown; however, additional MOSFETs 140 arranged in rows and / or columns can be implemented. The plurality of bigFET gate fingers that can be formed from these rows and / or columns of MOSFETs 140 can be interconnected via the gate finger manifold 148.

[0028] In some embodiments, each of the bigFET gate fingers is connected to both sides of the gate finger manifold 148. For example, a particular gate finger is represented by a longitudinal gate substrate having two edges. In this example, one edge of the gate finger is connected to one side (not shown) of the gate finger manifold 148, while the other edge of the gate finger is connected to the other side of the gate finger manifold 148.

[0029] The pre-driver 120 includes circuitry configured to condition the received ESD detection signal 112 and generate a trigger signal to turn on the bigFET 130. The conditioning of the received ESD detection signal 112 can include amplification, filtering, etc. of the ESD detection signal from the slew rate detector 110. In one embodiment, the MOSFETs of the pre-driver 120 can be split or divided into at least two portions when driving the MOSFETs 140 via the corresponding bigFET gate fingers 142 of the MOSFETs 140.

[0030] For example, the first set of PMOS pre-drivers 122 of the pre-driver 120 generates a first trigger signal 126 and sends the generated first trigger signal 126 via a first feed point 144, while the second set of PMOS pre-drivers 124 can generate a separate second trigger signal 128 and send the separate second trigger signal 128 via a second feed point 146. In this example, the first feed point 144 and the second feed point 146 would be located at opposite edges or ends of the length (in the y-direction) of the gate finger manifold 148, although embodiments are not limited thereto. By sending the trigger signals via separate feed points, the bigFET gate fingers 142 of the corresponding MOSFETs 140 will receive the trigger signals without delay, and thereby provide uniform turn-on of the associated MOSFETs that can shunt current during an ESD strike. For ease of illustration, the main driver stage is not shown, but the pre-driver 120 will typically drive a main driver, which can also be configured to generate and send trigger signals to different feed points on the gate finger manifold 148.

[0031] The slew rate detector 110 can be configured to detect an ESD event, as described herein. In some embodiments, for example, the slew rate detector 110 sends the ESD detection signal 112 in response to an IC pad-voltage change above a certain slew rate or preconfigured threshold. The slew rate detector 110 and the pre-driver 120 form a trigger circuit that controls activation and deactivation of the MOSFETs 140. For example, the slew rate detector 110 can detect a rise in the power supply voltage Vdd 106 of the IC device 100, which is characteristic of an ESD event. The pre-driver 120 can then receive the ESD detection signal 112 from the slew rate detector 110 and use the received ESD detection signal 112 as a reference for generating and sending trigger signals. In this example, the pre-driver 120 can only be active during the initial detection of an ESD event to trigger the bigFET 130.

[0032] Figure 2 is a block diagram illustrating a more detailed example of an ESD power clamer 202 with a pre-driver 220 (pre-driver portions 220-1 and 220-2) with a split circuit layout for activating a bigFET 230 in accordance with a number of embodiments of the present disclosure. As shown, the ESD power clamer 202, the slew rate detector 210, a first set of PMOS pre-drivers 222 of the pre-driver portion 220-1, a second set of PMOS pre-drivers 224 of the pre-driver portion 220-2, and the bigFET 230 with an array of MOSFETs 240 with bigFET gate fingers 242 correspond to the ESD power clamer 202, the slew rate detector 210, the first set of PMOS pre-drivers 122, the second set of PMOS pre-drivers 124, and the bigFET 130 with the array of MOSFETs 140 with the bigFET gate fingers 142, respectively, of Figure 1ESD power clamps 102, slew rate detector 110, first set of PMOS pre-drivers 122, second set of PMOS pre-drivers 124, and bigFET 130 having an array of MOSFETs 140 with bigFET gate fingers 142 in FIG. 1.

[0033] Similarly, ESD detection signal 212, first trigger signals 226-1 through 226-10, and second trigger signals 228-11 through 228-20 generated by slew rate detector 210 correspond to Figure 1 ESD detection signal 112, first trigger signal 126, and second trigger signal 128 generated by slew rate detector 110 in FIG. 1.

[0034] Figure 2 The grouping MOSFETs 240-1 through 240-40 are illustrated to include associated bigFET gate fingers 242 that can be formed from MOSFETs or transistors connected in parallel; however, the interconnections of drain, source, and bias voltages in the array of MOSFETs 240 are not shown to simplify the illustration. Further, although the embodiments described herein include PMOS pre-drivers and PMOS pre-driver portions to drive NMOS MOSFETs, the embodiments are not so limited. ESD power clamps can also utilize NMOS pre-drivers or NMOS pre-driver portions to drive an array of PMOS MOSFETs.

[0035] In embodiments, each of the MOSFETs 240-1 through 240-40 is associated with three bigFET gate fingers 242. For example, bigFET gate fingers 242-1 through 242-60 can be associated with MOSFETs 240-1 through 240-20 connected in parallel, which receive first trigger signals 226-1 through 226-10 from the first set of PMOS pre-drivers 222-1 through 222-10 of pre-driver portion 220-1. In another example, bigFET gate fingers 242-61 through 242-120 can be associated with MOSFETs 240-21 through 240-40 connected in parallel, which receive second trigger signals 228-11 through 228-20 from the second set of PMOS pre-drivers 224-11 through 224-20 of pre-driver portion 220-2. In these examples, the MOSFETs 240 can be arranged in rows and columns, and further connected in parallel to increase the effective width of the bigFET 240. Further, each pre-driver in the first and second set of PMOS pre-drivers can be configured to generate sufficient gate charge to drive the associated MOSFET 240.

[0036] For example, a first trigger signal 226-1 from PMOS pre-driver 222-1 is assigned to supply gate charge to bigFET gate fingers 242-1 through 242-6 associated with MOSFETs 240-1 and 240-2; a second trigger signal 226-2 is used to supply gate charge to bigFET gate fingers 242-7 through 242-12 associated with MOSFETs 240-3 and 240-4, and so on. At the opposite side or edge of bigFET 230, an eleventh trigger signal 228-11 from PMOS pre-driver 224-11 is assigned to supply gate charge to bigFET gate fingers 242-61 through 242-66 associated with MOSFETs 240-11 and 240-12; a next trigger signal 226-12 is used to supply gate charge to bigFET gate fingers 242-67 through 242-72 associated with MOSFETs 240-13 and 240-14, and so on. In these examples, the assigned MPS pre-drivers are configured to generate sufficient gate charge to drive the associated MOSFETs 240. Moreover, bigFET gate fingers 242-1 through 242-120 can be physically connected via a gate finger manifold—semiconductor substrate, for example, gate finger manifolds 248-1 through 248-10 corresponding to Figure 1 gate finger manifolds 148 in FIG. 1.

[0037] In some embodiments, a gate finger manifold can be represented individually by each row of MOSFETs 240 in bigFET 240. For example, MOSFETs 240-1 through 240-40 are arranged in 4 rows and 10 columns. In this example, ten separate gate finger manifolds (e.g., gate finger manifolds 248-1 through 248-10) can implement Figure 1 gate finger manifolds 148 in FIG. 1. In other embodiments, and for the same example, the 10 columns of MOSFETs 240 can only form one gate finger manifold 248. In these embodiments, a first set of trigger signals 226-1 through 226-10 are fed at one edge of the length of gate finger manifold 248, while a second set of trigger signals 228-11 through 228-20 are supplied via the opposite end or edge of gate finger manifold 248. The opposite edges of gate finger manifold 248, for example, correspond to first feed point 144 and second feed point 146 of FIG. 1. Figure 1

[0038] ​In some embodiments, each of the bigFET gate fingers 242-1 through 242-130 is connected to both sides of the gate finger manifold 248. For example, a particular gate finger is represented by a longitudinal gate substrate having two edges. In this example, one edge of the gate finger is connected to one side of the gate finger manifold 248, while the other edge of the gate finger is connected to the other side of the gate finger manifold 248. The two sides of the gate finger manifold 248 can include an upper surface and a lower surface, respectively, representing the physical conductive substrate lines of the gate finger manifold.

[0039] In some embodiments, the slew rate detector 210 includes a resistor-capacitor (RC) circuit having a resistor 213 connected in series with a capacitor 214 between Vdd 206 and Vss 208. A first terminal of the resistor 213 is connected to Vdd 206, while a second terminal of the resistor 213 is connected to a node 215, which provides an ESD detection signal 212 indicative of detection of an ESD event. For example, the ESD rise time detection limit of the power clamps is 60 ns. That is, a rise time of 60 ns or longer indicates normal operation, and the transistor switch circuit remains in an off state. However, in the case of a slew rate or rise time less than 60 ns, the RC circuit can generate the ESD detection signal 212, which can be used by the pre-driver 220 as a reference in actuating the bigFET 230 implemented by the MOSFETs 240, as described herein.

[0040] Each of the pre-drivers 220-1 and 220-2 is a circuit configured to condition the ESD detection signal 212 and generate a conditioned signal to turn on the MOSFETs 240-1 through 240-40 after an ESD event is detected by the slew rate detector 210. In embodiments, for example, the pre-drivers 220-1 and 220-2 (or the pre-driver 220) can turn on the MOSFETs 240-1 through 240-40 by sending a trigger signal to the associated bigFET gate fingers 242-1 through 242-120 interconnected along the length (i.e., y-direction) of the semiconductor substrate by the gate manifold. To reduce or eliminate delays in the transmission of the trigger signal, the circuit layout of the pre-driver 220 is subdivided into two parts to support the corresponding MOSFETs 240.

[0041] For example, a first set of PMOS pre-drivers 222-1 through 222-10 will provide a trigger signal to a first portion 231 of the bigFET 230, while a second set of PMOS pre-drivers 224-11 through 224-20 provide a trigger signal to a second portion 232. The first portion 231 includes MOSFETs 240-1 through 240-20 associated with bigFET gate fingers 242-1 through 242-60, while the second portion 232 can include MOSFETs 240-21 through 240-40 associated with bigFET gate fingers 242-61 through 242-120.

[0042] By separating the trigger signals of the first portion 231 and the second portion 232, a central portion 233 of the bigFET 230 can experience a high resistance, and thus the gate net resistance gradient across the bigFET 230 is normalized from both sides, i.e., the first portion 232 and the second portion 232. By feeding separate trigger signals through different edges or ends of the gate finger manifold to avoid a delay in turn-on of the MOSFETs 240, and thus effectively facilitate clamping suppression of the circuit, which can cause damage to the IC device, as described herein.

[0043] In some embodiments, each of the transistors in the pre-drivers 220-1 and 220-2 uses a single PMOS transistor to generate a trigger signal for one or more bigFET gate fingers. For example, a first PMOS pre-driver 222-1 can generate a trigger signal 226-1 for bigFET gate fingers 242-1 and 242-6, a second PMOS pre-driver 222-2 can generate a trigger signal 226-2 for bigFET gate fingers 242-7 and 242-12, and so on. In this example, the trigger signals 226 and 228 are supplied via different feed points (not shown) of the bigFET 230.

[0044] Figure 3 A method 360 for activating an ESD power clamer to provide uniform turn-on of a bigFET using pre-drivers with split circuit layout is illustrated in accordance with a number of embodiments of the present disclosure.

[0045] The method can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. One or more of the processes can be omitted in various embodiments. As such, not all processes are required in every embodiment. Other process flows are possible.

[0046] At block 361, a trigger signal is generated (e.g., via Figure 1The ESD event is detected (e.g., by the conversion rate detector 110 shown in FIG. 1).

[0047] At block 362, in response to the detected ESD event, a physically partitioned predriver layout is placed to send a plurality of trigger signals to a plurality of bigFET gate fingers via different feed points on a gate finger manifold that interconnects the plurality of bigFET gate fingers. For example, with reference to FIG. 2, the partitioned physical circuit layout of the predriver 220 can result in the formation of a first set of PMOS predrivers 222 and a second set of PMOS predrivers 224. In this example, the first set of PMOS predrivers 222 can send generated trigger signals to a front half of the bigFET gate fingers 242, while the second set of PMOS predrivers 224 can send generated trigger signals to another half of the bigFET gate fingers 242. The bigFET gate fingers 242 are associated with an array of MOSFETs 240 arranged in rows and columns to increase the current carrying capacity of the ESD power clamps. Figure 2

[0048] In some embodiments, the bigFET gate fingers are interconnected by a gate finger manifold that includes two or more feed points to receive trigger signals.

[0049] At block 363, ESD current is shunted using activated bigFETs. For example, and in response to the detection of an ESD event, the array of MOSFETs 240 is activated via the interconnected bigFET gate fingers. By supplying gate charge from two or more feed points on the gate finger manifold, the MOSFET array can turn on substantially simultaneously and without delay.

[0050] In some embodiments, the computer system can correspond to a system (e.g., with respect to the IC device 100 described above). The computer system can execute a set of instructions that are used to perform various embodiments of the present disclosure. For example, the computer system is coupled to or utilizes a memory subsystem that can be used to perform operations of the control circuitry (e.g., the ESD power clamps 102). In alternative embodiments, the computer system can be connected (e.g., networked) to other systems and / or devices in a LAN, an intranet, an extranet, and / or the Internet. The computer system can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in a cloud computing infrastructure or environment. Figure 1

[0051] ​​In the foregoing DETAILED DESCRIPTION, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure require more features than are explicitly recited in each claim. Rather, inventive subject matter can lie in fewer than all features of a single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this Detailed Description, with each claim acting as a separate embodiment of the present disclosure.

Claims

1. A method associated with an ESD power clamer, comprising: detecting an electrostatic discharge (ESD) event; in response to the detected ESD event, sending a plurality of trigger signals to a plurality of big field effect transistor (big FET) gate fingers (142; 242) via different feed points on a big FET gate finger manifold (148) via a physically segmented pre-driver layout (120; 220), the big FET gate finger manifold interconnecting the big FET gate fingers in parallel; and shunting ESD current using activated big FETs.

2. The method of claim 1, wherein the different feed points for different trigger signals include a first feed point (144) at one edge of the big FET gate finger manifold and a second feed point (146) at an opposite edge of the big FET gate finger manifold.

3. The method of claim 2, further comprising: using a first set of P-type metal oxide semiconductor (PMOS) pre-drivers to send a first trigger signal to a first portion of a metal oxide semiconductor field effect transistor (MOSFET) array via the first feed point; and using a second portion of PMOS pre-drivers to send a second trigger signal to a second portion of the MOSFET array via the second feed point.

4. The method of claim 3, wherein the use of the first feed point and the second feed point shifts higher net resistance to a central portion of the big FET gate finger manifold.

5. The method of any one of claims 1-4, wherein each of the big FET gate fingers is connected to both sides of the big FET gate finger manifold.

6. The method of any one of claims 1-4, wherein the activated big FETs are implemented by a parallel connected metal oxide semiconductor field effect transistor (MOSFET) array arranged in rows and columns.

7. The method of claim 6, wherein the big FET gate finger manifold interconnects the big FET gate fingers from the rows and columns of parallel connected MOSFETs.

8. The method of any one of claims 1-4, further comprising: detecting the ESD event using a resistor-capacitor (RC) circuit; sending an ESD detection signal to the pre-driver; and conditioning the ESD detection signal by the pre-driver to produce the trigger signals.

9. The method of claim 8, wherein the conditioning of the ESD detection signal includes amplifying the ESD detection signal.

10. An electrostatic discharge (ESD) power clamper, comprising: a slew rate detector (110; 210) that produces an ESD detection signal in response to a detected ESD event; a pre-driver (120; 220) configured to receive and condition the ESD detection signal to produce a plurality of trigger signals; and a big field effect transistor bigFET (130; 230) having a plurality of gate fingers (142; 242) connected through a gate finger manifold (148), wherein the generated trigger signals are fed to different feed points on the gate finger manifold to activate the bigFET as an ESD power clamer.

11. The ESD power clamper of claim 10, wherein the different feed points include a first feed point (144) at one edge of the gate finger manifold and a second feed point (146) at an opposite edge of the gate finger manifold.

12. The ESD power clamper of claim 11, wherein the pre-driver is further configured to: use a first portion of P-type metal-oxide-semiconductor PMOS pre-drivers to send first trigger signals to a first portion of a metal-oxide-semiconductor field effect transistor MOSFET array via the first feed point; and use a second portion of PMOS pre-drivers to send second trigger signals to a second portion of the MOSFET array via the second feed point.

13. The ESD power clamper of any of claims 10-12, further comprising: a power supply rail Vdd and a lower voltage rail Vss for biasing the bigFET, wherein the activated bigFET shunts ESD current from the Vdd to Vss.

14. An apparatus having an ESD power clamper, the apparatus comprising: a slew rate detector (110; 210) that detects an electrostatic discharge ESD event and in response to the detected ESD event, generates an ESD detection signal; a pre-driver (120; 220) having a physical layout that is partitioned into pre-driver portions to condition the ESD detection signal, wherein the pre-driver portions send trigger signals to a plurality of big field effect transistor bigFET gate fingers (142; 242) via different feed points on a gate finger manifold (148) that interconnects the bigFET gate fingers in parallel; and a bigFET (130; 230) having the plurality of bigFET gate fingers connected in parallel through the gate finger manifold, wherein the trigger signals activate the bigFET to shunt ESD current.

15. The apparatus of claim 14, wherein the different feed points include a first feed point at one end of the gate finger manifold and a second feed point at an opposite end of the gate finger manifold, and wherein the pre-driver portions include: a first set of N-channel metal-oxide-semiconductor NMOS pre-drivers to send first trigger signals to a first portion of a metal-oxide-semiconductor field effect transistor MOSFET array via the first feed point; and a second set of NMOS pre-drivers to send second trigger signals to a second portion of the MOSFET array via the second feed point.

16. The apparatus of claim 15, wherein the use of the first feed point and the second feed point shifts higher net resistance to a central portion of the gate finger manifold.

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