NMOSFET (N-channel metal oxide semiconductor field effect transistor) structure composite tube rapid triggering SCR (selective catalytic reduction) electrostatic protection device applied to multiple voltage domains

Abstract

The invention provides an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) structure composite tube rapid triggering SCR (Selective Catalytic Reduction) electrostatic protection device applied to multiple voltage domains, and relates to the technical field of electrostatic protection devices. The first P well, the first N well and the second P well are located on the P substrate; a plurality of implantation regions; a plurality of trenches; a gate oxide region; the fourth N + injection region is used as a drain electrode, the first gate oxide region is used as a gate electrode, the fifth N + injection region is used as a source electrode, and the second P well is used as a substrate to jointly form an NMOSFET; the bipolar junction transistor PNP and the bipolar junction transistor NPN jointly form an SCR structure; the P + injection region III, the N + injection region II, the P + injection region IV and the N + injection region III are of a crossed segmented structure; the gate oxide region I is connected with the N + injection region V and then is connected with the P + injection region II; the P + injection region I, the N + injection region I and the P + injection region V are jointly connected to a cathode; the protection capability of the core circuit in the chip can be comprehensively improved.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection device technology, and in particular to an ESD protection device for a fast-triggered SCR using an NMOSFET composite transistor with a multi-voltage domain structure. Background Technology

[0002] As semiconductor process linewidths continue to shrink, chip integration becomes increasingly higher, and gate oxide layer thickness continues to decrease. These factors lead to increasingly serious reliability issues for internal chip components. In complex electronic systems, electrostatic discharge (ESD) has become one of the key factors affecting circuit performance and long-term reliability.

[0003] Due to its unique positive current feedback mechanism, the silicon controlled rectifier (SCR) delivers a much higher discharge current per unit area than traditional ESD protection devices such as NMOSFETs and diodes once it is turned on. However, SCR devices inherently suffer from high trigger voltage and low sustaining voltage, thus requiring further optimization.

[0004] An existing solution embeds an N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) within an SCR device, with the drain of the NMOSFET connected across the reverse-biased P-well and N-well. Then, a low-voltage triggering silicon controlled rectifier (LVTSCR) is performed with the gate and source of the NMOSFET grounded, effectively reducing the trigger voltage of the SCR. However, this solution suffers from problems such as high overshoot voltage and slow turn-on speed under the Fast Transmission Line Pulse Test (VFTLP). Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: According to the electrostatic discharge protection device for fast-triggered SCR of NMOSFET structure composite transistor in multiple voltage domains provided in this application, the electrostatic discharge protection device includes: a P substrate (100); a P-well one (101), an N-well one (102) and a P-well two (103) located on the P substrate (100). Multiple injection zones, including P+ injection zone one (104), N+ injection zone one (106), P+ injection zone two (108), P+ injection zone three (110), N+ injection zone two (111), P+ injection zone four (112), N+ injection zone three (113), N+ injection zone four (115), N+ injection zone five (117), and P+ injection zone five (119). Multiple trenches, including trench one (105), trench two (107), trench three (109), trench four (114), trench five (118); gate oxide zone one (116); In this configuration, the N+ injection region four (115) serves as the drain, the gate oxide region one (116) serves as the gate, the N+ injection region five (117) serves as the source, and the P-well two (103) serves as the substrate, together forming an NMOSFET transistor. The P+ injection region three (110) and P+ injection region four (112) serve as emitters, the N-well one (102) serves as the base, and the P-well one (101) serves as the collector, together forming a bipolar junction transistor (PNP); the N+ injection region one (106) serves as the emitter, the P-well one (101) serves as the base, and the N-well one (102) serves as the collector, together forming a bipolar junction transistor (NPN); the bipolar junction transistor (PNP) and the bipolar junction transistor (NPN) together form an SCR structure; The P+ injection region three (110), N+ injection region two (111), P+ injection region four (112), and N+ injection region three (113) are cross-divided structures. The ratio of the division structure is adjusted according to the application voltage value of the device, and they are connected to the anode together with N+ injection region four (115). The first gate oxide region (116) and the fifth N+ implantation region (117) are connected and then connected to the second P+ implantation region (108); The P+ injection region one (104), N+ injection region one (106), and P+ injection region five (119) are all connected to the cathode.

[0006] Furthermore, the segmentation ratio of the segmentation structure is adjusted according to the applied voltage value, and the number and width of the segments are adjusted according to the device width.

[0007] Furthermore, the N+ injection region four (115), P-well two (103), and N+ injection region five (117) constitute a parasitic NPN1 device.

[0008] Furthermore, the base resistor RPW2 of the parasitic NPN1 device is composed of a P-type equivalent resistor consisting of a P-well (103) and a P-substrate (100).

[0009] Furthermore, the first trench (105) is located between the first P+ injection region (104) and the first N+ injection region (106), the second trench (107) is located between the first N+ injection region (106) and the second P+ injection region (108), the third trench (109) is located between the second P+ injection region (108) and the third P+ injection region (110), the fourth trench (114) is located between the third P+ injection region (110) and the fourth N+ injection region (115), and the fifth trench (118) is located between the fifth N+ injection region (117) and the fifth P+ injection region (119).

[0010] Furthermore, the multiple voltage domains are 1.8V, 2.5V, or 3.3V.

[0011] The present invention has at least the following beneficial effects: Fast triggering and low overshoot voltage: By directly connecting the drain of the NMOSFET to the anode and the gate and source to the base of the parasitic NPN transistor inside the SCR, the SCR can be quickly triggered to turn on by utilizing the high current gain of the composite transistor and the triggering principle of the NPN base inside the SCR structure. This significantly shortens the turn-on time, reduces the overshoot voltage in ESD events, and effectively avoids damage to the core circuit due to instantaneous high voltage.

[0012] High sustaining voltage adaptable to multiple voltage domains: The N+ and P+ strips connecting the anode are designed as a cross-segment structure (P+ injection region three, N+ injection region two, P+ injection region four, N+ injection region three). Through structural optimization, the sustaining voltage of the device is improved, enabling it to stably adapt to I / O scenarios with multiple voltage domains of 1.8V / 2.5V / 3.3V, solving the application limitation problem caused by insufficient sustaining voltage of traditional structures.

[0013] High-efficiency ESD discharge: Through the positive feedback mechanism of the SCR structure and the synergistic effect of the NMOSFET (parasitic NPN1), the SCR can dominate the discharge of ESD current after the device is turned on, resulting in strong discharge capability per unit area. At the same time, during negative ESD discharge, the PN junction diodes (PN1 / PN2 / PN3 / PN4) efficiently discharge current, comprehensively improving the protection capability of the core circuit inside the chip. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of the first electrostatic discharge protection device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the second electrostatic discharge protection device provided in an embodiment of the present invention; Figure 3 A schematic diagram of the cross-sectional structure along A to A1 provided in an embodiment of the present invention; Figure 4 A schematic diagram of the cross-sectional structure along B to B1 provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the equivalent circuit provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] It should be noted that, based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Furthermore, this device and / or practice the method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0018] The following will refer to Figure 1 The diagram shown is a structural schematic of a fast-triggered SCR electrostatic discharge (ESD) device for NMOSFET composite transistors applied in multiple voltage domains. This paper introduces a fast-triggered SCR ESD device for NMOSFET composite transistors applied in multiple voltage domains.

[0019] Combination Figure 2 As shown, the fast-triggered SCR electrostatic discharge protection device for multi-voltage domain NMOSFET structure composite transistor includes: a P substrate (100); and a P-well one (101), an N-well one (102), and a P-well two (103) located on the P substrate (100).

[0020] Multiple injection zones, including P+ injection zone one (104), N+ injection zone one (106), P+ injection zone two (108), P+ injection zone three (110), N+ injection zone two (111), P+ injection zone four (112), N+ injection zone three (113), N+ injection zone four (115), N+ injection zone five (117), and P+ injection zone five (119).

[0021] Multiple trenches, including trench one (105), trench two (107), trench three (109), trench four (114), trench five (118); and gate oxide zone one (116).

[0022] In this configuration, the N+ injection region four (115) serves as the drain, the gate oxide region one (116) serves as the gate, the N+ injection region five (117) serves as the source, and the P-well two (103) serves as the substrate, together forming an NMOSFET transistor.

[0023] The P+ injection region three (110) and P+ injection region four (112) serve as emitters, the N-well one (102) serves as the base, and the P-well one (101) serves as the collector, together forming a bipolar junction transistor (PNP); the N+ injection region one (106) serves as the emitter, the P-well one (101) serves as the base, and the N-well one (102) serves as the collector, together forming a bipolar junction transistor (NPN); the bipolar junction transistor (PNP) and the bipolar junction transistor (NPN) together form an SCR structure.

[0024] The P+ injection region three (110), N+ injection region two (111), P+ injection region four (112), and N+ injection region three (113) are cross-divided structures and are connected to the anode together with N+ injection region four (115).

[0025] The first gate oxide region (116) and the fifth N+ injection region (117) are connected and then connected to the second P+ injection region (108).

[0026] The P+ injection region one (104), N+ injection region one (106), and P+ injection region five (119) are all connected to the cathode.

[0027] In this embodiment, the core components and their functions are as follows: Basic structure: The device is based on a P substrate (100), on which P well one (101), N well one (102), and P well two (103) are set. These "wells" are the core functional areas of the semiconductor device, used to form regions of different conductivity types (P type or N type) to provide a working environment for transistors and SCR structures.

[0028] Injection regions and trenches: Multiple P+ injection regions (such as 104, 108, etc.) and N+ injection regions (such as 106, 111, etc.) are highly doped regions used to lead out electrodes or form PN junctions; trenches (such as 105, 107, etc.) serve an isolation function to prevent current from concentrating on the device surface and to isolate the main working area.

[0029] Key functional structure: The NMOSFET transistor consists of N+ injection region four (115, drain), gate oxide region one (116, gate), N+ injection region five (117, source), and P-well two (103, substrate). It is the "switch" that triggers the SCR and is responsible for quickly starting the protection mechanism.

[0030] The SCR structure consists of bipolar junction transistors (PNP, where P+ injection regions 110 and 112 are emitters, N-well 102 is the base, and P-well 101 is the collector) and NPN, where N+ injection region 106 is the emitter, P-well 101 is the base, and N-well 102 is the collector. It is the "main discharge channel" for ESD current and efficiently discharges current using a positive feedback mechanism.

[0031] The technical significance of the connection relationship: Anode connection: P+ injection region three (110), N+ injection region two (111), P+ injection region four (112), N+ injection region three (113) (cross-segment structure) and N+ injection region four (115) are connected to the anode to ensure that when an ESD event occurs, the parasitic NPN1 of the NMOSFET turns on first and then triggers the SCR to turn on.

[0032] Gate and source connection: After the gate oxide region 1 (116) and N+ injection region 5 (117) are connected, they are connected to P+ injection region 2 (108) to form the control loop of NMOSFET, ensuring that it turns on quickly when ESD is triggered.

[0033] Cathode connection: P+ injection region 1 (104), N+ injection region 1 (106), and P+ injection region 5 (119) are connected to the cathode to form the end point of the current discharge loop, ensuring that the ESD current eventually flows to the ground terminal.

[0034] Furthermore, the segmentation ratio of the segmentation structure is adjusted according to the applied voltage value, and the number and width of the segments are adjusted according to the device width.

[0035] By segmenting the N+ and P+ regions, the emitter area is reduced, and the injection of minority carriers into the PNP base region is decreased, weakening the positive feedback effect of the SCR and thus improving the SCR sustaining voltage (avoiding false triggering in low-voltage domains). For example, in the 3.3V voltage domain, the sustaining voltage can be further improved by adjusting the segmentation ratio of the P+ and N+ injection regions to meet higher voltage requirements.

[0036] The segments, such as P+ injection region three (110), N+ injection region two (111), P+ injection region four (112), and N+ injection region three (113), are automatically filled according to the actual process, and the segments are not connected.

[0037] Furthermore, the N+ injection region four (115), P-well two (103), and N+ injection region five (117) constitute a parasitic NPN1 device.

[0038] Parasitic NPN1 is a bipolar junction transistor that naturally forms during NMOSFET operation. Utilizing the high current gain principle of the composite transistor, it can amplify the trigger current and accelerate the turn-on speed of the SCR. For example, when an ESD event occurs, the parasitic NPN1 and the NPN transistor inside the SCR form a composite transistor, increasing the equivalent NPN transistor current gain, rapidly amplifying the current, and significantly shortening the SCR response time.

[0039] Furthermore, the NMOS substrate resistor RPW1 and the base resistor RPW2 of the parasitic NPN1 device are composed of a P-type equivalent resistance formed by the P-well (103) and the P-substrate (100).

[0040] This resistor is the inherent resistance of the P-type material, and its resistance value affects the conduction threshold of the parasitic NPN1. RPW1 is the P-type equivalent resistance. When ESD current flows, the parasitic NPN1 conducts when the voltage drop across the resistor reaches 0.7V (PN junction turn-on voltage), ensuring the accuracy of triggering.

[0041] Furthermore, the first trench (105) is located between the first P+ injection region (104) and the first N+ injection region (106), the second trench (107) is located between the first N+ injection region (106) and the second P+ injection region (108), the third trench (109) is located between the second P+ injection region (108) and the third P+ injection region (110), the fourth trench (114) is located between the third P+ injection region (110) and the fourth N+ injection region (115), and the fifth trench (118) is located between the fifth N+ injection region (117) and the fifth P+ injection region (119).

[0042] The purpose of trenches is to physically isolate adjacent injection regions, prevent premature failure of the current-carrying surface, and also prevent the generation of potential parasitic devices.

[0043] Furthermore, the multiple voltage domains are 1.8V, 2.5V, or 3.3V.

[0044] The device in this embodiment is suitable for multi-voltage domain I / O. Through segmented structure and optimized sustaining voltage, effective protection can be achieved under different voltages. For example, in the 1.8V interface, the sustaining voltage is designed to be 2.0V (higher than the operating voltage to avoid false triggering); in the 3.3V interface, the sustaining voltage is designed to be 4V to adapt to the operating voltage and avoid latch-up.

[0045] A schematic diagram of the cross-sectional structure along device A to A1 is shown below. Figure 3 As shown, the cross-sectional structure diagram along device B to B1 is as follows: Figure 4 As shown; via Figure 3 and Figure 4 The three-dimensional device structure is converted into a two-dimensional planar graphic for display. This cross-sectional view clearly shows the shape, position, and interconnection of each component of the device at the A and A1 sections. For example, the distribution of various regions such as the P substrate (100), P well-1 (101), and N well-1 (102), as well as the layout of the P+ and N+ implantation regions, and the positions of trenches and oxide layers can all be seen intuitively, which helps to understand the internal structure and working principle of the device.

[0046] The equivalent circuit diagram of the device is as follows: Figure 5 As shown: NMOSFET transistor model: In this embodiment, the NMOSFET is an enhancement-mode NMOSFET, corresponding to the NMOSFET structure consisting of N+ injection region four (115, drain), gate oxide region one (116, gate), N+ injection region five (117, source), and P-well two (103, substrate). In the equivalent circuit, this model is represented as a field-effect transistor, and the connection relationship between its gate (gate oxide region one) and source (N+ injection region five) directly affects the transmission of the trigger signal, serving as the core switch for the fast-start protection mechanism.

[0047] SCR structural model: Composed of bipolar junction transistors PNP and NPN, corresponding to the following device structures: PNP transistor: It consists of P+ injection region three (110), P+ injection region four (112) (emitter), N-well one (102) (base), and P-well one (101) (collector).

[0048] NPN transistor: It consists of N+ injection region (106) (emitter), P well (101) (base), and N well (102) (collector).

[0049] In the equivalent circuit, the two form a positive feedback loop, simulating the characteristics of efficient ESD current discharge after the SCR is turned on.

[0050] Parasitic NPN1 device model: The parasitic bipolar junction transistor (BJT) is formed by N+ injection region four (115), P-well two (103), and N+ injection region five (117) in the corresponding device structure. In the equivalent circuit, its function is to form a composite transistor with the NPN inside the SCR, and to amplify the trigger current by utilizing the high current gain principle of the composite transistor, thereby accelerating the turn-on speed of the SCR and solving the problem of slow response in the traditional structure.

[0051] Base resistors RPW1 and RPW2: The P-type equivalent resistance is formed by the P-well 2 (103) and the P-substrate (100) in the corresponding device structure. In the equivalent circuit, the voltage drop characteristic of this resistor determines the conduction threshold of the parasitic NPN1 (conducting when the voltage drop exceeds 0.7V), ensuring the accuracy of the triggering mechanism.

[0052] Electrode and connection relationship: The equivalent circuit clearly defines the electrical path of the anode (connecting P+ injection region 3, N+ injection region 2, P+ injection region 4, N+ injection region 3, and N+ injection region 4) and the cathode (connecting P+ injection region 1, N+ injection region 1, and P+ injection region 5), visually demonstrating the complete loop of ESD current flowing in from the anode, passing through the SCR or parasitic device, and finally being discharged from the cathode.

[0053] The purpose of equivalent circuit diagrams: Equivalent circuit diagrams simplify the physical structure and highlight the electrical functional logic, helping to understand the working mechanism of devices. For example, when an ESD event occurs, the equivalent circuit can clearly show how, after the NMOSFET is triggered, the parasitic NPN1 and the parasitic NPN connection inside the SCR become a composite transistor to amplify the current, triggering the SCR to enter a positive feedback state, and finally achieving rapid current discharge. At the same time, by labeling RPW1 and RPW2 and dividing details, the correlation between performance indicators such as trigger threshold and sustaining voltage and structural design can be intuitively analyzed, providing a theoretical basis for optimizing device adaptation to multiple voltage domains of 1.8V / 2.5V / 3.3V.

[0054] Regarding PN1-PN4: PN1-PN4 refer to the four PN junction diodes formed by a specific injection region, well, and substrate in an NMTSCR electrostatic discharge device during negative ESD discharge. Their specific composition and function are as follows: I. Composition of PN1-PN4 PN1 and PN2: It is composed of P+ implantation region 1 (104), P+ implantation region 5 (119) (as P-type region), P substrate (100) (P-type region), P well 1 (101), P well 2 (103) (as P-type region), N well 1 (102) (N-type region), and N+ implantation region 2 (111) and N+ implantation region 3 (113) (as N-type region).

[0055] Principle: The P-type region (P+ injection region, P substrate, P well) and the N-type region (N well, N+ injection region) form a PN junction. When negative ESD occurs, these PN junctions are forward biased and turned on.

[0056] PN3 and PN4: It is composed of P+ implantation region 1 (104), P+ implantation region 5 (119) (P-type region), P substrate (100) (P-type region), P well 2 (103) (P-type region) and N+ implantation region 4 (115) (N-type region).

[0057] Principle: Based on the PN junction structure of P-type and N-type regions, it conducts in the forward direction during negative ESD, forming a current discharge path.

[0058] The device in this embodiment has at least the following beneficial effects: 1. Fast response, reducing overshoot voltage By utilizing the high current gain principle of the composite transistor of NMOSFET (parasitic NPN1) and SCR internal NPN, the SCR can be quickly triggered to conduct when an ESD event occurs, reducing the impact of instantaneous high voltage on the core circuit. For example, in VFTLP testing, this solution reduces the overshoot voltage by at least 20% compared to the traditional structure, avoiding gate oxide breakdown of internal chip components.

[0059] 2. Improved sustaining voltage to adapt to multiple voltage domains The cross-segmented N+ / P+ structure increases the SCR's sustaining voltage (this solution can boost it to 2.0V~4.0V), meeting the requirements of 1.8V / 2.5V / 3.3V interfaces. For example, in a 2.5V interface, a sustaining voltage of 3V can prevent the device from mistakenly turning on during normal operation, ensuring circuit stability.

[0060] 3. Highly efficient ESD current discharge The positive feedback mechanism of the SCR structure ensures that the discharge current per unit area after conduction is much higher than that of traditional devices (such as NMOSFETs). At the same time, during negative ESD, the current is discharged through the PN junction diodes (PN1~PN4), which comprehensively improves the protection capability.

[0061] 4. Stable structure and strong compatibility Metal interconnects, trench isolation design, and adjustable partitioning structure adapt to different semiconductor processes (such as 28nm, 65nm, and 180nm processes), allowing for integration without significant modifications to the chip layout and reducing application costs.

[0062] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention.

Claims

1. An electrostatic discharge protection device for fast-triggered SCRs using an NMOSFET composite transistor in multiple voltage domains, characterized in that, The electrostatic discharge protection device includes: a P substrate (100); and a P-well one (101), an N-well one (102), and a P-well two (103) located on the P substrate (100). Multiple injection zones, including P+ injection zone one (104), N+ injection zone one (106), P+ injection zone two (108), P+ injection zone three (110), N+ injection zone two (111), P+ injection zone four (112), N+ injection zone three (113), N+ injection zone four (115), N+ injection zone five (117), and P+ injection zone five (119). Multiple trenches, including trench one (105), trench two (107), trench three (109), trench four (114), trench five (118); gate oxide zone one (116); In this configuration, the N+ injection region four (115) serves as the drain, the gate oxide region one (116) serves as the gate, the N+ injection region five (117) serves as the source, and the P-well two (103) serves as the substrate, together forming an NMOSFET transistor. The P+ injection region three (110) and P+ injection region four (112) serve as emitters, the N-well one (102) serves as the base, and the P-well one (101) serves as the collector, together forming a bipolar junction transistor (PNP); the N+ injection region one (106) serves as the emitter, the P-well one (101) serves as the base, and the N-well one (102) serves as the collector, together forming a bipolar junction transistor (NPN); the bipolar junction transistor (PNP) and the bipolar junction transistor (NPN) together form an SCR structure; The P+ injection region three (110), N+ injection region two (111), P+ injection region four (112), and N+ injection region three (113) are cross-divided structures. The ratio of the division structure is adjusted according to the application voltage value of the device, and they are connected to the anode together with N+ injection region four (115). The first gate oxide region (116) and the fifth N+ implantation region (117) are connected and then connected to the second P+ implantation region (108); The P+ injection region one (104), N+ injection region one (106), and P+ injection region five (119) are all connected to the cathode.

2. The NMOSFET composite transistor fast-triggered SCR electrostatic discharge protection device applied to multiple voltage domains as described in claim 1, characterized in that, The segmentation ratio of the segmentation structure is adjusted according to the applied voltage value, and the number and width of the segments are adjusted according to the width of the device.

3. The NMOSFET composite transistor fast-triggered SCR electrostatic discharge protection device applied to multiple voltage domains as described in claim 1, characterized in that, The N+ injection region four (115), P-well two (103), and N+ injection region five (117) constitute a parasitic NPN1 device.

4. The NMOSFET composite transistor fast-triggered SCR electrostatic discharge protection device applied to multiple voltage domains as described in claim 3, characterized in that, The base resistor RPW2 of the parasitic NPN1 device is composed of a P-type equivalent resistor consisting of a P-well (103) and a P-substrate (100).

5. The NMOSFET composite transistor fast-triggered SCR electrostatic discharge protection device applied to multiple voltage domains as described in claim 1, characterized in that, The first trench (105) is located between the first P+ injection area (104) and the first N+ injection area (106), the second trench (107) is located between the first N+ injection area (106) and the second P+ injection area (108), the third trench (109) is located between the second P+ injection area (108) and the third P+ injection area (110), the fourth trench (114) is located between the third P+ injection area (110) and the fourth N+ injection area (115), and the fifth trench (118) is located between the fifth N+ injection area (117) and the fifth P+ injection area (119).

6. The NMOSFET composite transistor fast-triggered SCR electrostatic discharge protection device applied to multiple voltage domains as described in claim 1, characterized in that, The multiple voltage domains are 1.8V, 2.5V, or 3.3V.

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