Plating single-layer capacitor

Abstract

A single-layer capacitor and a circuit board are provided. The circuit board may include a circuit board substrate having a mounting surface and a single layer capacitor at least partially embedded within the circuit board substrate. The single-layer capacitor may include a first passivation layer formed on at least a portion of a first surface of a substrate, a first conductive layer formed on at least a portion of the first passivation layer, and a second conductive layer formed on at least a portion of a second surface of the substrate. A method for forming a single layer capacitor may include: depositing a passivation layer on at least a portion of a first surface of a substrate; depositing a first conductive layer on at least a portion of the passivation layer; and depositing a second conductive layer on at least a portion of a second surface of the substrate opposite the first surface.

Description

Related Applications

[0001] This application is based on and claims priority to U.S. Provisional Patent Application No. 63 / 501,161, filed May 10, 2023, which is incorporated by reference herein. BACKGROUND

[0002] Single layer capacitors (SLCs) offer a variety of benefits, such as temperature stability, generally high breakdown voltage, and low leakage current. However, SLCs are generally relatively thin, which can hinder their usefulness in embedded applications, as embedded capacitors can require thick metal layers to allow for the formation of one or more vias for connection without running into or damaging the substrate layers of the capacitor. Accordingly, improved SLCs, such as for embedding, are needed. SUMMARY

[0003] According to one embodiment of the disclosure, a circuit board can include a circuit board substrate having a mounting surface and a single layer capacitor at least partially embedded within the circuit board substrate. The single layer capacitor can include a substrate having a first surface opposite a second surface, a first passivation layer formed on at least a portion of the first surface of the substrate, a first conductive layer formed on at least a portion of the first passivation layer, and a second conductive layer formed on at least a portion of the second surface of the substrate.

[0004] According to another embodiment of the disclosure, a single layer capacitor can include a substrate having a first surface and a second surface opposite the first surface, a first passivation layer formed on at least a portion of the first surface of the substrate, a first conductive layer formed on at least a portion of the first passivation layer, and a second conductive layer formed on at least a portion of the second surface of the substrate.

[0005] According to yet another embodiment of the disclosure, a method for forming a single layer capacitor can include depositing a first passivation layer on at least a portion of a first surface of a substrate, depositing a first conductive layer on at least a portion of the first passivation layer, and depositing a second conductive layer on at least a portion of a second surface of the substrate, the second surface opposite the first surface. BRIEF DESCRIPTION OF DRAWINGS

[0006] The complete and enabling disclosure of this application, including the best mode thereof, to one of ordinary skill in the art, is set forth in the remainder of the specification, which incorporates by reference the remaining portions of the drawings: Figure 1 Side view of a capacitor according to aspects of the disclosure; Figure 2AA circuit board according to various aspects of this disclosure is shown, the circuit board including capacitors fully embedded therein; Figure 2B Another circuit board according to various aspects of this disclosure is shown, the other circuit board including a capacitor fully embedded therein; Figure 2C A circuit board according to various aspects of the present disclosure is shown, the circuit board including capacitors partially embedded therein; Figure 3A A perspective view of a capacitor according to various aspects of this disclosure; Figure 3B for Figure 3A A side view of the capacitor; Figure 4 A circuit board according to various aspects of this disclosure is shown, the circuit board including capacitors fully embedded therein; Figure 5 A flowchart illustrating a method for forming a capacitor according to various aspects of this disclosure; and Figure 6 A flowchart of another method for forming a capacitor according to various aspects of this disclosure.

[0007] The reference numerals used repeatedly in this specification and drawings are intended to represent the same or similar features or elements of the invention. Detailed Implementation

[0008] Those skilled in the art will understand that this discussion is merely a description of exemplary embodiments and is not intended to limit the broader aspects of the invention embodied in the exemplary constructions.

[0009] Generally, the present invention relates to a single-layer capacitor having a passivation layer. For example, a single-layer capacitor (SLC or “capacitor” as used herein) may include a substrate, a passivation layer formed on at least a portion of a first surface of the substrate, a first conductive layer (or a first electrode) formed on at least a portion of the passivation layer, and a second conductive layer (or a second electrode) formed on at least a portion of a second surface of the substrate, the second surface of the substrate being opposite to the first surface of the substrate. The second passivation layer may be formed on the second surface of the substrate, and the second conductive layer may be formed on the second passivation layer such that the second passivation layer is disposed between the second conductive layer and the substrate.

[0010] A passivation layer between the substrate and the conductive layer can allow the conductive layer to be plated. More particularly, many embedded capacitor applications require a relatively thick conductive layer to allow via drilling for connections without hitting or damaging the substrate. A protective dielectric layer (i.e., passivation layer) would allow the wafer to be plated to obtain the desired thickness of the conductive layer to protect the substrate. The passivation layer can be formed on each of a pair of opposing surfaces of the substrate or wafer to allow the conductive layer to be plated on each of the pair of opposing surfaces.

[0011] Additionally or alternatively, the plated conductive layer or electrode can make the monolayer capacitor a solderable component. Typical monolayer capacitors without a plated conductive layer or electrode can only be wire bonded or connected with epoxy. A monolayer capacitor with a plated conductive layer or electrode can be soldered to, for example, a circuit board or the like, which can expand the possible applications of the monolayer capacitor.

[0012] In some embodiments, the substrate can be formed of a material having a dielectric constant (K) of less than about 30, as determined according to ASTM D2520-13 at an operating temperature of 25 °C and a frequency of 500 MHz, which in some embodiments is less than about 25, in some embodiments is less than about 20, in some embodiments is less than about 15. However, in other embodiments, a material having a dielectric constant higher than 30 can be used to achieve higher frequencies and / or smaller components. For example, in such embodiments, the dielectric constant can be in a range of about 30 to about 120 or more, as determined according to ASTM D2520-13 at an operating temperature of 25 °C and a frequency of 500 MHz, which in some embodiments is about 50 to about 100, in some embodiments is about 70 to about 90.

[0013] In other embodiments, the substrate can be formed of a material having a relatively high dielectric constant (K), such as about 10 to about 40,000, in some embodiments about 50 to about 30,000, in some embodiments about 100 to about 20,000.

[0014] The substrate can generally have a low thermal conductivity, such as less than about 10 W / (m-K), in some embodiments less than about 5 W / (m-K), in some embodiments less than about 3 W / (m-K), in some embodiments less than about 2 W / (m-K), in some embodiments less than about 1 W / (m-K), in some embodiments greater than about 0.1 W / (m-K). However, in other embodiments, the substrate can have a thermal conductivity greater than 10 W / (m-K).

[0015] The substrate can include one or more suitable ceramic materials. Suitable materials are generally electrically insulating and thermally conductive. For example, in some embodiments, the substrate can include sapphire, ruby, alumina (AI2O3), aluminum nitride (AIN), beryllium oxide (BeO), aluminum oxide (AI2O3), boron nitride (BN), silicon (Si), silicon carbide (SiC), silicon dioxide (SiO2), silicon nitride (Si3N4), gallium arsenide (GaAs), gallium nitride (GaN), zirconium dioxide (ZrO2), mixtures thereof, oxides and / or nitrides of these materials, or any other suitable ceramic material. Other example ceramic materials include barium titanate (BaTiO3), calcium titanate (CaTiO3), zinc oxide (ZnO), ceramic or other glass-bonded materials including Low-E low-fire glass. Dielectric materials such as diamond and cubic boron arsenide can also be used.

[0016] Particular examples of high dielectric material types include, for example, NPO (COG) (up to about 100) materials, X7R (about 3000 to about 7000) materials, X7S materials, Z5U materials, and / or Y5V materials. It should be understood that the above materials are described by their industry-recognized definitions, and that some of these materials are classified by standards established by the Electronic Industries Alliance (EIA) and should be recognized by one of ordinary skill in the art. For example, such materials can include ceramics. Such materials can include perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconium titanate, barium strontium zirconium titanate, barium calcium zirconium titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconium titanate, lead lanthanum titanate), bismuth sodium titanate, etc. In one particular embodiment, for example, barium strontium titanate ("BSTO") of the formula Ba x Sr 1-x TiO3, where x is from 0 to 1, in some embodiments from about 0.15 to about 0.65, in some embodiments from about 0.25 to about 0.6. Other suitable perovskites can include, for example: Ba x Ca 1-x TiO3, where x is from about 0.2 to about 0.8, in some embodiments from about 0.4 to about 0.6; Pb x Zr 1-xTi03("PZT"), where x is about 0.05 to about 0.4; lead lanthanum zirconate titanate ("PLZT"); lead titanate (PbTi03); barium calcium zirconium titanate (BaCaZrTi03); sodium nitrate (NaN03); KNb03; LiNb03; LiTa03; PbNb206; PbTa206; KSr(Nb03) and NaBa2(Nb03)5KHb2P04. Additional complex perovskites can include A[B1 1 / 3 B2 2 / 3 ]03materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1); B1is Mg y Zn 1-y (y can be a value from 0 to 1); B2is Ta z Nb 1-z (z can be a value from 0 to 1). In one particular embodiment, the dielectric material can include a titanate.

[0017] As used herein, "formed over" can mean that one layer is in direct contact with another layer. However, an intervening layer can also be formed between them. Further, "formed over" can be used in reference to a bottom surface relative to an outer surface of a component when used. Thus, a layer "formed over" a bottom surface can be closer to the exterior of the component than a layer over which the component is formed.

[0018] A passivation layer of the capacitor can be formed on at least a portion of a surface of the substrate. The passivation layer can cover the substrate and protect the substrate from a deposition process (e.g., electroplating) used to form the conductive layer on the surface of the substrate. The passivation layer can be formed from a variety of suitable materials, including polymeric materials. For example, in some embodiments, the passivation layer can be or include polyimide. In some embodiments, the one or more passivation layers can include at least one of silicon oxynitride, AI2O3, Si02, Si3N4, benzocyclobutene, or glass. The substrate and / or passivation layer can be formed from a variety of inorganic materials, such as glass, ceramic, or glass-ceramic mixtures. As noted above, the substrate can include silicon oxynitride, silicon oxide, silicon, alumina, sapphire, and / or another suitable material.

[0019] In some embodiments, the passivation layer can be formed by depositing a slurry (e.g., a glass slurry, a glass-ceramic slurry, etc.) followed by a firing step. However, any suitable process can be used to form the passivation layer.

[0020] The first conductive layer of the capacitor can be formed on at least a portion of the passivation layer. The first conductive layer can not be in direct contact and / or direct electrical connection with the substrate. In an exemplary configuration, the conductive material forming the first conductive layer can be electroplated on the passivation layer. Other methods of depositing the conductive material can also be employed, as known to those of ordinary skill in the art.

[0021] The capacitor can also include an additional conductive layer or a second conductive layer. In some embodiments, the second conductive layer can be formed on a second surface of the substrate, the second surface being opposite the first surface of the substrate on which the passivation layer and the first conductive layer are formed. Further, in some embodiments, a second passivation layer can be formed on at least a portion of the second surface of the substrate, and the second conductive layer can be formed on the second passivation layer such that the second passivation layer is disposed between the second conductive layer and the substrate. As described above with respect to the passivation layer formed between the first conductive layer and the substrate, the second passivation layer can be formed by depositing a paste (e.g., a glass paste, a glass-ceramic paste, etc.) followed by a firing step, although any suitable process can be used to form the second passivation layer. Further, the second passivation layer can be formed from a variety of suitable materials, including polymeric materials. For example, in some embodiments, the second passivation layer can be or include polyimide and / or can be or include at least one of silicon oxynitride, AI2O3, SiO2, Si3N4, benzocyclobutene, glass, ceramic, or a glass-ceramic hybrid.

[0022] The conductive layer can be formed from any of a variety of different metals known in the art. The conductive layer or electrode layer can be made of a metal (e.g., a conductive metal). The conductive material can include a noble metal (e.g., silver, gold, palladium, platinum, etc.), a base metal (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), etc., as well as various combinations thereof. The conductive layer or electrode can also be made of a low resistance material (e.g., silver, copper, gold, aluminum, palladium, etc.). In one particular embodiment, the conductive layer can include nickel or an alloy thereof.

[0023] One or more protective layers can be formed on the substrate and / or one or more passivation layers. For example, one or more protective layers can be formed on the first surface and / or the second surface of the substrate. As another example, one or more protective layers can be formed on the first passivation layer (the first passivation layer is formed on the first surface of the substrate) such that the first conductive layer is formed on the one or more protective layers. In some embodiments, one or more protective layers can similarly be formed on the second passivation layer, e.g., between the second passivation layer and the second conductive layer. Example materials for the one or more protective layers include benzocyclobutene (BCB), polyimide, silicon oxynitride, alumina (AI2O3), silicon dioxide (SiO2), silicon nitride (Si3N4), epoxy, glass, or another suitable material.

[0024] Various thin film techniques can be used to form the thin film layers of the capacitor. For example, one or more of the first conductive layer, the second conductive layer, the first passivation layer, and the second passivation layer can be a thin film layer of the capacitor. Examples of such techniques that can be employed include chemical deposition (e.g., chemical vapor deposition), Plasma Enhanced Chemical Vapor Deposition (PECVD) processing, physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin film elements. Additional examples include any suitable patterning technique (e.g., photolithography), etching, and any other suitable subtractive technique for forming thin film elements.

[0025] The thin film layers can have a range of thicknesses. For example, the thickness of the thin film layers can be in some embodiments from about 0.001 micrometers to about 100 micrometers, in some embodiments from about 0.0375 micrometers to about 40 micrometers, in some embodiments from about 0.1 micrometers to about 30 micrometers, in some embodiments from about 0.2 micrometers to about 20 micrometers, in some embodiments from about 0.4 micrometers to about 10 micrometers. For example, in some embodiments, the thickness of the resistive layer can be less than about 10 micrometers, in some embodiments less than about 8 micrometers, in some embodiments less than about 6 micrometers, in some embodiments less than about 4 micrometers.

[0026] The conductive layers can be plated on the respective passivation layers. For example, where the first passivation layer is formed on the first surface of the substrate, the first conductive layer can be plated on the first passivation layer. In embodiments that also include the second passivation layer formed on the second surface of the substrate, the second conductive layer can be plated on the second passivation layer.

[0027] The conductive layers can be formed as thin film platings of metal for each conductive layer. Such thin film platings can be formed by depositing a conductive material (e.g., a conductive metal) on the passivation layer. The plated conductive layers or electrodes can be formed by techniques known in the art, such as electroless plating, electroplating, or a combination thereof. When multiple layers are used to form the electrode, the electrode can include both electroplated layers and electroless plated layers. For example, an initial layer of material can be deposited first using electroless plating. Then, the plating technique can switch to an electrochemical plating system, which can allow for faster build-up of material. When forming one or more plated conductive layers or one or more electrodes with either plating method, at least a portion of the capacitor is subjected to the plating bath. In one embodiment, by subjected, the capacitor can be immersed in the plating bath.

[0028] The plating bath used in the plating process can include a conductive material, such as a conductive metal. For example, the plating bath can be a nickel sulfamate bath solution or other nickel solution, such that the plating layer and external terminals include nickel. Alternatively, the plating bath can be a copper acid bath or other suitable copper solution, such that the plating layer and external terminals include copper. Additionally, it should be understood that the plating bath can contain other additives known in the art. For example, the additives can include other organic additives and media that can aid in the plating process. Additionally, additives can be employed to employ the plating bath at a desired pH level. In one embodiment, a thrower additive can be employed in the solution to aid in full plating coverage and bonding of the plating material to the capacitor. The capacitor can be exposed, submerged, or immersed in the plating bath for a predetermined amount of time. The exposure time is not necessarily limited, but can be an amount of time sufficient to allow for sufficient deposition of the plating material to form the plating layer. In this regard, the time should be sufficient to allow for a continuous layer to be formed on the respective surfaces of the substrate.

[0029] The difference between electroplating and electroless plating is that electroplating employs an electrical bias, such as by using an external power source. Electroplating baths can typically be subjected to a high current density range, such as ten to fifteen amps per square foot (amp / ft 2 The connections can be made in the same plating bath as the negative connection to the capacitor that needs to form the plated terminal, and the positive connection to the solid material (e.g., copper in a copper plating bath). That is, the capacitor is biased to the opposite polarity of the plating bath. Using this method, the conductive material of the plating bath is attracted to the metal that has been disposed on the substrate. For example, as previously described, an initial amount of metal can be deposited on the substrate using an electroless plating process, while the remaining amount of metal for the conductive layer can be deposited using electroplating.

[0030] Various pretreatment steps can be employed prior to immersion of the capacitor into the plating solution or subjecting the capacitor to the plating solution. These steps can be performed for various purposes, including catalyzing, accelerating, and / or improving adhesion of the plating material to the initial metal deposit. Additionally, an initial cleaning step can be employed prior to plating or any other pretreatment step. This step can be employed to remove any oxide buildup formed on the substrate and / or initial metal deposit. Component cleaning can be achieved by complete immersion into a pre-cleaning bath (e.g., a bath including an acidic cleaner). In one embodiment, the exposure can be for a predetermined time, such as on the order of about 10 minutes. Cleaning can also be achieved alternatively by a chemical polishing or harperizing step.

[0031] Further, a step of activating the metal can be performed to facilitate deposition of the conductive material. Activation can be achieved by immersion into a palladium salt, photo patterning of a palladium organometallic precursor (through a mask or laser), screen printing or ink jet deposition of a palladium compound, or electrophoretic palladium deposition. It should be understood that palladium-based activation is presently disclosed only as an example of an activation solution that generally works well with activation of exposed portions formed from nickel or alloys thereof. However, it should be understood that other activation solutions can also be used, and thus the activation solution is not necessarily limited. Additionally, as an alternative to or in addition to the above-described activation step, an activation dopant can be introduced into the conductive material. For example, when the conductive layer includes nickel and the activation dopant includes palladium, the palladium dopant can be introduced into the nickel ink or composition forming the one or more conductive layers. Doing so can eliminate the palladium activation step. It should be further understood that some of the above-described activation methods (e.g., organometallic precursor) also facilitate co-deposition of the glass former by itself to increase adhesion to the general ceramic body of the capacitor. When an activation step is used as described above, trace amounts of the activation agent material can often remain at the exposed conductive portions before and after plating.

[0032] Additionally, post-plating treatment steps can also be employed as desired or necessary. These steps can be performed for a variety of purposes, including enhancing and / or improving adhesion of the material. For example, a heating (or annealing) step can be employed after performing the plating step. Such heating can be performed by baking, subjecting to a laser, ultraviolet (UV) exposure, microwave exposure, electric arc welding, etc.

[0033] Accordingly, as noted above, the conductive layer employed in the capacitor can include at least one plating layer. In one embodiment, the conductive layer can include only one plating layer. However, it should be appreciated that the conductive layer can include multiple plating layers. For example, the conductive layer or electrode can include a first plating layer and a second plating layer. Further, the conductive layer or electrode can also include a third plating layer. Further, the materials of these plating layers can be any of the aforementioned materials and are well known in the art. For example, one plating layer (e.g., the first plating layer) can include copper or an alloy thereof. Another plating layer (e.g., the second plating layer) can include nickel or an alloy thereof. Alternatively, another plating layer (e.g., the second plating layer) can include copper or an alloy thereof. Another plating layer (e.g., the third plating layer) can include tin, lead, gold, or a combination (e.g., alloy) thereof. Alternatively, the initial plating layer can include nickel followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper can be formed followed by a layer of nickel.

[0034] In one embodiment, the initial plating layer or first plating layer can be a conductive metal (e.g., copper). This area can then be covered with a second layer including a resistive polymeric material for sealing. This area can then be polished to selectively remove the resistive polymeric material and then plated again with a third layer including a conductive metal material (e.g., copper). The above-described second layer over the initial plating layer can correspond to a solder barrier layer, such as a nickel solder barrier layer. In some embodiments, the above-described layer can be formed by electroplating an additional metal (e.g., nickel or copper) layer on top of the initial electroplated layer or plated layer (e.g., copper plated). Other exemplary materials for the above-described solder barrier layer include nickel-phosphorous, gold, and silver. In some embodiments, the third layer over the above-described solder barrier layer can correspond to a conductive layer, such as a plated nickel Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder. Additionally, one metal plating layer can be formed followed by an electroplating step to provide a resistive alloy or higher resistance metal alloy coating over this metal plating layer, such as an electroless Ni-P alloy. However, it should be appreciated that any metal coating can be included as would be understood by one of ordinary skill in the art from the complete disclosure herein. It should be appreciated that any of the above-described steps can occur as a bulk process, such as a barrel plating process, a fluidized bed plating process, and / or a flow-through plating terminal process, all of which are well known in the art. Such bulk processes enable simultaneous processing of multiple components, thereby providing an efficient and fast electrode deposition process. This is a particular advantage over traditional electrode deposition methods, such as the printing of thick film conductive layers or electrode layers that require individual component processing.

[0035] In some embodiments, the electrically conductive layer can be formed such that the electrically conductive layer is relatively thick. For example, such an electrically conductive layer can be formed by applying a thick film strip of metal to the substrate. Such a metal can be in a glass matrix and can include silver or copper. For example, such a strip can be printed and fired onto the capacitor, or can be deposited by immersing the capacitor in a liquid conductive material. Such application of a thick film electrically conductive layer can include any method known in the art (e.g., by a print wheel transferring a metal-laden paste to the substrate). In some embodiments, additional layers can be plated over one or more thick film electrically conductive layers using any suitable plating method described herein.

[0036] The thick film electrically conductive layer can have an average thickness of at least about 5 μιη (microns), such as about 10 microns or greater, about 20 microns or greater, about 25 microns or greater, about 35 microns or greater, about 50 microns or greater, or about 75 microns or greater. The thick film electrically conductive layer can have an average thickness of about 500 microns or less, such as about 300 microns or less, such as about 200 microns or less, such as about 150 microns or less, such as about 100 microns or less, such as about 80 microns or less. For example, the thick film electrically conductive layer can have an average thickness in a range of about 5 microns to about 150 microns, such as in a range of about 10 microns to about 100 microns, such as in a range of about 25 microns to about 75 microns. In one embodiment, the above thickness refers to the average thickness of the entire electrically conductive portion or electrode of the capacitor that is applied or deposited on one surface of the capacitor (e.g., can include applying more than one layer of electrically conductive material to achieve a first electrically conductive layer or electrode on a first surface of the substrate and / or a second electrically conductive layer or electrode on a second surface of the substrate). In another embodiment, the above thickness refers to the average thickness of an individual layer of the electrically conductive layer or electrode of the capacitor.

[0037] In some embodiments, the capacitor can be at least partially embedded in a circuit board (e.g., a printed circuit board (PCB), etc.). For example, the capacitor can be disposed in an opening or cavity of the circuit board such that at least a portion of the capacitor is surrounded by the circuit board. A portion of the capacitor can protrude or extend above a mounting surface of the circuit board, or at most, an outermost surface of the capacitor can be coplanar with the mounting surface of the circuit board, while the remainder of the capacitor is within the opening or cavity and surrounded by the circuit board. In at least some embodiments, the capacitor can be electrically connected to the circuit board, for example, through a via or other conductive path extending from the capacitor to a conductive region (e.g., an electrically conductive layer, terminal, or port) of the circuit board.

[0038] Figure 1is a side view of a single-layer capacitor 100 in accordance with aspects of the present disclosure. The single-layer capacitor 100 can also be referred to herein as an SLC 100 or a capacitor 100. As shown, the capacitor 100 can include a substrate 102 having a first surface 104 and a second surface 106 opposite the first surface 104 along a height or thickness direction Z. The substrate 102 can be formed of a dielectric material. In some embodiments, the dielectric material can have a relatively low dielectric constant (K), although in other embodiments the dielectric material can have a relatively high dielectric constant. Figure 1

[0039] The capacitor 100 can include a first conductive layer 108 formed on at least a portion of the first surface 104 of the substrate 102 and a second conductive layer 110 formed on at least a portion of the second surface 106 of the substrate 102. In some embodiments, the first conductive layer 108 is a thick-film conductive layer and has a first thickness ti of at least about 5 microns. For example, the first conductive layer 108 can have a first thickness ti of at least about 10 microns, a first thickness ti of at least about 12 microns, a first thickness ti of at least about 20 microns, a first thickness ti of at least about 40 microns, a first thickness ti of at least about 80 microns, a first thickness ti of at least about 100 microns, a first thickness ti of at least about 250 microns, or a first thickness ti of at least about 500 microns. In some embodiments, the first thickness ti can be in a range of about 5 microns to about 150 microns, about 10 microns to about 100 microns, or about 25 microns to about 75 microns. The first conductive layer 108 can also have other thicknesses.

[0040] Similarly, in at least some embodiments, the second conductive layer 110 is a thick-film conductive layer and has a second thickness t2 of at least about 5 microns. For example, the second conductive layer 110 can have a second thickness t2 of at least about 10 microns, a second thickness t2 of at least about 12 microns, a second thickness t2 of at least about 20 microns, a second thickness t2 of at least about 40 microns, a second thickness t2 of at least about 80 microns, a second thickness t2 of at least about 100 microns, a second thickness t2 of at least about 250 microns, or a second thickness t2 of at least about 500 microns. In some embodiments, the second thickness t2 can be in a range of about 5 microns to about 150 microns, about 10 microns to about 100 microns, or about 25 microns to about 75 microns. The second conductive layer 110 can also have other thicknesses.

[0041] Further, in at least some embodiments, the substrate thickness t sub may be at least about 50 microns. For example, the substrate thickness t sub ​The substrate thickness can be at least about 75 micrometers, at least about 100 micrometers, at least about 150 micrometers, at least about 250 micrometers, at least about 500 micrometers, or at least about 1000 micrometers. In some embodiments, the substrate thickness t sub The ratio to the first thickness t1 can be at least 2, for example, at least 2, at least 2.5, at least 3, or at least 4. Similarly, in some embodiments, the substrate thickness t... sub The ratio to the second thickness t2 can be at least 2, for example at least 2, at least 2.5, at least 3 or at least 4.

[0042] Still referencing Figure 1 The substrate can have a substrate thickness t along the height direction or the thickness direction Z. sub In some embodiments, the substrate thickness t sub The thickness t1 can be greater than at least one of the thickness t1 of the first conductive layer 108 or the thickness t2 of the second conductive layer 110. In other embodiments, the substrate thickness t sub It can be greater than the sum of the thickness t1 of the first conductive layer 108 and the thickness t2 of the second conductive layer 110. In other embodiments, the substrate thickness t... sub It can be less than at least one of the thickness t1 of the first conductive layer 108 or the thickness t2 of the second conductive layer 110.

[0043] It should be understood that the first conductive layer 108 and the second conductive layer 110 may be formed of any suitable conductive material described elsewhere herein, and the substrate 102 may be formed of any suitable dielectric material described elsewhere herein.

[0044] In some embodiments, the first conductive layer 108 and / or the second conductive layer 110 may extend over the entire respective surfaces 104, 106, on which the respective layers 108, 110 are formed. For example, the first conductive layer 108 may extend to each edge of the first surface 104 defining the substrate 102, and / or the second conductive layer 110 may extend to each edge of the second surface 106 defining the substrate 102. Alternatively, the first conductive layer 108 and / or the second conductive layer 110 may be offset from one or more edges of the respective surfaces 104, 106, for example, as shown below. Figure 1 As shown.

[0045] Now for reference Figures 2A to 2C The diagram shows a side view of a circuit board 250 according to various aspects of the present disclosure, the circuit board having a single-layer capacitor 100 at least partially embedded therein. The circuit board 250 may include a circuit board substrate 252 having a mounting surface 254. Figure 2A and Figure 2B In the illustrated embodiment, capacitor 100 is fully embedded in circuit board substrate 252. More specifically, inFigure 2A In embodiments, the capacitor 100 is fully embedded within the circuit board substrate 252 such that the substrate 102, the first conductive layer 108, and the second conductive layer 110 of the capacitor 100 are each positioned below the mounting surface 254 of the circuit board 250 along the height or thickness direction Z. In such embodiments, the capacitor 100 is considered to be fully embedded in the circuit board 250 because no portion of the capacitor 100 extends above, beyond, or outside of the circuit board 250. Figure 2B In embodiments, the capacitor 100 is fully embedded within the circuit board substrate 252 such that the first conductive layer 108 of the capacitor 100 is coplanar with the mounting surface 254 of the circuit board 250. For example, the outermost surface of the first conductive layer 108 (i.e., the surface of the first conductive layer 108 opposite the first surface 104 of the substrate 102) can be coplanar with the mounting surface 254 of the circuit board 250, and the capacitor 100 is still considered to be fully embedded in the circuit board 250 because no portion of the capacitor 100 extends above, beyond, or outside of the circuit board 250. In other embodiments, the capacitor 100 can be partially embedded within the circuit board substrate 252 such that a portion of the capacitor 100 is disposed within the circuit board 250, while the remaining portion of the capacitor 100 (e.g., the first conductive layer 108 of the capacitor 100 and / or at least a portion of the substrate 102 of the capacitor 100) protrudes from or is outside of the circuit board 250, for example, along the height or thickness direction Z. For example, in embodiments where the capacitor 100 is partially embedded within the circuit board substrate 252, the first conductive layer 108 of the capacitor 100 can be coplanar with the mounting surface 254 of the circuit board 250, and the substrate 102 of the capacitor 100 can protrude from or be outside of the circuit board 250 along the height or thickness direction Z. Figure 2C In embodiments, the capacitor 100 is partially embedded within the circuit board substrate 252 such that the first conductive layer 108 extends above the mounting surface 254 of the circuit board 250.

[0046] As further shown in Figures 2A to 2C The capacitor 100 can be electrically connected with the conductive layer 256 of the circuit board 250. For example, as shown in Figure 2A The via 258 can extend from the first conductive layer 108 of the capacitor 100 to the mounting surface 254 of the circuit board 250 and connect to the conductive layer 256 formed on the mounting surface 254. In this way, the via 258 of the circuit board 250 can electrically connect the capacitor 100 with the conductive layer 256 of the circuit board 250.

[0047] Referring to Figure 2B and Figure 2C In other embodiments, the conductive path 260 can electrically connect the capacitor 100 with the conductive layer 256 of the circuit board 250. As shown in Figure 2B and Figure 2C The conductive path 260 extends from the first conductive layer 108 of the capacitor 100 to the conductive layer 256 of the circuit board 250. In this way, the conductive path 260 of the circuit board 250 can electrically connect the capacitor 100 with the conductive layer 256 of the circuit board 250.

[0048] Turning now to Figure 3A ,Figure 3B and Figure 4 Other embodiments of embedded single-layer capacitors will be described. Figure 3A and Figure 3B depict perspective and side views, respectively, of a single-layer capacitor 300. Similar to the capacitor 100 described above, the capacitor 300 includes a substrate 302 having a first surface 304 and a second surface 306 opposite the first surface 304 along a height or thickness direction Z. The capacitor 300 also includes a first conductive layer 308 formed on at least a portion of the first surface 304 of the substrate 302 and a second conductive layer 310 formed on at least a portion of the second surface 306 of the substrate 302.

[0049] However, unlike the capacitor 100, Figure 3A and Figure 3B The capacitor 300 shown also includes a first passivation layer 312 and a second passivation layer 314. The first passivation layer 312 is formed on at least a portion of the first surface 304 of the substrate 302 such that the first passivation layer 312 is disposed between the substrate 302 and the first conductive layer 308. The second passivation layer 314 is formed on at least a portion of the second surface 306 of the substrate 302 such that the second passivation layer 314 is disposed between the substrate 302 and the second conductive layer 310. The passivation layers 312, 314 can facilitate formation of the conductive layers 308, 310 using a plating method (e.g., electroless plating, electroplating, etc.), which can increase the utility or functionality of the single-layer capacitor.

[0050] In some embodiments, the first passivation layer 312 and / or the second passivation layer 314 can extend across the respective surface 304, 306 on which the respective passivation layer 312, 314 is formed. For example, the first passivation layer 312 can extend to each edge defining the first surface 304 of the substrate 302 and / or the second passivation layer 314 can extend to each edge defining the second surface 306 of the substrate 302. Alternatively, the first passivation layer 312 and / or the second passivation layer 314 can be offset from one or more edges of the respective surface 304, 306, e.g., as shown in Figure 3A and Figure 3B

[0051] ​Similarly, the first conductive layer 308 may extend over the entire first passivation layer 312, for example, the first conductive layer 308 may extend to each edge of the first passivation layer 312, and / or the second conductive layer 310 may extend over the entire second passivation layer 314, for example, the second conductive layer 310 may extend to each edge of the second passivation layer 314. In other embodiments, the first conductive layer 308 and / or the second conductive layer 310 may be offset from one or more edges of the respective passivation layers 312, 314, on which the respective conductive layers 308 and 310 are formed.

[0052] like Figure 3B As shown, the first conductive layer 308 may have a first thickness t1 along the height direction or the thickness direction Z, and the second conductive layer 310 may have a second thickness t2 along the height direction or the thickness direction Z. The first passivation layer 312 may have a first passivation thickness t along the height direction or the thickness direction Z. p1 The second passivation layer 314 may have a second passivation thickness t along the height direction or the thickness direction Z. p2 Similarly, substrate 302 may have a substrate thickness t along the height direction or the thickness direction Z. sub .

[0053] In some embodiments, the thickness t1 of the first conductive layer 308 and the thickness t2 of the second conductive layer 310 may be approximately equal. However, in other embodiments, the first thickness t1 of the first conductive layer 308 or the second thickness t2 of the second conductive layer 310 may be greater than another thickness t1, t2. Similarly, in various embodiments, the passivation thickness t of the first passivation layer 312 is... p1 The passivation thickness t of the second passivation layer 314 p2 They can be approximately equal, or the passivation thickness t of the first passivation layer 312. p1 The passivation thickness t of the second passivation layer 314 p2 They can be different. In some embodiments, the first thickness t1 of the first conductive layer 308 and / or the second thickness t2 of the second conductive layer 310 can be greater than the first passivation thickness t. p1 Second passivation thickness t p2 In other embodiments, the first passivation thickness t p1 Or the second passivation thickness t p2 At least one of the following can be greater than at least one of the first thickness t1 or the second thickness t2.

[0054] In addition, substrate thickness t sub The thickness can be greater than the corresponding thickness of each individual layer 308, 310, 312, 314. In some embodiments, the substrate thickness t submay be equal to or greater than the sum of the respective thicknesses of each individual layer 308, 310, 312, 314. However, in other embodiments, the thickness of at least one of the first conductive layer 308, the second conductive layer 310, the first passivation layer 312, or the second passivation layer 314 can be greater than the substrate thickness t sub , or in other embodiments, the substrate thickness t sub may be less than the sum of the respective thicknesses of each individual layer 308, 310, 312, 314. For example, in some embodiments, the ratio of the substrate thickness t sub to the sum of the respective thicknesses of each individual layer 308, 310, 312, 314 can be at least about 1, such as at least about 1.5, at least about 2, at least about 2.5, at least about 3, or at least about 4. However, in other embodiments, the ratio of the substrate thickness t sub to the sum of the respective thicknesses of each individual layer 308, 310, 312, 314 can be about 1 or less, such as about 0.9 or less, about 0.8 or less, about 0.75 or less, or about 0.7 or less.

[0055] In some embodiments, the first passivation thickness t p1 and / or the second passivation thickness t p2 may be at least about 50 Angstroms, such as at least about 75 Angstroms, at least about 100 Angstroms, or at least about 150 Angstroms. Further, the substrate thickness t sub may be at least about 50 microns, such as at least about 75 microns, at least about 100 microns, at least about 150 microns, at least about 250 microns, at least about 500 microns, or at least about 1000 microns.

[0056] Referring now to Figure 4 , a side view of a circuit board 450 having a single-layer capacitor 300 at least partially embedded therein is provided in accordance with aspects of the present disclosure. The circuit board 450 can include a circuit board substrate 452 having a mounting surface 454. In the embodiment shown in Figure 4 , the capacitor 300 is fully embedded in the circuit board substrate 452. More particularly, in the embodiment shown in Figure 4 , the capacitor 300 is fully embedded within the circuit board substrate 452 such that the substrate 302, the first conductive layer 308, the first passivation layer 312, the second passivation layer 314, and the second conductive layer 310 of the capacitor 300 are each positioned below the mounting surface 454 of the circuit board 450 along a height or thickness direction Z. Although not shown herein, it should be appreciated that in other embodiments, the capacitor 300 can be fully embedded within the circuit board substrate 452 such that the first conductive layer 308 of the capacitor 300 is coplanar with the mounting surface 454 of the circuit board 450 in a manner similar to that described with respect to Figure 2BIn other embodiments, the capacitor 300 can be partially embedded within the circuit board substrate 452 such that the first conductive layer 308, the first passivation layer 312, at least a portion of the substrate 302, the second passivation layer 314, and / or a portion of the second conductive layer 310 of the capacitor 300 extend above the mounting surface 454 of the circuit board 450 along the height or thickness direction Z, as shown with respect to the capacitor 100 in Figure 2C .

[0057] As further shown, the capacitor 300 can be electrically connected with the conductive layer 456 of the circuit board 450. For example, as shown in Figure 4 , a via 458 can extend from the first conductive layer 308 of the capacitor 300 to the mounting surface 454 of the circuit board 450 and connect to the conductive layer 456 formed on the mounting surface 454. In this way, the via 458 of the circuit board 450 can electrically connect the capacitor 300 with the conductive layer 456 of the circuit board 450. In other embodiments, a conductive path (e.g., a conductive path formed on the mounting surface 454 similar to the conductive path 260 of the circuit board 250 shown in Figure 4 and Figure 2B may electrically connect the capacitor 300 with the conductive layer 456 of the circuit board 450. Figure 2C

[0058] Referring now to Figure 5 , aspects of the present subject matter are directed to a method 500 for forming a single-layer capacitor as described herein. Generally, the method 500 will be described herein with reference to the capacitor 100 of Figure 1 , Figure 2A , Figure 2B and Figure 2C . However, it should be understood that the disclosed method 500 can be implemented with any suitable capacitor. Moreover, although the steps are depicted in a particular order for purposes of illustration and discussion, the methods discussed herein are not limited to any particular order or arrangement. Using the disclosure provided herein, those skilled in the art will appreciate that the individual steps of the methods disclosed herein can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present subject matter. Figure 5

[0059] ​​The method 500 can include (502) depositing a first conductive layer 108 on at least a portion of the first surface 104 of the substrate 102 of the capacitor 100. The first conductive layer 108 can have a thickness of at least about 10 microns, such as a thickness of at least about 20 microns, at least about 40 microns, or at least about 80 microns. The first conductive layer 108 can cover the entire first surface 104 of the substrate 102, or can be offset from one or more edges defining a perimeter of the first surface 104. The first conductive layer 108 can be formed from any suitable conductive material, such as described herein.

[0060] The method 500 can also include (504) depositing a second conductive layer 110 on at least a portion of the second surface 106 of the substrate 102 of the capacitor 100. The second conductive layer 110 can have a thickness of at least about 10 microns, such as a thickness of at least about 20 microns, at least about 40 microns, or at least about 80 microns. The second conductive layer 110 can cover the entire second surface 106 of the substrate 102, or can be offset from one or more edges defining a perimeter of the second surface 106. The second conductive layer 110 can be formed from any suitable conductive material, such as described herein.

[0061] It should be appreciated that (502) depositing the first conductive layer 108 and (504) depositing the second conductive layer 110 can include finishing the capacitor 100 (the substrate 102 having the first and second conductive layers 108, 110 on opposing surfaces) using any suitable method (e.g., firing, etc.) to ensure that the components of the capacitor 100 adhere to one another and prepare the capacitor 100 for use in, for example, the circuit board 250 described herein.

[0062] In some embodiments, depositing the first conductive layer 108 can include printing (e.g., screen printing) the first conductive layer 108 on at least a portion of the first surface 104 of the substrate 102. Similarly, in some embodiments, depositing the second conductive layer 110 can include printing (e.g., screen printing) the second conductive layer 110 on at least a portion of the second surface 106 of the substrate 102. It should be appreciated that screen printing the first and / or second conductive layers 108, 110 can include utilizing screen printing techniques known in the art. However, one or more of the conductive layers 108, 110 can be applied to the substrate 102 by any known process, such as spin coating, dipping, casting, drop casting, spraying, vapor deposition, sputtering, sublimation, doctor blading, daubing, or printing (e.g., inkjet printing, screen printing, or pad printing).

[0063] In some embodiments, one or more additional conductive material layers may be deposited on an initially printed conductive material layer to form a first conductive layer 108 and / or a second conductive layer 110, wherein the thickness of the first and second conductive layers is at least about 5 micrometers, for example, about 10 micrometers or greater. For example, depositing the first conductive layer 108 may include printing the first conductive material layer on a first surface 104 of the substrate 102, and then depositing at least one additional conductive material layer on the first conductive material layer. Similarly, depositing the second conductive layer 110 may include printing the second conductive material layer on a second surface 106 of the substrate 102, and then depositing at least one additional conductive material layer on the second conductive material layer.

[0064] Now go to Figure 6 This subject matter relates to a method 600 for forming a single-layer capacitor as described herein. Generally, this document will refer to... Figure 3A , Figure 3B and Figure 4 The method 600 is described using a capacitor 300. However, it should be understood that the disclosed method 600 can be implemented with any suitable capacitor. Furthermore, although... Figure 6 The steps performed in a particular order are depicted for illustrative and discussion purposes, but the methods discussed herein are not limited to any particular order or arrangement. Those skilled in the art will understand, using the disclosure provided herein, that the steps of the methods disclosed herein can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the subject matter.

[0065] Method 600 may include (602) depositing a first passivation layer 312 on at least a portion of a first surface 304 of a substrate 302 of a monolayer capacitor 300. The passivation layer 312 may be formed of a variety of suitable materials, including polymeric and / or inorganic materials such as glass or ceramic. For example, in some embodiments, the first passivation layer 312 may be or include polyimide. In some embodiments, one or more passivation layers may include at least one of silicon oxynitride, Al2O3, SiO2, Si3N4, benzocyclobutene, or glass.

[0066] Method 600 may include (604) depositing a first conductive layer 308 on at least a portion of the first passivation layer 312, such that the first passivation layer 312 is disposed between the first surface 304 of the substrate 302 and the first conductive layer 308. The first conductive layer 308 may be contained within the periphery of the first passivation layer 312; for example, the first conductive layer 308 may extend to the edge of the first passivation layer 312 and / or deviate from one or more edges of the first passivation layer 312. The first conductive layer 308 may not be in direct contact with and / or directly electrically connected to the substrate 302.

[0067] Further, the method 600 can include (606) depositing a second passivation layer 314 on at least a portion of the second surface 306 of the substrate 302, where the second surface 306 is opposite the first surface 304 on which the first passivation layer 312 is formed. Like the first passivation layer 312, the second passivation layer 314 can be formed of various suitable materials, including polymeric materials and / or inorganic materials, such as at least one of glass, ceramic, polyimide, silicon oxynitride, AI2O3, SiO2, Si3N4, or benzocyclobutene.

[0068] Further, the method 600 can include (608) depositing a second conductive layer 310 on at least a portion of the second passivation layer 314 such that the second passivation layer 314 is disposed between the second surface 306 of the substrate 302 and the second conductive layer 310. The second conductive layer 310 can be contained within a perimeter of the second passivation layer 314, e.g., the second conductive layer 310 can extend to the edges of the second passivation layer 314 and / or offset from one or more edges of the second passivation layer 314. The second conductive layer 310 can not be in direct contact and / or direct electrical connection with the substrate 302.

[0069] As described elsewhere herein, depositing the first passivation layer 312 and / or the second passivation layer 314 can include depositing a paste (e.g., a glass paste, a glass-ceramic paste, etc.) on the substrate 302 and then firing the substrate and paste to form one or more passivation layers on the substrate 302. However, any suitable process can be used to form the one or more passivation layers. It will be appreciated that depositing the one or more passivation layers on the substrate 302, e.g., by depositing a paste as described above and firing the paste and substrate 302 to deposit the one or more passivation layers on the substrate, is followed by depositing the respective conductive layers 308, 310 on the respective passivation layers 312, 314.

[0070] Further, depositing the first conductive layer 308 and / or the second conductive layer 310 can include plating the first conductive layer 308 on the first passivation layer 312 and / or plating the second conductive layer 310 on the second passivation layer 314. As described above, the first conductive layer 308 and / or the second conductive layer 310 can be plated using an electroplating method and / or an electroless plating method.

[0071] In any case, it should be understood that the (602) depositing the first passivation layer 312, (604) depositing the first conductive layer 308, (606) depositing the second passivation layer 314, and (608) depositing the second conductive layer 310 can include finishing the capacitor 300 (the substrate 302 having the first conductive layer 308 and the first passivation layer 312 on the surface opposite the second conductive layer 310 and the second passivation layer 314) using any suitable method (e.g., firing, etc.) to ensure that the components of the capacitor 300 adhere to one another and prepare the capacitor 300 for use, for example, in the circuit board 450 described herein.

[0072] Application The capacitors described herein can be used in a variety of applications, such as hybrid packaged components and filtering internal packaged semiconductors. In addition, the capacitors can be used in devices that process wideband radio frequency signals because the capacitors exhibit superior performance at high frequencies (e.g., frequencies of 20 GHz or higher). Example devices include mobile devices (e.g., cell phones, tablets, etc.), cell phone towers, Receiver Optical Sub Assemblies (ROSA), Transmission Optical Sub Assemblies (TOSA), and other RF communication devices. Such RF devices are particularly useful in military and space applications.

[0073] These and other modifications and variations to the present application can be practiced by those of ordinary skill in the art, without departing from the spirit and scope of the present application. In addition, it should be understood that aspects of the various embodiments can be interchanged either in whole or in part. In addition, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the present application further described in the appended claims.

Claims

1. A circuit board, comprising: a circuit board substrate having a mounting surface; and a monolayer capacitor at least partially embedded within the circuit board substrate, the monolayer capacitor comprising: a substrate having a first surface opposite a second surface, a first passivation layer formed on at least a portion of the first surface of the substrate, a first conductive layer formed on at least a portion of the first passivation layer, and a second conductive layer formed on at least a portion of the second surface of the substrate.

2. The circuit board of claim 1, the monolayer capacitor further comprising: a second passivation layer formed on at least a portion of the second surface of the substrate, wherein the second conductive layer is formed on the second passivation layer such that the second passivation layer is disposed between the substrate and the second conductive layer.

3. The circuit board of claim 1, the monolayer capacitor further comprising: at least one via connected with the first conductive layer, the at least one via extending toward the mounting surface of the circuit board substrate. a circuit board conductive layer is formed on the mounting surface, and wherein the at least one via electrically connects the circuit board conductive layer and the first conductive layer of the monolayer capacitor.

4. The circuit board of claim 3, wherein, the monolayer capacitor is completely embedded within the circuit board substrate such that the substrate, the first passivation layer, the first conductive layer, and the second conductive layer are each positioned below the mounting surface along a height direction.

5. The circuit board of claim 1, wherein, the monolayer capacitor is completely embedded within the circuit board substrate such that the first conductive layer is coplanar with the mounting surface.

6. The circuit board of claim 1, wherein, the monolayer capacitor is partially embedded within the circuit board substrate such that one or more of the substrate, the first passivation layer, the first conductive layer, or the second conductive layer extend above the mounting surface along a height direction.

7. The circuit board of claim 1, wherein, 8. A monolayer capacitor, comprising: a substrate having a first surface and a second surface opposite the first surface; a first passivation layer formed on at least a portion of the first surface of the substrate; a first conductive layer formed on at least a portion of the first passivation layer; and a second conductive layer formed on at least a portion of the second surface of the substrate.

9. The monolayer capacitor of claim 8, further comprising: a second passivation layer formed on at least a portion of the second surface of the substrate, wherein the second conductive layer is formed on the second passivation layer such that the second passivation layer is disposed between the substrate and the second conductive layer.

10. A method for forming a monolayer capacitor, the method comprising: depositing a first passivation layer on at least a portion of a first surface of a substrate; depositing a first conductive layer on at least a portion of the first passivation layer; and depositing a second conductive layer on at least a portion of a second surface of the substrate. ​ ​ depositing a second conductive layer on at least a portion of a second surface of the substrate, the second surface opposite the first surface.

11. The method of claim 10, further comprising: depositing a second passivation layer on at least a portion of the second surface of the substrate such that the second passivation layer is disposed between the second surface of the substrate and the second conductive layer.

12. The method of claim 11, wherein, depositing the first passivation layer and the second passivation layer prior to depositing the first conductive layer or the second conductive layer, and wherein depositing the first passivation layer and depositing the second passivation layer comprise depositing a slurry and firing the substrate on which the slurry is deposited.

13. The method of claim 12, wherein, depositing the second conductive layer comprises plating the second conductive layer on the second passivation layer.

14. The method of claim 10, wherein, depositing the first passivation layer comprises depositing a slurry and firing the substrate on which the slurry is deposited.

15. The method of claim 14, wherein, depositing the first conductive layer comprises plating the first conductive layer on the first passivation layer.

Images