Automatic integrated debugging method for FPGA (Field Programmable Gate Array) design and simulation platform
By automating the acquisition of HDL source code paths and updating the top-level files of the simulation platform, combined with a solution database, the file and path errors in FPGA design and simulation platform integration were resolved, improving debugging efficiency and reducing development difficulty.
Patent Information
- Application Number
- CN202511073740.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2025-11-25
AI Technical Summary
During the integration of FPGA design and simulation platforms, issues such as file mismatch, path errors, and signal errors can occur, making manual debugging time-consuming and difficult to resolve. This is especially true for inexperienced engineers, increasing the difficulty of development and verification.
It employs automated methods to obtain HDL source code and its path, creates or updates top-level files for the simulation platform, automatically integrates HDL source code and the simulation platform, and provides solutions by matching warnings and errors in the problem-solving database.
It reduces the difficulty of FPGA design and simulation platform integration, improves debugging efficiency, and saves critical time, especially in the early stages of FPGA development.
Smart Images
Figure CN121009844A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of aerospace FPGA design and verification, and in particular to an automated integrated debugging method for FPGA design and simulation platforms. Background Technology
[0002] Simulation is a crucial verification method in FPGA development and verification. Simulation waveforms allow observation of all internal signals within the FPGA, playing a vital role in FPGA development, debugging, and verification. However, FPGA logic simulation requires integrating FPGA design files and simulation files, a process typically performed manually. Resolving various issues that arise during this process demands significant experience.
[0003] As FPGA designs continue to grow in scale, the number of files in FPGA projects also increases, including some unused files. Simulation technology has evolved, and to adapt to large-scale FPGA design and reduce the development difficulty of simulation platforms, a generalized architecture has been developed. However, the number of simulation platform files remains large. Currently, when integrating FPGA designs with simulation platforms, various problems arise, such as redundant or missing files, path errors, and signal errors. Furthermore, because the top-level files of FPGA designs can have hundreds of module ports, manually connecting them to the simulation platform is extremely time-consuming. Therefore, during integration and testing, a large number of errors and warnings are frequently reported for various reasons. For less experienced FPGA engineers, resolving these errors and warnings is very difficult, posing a significant challenge to the entire FPGA development and verification process. Summary of the Invention
[0004] The purpose of this invention is to provide an automated integration and debugging method for FPGA design and simulation platforms, which reduces the difficulty and probability of errors in FPGA design and simulation platform integration, and efficiently completes FPGA development and verification work.
[0005] The objective of this invention is achieved through the following technical solution:
[0006] An automated integration and debugging method for FPGA design and simulation platforms includes the following steps:
[0007] Step 1: Automatically obtain the HDL source code and its path from the FPGA design project file under test;
[0008] Step 2: Create or update the top-level file of the simulation platform and automatically obtain the simulation platform code path;
[0009] Step 3: Automated integration of the HDL source code under test and the simulation platform;
[0010] Step 4: Automated matching of warnings and errors with solutions provided by the database.
[0011] Preferably, step one includes the following steps:
[0012] Step 11: Write a tcl file to automatically read FPGA design project file information and store it in a .txt file;
[0013] Step 12: Automatically obtain the HDL source code file path based on the keywords in the .txt file and write it to the HDL source code path file;
[0014] Step 13: Automatically read valid HDL source code from the project files into the HDL source code folder using the HDL source code path file.
[0015] Preferably, in step two, when integrating the simulation platform and HDL source code for the first time, a top-level file of the simulation platform is created to obtain this information; if there is new HDL source code, it is determined whether the top-level file of the simulation platform needs to be updated, and if so, it is updated.
[0016] During updates, the system automatically retrieves the top-level file template of the simulation platform, automatically compares it with existing top-level files to generate a new top-level file, and automatically retrieves the simulation platform code path.
[0017] Preferably, in step three, the simulation platform code is placed into the corresponding folder according to the defined simulation directory, and the Make script file and its commands are written according to the defined template file to automatically integrate the HDL source code to be tested and the simulation platform code file.
[0018] The Make script file sets up commands through five processes and then automatically runs the commands to integrate the HDL source code under test and the simulation platform code files. The five processes include setting up the logic compilation library, linking the actual compilation library and the logic compilation library, compiling the design file, compiling the simulation platform file and the simulation test case file, and executing the simulation.
[0019] Preferably, in step four, the solution database is formed by confirming the warnings and error types of the simulation tool and collecting corresponding solutions; during simulation compilation, warnings and errors are automatically matched with the solution database, and the database suggests solutions; FPGA designers and verification personnel try to solve the problem according to the solutions, and if the solutions provided cannot solve the problem, they solve the problem themselves, and after the problem is solved, the solution is added to the solution database.
[0020] The beneficial effects of this invention are as follows:
[0021] This invention provides an automated integration and debugging method for FPGA design and simulation platforms, which can effectively reduce the difficulty of debugging the simulation environment and improve the efficiency of simulation verification. Since this method can be used repeatedly in any FPGA design and verification process, especially in the early stages of FPGA development, its application is very wide and can save the most critical time in FPGA development. Attached Figure Description
[0022] Figure 1 Flowchart of Automated Integration and Debugging Methods for FPGA Design and Simulation Platforms
[0023] Figure 2 Method for automatically obtaining HDL source code and its path from FPGA project packages
[0024] Figure 3 Automated process of obtaining simulation platform templates and updating simulation platform top-level files
[0025] Figure 4 Simulation of compilation warnings and error automation matching company database process
[0026] Figure 5 FPGA simulation compilation warnings and error troubleshooting database Detailed Implementation
[0027] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.
[0028] This embodiment illustrates an automated integration and debugging method for an FPGA design and simulation platform. It can automatically acquire valid files from the HDL source code of the FPGA design under test, automatically integrate the simulation platform and the FPGA design under test, automatically link with the database, and provide solutions for compilation errors and warnings, thereby quickly resolving problems encountered during the integration and debugging process.
[0029] See Figure 1 As shown, the automated integration and debugging method for FPGA design and simulation platform consists of four steps: automatically obtaining HDL source code and its path from the FPGA project under test, updating the top-level file of the simulation platform and automatically obtaining the simulation platform code path, automatically integrating HDL source code and simulation platform, and automatically matching and resolving warnings and errors during the simulation compilation stage with solutions provided by the database. The final result is a debugged simulation environment. Each step is described in detail below.
[0030] Step 1: Automatically obtain HDL source code and its path from the FPGA design project file under test.
[0031] There are currently many FPGA products on the market. The following implementation will use Microchip's FPGA and the corresponding development tool Libero SOC as an example.
[0032] HDL source code includes manually written HDL code and tool-generated IP core source code, which are displayed in the project file according to the design concept. In addition to the required HDL source code, the actual project file may also contain some unused code. Therefore, directly copying the code from the project file as the HDL source code will result in redundant code in the HDL source code. During subsequent simulation and debugging, each problem needs to be analyzed and the redundant code deleted one by one, which is very troublesome. Therefore, it is possible to use... Figure 2 The automated method shown below is for obtaining the HDL source code and its path.
[0033] Step 11: Write a tcl file to automatically read FPGA design project file information and store it in a .txt file;
[0034] Step 12: Automatically obtain the HDL source code file path based on the keywords in the .txt file and write it to the HDL source code path file;
[0035] Step 13: Automatically read valid HDL source code from the project files into the HDL source code folder using the HDL source code path file.
[0036] Step 2: Create or update the top-level file of the simulation platform and automatically obtain the simulation platform code path.
[0037] The simulation platform's top-level file consists of multiple parts. Taking the System Verilog top-level file as an example, it includes basic functions such as signal definitions, interface instantiation, design instantiation and program (test) instantiation, clock functions, and initial block reset. When integrating the simulation platform and HDL source code for the first time, the simulation platform's top-level file should be created to obtain this information. If new HDL source code is available, it's necessary to determine whether the simulation platform's top-level file needs updating. If so, it should be updated. For example, if the signals in the PFGA design's top-level file change, the simulation platform's top-level file should be updated; otherwise, updating it is generally unnecessary.
[0038] When an FPGA design has a large number of top-level signals, errors in signal count or signal name are very likely to occur during instantiation. Therefore, this paper proposes an automated method to obtain the top-level file template of the simulation platform, automatically compare it with existing top-level files to generate a new top-level file, and automatically obtain the simulation platform code path. This provides input for automated integration. For details, please refer to [reference needed]. Figure 3 .
[0039] Step 21: Use tcl files to automatically read the FPGA top-level design file and the test program (test) file in the HDL source code file, automatically obtain all signals and signal directions in the FPGA top-level file, and automatically obtain all interface types in the program.
[0040] Step 22: If this is the first time writing the top-level file for the simulation platform, automatically generate the design instantiation (without signal connections), program instantiation (without signal connections), interface instantiation, clock function block, signal declaration, and initial block based on the acquired information; then manually complete the signal connections in the program instantiation and program instantiation.
[0041] Step 23: If this is not the first time writing the simulation platform top-level file, then the simulation platform top-level file needs to be updated. Automated comparison of the FPGA top-level design signals is performed using the simulation platform top-level file template and existing simulation platform top-level files. Comparison information such as unchanged signals, added signals, and deleted signals is provided, and the simulation platform top-level file is updated accordingly.
[0042] Step 24: Automated acquisition of the simulation platform code folder path and file path.
[0043] Step 3: Automated integration of the HDL source code under test and the simulation platform
[0044] According to the defined simulation directory, put the simulation platform code into the corresponding folder, and write the Make script file and its commands according to the defined template file to automatically integrate the HDL source code to be tested and the simulation platform code file.
[0045] The Make script file sets up commands through five processes, then automates the execution of these commands to integrate the HDL source code under test and the simulation platform code files. The five processes include setting up the logic compilation library, linking the actual compilation library and the logic compilation library, compiling the design files, compiling the simulation platform files and simulation test case files, and executing the simulation.
[0046] Step 4: Automated matching of warnings and errors with solutions provided by the database.
[0047] After integrating the simulation platform and HDL source code, the biggest problem encountered was the numerous warnings and errors reported during execution. Resolving these issues required significant time and effort, and less experienced engineers might struggle to find solutions. Therefore, this paper proposes establishing a database of simulation warnings and error troubleshooting approaches within the company. This database primarily identifies the types of warnings and errors encountered by the simulation tool and collects corresponding solutions. During simulation compilation, the database is automatically matched, and it provides suggested troubleshooting approaches. FPGA designers and verification personnel attempt to resolve the problem based on these approaches. If the suggested solutions fail, they attempt to solve the problem independently. After a problem is resolved, the solution approach is added to the company database. For details, please refer to [link to relevant documentation]. Figure 4 For example, if you encounter the problem "No such file or directory" during simulation, please refer to [link / reference needed]. Figure 5 This database of FPGA simulation compilation warnings and errors categorizes issues into two types: warnings and errors. For each warning and error, it provides multiple solutions. FPGA designers and verifiers can use these solutions to address the problems step by step, reducing the difficulty and efficiency of simulation and saving time in FPGA design and verification.
[0048] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.
Claims
1. An automated integrated debugging method for an FPGA design and simulation platform, comprising the following steps: Step 1: Automatically obtain the HDL source code and its path from the FPGA design project file under test; Step 2: Create or update the top-level file of the simulation platform and automatically obtain the simulation platform code path; Step 3: Automated integration of the HDL source code under test and the simulation platform; Step 4: Automated matching of warnings and errors with solutions provided by the database.
2. The automated integration and debugging method for an FPGA design and simulation platform according to claim 1, characterized in that... Step one includes the following steps: Step 11: Write a tcl file to automatically read FPGA design project file information and store it in a .txt file; Step 12: Automatically obtain the HDL source code file path based on the keywords in the .txt file and write it to the HDL source code path file; Step 13: Automatically read valid HDL source code from the project files into the HDL source code folder using the HDL source code path file.
3. The automated integration and debugging method for an FPGA design and simulation platform according to claim 1, characterized in that... In step two, when integrating the simulation platform and HDL source code for the first time, a top-level file of the simulation platform is created to obtain this information; if there is new HDL source code, it is determined whether the top-level file of the simulation platform needs to be updated, and if so, it is updated. During the update, the system automatically retrieves the top-level file template of the simulation platform, automatically compares it with the existing top-level file of the simulation platform to generate a new top-level file of the simulation platform, and automatically retrieves the code path of the simulation platform.
4. The automated integration and debugging method for an FPGA design and simulation platform according to claim 1, characterized in that... In step three, the simulation platform code is placed into the corresponding folder according to the defined simulation directory, and the Make script file and its commands are written according to the defined template file to automatically integrate the HDL source code to be tested and the simulation platform code file. The Make script file sets up commands through five processes and then automatically runs the commands to integrate the HDL source code under test and the simulation platform code files. The five processes include setting up the logic compilation library, linking the actual compilation library and the logic compilation library, compiling the design file, compiling the simulation platform file and the simulation test case file, and executing the simulation.
5. The automated integration and debugging method for an FPGA design and simulation platform according to claim 1, characterized in that... In step four, the solution database is formed by confirming the warnings and error types of the simulation tool and collecting corresponding solutions. During simulation compilation, warnings and errors are automatically matched with the solution database, and the database suggests solutions to the problems. FPGA designers and verification personnel attempt to solve problems based on existing solutions. If a solution fails to resolve the issue, they solve it independently and add the solution to the solution database afterward.