Electrostatic protection structure, preparation method and electrostatic protection circuit

Abstract

The invention provides an electrostatic protection structure, a preparation method and an electrostatic protection circuit. The electrostatic protection structure comprises a substrate, a well region which is formed on the substrate and has a second doping type, a gate structure which is formed on the surface of the well region, and a drain region and a source region which are formed in the well region at two sides of the gate structure, the drain region at least comprises a first drift region with a first doping type, a first heavily doped region with the first doping type and a second heavily doped region with a second doping type, wherein the first heavily doped region and the second heavily doped region are formed in the first drift region at intervals; and the source region at least comprises a second drift region with the first doping type and a third drift region with the second doping type which are arranged at intervals, a fourth heavily doped region with the first doping type formed in the second drift region, and a fourth heavily doped region with the second doping type formed in the third drift region. A positive feedback loop is formed in the electrostatic protection structure, so that the amplified ESD current is discharged.

Description

Technical Field

[0001] This application belongs to the field of semiconductors, and in particular relates to an electrostatic discharge (ESD) protection structure and its preparation method, as well as an ESD protection circuit. Background Technology

[0002] ESD HVMOS devices are electrostatic discharge (ESD) protection devices specifically designed for high voltage (HV) integrated circuits, and are widely used in power management, display drivers, automotive electronics, and other fields.

[0003] The existing technology provides an ESD HVMOS device that is a gate-grounded NMOS (GGNMOS) device. See [link to relevant documentation] Figure 1 The ESD HVMOS device includes: a P-type substrate 10a, a P-type well region 11a formed on the P-type substrate 10a, a first N-type heavily doped region 12a located in the drain region, a second N-type heavily doped region 13a located in the source region, and a P-type heavily doped region 14a located in the base region of the P-type well region 11a; the first N-type heavily doped region 12a, the second N-type heavily doped region 13a, and the P-type heavily doped region 14a are separated by an isolation structure 15a; a first N-type drift region 121a, a second N-type drift region 131a, and a P-type drift region 141a are formed in the P-type well region 11a; a gate 16a is formed on the surface of the P-type well region 11a, and an oxide layer 161a is formed between the gate 16a and the P-type well region 11a; and a contact layer 17a is formed on the surface of the first N-type heavily doped region 12a, the second N-type heavily doped region 13a, the P-type heavily doped region 14a, and the gate 16a.

[0004] The principle of this ESD HVMOS device for discharging ESD current is as follows: When ESD current flows through the anode into the first heavily doped region 12a and the first N-type drift region 121a, the PN junction formed by the first N-type drift region 121a and the P-type well region 11a is reverse-broken down, thereby generating a large number of electron-hole pairs. The generated holes flow into the P-type well region 11a, thus raising the potential of the P-type well region 11a. When the potential of the P-type well region 11a is higher than 0.7V, the PN junction formed by the second heavily doped region 13a and the P-type well region 11a is forward-biased. Ultimately, the parasitic bipolar junction transistor (BJT) inside the ESD HVMOS device is turned on, that is, the NPN parasitic BJT formed between the first N-type heavily doped region 12a-first N-type drift region 121a / P-type heavily doped region 14a-P-type drift region 141a-P-type well region 11a / second N-type heavily doped region 13a-second N-type drift region 131a is turned on, thereby forming a low-resistance channel to discharge the ESD current.

[0005] However, the aforementioned ESD HVMOS devices can only discharge ESD current through parasitic BJTs with NPN conduction. Their trigger voltage is high (dependent on avalanche breakdown) and the current is relatively concentrated. The devices have poor robustness and can only discharge small ESD currents, not large ESD currents. Summary of the Invention

[0006] In view of this, one of the objectives of this application is to provide an electrostatic protection structure and its fabrication method, which aims to solve the technical problem in the related art that ESD HVMOS devices based on GGNMOS structures cannot discharge large ESD currents.

[0007] Another objective of this application is to provide an electrostatic protection circuit that applies the above-mentioned electrostatic protection structure, thereby providing electrostatic protection through the above-mentioned electrostatic protection structure.

[0008] In a first aspect, this application provides an electrostatic protection structure, comprising: The substrate, a well region having a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region in the well regions on both sides of the gate structure; The drain region includes at least a first drift region having a first doping type, a first heavily doped region having a first doping type and a second heavily doped region having a second doping type formed in the first drift region at intervals; The source region includes at least a second drift region with a first doping type and a third drift region with a second doping type, which are spaced apart, a third heavily doped region with a first doping type formed in the second drift region, and a fourth heavily doped region with a second doping type formed in the third drift region.

[0009] Optionally, one of the first doping type and the second doping type is N-type doping and the other is P-type doping.

[0010] Optionally, the drain region further includes: A fifth doped region having a first doping type, the fifth doped region being in contact with the first drift region.

[0011] Optionally, the drain region further includes a fourth drift region having a first doping type, the fourth drift region extending below the gate structure and contacting a fifth heavily doped region.

[0012] Optionally, the depth of the fourth drift region is the same as the depth of the first drift region.

[0013] Optionally, the first drift region of the drain region is formed with a plurality of first isolation structures; the first isolation structures are formed between the first heavily doped region and the second heavily doped region, and between the second heavily doped region and the fifth heavily doped region.

[0014] Optionally, the depth of the first isolation structure is lower than the depth of the first drift region, and the depth of the first isolation structure is greater than the depth of the first heavily doped region, the depth of the second heavily doped region, and the depth of the fifth heavily doped region, respectively.

[0015] Secondly, this application provides a method for preparing an electrostatic protection structure, including: Provide substrate; A well region with a second doping type is formed on the substrate; An isolation structure is formed in the well region to isolate at least the regions containing the first and second heavily doped regions in the well region of the drain region, and to isolate the regions containing the third and fourth heavily doped regions in the well region of the source region. Through ion implantation, several drift regions with a certain spacing are formed in the well region, including at least a first drift region with a first doping type located in the drain region, a second drift region with a first doping type located in the source region, and a third drift region with a second doping type. A gate structure is fabricated on the well region between the first drift region and the second drift region; First to fourth doped regions are formed by ion implantation. The first and third doped regions have a first doping type, and the second and fourth doped regions have a second doping type.

[0016] Optionally, it also includes: A fifth doped region with a first doping type is formed in the well region and the first drift region by ion implantation.

[0017] Optionally, it also includes: A fourth drift region with a first doping type is formed in the well region by ion implantation process, and the fourth drift region extends below the gate structure. A fifth doped region with the first doping type is formed in the fourth drift region, the well region, and the first drift region by ion implantation.

[0018] Optionally, the isolation structure of the drain region is a first isolation structure, the depth of the first isolation structure is lower than the depth of the first drift region, and the depth of the first isolation structure is greater than the depth of the first heavily doped region, the depth of the second heavily doped region, and the depth of the fifth heavily doped region, respectively.

[0019] Optionally, the depth of the fourth drift region is the same as the depth of the first drift region.

[0020] Thirdly, this application provides an electrostatic discharge (ESD) protection circuit formed using the ESD protection structure described in any of the preceding claims, or including an ESD protection structure prepared using the method described in any of the preceding claims.

[0021] The unexpected technical effects of the technical solution provided in this application include: This application provides an electrostatic discharge (ESD) protection structure. A first drift region is formed in the source region of the ESD protection structure, along with a first heavily doped region and a second heavily doped region within the first drift region. An unexpected technical effect is that the first heavily doped region, the first drift region, the well region, the second drift region, and the third heavily doped region form one of an NPN-triggered first parasitic BJT or a PNP-triggered second parasitic BJT. A fourth heavily doped region, the third drift region, the well region, the first drift region, and the second heavily doped region form the other of the NPN-triggered first parasitic BJT or a PNP-triggered second parasitic BJT. The base of the NPN-triggered first parasitic BJT serves as the collector of the PNP-triggered second parasitic BJT, and the base of the PNP-triggered second parasitic BJT also serves as the collector of the NPN-triggered first parasitic BJT. The collector current of the NPN-triggered first parasitic BJT directly drives the base of the PNP-triggered second parasitic BJT, and the collector current of the PNP-triggered second parasitic BJT in turn drives the base of the NPN-triggered first parasitic BJT. Ultimately, a positive feedback loop is formed between the NPN-triggered first parasitic BJT and the PNP-triggered second parasitic BJT (the current amplification factor of the first parasitic BJT is...). The current amplification factor of the second parasitic BJT is The current amplification factor of the formed positive feedback loop is The current amplification factor of the electrostatic protection structure is increased through a positive feedback loop, thereby enabling the electrostatic protection structure to discharge amplified current.

[0022] A high current amplification factor can reduce the trigger voltage of the electrostatic discharge (ESD) protection structure, thereby reducing heat accumulation and the likelihood of secondary breakdown when discharging amplified ESD current. Furthermore, the positive feedback loop can distribute the current evenly throughout the entire ESD protection structure, further preventing localized overheating. Simultaneously, the positive feedback loop forces the current to be evenly distributed within the ESD protection structure, increasing its secondary breakdown voltage. This allows the electrostatic discharge protection structure to operate at higher voltages without secondary breakdown. Ultimately, it achieves the goal of discharging amplified ESD current using an ESD HVMOS device based on a GGNMOS structure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of the structure of an ESD HVMOS device is provided for related technologies; Figure 2 This is a schematic diagram of the electrostatic protection structure provided in one embodiment of this application; Figure 3 A flowchart illustrating the preparation method of an electrostatic protection structure provided in an embodiment of this application; Figure 4 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 5 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 6 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 7 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 8 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 9 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 10 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 11 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 12 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 13 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 14 This is a schematic diagram of the electrostatic protection structure provided in an embodiment of this application during the fabrication process; Figure 15 A schematic diagram of the simulation results of an electrostatic protection structure provided in this application.

[0025] Related technologies provided Figure 1 The accompanying figure labels are as follows: 10a: P-type substrate; 11a: P-type well region; 12a: First heavily doped N-type region; 121a: First N-type drift region; 13a: Second heavily doped N-type region; 131a: Second N-type drift region; 14a: Heavily doped P-type region; 141a: P-type drift region; 15a: Isolation structure; 16a: Gate; 161a: Oxide layer; 17a: Contact layer.

[0026] This application provides Figures 2 to 14 The accompanying figure labels are as follows: 10: Substrate; 21: Well region; 22: Drain region; 221: First drift region; 222: First heavily doped region; 223: Second heavily doped region; 224: Fifth heavily doped region; 225: Fourth drift region; 226: First isolation structure; 23: Source region; 231: Second drift region; 232: Third drift region; 233: Third heavily doped region; 234: Fourth heavily doped region; 235: Second isolation structure; 30: Gate structure; 31: Gate; 32: Gate dielectric layer; 33: Gate sidewall.

[0027] 40: Ohmic contact layer. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] Related technologies provide ESD HVMOS devices based on GGNMOS structures that rely on the low-resistance discharge path formed by the parasitic BJT with NPN conduction to discharge ESD current, but the following problems exist: In GGNMOS-based ESD HVMOS devices, the parasitic BJT with NPN conduction has a low current amplification factor (β value) (typically only 1~10). A low β value means that the avalanche injection current is insufficient to maintain large current conduction (i.e., insufficient to sustain large ESD current discharge), requiring a higher trigger voltage. and maintaining current This will further exacerbate the heat generation of the device.

[0030] The conduction of an NPN depends on avalanche breakdown (avalanche breakdown of the PN junction formed between the drain and well regions, or avalanche breakdown of the PN junction formed between the drift region connected to the drain and the well region), reaching [a certain value]. Previously, some of the ESD current had been dissipated within the device, exacerbating localized heating. A higher trigger voltage means higher power consumption, which will further exacerbate heat accumulation.

[0031] In a GGNMOS structure, the conduction of a parasitic BJT depends on avalanche breakdown (primary breakdown), but the secondary breakdown current of the parasitic BJT in a GGNMOS structure ( Generally small (in the mA to A range).

[0032] The base region of a parasitic BJT consists of a lightly doped P-type well with high resistivity (typically 10~100 Ω·cm). Under large ESD currents, the ohmic voltage drop in the base region is significant (due to the presence of base resistance, the base current ( The generation of an ohmic voltage drop in the base region leads to a weak base region conductivity modulation effect. In other words, the hole injection efficiency is low, making it difficult to conduct the entire device uniformly. The current is non-uniformly distributed and the local current density is high. The current will preferentially pass through low-resistance paths (such as the edge of the drain region), thus forming local hot spots.

[0033] High local current density can trigger Joule heating, causing the device temperature to rise. This temperature increase leads to an exponential increase in intrinsic carrier concentration. The increased intrinsic carrier concentration further reduces local resistivity, causing current concentration to increase further, resulting in a positive thermal feedback loop. Ultimately, this leads to thermal runaway, secondary breakdown, and device failure.

[0034] Based on the above analysis, the following defects can be identified in the existing ESD HVMOS devices based on the GGNMOS structure: (1) High trigger voltage caused by low β value ( This can lead to localized overheating of the device.

[0035] (2) Thermal positive feedback formed by non-uniform current distribution, and the secondary breakdown current of the device ( The lower ) makes the device more susceptible to secondary breakdown.

[0036] Figure 2 This is a schematic diagram of an electrostatic protection structure provided in one embodiment of this application. See also... Figure 2 ,include: Substrate 10, well region 21 with a second doping type formed on the substrate 10, gate structure 30 formed on the surface of well region 21, and drain region 22 and source region 23 formed in well regions 21 on both sides of gate structure 30; The drain region 22 includes at least a first drift region 221 with a first doping type, and a first heavily doped region 222 with a first doping type and a second heavily doped region 223 with a second doping type formed in the first drift region 221. The source region 23 includes at least a second drift region 231 with a first doping type and a third drift region 232 with a second doping type, which are spaced apart, a third heavily doped region 233 with a first doping type formed in the second drift region 231, and a fourth heavily doped region 234 with a second doping type formed in the third drift region 232.

[0037] It should be noted that when the electrostatic discharge structure discharges ESD current, the first heavily doped region 222 and the second heavily doped region 223 of the electrostatic discharge structure are connected to the anode, and the third heavily doped region 233, the fourth heavily doped region 234 and the gate structure 30 of the electrostatic discharge structure are connected to the cathode.

[0038] It should be noted that in the embodiments of the present invention, the depth of all drift regions is basically the same, all of which are greater than the depth of the heavily doped regions, the depth of all heavily doped regions is basically the same, and the depth of all isolation structures is between the drift region and the heavily doped region.

[0039] In one example, substrate 10 can be any one of a silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a silicon carbide (SiC) substrate, a silicon-on-sapphire (SOS) substrate, a gallium arsenide (GaAs) substrate, a gallium nitride (GaN) substrate, or a germanium (Ge) substrate.

[0040] For example, substrate 10 can be a Si substrate.

[0041] In one example, the drain region 22 further includes: A fifth doped region 224 having a first doping type is in contact with the first drift region 221.

[0042] In this embodiment, a fifth doped region 224 is further provided, which connects the well region 21 and the first drift region 221. Since the doping concentration of the fifth doped region 224 is higher than that of the first drift region 221, when the first doped region 222 and the second doped region 223 receive ESD current, the fifth doped region 224 with a higher doping concentration is more prone to avalanche breakdown than the first drift region 221 (the higher the doping concentration, the lower the difficulty of avalanche breakdown), thereby conducting the positive feedback loop formed by the NPN and PNP parasitic BJTs in the electrostatic protection structure.

[0043] In this embodiment, the fifth doped region 224 is located between the gate structure 30 and the second doped region 223.

[0044] In one example, the drain region 22 further includes: A fourth drift region 225 having a first doping type extends below the gate structure 30 and contacts a fifth heavily doped region 224, the depth of the fourth drift region 225 being greater than that of the fifth heavily doped region 224.

[0045] In this embodiment, a fourth drift region 225 is additionally provided between the fifth doped region 224 and the gate structure 30. The fourth drift region 225, with a doping concentration higher than that of the well region 21, can increase the flow path of charge carriers. The base region for charge carrier movement is lengthened from the original width of the first drift region 221 to the width of the first drift region 221 and the fourth drift region 225 plus the depth of the fourth drift region 225, which is beneficial to further increase the secondary breakdown voltage of the electrostatic protection structure.

[0046] In one example, the depth of the fourth drift region 225 is the same as the depth of the first drift region 221.

[0047] In one example, a first isolation structure 226 is formed in the drain region 22, the first isolation structure 226 being disposed between the first heavily doped region 222 and the second heavily doped region 223, and between the second heavily doped region 223 and the fifth heavily doped region 224.

[0048] In one example, the depth of the first isolation structure 226 is lower than the depth of the first drift region 221, and the depth of the first isolation structure 226 is greater than the depth of the first heavily doped region 222, the depth of the second heavily doped region 223, and the depth of the fifth heavily doped region 224, respectively.

[0049] In one example, the source region 23 has a second isolation structure 235, which is disposed between the third doped region 233 and the fourth doped region 234, and between the third doped region 233 and the gate structure 30.

[0050] As an example provided in this application, the first isolation structure 226 and the second isolation structure 235 are shallow trench isolation (STI) structures.

[0051] In one example, one of the first doping type and the second doping type is N-type doping and the other is P-type doping.

[0052] In one example, N-type doping can be done with pentavalent elements, and P-type doping can be done with trivalent elements.

[0053] As an example, N-type doping elements can include elements such as phosphorus and arsenic.

[0054] As an example, p-type doping elements can include elements such as boron and indium.

[0055] As the first possible implementation provided in this application, the first doping type is N-type doping and the second doping type is P-type doping.

[0056] In the first possible implementation provided in this application, the well region 21 is a P-type well region. In the drain region 22, the first drift region 221, the first heavily doped region 222, and the fifth heavily doped region 224 are N-type doped regions, and the second heavily doped region 223 is a P-type doped region. In the source region 23, the second drift region 231 and the third heavily doped region 233 are N-type doped regions, and the third drift region 232 and the fourth heavily doped region 234 are P-type doped regions.

[0057] In the first possible implementation provided in this application, the first heavily doped region 222, the first drift region 221, the fifth heavily doped region 224, the well region 21, the second drift region 231, and the third heavily doped region 233 form an NPN-triggered first parasitic BJT. The fourth heavily doped region 234, the third drift region 232, the well region 21, the first drift region 221, and the second heavily doped region 223 form a PNP-triggered second parasitic BJT.

[0058] At this time, when the electrostatic protection structure encounters an ESD event, after an avalanche breakdown occurs between the fifth heavily doped region 224 and the well region 21, the positive feedback loop formed by the first parasitic BJT triggered by NPN and the second parasitic BJT triggered by PNP is turned on. The ESD current is introduced from the anode into the first heavily doped region 222 and the first drift region 221 and then flows to the fifth heavily doped region 224, thereby discharging the ESD current from the cathode through the low-resistance discharge path formed by the positive feedback loop.

[0059] In the first possible implementation, well region 21 is a high-voltage (HV) P-type well region, and the P-type doping concentration of well region 21 is [missing information]. .

[0060] In the first possible implementation, the first drift region 221 is an N-type drift region, and the N-type doping concentration of the first drift region 221 is... .

[0061] In the first possible implementation, the first heavily doped region 222 is an N+ type doped region, and the N-type doping concentration of the first heavily doped region 222 is... .

[0062] In the first possible implementation, the second doped region 223 is a P+ type doped region, and the P-type doping concentration of the second doped region 223 is... .

[0063] In the first possible implementation, the fifth doped region 224 is an N+ type doped region, and the N-type doping concentration of the fifth doped region 224 is... .

[0064] In the first possible implementation, the fourth drift region 225 is an N-type drift region, and the N-type doping concentration of the fourth drift region 225 is... .

[0065] In the first possible implementation, the second drift region 231 is an N-type drift region, and the N-type doping concentration of the second drift region 231 is... .

[0066] In the first possible implementation, the third drift region 232 is a P-type drift region, and the P-type doping concentration of the third drift region 232 is... .

[0067] In the first possible implementation, the third doped region 233 is an N+ type doped region, and the N-type doping concentration of the third doped region 233 is... .

[0068] In the first possible implementation, the fourth doped region 234 is a P+ type doped region, and the P-type doping concentration of the fourth doped region 234 is [missing information]. .

[0069] In the second possible implementation provided in this application, the first doping type is P-type doping and the second doping type is N-type doping.

[0070] In the second possible implementation provided in this application, the well region 21 is an N-type well region. In the drain region 22, the first drift region 221, the first heavily doped region 222, and the fifth heavily doped region 224 are P-type doped regions, and the second heavily doped region 223 is an N-type doped region. In the source region 23, the second drift region 231 and the third heavily doped region 233 are P-type doped regions, and the third drift region 232 and the fourth heavily doped region 234 are N-type doped regions.

[0071] In a second possible implementation provided in this application, the first heavily doped region 222, the first drift region 221, the fifth heavily doped region 224, the well region 21, the second drift region 231, and the third heavily doped region 233 form a PNP-triggered second parasitic BJT. The fourth heavily doped region 234, the third drift region 232, the well region 21, the first drift region 221, and the second heavily doped region 223 form an NPN-triggered first parasitic BJT.

[0072] In the second possible implementation provided in this application, well region 21 is a high-voltage well N-type well region, and the N-type doping concentration of well region 21 is [missing information]. .

[0073] In the second possible implementation provided in this application, the first drift region 221 is a P-type drift region, and the P-type doping concentration of the first drift region 221 is [missing information]. .

[0074] In the second possible implementation provided in this application, the first heavily doped region 222 is a P+ type doped region, and the P-type doping concentration of the first heavily doped region 222 is [missing information]. .

[0075] In the second possible implementation provided in this application, the N+ type doping region of the second heavily doped region 223 has an N-type doping concentration of [missing information]. .

[0076] In the second possible implementation provided in this application, the fifth doped region 224 is a P+ type doped region, and the P-type doping concentration of the fifth doped region is [missing information]. .

[0077] In the second possible implementation provided in this application, the fourth drift region 225 is a P-type drift region, and the P-type doping concentration of the fourth drift region 225 is [missing information]. .

[0078] In the second possible implementation provided in this application, the second drift region 231 is a P-type drift region, and the P-type doping concentration of the second drift region 231 is [missing information]. .

[0079] In the second possible implementation provided in this application, the third drift region 232 is an N-type drift region, and the N-type doping concentration of the third drift region 232 is [missing information]. .

[0080] In the second possible implementation provided in this application, the third doped region 233 is a P+ type doped region, and the P-type doping concentration of the third doped region 233 is [missing information]. .

[0081] In the second possible implementation provided in this application, the fourth doped region 234 is an N+ type doped region, and the N-type doping concentration of the fourth doped region 234 is [missing information]. .

[0082] In one example provided in this application, the gate structure 30 includes a gate 31, a gate dielectric layer 32, and a gate sidewall 33.

[0083] In one example, the gate 31 may be made of polysilicon after ion implantation or a metal material, including TiN or W.

[0084] In one example, the gate dielectric layer 32 is made of any one of silicon dioxide (SiO2), silicon oxynitride (SiON), or high-k materials.

[0085] As an example, high-k dielectric materials include materials such as HfO2, HfSiO4, and HfLaO.

[0086] In one example, the material used for the gate sidewall 33 includes Si3N4 or SiO2.

[0087] In one example, the first heavily doped region 222, the second heavily doped region 223, and the anode are connected by an ohmic contact layer 40, and the third heavily doped region 233, the fourth heavily doped region 234, the gate structure 30, and the cathode are connected by an ohmic contact layer 40.

[0088] In one example, the ohmic contact layer 40 can be made of any of the following materials: Ti, TiN, Ni, etc.

[0089] Figure 3 A flowchart illustrating the fabrication method of an electrostatic protection structure according to an embodiment of this application. See also... Figure 3 ,include: S101, Provide substrate.

[0090] The substrate material is described in the aforementioned description of the electrostatic protection structure and will not be repeated here.

[0091] S102, A well region with a second doping type is formed on the substrate.

[0092] In one example, well region 21 can be formed by ion implantation into substrate 10. If well region 21 is a P-type well region, P-type dopant is implanted. If well region 21 is an N-type well region, N-type dopant is implanted. The range of doping concentrations for well region 21 is described in the preceding description of the electrostatic protection structure and will not be repeated here.

[0093] See Figure 4 The diagram shows the well region 21 prepared on the substrate 10.

[0094] S103. An isolation structure is formed in the well region to isolate at least the regions where the first and second heavily doped regions are located in the well region of the drain region, and to isolate the regions where the third and fourth heavily doped regions are located in the well region of the source region.

[0095] In one example, step S103 includes: Multiple first isolation structures 226 are formed in the drain region and multiple second isolation structures 235 are formed in the source region.

[0096] In one example, the isolation structure of the drain region 22 is a first isolation structure 226, the depth of the first isolation structure 226 is lower than the depth of the first drift region 221, and the depth of the first isolation structure 226 is greater than the depth of the first heavily doped region 222 (prepared in step S106), the depth of the second heavily doped region 223 (prepared in step S106), and the depth of the fifth heavily doped region 224 (prepared in step S106).

[0097] In one example, the first isolation structure 226 and the second isolation structure 235 are shallow trench isolation structures, which can be obtained by etching the well region 21 to form shallow trenches and filling the shallow trenches with insulating material, such as silicon dioxide.

[0098] See Figure 5 The first isolation structure 226 and the second isolation structure 235 prepared are shown.

[0099] S104. Through ion implantation, a number of drift regions with a first doping type are formed in the well region, including at least a first drift region with a first doping type located in the drain region, a second drift region with a first doping type located in the source region, and a third drift region with a second doping type.

[0100] In the first example provided in this application, step S104 includes: Step 1: Form a first drift region 221 and a second drift region 231 with a first doping type in the drain region 22 and the source region 23, respectively.

[0101] The first drift region 221 is located in the drain region 22, and the second drift region 231 is located in the source region 23.

[0102] The second step is to form a third drift region 232 with a second doping type in the source region 23.

[0103] See Figure 6 The first drift region 221, the second drift region 231, and the third drift region 232 prepared are shown.

[0104] In the second example provided in this application, a fourth drift region 225 is further prepared in the drain region 22, and step S104 includes: Step 1: Form a first drift region 221, a fourth drift region 225, and a second drift region 231 with a first doping type in the drain region 22 and the source region 23, respectively.

[0105] Among them, the first drift region 221 and the fourth drift region 225 are located in the drain region 22, and the second drift region 231 is located in the source region 23.

[0106] The second step is to form a third drift region 232 with a second doping type in the source region 23.

[0107] See Figure 7 Specifically, the second example shows the first drift zone 221, the fourth drift zone 225, the second drift zone 231, and the third drift zone 232 formed.

[0108] S105. A gate structure is fabricated on the well region between the first drift region and the second drift region.

[0109] In one example, step S105 includes: The first step is to sequentially form the original gate dielectric layer and the gate material layer on the surface of the well region.

[0110] In one example, the gate dielectric layer is a silicon dioxide layer, in which case the original gate dielectric layer can be formed by thermal oxidation.

[0111] In another example, the gate dielectric layer is a high-k dielectric layer, in which case the original gate dielectric layer can be formed by atomic layer deposition or physical vapor deposition.

[0112] In one example, the gate is doped polysilicon, and the gate material layer is formed by chemical vapor deposition. The polysilicon can be doped with phosphorus or arsenic.

[0113] In another example, if the gate is a metal gate, the gate material layer is formed by physical vapor deposition or atomic layer deposition.

[0114] The second step involves etching the original gate dielectric layer and gate material layer using dry or wet etching processes to obtain the gate dielectric layer 32 and the gate 31.

[0115] The gate dielectric layer 32 is formed by etching the original gate dielectric layer, and the gate 31 is formed by etching the gate material layer.

[0116] The third step is to deposit a layer of sidewall material.

[0117] As an example, the gate sidewall is Si3N4 or SiO2, and the sidewall material layer can be deposited by atomic layer deposition or plasma-enhanced chemical vapor deposition.

[0118] The fourth step involves using a dry etching process to etch the sidewall material layer, forming the gate sidewall 33, and obtaining the gate structure 30.

[0119] exist Figure 6 Based on the structure shown, the gate structure 30 prepared is described in detail below. Figure 8 .

[0120] exist Figure 7 Based on the structure shown, the gate structure 30 prepared is described in detail below. Figure 9 .

[0121] S106. First to fourth doped regions are formed by ion implantation process, wherein the first and third doped regions have a first doping type, and the second and fourth doped regions have a second doping type.

[0122] In the first example provided in this application, step S106 includes: The first step is to prepare a first heavily doped region 222 and a third heavily doped region 233 with the first doping type in the drain region 22 and the source region 23, respectively.

[0123] The first doped region 222 is located in the drain region 22, and the third doped region 233 is located in the source region 23.

[0124] The second step involves preparing a second heavily doped region 223 and a fourth heavily doped region 234 with the second doping type in the drain region 22 and the source region 23, respectively.

[0125] The second doped region 223 is located in the drain region 22, and the fourth doped region 234 is located in the source region 23.

[0126] exist Figure 8Based on the structure shown, the first to fourth doped regions prepared using the method in the first example provided in this application are described below. Figure 10 .

[0127] In the second example provided in this application, step S106 includes: In the first step, a first heavily doped region 222, a third heavily doped region 233, and a fifth heavily doped region 224 with the first doping type are prepared in the drain region 22 and the source region 23, respectively.

[0128] Among them, the first doped region 222 and the fifth doped region 224 are located in the drain region 22, and the third doped region 233 is located in the source region 23.

[0129] The second step involves preparing a second heavily doped region 223 and a fourth heavily doped region 234 with the second doping type in the drain region 22 and the source region 23, respectively.

[0130] The second doped region 223 is located in the drain region 22, and the fourth doped region 234 is located in the source region 23.

[0131] exist Figure 8 Based on the structure shown, the first to fifth heavily doped regions prepared using the method in the second example provided in this application are described below. Figure 11 .

[0132] exist Figure 9 Based on the structure shown, the first to fifth heavily doped regions prepared using the method in the second example provided in this application are described below. Figure 12 .

[0133] After the gate structure 30 is fabricated, an ohmic contact layer 40 is further fabricated.

[0134] The ohmic contact layer 40 can be formed by atomic layer deposition or magnetron sputtering. Subsequently, the material layer is etched by an etching process, and the remaining material layer forms the ohmic contact layer 40.

[0135] exist Figure 10 Based on the structure shown, an ohmic contact layer 40 is further fabricated. The resulting structure can be found in [reference needed]. Figure 13 .

[0136] exist Figure 11 Based on the structure shown, an ohmic contact layer 40 is further fabricated. The resulting structure can be found in [reference needed]. Figure 14 .

[0137] exist Figure 12 Based on the structure shown, an ohmic contact layer 40 is further fabricated. The resulting structure can be found in [reference needed]. Figure 2 .

[0138] It should be noted that, due to the aforementioned Figure 2 The doping type, doping element, doping concentration, and material type of each region in the electrostatic protection structure have already been described, therefore in Figure 3 The preparation method shown will not be elaborated upon here; please refer to the foregoing. Figure 2 The doping type, doping element, doping concentration, and material type are specified.

[0139] Figure 15 This is a schematic diagram illustrating the simulation results of an ESD HVMOS device provided in one embodiment of this application. See also... Figure 15 ,right Figure 1 (ESD HVMOS devices provided by related technologies) and Figure 2 The devices in the electrostatic protection structure provided in this application were simulated using TCAD, and the final result is as follows: Figure 15 The transmission line pulse TCAD simulation result is shown.

[0140] TCAD simulation is a physical model-based semiconductor process and device simulation technology used to predict the electrothermal behavior of devices during transmission line pulse (TLP) testing.

[0141] analyze Figure 15 As can be seen, when the ESD HVMOS device provided in this application and related technologies encounters an ESD event, as the drain voltage increases, the ESD HVMOS device provided in related technologies activates the parasitic NPN through avalanche breakdown. In contrast, the ESD protection structure provided in this application activates both the parasitic NPN and parasitic PNP, causing the drain voltage to begin to decrease. Subsequently, the parasitic NPN in the ESD HVMOS device provided in this application and related technologies begins to discharge the ESD current, and the device enters a sustaining state.

[0142] The related technology provides ESD HVMOS devices with drain current rising to 7.90E-03A / μm (i.e. When the drain current reaches 0.90E-03A / μm, the ESD HVMOS device fails. The ESD protection structure provided in this application fails when the drain current rises to 0.90E-03A / μm. This means that the failure current (also the secondary breakdown current) of the ESD HVMOS device provided in related technologies is... The failure current of the ESD HVMOS device provided in this application is 0.90E-03 A / μm, while the failure current of the device is 7.90E-03 A / μm. (A / μm). Compared with ESD HVMOS devices provided by related technologies, the electrostatic discharge protection structure provided in this application improves the failure current by approximately 20%, and the robustness of the electrostatic discharge protection structure is enhanced.

[0143] It should be noted that the electrostatic discharge protection structure provided in this application is based on the ESD HVMOS device with GGNMOS structure.

[0144] Finally, it should be noted that the unexpected technical effects of the technical solution provided in this application include: This application provides an electrostatic discharge (ESD) protection structure. A first drift region is formed in the source region of the ESD protection structure, along with a first heavily doped region and a second heavily doped region within the first drift region. An unexpected technical effect is that the first heavily doped region, the first drift region, the well region, the second drift region, and the third heavily doped region form one of an NPN-triggered first parasitic BJT or a PNP-triggered second parasitic BJT. A fourth heavily doped region, the third drift region, the well region, the first drift region, and the second heavily doped region form the other of the NPN-triggered first parasitic BJT or a PNP-triggered second parasitic BJT. The base of the NPN-triggered first parasitic BJT serves as the collector of the PNP-triggered second parasitic BJT, and the base of the PNP-triggered second parasitic BJT also serves as the collector of the NPN-triggered first parasitic BJT. The collector current of the NPN-triggered first parasitic BJT directly drives the base of the PNP-triggered second parasitic BJT, and the collector current of the PNP-triggered second parasitic BJT in turn drives the base of the NPN-triggered first parasitic BJT. Ultimately, a positive feedback loop is formed between the NPN-triggered first parasitic BJT and the PNP-triggered second parasitic BJT (the current amplification factor of the first parasitic BJT is...). The current amplification factor of the second parasitic BJT is The current amplification factor of the formed positive feedback loop is The current amplification factor of the electrostatic protection structure is increased through a positive feedback loop, thereby enabling the electrostatic protection structure to discharge amplified current.

[0145] A high current amplification factor can reduce the trigger voltage of the electrostatic discharge (ESD) protection structure, thereby reducing heat accumulation and the likelihood of secondary breakdown when discharging amplified ESD current. Furthermore, the positive feedback loop can distribute the current evenly throughout the entire ESD protection structure, further preventing localized overheating. Simultaneously, the positive feedback loop forces the current to be evenly distributed within the ESD protection structure, increasing its secondary breakdown voltage. This allows the electrostatic discharge protection structure to operate at higher voltages without secondary breakdown. Ultimately, it achieves the goal of discharging amplified ESD current using an ESD HVMOS device based on a GGNMOS structure.

[0146] A fifth doped region is further provided, which connects the well region and the first drift region. Since the doping concentration of the fifth doped region is higher than that of the first drift region, when the first and second doped regions receive ESD current, the second doped region with a higher doping concentration is more prone to avalanche breakdown than the first drift region (the higher the doping concentration, the lower the difficulty of avalanche breakdown), thereby conducting the positive feedback loop formed by the NPN and PNP parasitic BJTs in the electrostatic protection structure.

[0147] An additional fourth drift region is provided between the fifth doped region and the gate structure. The fourth drift region, with a higher doping concentration than the well region, can increase the flow path of charge carriers. The base region where charge carriers move has the original width of the first drift region in the lateral direction, which is extended to the width of the first drift region and the fourth drift region plus the depth of the fourth drift region. This is beneficial to further increase the secondary breakdown voltage of the electrostatic protection structure.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electrostatic protection structure, characterized in that, include: The substrate, a well region having a second doping type formed on the substrate, a gate structure formed on the surface of the well region, and a drain region and a source region in the well regions on both sides of the gate structure; The drain region includes at least a first drift region having a first doping type, a first heavily doped region having a first doping type and a second heavily doped region having a second doping type formed in the first drift region at intervals; The source region includes at least a second drift region with a first doping type and a third drift region with a second doping type, which are spaced apart, a third heavily doped region with a first doping type formed in the second drift region, and a fourth heavily doped region with a second doping type formed in the third drift region.

2. The electrostatic protection structure according to claim 1, characterized in that, One of the first doping type and the second doping type is N-type doping, and the other is P-type doping.

3. The electrostatic protection structure according to claim 1, characterized in that, The drain region also includes: A fifth doped region having a first doping type, the fifth doped region being in contact with the first drift region.

4. The electrostatic protection structure according to claim 3, characterized in that, The drain region also includes a fourth drift region having a first doping type, the fourth drift region extending below the gate structure and contacting a fifth heavily doped region.

5. The electrostatic protection structure according to claim 3, characterized in that, The first drift region of the drain region is formed with a plurality of first isolation structures; the first isolation structures are formed between the first heavily doped region and the second heavily doped region, and between the second heavily doped region and the fifth heavily doped region.

6. The electrostatic protection structure according to claim 5, characterized in that, The depth of the first isolation structure is lower than the depth of the first drift region, and the depth of the first isolation structure is greater than the depth of the first heavily doped region, the depth of the second heavily doped region, and the depth of the fifth heavily doped region, respectively.

7. A method for preparing an electrostatic protection structure, characterized in that, include: Provide substrate; A well region with a second doping type is formed on the substrate; An isolation structure is formed in the well region to isolate at least the regions containing the first and second heavily doped regions in the well region of the drain region, and to isolate the regions containing the third and fourth heavily doped regions in the well region of the source region. Through ion implantation, several drift regions with a certain spacing are formed in the well region, including at least a first drift region with a first doping type located in the drain region, a second drift region with a first doping type located in the source region, and a third drift region with a second doping type. A gate structure is fabricated on the well region between the first drift region and the second drift region; First to fourth doped regions are formed by ion implantation. The first and third doped regions have a first doping type, and the second and fourth doped regions have a second doping type.

8. The method for preparing the electrostatic protection structure according to claim 7, characterized in that, Also includes: A fifth doped region with a first doping type is formed in the well region and the first drift region by ion implantation.

9. The method for preparing the electrostatic protection structure according to claim 7, characterized in that, Also includes: A fourth drift region with a first doping type is formed in the well region by ion implantation process, and the fourth drift region extends below the gate structure. A fifth doped region with the first doping type is formed in the fourth drift region, the well region, and the first drift region by ion implantation.

10. The method for preparing the electrostatic protection structure according to claim 8 or 9, characterized in that, The isolation structure of the drain region is a first isolation structure. The depth of the first isolation structure is lower than the depth of the first drift region, and the depth of the first isolation structure is greater than the depth of the first heavily doped region, the depth of the second heavily doped region, and the depth of the fifth heavily doped region, respectively.

11. An electrostatic discharge protection circuit, characterized in that, The electrostatic protection structure is formed using any one of claims 1 to 6, or includes an electrostatic protection structure prepared using any one of claims 7 to 10.

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