Imaging element and imaging device

Abstract

An imaging element is provided with: a first substrate provided with a photoelectric conversion unit that photoelectrically converts light and generates electric charges, and a readout circuit that outputs a signal based on the electric charges generated by the photoelectric conversion unit; a second substrate laminated on the first substrate and provided with a processing unit for processing a signal output from the readout circuit; and a connection part which is provided with a bent part that is bent at a portion other than the vicinity of the first substrate and the second substrate, and which electrically connects the readout circuit and the processing part.

Description

[0001] This invention application is a divisional application of the invention application with an international filing date of September 30, 2020, international application number PCT / JP2020 / 037287, national application number 202080067137.2 which entered the Chinese national phase, and the invention title "Image Capture Element and Image Capture Device". Technical Field

[0002] This invention relates to imaging elements and imaging devices. Background Technology

[0003] Conventionally, a stacked imaging element is known, which is obtained by stacking a first semiconductor chip having a pixel array and a second semiconductor chip having an AD converter and logic circuit (e.g., Patent Document 1). In the imaging element of Patent Document 1, each pixel in the first semiconductor chip is connected to each AD converter in the second semiconductor chip via conductive vias. However, the conductive vias limit the freedom of layout for other wiring.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-182038 Summary of the Invention

[0007] According to a first aspect of the present invention, the imaging element comprises: a first substrate having a photoelectric conversion unit that performs photoelectric conversion on light to generate charge, and a readout circuit that outputs a signal based on the charge generated by the photoelectric conversion unit; a second substrate having a second substrate stacked on the first substrate having a second processing unit that processes the signal output from the second readout circuit; and a connecting portion having a second bending portion that bends in a portion other than the vicinity of the first substrate and the second substrate, electrically connecting the second readout circuit and the second processing unit.

[0008] According to a second aspect of the present invention, the imaging element comprises: a first substrate having a photoelectric conversion unit that performs photoelectric conversion on light to generate charge, and a readout circuit that outputs a signal based on the charge generated by the photoelectric conversion unit; a second substrate stacked on the first substrate having a control unit that controls the readout circuit; and a connecting portion having a bending portion that bends in a portion other than near the first substrate and the second substrate, electrically connecting the readout circuit and the control unit.

[0009] According to a third aspect of the present invention, the imaging device includes an imaging element of the first or second aspect, and a generation unit that generates image data based on a signal output from the imaging element. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view schematically illustrating the structure of the imaging device according to the first embodiment.

[0011] Figure 2 This is a top view of the imaging element of the first embodiment, viewed from the imaging surface side.

[0012] Figure 3 This is a cross-sectional view of a portion of the imaging element in the first embodiment.

[0013] Figure 4 This is a diagram showing the structure of the pixels and circuit units of the imaging element in the first embodiment.

[0014] Figure 5 This is a cross-sectional view of a portion of the imaging element in the second embodiment. Detailed Implementation

[0015] (First Embodiment)

[0016] Figure 1 This is a diagram showing an example of the structure of a camera 1, which is an example of the imaging device in the first embodiment.

[0017] Figure 1 In the X, Y, and Z directions indicated by the middle arrow, the direction pointed to by the arrow is designated as the "+" direction. The X, Y, and Z directions are mutually orthogonal. Furthermore, the X, Y, and Z directions shown in subsequent figures are also perpendicular to each other. Figure 1 The X, Y, and Z directions shown are the same.

[0018] Camera 1 includes a camera optical system (imaging optical system) 2, an imaging element 3, an imaging control unit 4, a memory 5, a display unit 6, and an operation unit 7. The camera optical system 2 includes multiple lenses, including a focus adjustment lens (focusing lens), and an aperture, which images the subject onto the imaging element 3. Furthermore, the camera optical system 2 can be attached to and detached from camera 1.

[0019] The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. The imaging element 3 receives a light beam passing through the imaging optical system 2 and captures an image of the subject formed by the imaging optical system 2. In the imaging element 3, multiple pixels having photoelectric conversion units are arranged in a two-dimensional configuration (row and column directions). The imaging element 3 performs photoelectric conversion on the received light to generate a signal and outputs the generated signal to the imaging control unit 4.

[0020] The memory 5 is a recording medium such as a memory card. Image data, control programs, etc., are recorded in the memory 5. The writing of data to and reading of data from the memory 5 is controlled by the shooting control unit 4. The display unit 6 displays information related to video recording, such as images based on the image data, shutter speed, aperture value, and menu screens. The operation unit 7 includes a release button, a power switch, switches for switching various modes, and various setting switches, and outputs signals based on various operations to the shooting control unit 4.

[0021] The shooting control unit 4 consists of processors such as CPU, FPGA, and ASIC, as well as memories such as ROM and RAM, and controls various parts of the camera 1 based on the control program. The shooting control unit 4 supplies signals to the shooting element 3 to control the operation of the shooting element 3. When performing still image shooting, performing moving image shooting, or displaying a real-time viewfinder image (preview image) of the subject on the display unit 6, the shooting control unit 4 causes the shooting element 3 to capture an image of the subject and output a signal.

[0022] The imaging control unit 4 performs various image processing operations on the signals output from the imaging element 3 to generate image data. The imaging control unit 4 is also the image data generation unit 4, generating still image data and moving image data based on the signals output from the imaging element 3. Image processing includes grayscale conversion processing, color interpolation processing, and other image processing techniques.

[0023] (First embodiment of the imaging element)

[0024] Next, refer to Figures 2 to 4 The structure of the imaging element 3 in the first embodiment will be described.

[0025] Figure 2 This is a view of the imaging element 3 according to the first embodiment, observed from the light incident side (-Z side). The imaging element has a plurality of pixels 10 arranged along the X direction (horizontal direction) and the Y direction (vertical direction). More than 1000 pixels 10 can be arranged in both the X and Y directions.

[0026] A horizontal control unit HC is provided at the -X end of the region (pixel region) where multiple pixels 10 are arranged, and a vertical control unit VC is provided at the +Y end. The horizontal control unit HC and the vertical control unit VC are also collectively referred to as the element control unit CU.

[0027] Multiple pixels 10 are arranged, for example, in a so-called Bayer array. Alternatively, a number of pixels 10 can also be pixels used for focus detection in a so-called image plane phase difference manner.

[0028] Figure 3 This is a diagram showing a cross-section (XZ plane) of the pixel area of ​​the imaging element 3. Furthermore, in Figure 3The image shows only a portion of the pixel region of the imaging element 3. The imaging element 3 is an imaging element in which a first substrate 20 and a second substrate 30 are stacked along the Z direction. The first substrate 20 and the second substrate 30 are made of semiconductors such as silicon. A plurality of pixels 10, shown in dashed boxes, are provided on the imaging element 3. Each pixel 10 has a microlens 11, a color filter 12, a photoelectric conversion unit 13, and a readout circuit 14. In addition, a single pixel 10 may have multiple photoelectric conversion units 13 or multiple readout circuits 14.

[0029] A photoelectric conversion unit 13 and a readout circuit 14 are provided on the first substrate 20. The photoelectric conversion unit 13 converts light incident on the first substrate 20 into electrical charge by photoelectric conversion. The photoelectric conversion unit 13 is, for example, composed of a photodiode. The readout circuit 14 outputs a pixel signal based on the charge generated by the photoelectric conversion unit 13 to the vertical wiring described later. The structure of the readout circuit 14 will be described later.

[0030] Microlens 11 is disposed on the light incident side (-Z direction side) of the first substrate 20. Microlens 11 concentrates the light incident on the first substrate 20 to the photoelectric conversion unit 13.

[0031] A color filter 12 is disposed between the microlens 11 and the photoelectric conversion unit 13. The color filter 12 has the beam splitting characteristic of directing light of a specific wavelength into each photoelectric conversion unit 13. The color filter 12 has the beam splitting characteristic of a Bayer array.

[0032] On the second substrate 30, there are a plurality of circuit units 15 shown in dashed boxes. The circuit unit 15 has a processing unit 16 that processes the signals output from the readout circuit 14 and a control unit 17 that controls the readout circuit 14.

[0033] On the surface of the first substrate 20 on the side of the second substrate 30 (+Z direction side), a first wiring layer 21 is provided, including a first insulating layer 22, pads 23, and wirings 24 to 29. On the other hand, on the surface of the second substrate 30 on the side of the first substrate 20 (-Z direction side), a second wiring layer 31 is provided, including a second insulating layer 32, pads 33, and wirings 34 to 39.

[0034] Wiring 24-29 and wiring 34-39 are formed on the first substrate 20 or the second substrate 30 using photolithography, similar to the wiring constituting a typical semiconductor integrated circuit. Therefore, wiring 24-29 and wiring 34-39 include wiring 26-29 and 37-39 (hereinafter also referred to as "horizontal wiring") that extend substantially parallel to the surface of the first substrate 20 or the second substrate 30 in the XY plane. Additionally, wiring 24-29 and wiring 34-39 include wiring 24, 25, and 34 (hereinafter also referred to as "vertical wiring") that extend substantially parallel to the surface of the first substrate 20 or the second substrate 30 in the Z direction.

[0035] Horizontal wirings 26-29 and 37-39 are formed on each wiring layer. For example, horizontal wirings 26-29 and 37-39 are formed by photolithography to pattern a layer of conductors such as metal formed on the surface of the first substrate 20 or the second substrate 30. Alternatively, horizontal wirings 26-29 and 37-39 may also be formed by photolithography to form trenches on an insulating layer formed on the surface of the first substrate 20 or the second substrate 30, and filling the trenches with conductors such as metal.

[0036] Additionally, the vertical wirings 24, 25, and 34 are, for example, so-called VIA plugs formed in the insulating layer formed on the first substrate 20 or the second substrate 30 along the vertical direction (Z direction). Each of the vertical wirings 24, 25, and 34 can be a single VIA plug extending along the Z direction. Alternatively, the vertical wirings 24, 25, and 34 can also be formed by stacking multiple VIA plugs extending along the Z direction at the same location in the XY plane.

[0037] Alternatively, the first insulating layer 22 and the second insulating layer 32 may also be insulating layers formed by stacking multiple insulating layers.

[0038] also, Figure 3 The wiring diagrams 24-29 and 34-39 shown are merely illustrative, and their total number is not limited to [specific number]. Figure 3 The quantities shown. The total number of horizontal and vertical cabling can be more than [amount not specified]. Figure 3 The quantity shown.

[0039] In this embodiment, the wiring layers on which horizontal wirings 26 to 29 are formed and the first insulating layer 22 on which vertical wirings 24 and 25 are formed are collectively referred to as the first wiring layer 21. Similarly, the wiring layers on which horizontal wirings 37 to 39 are formed and the second insulating layer 32 on which vertical wiring 34 is formed are collectively referred to as the second wiring layer 31.

[0040] The first insulating layer 22 contained in the first wiring layer 21 and the second insulating layer 32 contained in the second wiring layer 31 are joined (stacked) at the joint surface (stacked surface) 50.

[0041] The readout circuits 14 on the first substrate 20 are electrically connected directly or via other wiring to at least one vertical wiring 24. The lower end (the end on the +Z direction side) of the vertical wiring 24 is connected to one end of the horizontal wiring 26 in the first wiring layer 21. The other end of the horizontal wiring 26 is connected to the upper end (the end on the -Z direction side) of the vertical wiring 25. The lower end (the end on the +Z direction side) of the vertical wiring 25 is connected to a pad 23 serving as a connection electrode.

[0042] Pads 23 and 33 are connecting electrodes and are bonded at the bonding surface 50. Pad 33 is connected to the upper end (end on the -Z direction side) of the vertical wiring 34. The lower end (end on the +Z direction side) of the vertical wiring 34 is electrically connected, for example, directly or via other wiring to one of the processing units 16 provided on the second substrate 30.

[0043] Pad 23 and pad 33 constitute a joint that joins wirings 24 to 29 in the first wiring layer 21 formed on the first substrate 20 with wirings 34 to 39 in the second wiring layer 31 formed on the second substrate 30.

[0044] In this embodiment, the vertical wiring 24, horizontal wiring 26, vertical wiring 25, pad 23, pad 33 and vertical wiring 34 are collectively referred to as "first connection part".

[0045] Furthermore, the first connecting portion is a wiring that connects the pixel provided on the first substrate 20 and the circuit unit 15 provided on the second substrate 30, which are separated along the Z direction (vertical direction), and it is a wiring that extends along the Z direction. The horizontal wiring 26 in the first connecting portion extends in the XY plane (horizontal direction) and is curved relative to the other first connecting portions, so the horizontal wiring 26 is also referred to as a "curved portion".

[0046] At the same position as the Z position where the bend 26 (horizontal wiring 26) is configured, other horizontal wirings 26a besides the bend 26 may also be formed. That is, a portion of multiple horizontal wirings 26, 26a in the same wiring layer may also be used as the bend 26.

[0047] In the imaging element 3 of the first embodiment, a bend 26 is provided in the horizontal wiring 26, 26a of the second layer in the wiring layer 21 counting from the bonding surface 50 in the -Z direction. However, the bend 26 may also be provided in the horizontal wiring 29 of the first layer in the wiring layer 21 counting from the bonding surface 50 in the -Z direction. As long as the bend 26 is on the side close to the bonding surface 50, it may also be provided in the horizontal wiring of the third or higher layer in the wiring layer 21 counting from the bonding surface 50 in the -Z direction.

[0048] In the above description, a first connection portion is provided to electrically connect each readout circuit 14 provided on the first substrate 20 and the processing portion 16 provided on the second substrate 30 corresponding to each readout circuit 14.

[0049] However, the first connection portion may also be various control lines (selection control lines SEL, etc.) that are electrically connected to each readout circuit 14 provided on the first substrate 20 and the control unit 17 provided on the second substrate 30 corresponding to each readout circuit 14. As will be described later, when multiple control units 17 are provided corresponding to each readout circuit 14, multiple first connection portions may be provided in proportion to the number of control units 17.

[0050] also, Figure 3 The horizontal wiring 39 shown is, for example, wiring that supplies power supply voltage, GND voltage, or control signals to each control unit 17 provided on the second substrate 30. Figure 3 For example, an example is shown where horizontal wiring 39 is connected to each control unit 17. However, other methods are also possible. Figure 3 In addition to the horizontal wiring 39 shown, there is also horizontal wiring that supplies power supply voltage, GND voltage or control signals to each processing unit 16, or outputs output signals from the processing unit 16.

[0051] Figure 4 This diagram illustrates the structure of the photoelectric conversion unit 13 and readout circuit 14 included in the pixel 10 provided on the first substrate 20, and the processing unit 16 and control unit 17 (17a-17d) included in the circuit unit 15 provided on the second substrate 30. In the imaging element 3 of the first embodiment, the pixel 10 is also configured, for example, as a so-called 4-transistor CMOS imaging pixel.

[0052] The photoelectric conversion unit 13 performs photoelectric conversion on the light incident on the first substrate 20 to generate an electric charge. The photoelectric conversion unit 13 is, for example, composed of a photodiode.

[0053] The readout circuit 14 reads the pixel signal based on the charge generated by the photoelectric conversion unit 13. The readout circuit 14 has a transmission unit TX, an output unit TR, a floating diffusion unit (FD), and an output unit OU including an amplification unit TA and a selection unit TS.

[0054] The transmission section TX transmits the charge obtained by photoelectric conversion by the photoelectric conversion section 13 to the floating diffusion section FD. That is, the transmission section TX is a transmission transistor TX that forms a charge transmission path between the photoelectric conversion section 13 and the floating diffusion section FD.

[0055] The floating diffuser FD transmits the charge obtained by photoelectric conversion by the photoelectric conversion unit 13 through the transmission unit. The floating diffuser FD stores the charge obtained by photoelectric conversion by the photoelectric conversion unit 13 through the transmission unit TX. That is, the floating diffuser FD is a storage unit for storing charge.

[0056] The discharge section TR resets the potential of the floating diffuser section to a reference potential by discharging the charge stored in the floating diffuser section FD. The discharge section TR is a reset transistor TR that resets the potential of the floating diffuser section to a reference potential.

[0057] The output unit OU outputs the pixel signal generated by the charge of the floating diffuser FD to the signal line SL. The signal line SL is one of the first connection units (23-26, 33-34). The signal line SL is the wiring used to output the pixel signal to the processing unit 16. The output unit OU has an amplification unit TA and a selection unit TS. The amplification unit TA is an amplification transistor TA that generates the pixel signal through the charge of the floating diffuser FD. The selection unit TS is a selection transistor TS that controls the connection between the pixel 10 and the signal line SL. The selection unit TS outputs the pixel signal generated by the amplification unit TA to the signal line SL.

[0058] The analog signal (pixel signal) output from the output section OU of the readout circuit 14 provided on the first substrate 20 is transmitted via the signal line SL to the processing section 16 of the circuit unit 15 provided on the second substrate 30. The processing section 16 includes, for example, an analog-to-digital converter (ADC) and a current source CS. The ADC converts the analog signal (pixel signal) output from the selection transistor TS of the readout circuit 14 into a digital signal.

[0059] The aforementioned vertical wirings 24, 25, and 34 include at least a portion of the signal line SL for transmitting pixel signals from pixel 10 to the readout unit ADC.

[0060] The circuit unit 15 has multiple control units 17 (17a to 15d). In this embodiment, the selection control unit 17a, voltage control unit 17b, reset control unit 17c, and transmission control unit 17d are also collectively referred to as "control units 17" or individually.

[0061] The selection control unit 17a is electrically connected to the gate of the selection transistor TS of the readout circuit 14 via the selection control line SEL, which is one of the first connection units (23-26, 33-34). That is, the selection control unit 17a controls the selection transistor TS.

[0062] The voltage control unit 17b controls the supply of power voltage to the readout circuit 14 or the photoelectric conversion unit 13 via the power supply voltage line VDD, which is one of the first connection units (23-26, 33-34).

[0063] The reset control unit 17c is electrically connected to the gate of the reset transistor TR of the readout circuit 14 via the reset control line RST, which is one of the first connection units (23-26, 33-34). That is, the reset control unit 17c controls the reset transistor TR.

[0064] Transmission control unit 17d via as Figure 3 The transmission control line TRN of one of the first connection sections (23-26, 33-34) shown is electrically connected to the gate of the transmission transistor TX of the readout circuit 14. That is, the transmission control section 17d controls the transmission transistor TX.

[0065] Hereinafter, the selection control line SEL, reset control line RST, and transmission control line TRN will be collectively referred to as "control lines". Control lines are wiring used to send control signals for controlling each transistor from the control unit 17 to the readout circuit 14. Furthermore, the control signals for controlling each transistor are transmitted from the control unit 17 to at least a portion of the horizontal wirings 27 and 28 via the first connection portions (23-26, 33-34).

[0066] The imaging element 3 of the first embodiment includes a plurality of processing units 16 corresponding to the number of pixels 10. Therefore, the imaging element 3 can read out pixel signals for each pixel 10. That is, the imaging element 3 can read out and process pixel signals generated by a plurality of pixels 10 at high speed. The imaging element 3 of the first embodiment includes a plurality of control units 17 corresponding to the number of pixels 10. Therefore, the imaging element 3 can control pixels 10 for each pixel. That is, the imaging element 3 can set different exposure times for each pixel, generate and output pixel signals.

[0067] Depending on the structure of the imaging element 3, there may be a situation where the arrangement period of the pixels 10 having the photoelectric conversion unit 13 and the readout circuit 14 in the X or Y direction is different from the arrangement period of the circuit unit 15 having the processing unit 16 and the control unit 17 in the X or Y direction. In other words, there may be a situation where the interval (pixel pitch) between two adjacent pixels 10 in the X or Y direction is different from the interval (circuit pitch) between two adjacent circuit units 15 in the X or Y direction. This is because it is necessary to arrange circuits other than the circuit units 15 on the second substrate 30. On the other hand, it is because it is necessary to arrange the pixels 10 at regular intervals on the first substrate 20. It is also because it is necessary to arrange control circuits 15e of the control circuit units 15 on the second substrate 30, for example, at every predetermined number of circuit units 15 arranged along the X or Y direction. The circuits arranged on the second substrate 30 are not limited to the control circuit 15e, and may also be other circuits such as shift registers or storage units.

[0068] Therefore, the width (circuit spacing) of the circuit unit 15 in the X or Y direction needs to be smaller than the width (pixel spacing) of the pixel 10 in the X or Y direction. Consequently, there are cases where the configuration period of the pixel 10 in the X or Y direction differs from the configuration period of the circuit unit 15 in the X or Y direction.

[0069] In this case, some of the multiple circuit units 15 cannot be positioned directly below (in the +Z direction) the corresponding pixel 10, but are instead positioned offset from the pixel 10 in the X or Y direction. Specifically, some of the multiple circuit units 15 cannot be positioned directly below (in the +Z direction) the readout circuit 14 of the corresponding pixel 10, but are instead positioned offset from the readout circuit 14 in the X or Y direction. Furthermore, this problem of not being able to position the corresponding circuit unit 15 directly below the pixel 10 arises because the imaging element 3 of the first embodiment has a structure that positions the circuit unit 15 in each pixel 10.

[0070] The imaging element 3 of the first embodiment adjusts the positional offset in the X or Y direction caused by the difference between the arrangement period of the pixel 10 and the arrangement period of the circuit unit 15 by means of the bending portion 26 in the first connecting portion (23-26, 33-34). Thus, the imaging element 3 of the first embodiment solves the problem that the circuit unit 15 cannot be arranged directly below the pixel 10 due to the difference between the arrangement period of the pixel 10 and the arrangement period of the circuit unit 15.

[0071] Specifically, such as Figure 3As shown, the imaging element 3 of the first embodiment has pads 33 connected to vertical wiring 34 extending upward (in the -Z direction) from each circuit unit 15. The pads 33 are positioned approximately directly above the circuit unit 15. Therefore, the arrangement period of the joints (pads 23, 33) in the X or Y direction is set to coincide with the arrangement period of the circuit unit 15. Furthermore, the imaging element 3 of the first embodiment has a curved portion 26 on the first wiring layer 21 for adjusting the position of the pixel 10 and the joint 23 in the X or Y direction to align them. Thus, even if the arrangement period of the pixel 10 in the X or Y direction differs from the arrangement period of the circuit unit 15, the pixel 10 (readout circuit 14) and the circuit unit 15 can be electrically connected via the first connection portion (23-26, 33-34). In other words, even when the pixel pitch and the circuit pitch are different, the first connecting part (23-26, 33-34) can be used to electrically connect the pixel 10 (readout circuit 14) and the circuit unit 15.

[0072] The direction of the curved portion 26 (the direction of bending) can be, for example, the same X or Y direction as the arrangement direction of the pixels 10.

[0073] Alternatively, the curved portion 26 may also include a first portion extending in one direction within the XY plane, and a first portion extending in a direction within the XY plane that intersects that direction. That is, the curved portion 26 may also include within itself a portion that is curved within the XY plane.

[0074] Additionally, near the first substrate 20, there are, for example, multiple horizontal wirings 27-29 for controlling the readout circuit 14. Also, near the second substrate 30, there are, for example, multiple horizontal wirings 37-39 for controlling the processing unit 16 or the control unit 17.

[0075] Therefore, if the bend 26 is formed near the first substrate 20, it will hinder the layout of the horizontal wirings 27 and 28 used to control the readout circuit 14. Specifically, the degree of freedom of the wiring layout of the horizontal wirings 27 and 28 is restricted by the bend 26. In addition, the integration density of the wirings of the horizontal wirings 27 and 28 is reduced due to the bend 26.

[0076] If the bend 26 is formed near the second substrate 30, it will hinder the layout of the horizontal wirings 38 and 39 used for the control processing unit 16 or the control unit 17. Specifically, the freedom of the wiring layout of the horizontal wirings 38 and 39 is restricted. In addition, the integration density of the wirings of the horizontal wirings 38 and 39 is reduced due to the bend 26.

[0077] The horizontal wirings 26-29 included in the first wiring layer 21 include wiring for controlling the pixel 10, a GND line supplying GND voltage to the pixel 10, and a power supply line supplying power supply voltage to the pixel 10. The wiring for controlling the pixel 10 is, for example, wiring that controls the transmission transistor TX, reset transistor TR, and selection transistor TS included in the pixel 10 respectively. The wiring for controlling the transmission transistor TX or the reset transistor TR can be set for each pixel 10 or for each pixel block containing a predetermined number of pixels 10.

[0078] The wiring of these control transistors (hereinafter also referred to as "first control lines") is provided in the first wiring layer 21 at a position close to the first substrate 20 (first substrate side, -Z direction side) in order to control the transmission transistor TX, the reset transistor TR, and the selection transistor TS. That is, the horizontal wirings 27 and 28 disposed near the first substrate 20 contain a plurality of first control lines.

[0079] GND lines and power lines are commonly provided in multiple pixels 10 or multiple pixel blocks. Therefore, the GND lines and power lines are disposed in the first wiring layer 21 at a position farther from the first substrate 20 than the first control lines (second substrate side, +Z direction side). In other words, the GND lines and power lines are provided close to the bonding surface 50. Furthermore, as described above, multiple first control lines are disposed near the pixels 10, i.e., near the first substrate 20. Therefore, the GND lines and power lines are disposed in the first wiring layer 21 at a position farther from the first substrate 20 than the first control lines. That is, the horizontal wiring 29 disposed in the first wiring layer 21 at a position farther from the first substrate 20 includes multiple GND lines and power lines.

[0080] The second wiring layer 31 includes horizontal wiring 37-39, which includes wiring for controlling the processing unit 16 or the control unit 17, GND lines supplying GND voltage to the processing unit 16 or the control unit 17, and power lines supplying power supply voltage to the processing unit 16 or the control unit 17. The wiring for controlling the processing unit 16 or the control unit 17 is, for example, wiring for controlling various switching elements such as transistors included in the processing unit 16 or the control unit 17.

[0081] The wiring of these control transistors (hereinafter also referred to as "second control lines") is provided in the second wiring layer 31 at a position close to the second substrate 30 (second substrate side, +Z direction side) for controlling various switching elements. That is, the horizontal wirings 38, 39 disposed near the second substrate 30 contain a plurality of second control lines.

[0082] GND lines and power lines are commonly provided in multiple processing units 16 or multiple control units 17. Therefore, the GND lines and power lines are provided in the second wiring layer 31 at a position farther from the second substrate 30 than the second control lines (first substrate side, -Z direction side). In other words, the GND lines and power lines are provided close to the bonding surface 50. Furthermore, as described above, multiple second control lines are arranged near the processing units 16 or control units 17, that is, near the second substrate 30. Therefore, the GND lines and power lines are provided in the second wiring layer 31 at a position farther from the second substrate 30 than the second control lines. That is, the horizontal wiring 37 of the second wiring layer 31 arranged at a position far from the second substrate 30 includes multiple GND lines and power lines.

[0083] The control line transmits high-frequency control signals to control the various transistors and switching elements. Therefore, the control line may become a noise source for the signal line SL, which includes the bend 26. Conversely, the bend 26 of the signal line SL may also become a noise source for the control line.

[0084] To avoid this situation, the imaging element 3 of the first embodiment has a bent portion 26 provided in the portion other than near the first substrate 20 and near the second substrate 30. In other words, the imaging element 3 of the first embodiment has a bent portion 26 provided near the mating surface 50. According to this structure, the imaging element 3 of the first embodiment does not restrict the degree of freedom of the wiring layout of other wirings 27, 28, 37, 38 by the first connecting portion (23-26, 33-34) including the bent portion 26, and can route the horizontal wirings 27, 28, 37, 38 in an optimal layout. As a result, the reduction of the integration density of wirings 27, 28, 37, 38 can be prevented.

[0085] Furthermore, the imaging element 3 of the first embodiment has a curved portion 26 at a position far from the first control line (horizontal wirings 27, 28) disposed near the first substrate 20 and the second control line (horizontal wirings 38, 39) disposed near the second substrate 30. In other words, the imaging element 3 of the first embodiment has a curved portion 26 near the joint. According to this structure, the imaging element 3 of the first embodiment can suppress the noise influence from these control lines on the curved portion 26. Conversely, it can also suppress the noise influence from these curved portions 26 on the control lines.

[0086] Furthermore, the imaging element 3 of the first embodiment has a bend 26 located close to the GND line and the power line. Since the GND line and the power line are supplied with a essentially fixed voltage, the noise impact on the signal line SL, which includes the bend 26, is minimal. Additionally, the GND line and the power line are less susceptible to noise from the bend 26 in the signal line SL. According to this structure, the imaging element 3 of the first embodiment can minimize the noise impact on the bend 26. Moreover, the noise impact from the bend 26 can also be minimized.

[0087] In addition, the bending portion 26 may not be provided near the first substrate 20 and the second substrate 30, but may be provided at a position away from the first substrate 20 and the second substrate 30 to a certain extent.

[0088] For example, the imaging element 3 may be provided with a curved portion 26 at a distance of more than 1 / 4 from the first substrate 20 and the second substrate 30. Therefore, the degree of freedom in the wiring layout of the horizontal wirings 27, 28 for controlling the readout circuit 14, and the horizontal wirings 37, 38 for controlling the processing unit 16 or the control unit 17, etc., is not restricted. Thus, the horizontal wirings 27, 28, 37, 38 can be wired in an optimal layout.

[0089] Furthermore, the imaging element 3 may also have at least two wiring layers (horizontal wiring 27, 28 or horizontal wiring 37, 38) provided between the first substrate 20 and the bent portion 26, and between the second substrate 30 and the bent portion 26. Therefore, the degree of freedom in the wiring layout of the horizontal wiring 27, 28 for controlling the readout circuit 14, and the horizontal wiring 37, 38 for controlling the processing unit 16 or the control unit 17, etc., is not limited. Thus, the horizontal wiring 27, 28, 37, 38 can be wired in an optimal layout.

[0090] Furthermore, the first connecting portion (23-26, 33-34) of the first embodiment has a first wiring portion (24-26) provided on the first wiring layer 21, a second wiring portion (34) provided on the second wiring layer 31, and pads 23 and 33 serving as bonding portions to join the first wiring portion and the second wiring portion. A bending portion 26 is provided near the pads 23 and 33 serving as bonding portions. In other words, the bending portion 26 is provided on the side closer to the pads 23 and 33 serving as bonding portions than on the first substrate 20 and the second substrate 30.

[0091] (Second embodiment of the imaging element)

[0092] Next, refer to Figure 5The structure of the imaging element 3a in the second embodiment will be described below. Most of the structure of the imaging element 3a in the second embodiment is the same as that of the imaging element 3 in the first embodiment described above. Hereinafter, the same reference numerals will be used to refer to the common structures, and descriptions will be omitted where appropriate.

[0093] Figure 5 This is a cross-sectional (XZ plane) view of the pixel 10 portion of the imaging element 3a in the second embodiment, which is consistent with the above. Figure 3 Same diagram. The imaging element 3a of the second embodiment differs from the imaging element 3 of the first embodiment in that it uses vertical wiring 24, pad 23, pad 33, vertical wiring 35, horizontal wiring 36 and vertical wiring 34 to make electrical connections between the readout circuit 14 and the processing unit 16 or the control unit 17.

[0094] In this embodiment, the vertical wiring 24, pad 23, pad 33, vertical wiring 35, horizontal wiring 36, and vertical wiring 34 described above are collectively referred to as the "second connection portion". Additionally, the first connection portion and the second connection portion described above are collectively referred to as "connection portion" or simply as such.

[0095] In the imaging element 3a of the second embodiment, the second connecting portion (23-24, 33-36) has a first portion (24) provided on the first wiring layer 21, a second portion (34-36) provided on the second wiring layer 31, and pads 23 and 33 serving as connecting portions to join the first portion and the second portion.

[0096] Furthermore, in the imaging element 3a of the second embodiment, the horizontal wiring 36, which is a curved portion, is arranged in the second part of the second substrate 30, which is closer to the second substrate 30 than the pads 23, 33, which are joint portions.

[0097] Specifically, such as Figure 5 As shown, the imaging element 3a of the second embodiment has pads 23 connected to vertical wiring 24 extending downward (+Z direction) from the readout circuits 14 of each pixel 10. The pads 23 are positioned approximately directly below the pixels 10 (readout circuits 14). Therefore, the arrangement period of the joints (pads 23, 33) in the X or Y direction is set to match the arrangement period of the readout circuits 14 of the pixels 10. Furthermore, the imaging element 3a of the second embodiment has a curved portion 26 in the second wiring layer 31 for adjusting the position of the joints 33 and the circuit units 15 in the X or Y direction to align them. Thus, even when the arrangement period of the pixels 10 in the X or Y direction differs from the arrangement period of the circuit units 15, the readout circuits 14 and the circuit units 15 can be electrically connected using the first connecting portions (23-26, 33-34).

[0098] Therefore, even when the arrangement period of pixel 10 differs from the arrangement period of circuit unit 15 in the X or Y direction, pixel 10 (readout circuit 14) can be electrically connected to circuit unit 15 using the first connecting portion (23-26, 33-34). In other words, even when the pixel pitch and circuit pitch differ, pixel 10 (readout circuit 14) can be electrically connected to circuit unit 15 using the first connecting portion (23-26, 33-34).

[0099] The arrangement period of pixels 10 in the X or Y direction is approximately uniform within the imaging surface (XY plane on the -Z side) of the imaging element 3a. Therefore, the imaging element 3a of the second embodiment can arrange the bonding portions (pads 23, 33) at approximately equal intervals in the X or Y direction. In other words, the bonding portions (pads 23, 33) are arranged approximately uniformly in the bonding surface 50. Therefore, the electrical effects of the bonding portions on the readout circuit 14 and the circuit unit 15 can be approximately uniformly distributed in the direction within the imaging surface (XY direction), and noise unevenness within the imaging surface can be suppressed.

[0100] Furthermore, in the second embodiment, the structure and function of the horizontal wirings 27, 28, 37-39, etc., are the same as in the first embodiment described above. In the second embodiment, the structure and function of the bent portion (horizontal wiring 36) are the same as in the first embodiment. In the second embodiment, the positional relationship between the first substrate 20 and the second substrate 30 in the Z direction and the bent portion (horizontal wiring 36) is the same as in the first embodiment. In the second embodiment, the positional relationship between the horizontal wirings 27, 28, 37-39 in the Z direction and the bent portion (horizontal wiring 36) is the same as in the first embodiment. In the second embodiment, the positional relationship between the pads 23, 33, which serve as bonding portions in the Z direction and the bent portion is the same as in the first embodiment. Additionally, other horizontal wirings 36a besides the bent portion may be formed at the same position as the Z position where the bent portion is located, which is also the same as in the first embodiment.

[0101] In addition, in the second embodiment, the upper end of the vertical wiring 24 is electrically connected directly or via other wiring to the readout circuit 14 provided on the first substrate 20. Furthermore, the lower end of the vertical wiring 34 is electrically connected directly or via other wiring to the processing unit 16 or the control unit 17 provided on the second substrate 30.

[0102] In the imaging element 3 of the first embodiment or the imaging element 3a of the second embodiment described above, the bent portions 26 and 36 are provided in the first or second portion near the pads 23 and 33, which serve as joint portions. As a result, the impact on the layout of wiring used to control the readout circuit 14, the processing unit 16, or the control unit 17 can be reduced.

[0103] Alternatively, the bent portions 26 and 36 can be located at a distance of less than 1 / 4 of the distance between the first substrate 20 and the second substrate 30 from the pads 23 and 33, which serve as the joint portions. This reduces the impact on the layout of wiring used to control the readout circuit 14, the processing unit 16, or the control unit 17.

[0104] Furthermore, pads 23 and 33 refer to electrodes in the XY plane with an area larger than that of the vertical wirings 24, 25, and 34. However, if the first substrate 20 and the second substrate 30 can be stacked with high positional accuracy, it is not necessary to make the bonding area large. In this case, electrodes with an area in the XY plane that is the same as that of the vertical wirings 24, 25, and 34 can also be used as bonding areas.

[0105] In the imaging elements 3 and 3a of the above embodiments, the photoelectric conversion unit 13 and the readout circuit 14 disposed on the first substrate 20 may be provided with connection parts (23-26, 33-36) that are connected to the processing unit 16 or the control unit 17 of the second substrate 30.

[0106] However, the number of connecting parts (23-26, 33-36) can also be less than the number of readout circuits 14. For example, in Figure 2 In the imaging surface of the imaging element 3 shown, multiple pixels 10 can also be arranged relative to each of the blocks BC surrounded by dashed lines (in... Figure 2 For example, a connecting portion (23-26, 33-36) can be configured in a 4×4 grid. In other words, a connecting portion (23-26, 33-36) is shared by multiple pixels 10 configured within block BC. Alternatively, a circuit unit 15 can be configured relative to the multiple pixels 10 configured within block BC. In other words, a circuit unit 15 is shared by multiple pixels 10 configured within block BC.

[0107] In this case, the signals (pixel signals) generated by the multiple photoelectric conversion units 13 of the multiple pixels 10 within a block BC are sequentially output to the processing unit 16 of the second substrate 30 via a connection unit (23-26, 33-36). In addition, control signals from the control units 17a-17d of the second substrate 30 are also sequentially or simultaneously output to the multiple readout circuits 14 included in a block BC of the first substrate 20 via a connection unit (23-26, 33-36).

[0108] Furthermore, in imaging elements 3 and 3a, which have a structure that provides a connection portion and a circuit unit 15 (processing unit 16, control unit 17) for each block BC having multiple pixels 10, the problem arises that it is impossible to arrange the corresponding circuit unit 15 directly below each block BC. However, this problem is solved by providing a bending portion 26 in the wiring layer 21 in the imaging element 3 of the first embodiment, as described above, and by providing a bending portion 36 in the wiring layer 31 in the imaging element 3a of the second embodiment.

[0109] Furthermore, in the imaging element 3a of the second embodiment, similarly to the imaging element 3 of the first embodiment described above, a plurality of control lines for transmitting high-frequency control signals for controlling various transistors or switching elements are arranged near the substrate 20 and near the substrate 30. Therefore, in the imaging element 3a of the second embodiment, by providing the bending portion 36 in areas other than near the first substrate 20 and near the second substrate 30, the noise impact from the control lines on the bending portion 36 and the noise impact from the bending portion 36 on the control lines are reduced.

[0110] In the imaging element 3a of the second embodiment, a bend 36 is provided in the horizontal wiring 36, 36a of the second layer in the wiring layer 31, counting from the bonding surface 50 in the +Z direction. However, the bend 36 may also be provided in the horizontal wiring 40 of the first layer in the wiring layer 31, counting from the bonding surface 50 in the +Z direction. As long as the bend 36 is on the side close to the bonding surface 50, it may also be provided in the horizontal wiring of the third or higher layer in the wiring layer 31, counting from the bonding surface 50 in the +Z direction.

[0111] The imaging element 3 in the first embodiment and the imaging element 3a in the second embodiment are both so-called stacked sensors formed by stacking a first substrate 20 and a second substrate 30. Therefore, multiple control lines for controlling transistors and the like formed on each substrate are formed near the first substrate 20 and near the second substrate 30. To suppress noise from these control lines and ensure flexibility in arrangement, the placement of bent portions 26 and 36 in areas other than near the first substrate 20 and the second substrate 30 is a configuration unique to stacked sensors. In other words, the placement of bent portions 26 and 36 near the joints (pads 23 and 33) of the first substrate 20 and the second substrate 30 is a configuration unique to stacked sensors.

[0112] Furthermore, in the imaging elements 3 and 3a of the above embodiments, the lengths of the connecting portions (23-26, 33-36) connected to each readout circuit 14 vary depending on the length of their included bends 26 and 36. Therefore, the impedance of each connecting portion (23-26, 33-36) varies depending on the length of the bends 26 and 36. If the impedance of each connecting portion (23-26, 33-36) changes, there is a concern that stripe noise accompanying the impedance change may occur in the image obtained from the imaging elements 3 and 3a.

[0113] To avoid strip noise, the thickness (line width) of the wiring in each connection (23-26, 33-36) can be varied based on the length of the bends 26 and 36, so that the impedance of each connection is approximately equal. Alternatively, a low-resistance conductor can be used in the wiring layer used as the bends 26 and 36 to minimize the impedance variation in each connection (23-26, 33-36).

[0114] Alternatively, the connecting portions with shorter bends 26 and 36 compared to other connecting portions may have components that generate resistance so that the impedances of each connecting portion are approximately equal. Alternatively, to avoid strip noise, the characteristics of the current source CS connected to each connecting portion (23-26, 33-36) may vary according to the length of the bends 26 and 36 included in each connecting portion. The varying characteristics of the current source CS may be, for example, the amount of current supplied.

[0115] (1) From a first point of view, the imaging elements 3 and 3a of the above embodiments include: a first substrate 20, which is provided with a photoelectric conversion unit 13 that performs photoelectric conversion to generate charge and a readout circuit 14 that outputs a signal based on the charge generated by the photoelectric conversion unit 13; a second substrate 30, which is stacked on the first substrate 20 and is provided with a processing unit 16 that processes the signal output from the readout circuit 14; and connecting portions (23-26, 33-36), which are provided with bending portions 26 and 36 that bend in the vicinity of the first substrate 20 and the second substrate 30, and electrically connect the readout circuit 14 and the processing unit 16.

[0116] Because of this structure, even if the photoelectric conversion unit 13 or the readout circuit 14 and the corresponding processing unit 16 have different configuration cycles in the X or Y directions, they can be electrically connected by the connecting parts (23-26, 33-36).

[0117] Furthermore, since the bends 26 and 36 are arranged near the first substrate 20 and the second substrate 30 to avoid the concentration of various wirings, the bends 26 and 36 can be arranged without adversely affecting the layout of other wirings. As a result, the increase in impedance in various wirings can be prevented.

[0118] (2) From the second viewpoint, the imaging elements 3 and 3a of the above embodiments include: a first substrate 20, which is provided with a photoelectric conversion unit 13 that performs photoelectric conversion on light to generate charge, and a readout circuit 14 that outputs a signal based on the charge generated by the photoelectric conversion unit 13; a second substrate 30, which is stacked on the first substrate 20 and is provided with a control unit 17 that controls the readout circuit 14; and a connecting part (23-26, 33-36), which has a bending part 26 and 36 that bends in the vicinity of the first substrate 20 and the second substrate 30, and electrically connects the readout circuit 14 to the control unit 17.

[0119] Because of this structure, even if the photoelectric conversion unit 13 or the readout circuit 14 and the corresponding control unit 17 have different configuration cycles in the X or Y directions, they can be electrically connected by the connection parts (23-26, 33-36).

[0120] Furthermore, since the bending portions 26 and 36 are arranged to avoid the vicinity of the first substrate 20 and the second substrate 30 where various wirings are concentrated, the bending portions 26 and 36 can be arranged without adversely affecting the layout of other wirings. As a result, it is possible to prevent the increase of impedance in various wirings.

[0121] (3) Furthermore, the connecting parts (23-26, 33-36) are designed such that no bending parts 26 and 36 are provided near the first substrate 20 and near the second substrate 30, thereby further increasing the freedom of layout of various wirings and further suppressing the increase of impedance of various wirings.

[0122] (4) Furthermore, by providing a structure in which the bent portions 26 and 36 are located at a distance of more than 1 / 4 from the first substrate 20 and the second substrate 30, the freedom of layout of various wirings can be further increased, and the increase of impedance of various wirings can be further suppressed.

[0123] (5) Furthermore, by providing a structure having multiple wiring layers 26-28, 36-38 provided between the first substrate 20 and the second substrate 30, and bending portions 26, 36 provided in the wiring layers, the manufacturing cost of the wiring layers and bending portions can be reduced.

[0124] (6) Furthermore, by providing at least two wiring layers 27, 28, 37, and 38 between the first substrate 20 and the bent portions 26 and 36, and between the second substrate 30 and the bent portions 26 and 36, wiring layers 27, 28, 37, and 38 can be used to wire circuits formed on the first substrate 20 and the second substrate 30.

[0125] The foregoing has described various embodiments and modifications, but the present invention is not limited to these. Furthermore, each embodiment and modification can be applied individually or in combination. Other methods conceived within the scope of the technical concept of the present invention are also included within the scope of the present invention.

[0126] The disclosure of the following priority-based application is incorporated herein by reference.

[0127] Japan Special Application No. 2019-180783 (submitted on September 30, 2019)

[0128] Explanation of reference numerals in the attached figures

[0129] 1: Imaging device, 2: Imaging lens, 3: Imaging element, 4: Imaging control unit (generation unit), 5: Lens moving unit, BC: Pixel block, HC: Horizontal control unit, VC: Vertical control unit, CU: Element control unit, 10: Pixel, 20: First substrate, 30: Second substrate, 11: Microlens, 12: Color filter, 13: Photoelectric conversion unit, 14: Readout circuit, 15: Circuit unit, 16: Processing unit, 17: Control unit, 17a: Selection control unit, 17b: Voltage control unit, 17c: Reset control unit, 17d: Transmission control unit, 21: Layer 1, 22: First insulating layer, 24-29: Wiring, 31: Second layer, 32: Second insulating layer, 34-40: Wiring, 23, 33: Pads, 50: Bonding surface, TX: Transmission section (transmission transistor), TR: Discharge section (reset transistor), TA: Amplification section (amplification transistor), TS: Selection section (selection transistor), FD: Floating diffuser (FD), TRN: Transmission control line, RST: Reset control line, VDD: Power supply voltage line, SEL: Selection control line, SL: Output signal line, ADC: Readout section, CS: Current source.

Claims

1. A shooting element, characterized in that, have: A first substrate has a first pixel and a second pixel. The first pixel includes a first photoelectric conversion unit that converts light into charge and outputs a first signal based on the charge converted by the first photoelectric conversion unit. The second pixel includes a second photoelectric conversion unit that converts light into charge and outputs a second signal based on the charge converted by the second photoelectric conversion unit. The second substrate is a substrate stacked with the first substrate, and has a first processing unit for signal processing of the first signal output from the first pixel, and a second processing unit for signal processing of the second signal output from the second pixel. The first connection portion is a connection portion that electrically connects the first pixel and the first processing portion. It has a first conductive portion arranged so as to face each other in a first direction in which the first substrate and the second substrate are stacked, and a second conductive portion extending along a second direction intersecting the first direction. The first signal is output to the first connection portion. as well as The second connection portion, which is a connection portion that electrically connects the second pixel and the second processing unit, has a third conductive portion arranged opposite to each other in the first direction, and a fourth conductive portion extending along the second direction and having a length different from that of the second conductive portion in the second direction, and outputs the second signal to the second connection portion.

2. The imaging element according to claim 1, characterized in that, The first conductive portion has a first pad disposed on the first substrate side and a second pad disposed on the second substrate side. The third conductive portion has a third pad disposed on the side of the first substrate and a fourth pad disposed on the side of the second substrate.

3. The imaging element according to claim 2, characterized in that, The second conductive portion is disposed on the side of the first substrate in the first direction compared to the first pad. The fourth conductive portion is disposed on the side of the first substrate in the first direction compared to the third pad.

4. The imaging element according to claim 3, characterized in that, The second conductive portion is disposed in the first direction between the first pixel and the first pad.

5. The imaging element according to claim 4, characterized in that, The second conductive portion is disposed in the first direction between the first photoelectric conversion portion and the first pad.

6. The imaging element according to claim 4, characterized in that, The fourth conductive portion is disposed in the first direction between the second pixel and the third pad.

7. The imaging element according to claim 6, characterized in that, The fourth conductive portion is disposed in the first direction between the second photoelectric conversion portion and the third pad.

8. The imaging element according to claim 3, characterized in that, The second conductive portion is disposed in the first direction at a position closer to the first pad than to the first substrate. The fourth conductive portion is disposed in the first direction at a position closer to the third pad than to the first substrate.

9. The imaging element according to claim 8, characterized in that, The second conductive portion is disposed in the first direction between the first pixel and the first pad.

10. The imaging element according to claim 9, characterized in that, The second conductive portion is disposed in the first direction between the first photoelectric conversion portion and the first pad.

11. The imaging element according to claim 9, characterized in that, The fourth conductive portion is disposed in the first direction between the second pixel and the third pad.

12. The imaging element according to claim 11, characterized in that, The fourth conductive portion is disposed in the first direction between the second photoelectric conversion portion and the third pad.

13. The imaging element according to claim 2, characterized in that, The second conductive portion is disposed on the side of the second substrate in the first direction compared to the second pad. The fourth conductive portion is disposed on the side of the second substrate in the first direction compared to the fourth pad.

14. The imaging element according to claim 13, characterized in that, The second conductive portion is disposed in the first direction between the second pad and the first processing portion.

15. The imaging element according to claim 14, characterized in that, The fourth conductive part is disposed in the first direction between the fourth pad and the second processing part.

16. The imaging element according to claim 13, characterized in that, The second conductive portion is disposed in the first direction at a position closer to the second pad than to the second substrate. The fourth conductive portion is disposed in the first direction at a position closer to the fourth pad than the second substrate.

17. The imaging element according to claim 16, characterized in that, The second conductive portion is disposed in the first direction between the second pad and the first processing portion.

18. The imaging element according to claim 17, characterized in that, The fourth conductive part is disposed in the first direction between the fourth pad and the second processing part.

19. A shooting device, characterized in that, It has the imaging element as described in any one of claims 1 to 18.

20. The imaging element according to any one of claims 1 to 18, characterized in that, The first substrate has a pixel portion in which the first photoelectric conversion unit and the second photoelectric conversion unit are disposed. The first photoelectric conversion unit and the second photoelectric conversion unit are arranged in the pixel unit along the second direction.

21. A shooting device, characterized in that, It has the imaging element as described in claim 20.

22. The imaging element according to claim 20, characterized in that, The second photoelectric conversion unit is disposed on the inner side of the pixel unit compared to the first photoelectric conversion unit. The length of the second conductive portion in the second direction is shorter than the length of the first conductive portion in the second direction.

23. A shooting device, characterized in that, It has the imaging element as described in claim 22.

24. The imaging element according to claim 22, characterized in that, The first photoelectric conversion unit and the second photoelectric conversion unit are arranged adjacent to each other in the second direction.

25. A shooting device, characterized in that, It has the imaging element as described in claim 24.

26. The imaging element according to any one of claims 1 to 18, characterized in that, The first substrate has a pixel portion in which the first photoelectric conversion unit and the second photoelectric conversion unit are disposed. The first photoelectric conversion unit and the second photoelectric conversion unit are arranged in the pixel unit along a third direction that intersects the second direction.

27. A shooting device, characterized in that, It has the imaging element as described in claim 26.

28. The imaging element according to claim 26, characterized in that, The second photoelectric conversion unit is disposed on the inner side of the pixel unit compared to the first photoelectric conversion unit. The length of the second conductive portion in the second direction is shorter than the length of the first conductive portion in the second direction.

29. A shooting device, characterized in that, It has the imaging element as described in claim 28.

30. The imaging element according to claim 28, characterized in that, The first photoelectric conversion unit and the second photoelectric conversion unit are arranged adjacent to each other in the third direction.

31. A shooting device, characterized in that, It has the imaging element as described in claim 30.

32. The imaging element according to any one of claims 1 to 18, characterized in that, The first processing unit includes a first conversion unit that converts the first signal into a digital signal. The second processing unit has a second conversion unit that converts the second signal into a digital signal.

33. A shooting device, characterized in that, It has the imaging element as described in claim 32.

34. The imaging element according to any one of claims 1 to 18, characterized in that, The second substrate has a first control unit that outputs a control signal for controlling the first pixel, and a second control unit that outputs a control signal for controlling the second pixel.

35. A shooting device, characterized in that, It has the imaging element as described in claim 34.

36. The imaging element according to claim 34, characterized in that, have: The third connection portion, which electrically connects the first pixel and the first control portion, outputs a first control signal for controlling the first pixel to the third connection portion; and The fourth connection part is a connection part that electrically connects the second pixel and the second control part, and outputs a second control signal for controlling the second pixel to the fourth connection part.

37. A shooting device, characterized in that, It has the imaging element as described in claim 36.

38. The imaging element according to claim 36, characterized in that, The first pixel has a first transmission unit that transmits the charge converted by the first photoelectric conversion unit. The second pixel has a second transmission unit that transmits the charge converted by the second photoelectric conversion unit. The first control unit outputs a first transmission control signal as the first control signal for controlling the first transmission unit. The second control unit outputs a second transmission control signal as the second control signal for controlling the second transmission unit.

39. A shooting device, characterized in that, It has the imaging element as described in claim 38.

40. The imaging element according to claim 38, characterized in that, The first pixel has a first discharge section that discharges the charge converted by the first photoelectric conversion section. The second pixel has a second discharge section that discharges the charge converted by the second photoelectric conversion section. The first control unit outputs a first discharge control signal as the first control signal to control the first discharge unit. The second control unit outputs a second discharge control signal as the second control signal for controlling the second discharge unit.

41. A shooting device, characterized in that, It has the imaging element as described in claim 40.

42. The imaging element according to claim 36, characterized in that, The first pixel has a first discharge section that discharges the charge converted by the first photoelectric conversion section. The second pixel has a second discharge section that discharges the charge converted by the second photoelectric conversion section. The first control unit outputs a first discharge control signal as the first control signal to control the first discharge unit. The second control unit outputs a second discharge control signal as the second control signal for controlling the second discharge unit.

43. A shooting device, characterized in that, It has the imaging element as described in claim 42.

Images