Simulation device, method, program, material selection method, manufacturing method, and photosensitive insulating material

Abstract

A setting unit (32) sets the adhesion state of the interface between each material for a simulation model (40) indicating a semiconductor package including a plurality of materials, and a simulation unit (34) simulates the presence or absence of peeling between the materials when a force or heat is applied to the semiconductor package, using the simulation model (40) in which the adhesion state of the interface between each material is set.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a simulation device, a simulation method, a simulation program, a material selection method, a manufacturing method of a semiconductor package, and a photosensitive insulating material. BACKGROUND

[0002] In the past, in order to evaluate characteristics of a semiconductor package, simulation using a simulation model has been performed. For example, a technique of providing simulation data that takes into account a joining member used when a semiconductor package is mounted on a mounting substrate to a customer has been proposed (see Patent Literature 1). In this technique, the simulation data is simulation data for input to a simulation device to generate a simulation model. The simulation data has a configuration that has a first data element for modeling heat conduction of a semiconductor package and a second data element for modeling heat conduction of a joining member when the semiconductor package is mounted on a mounting substrate. Further, the simulation data, when input to a simulation device, becomes integral with a simulation program possessed by the simulation device, and a thermal analysis model is generated based on the first data element and the second data element. Then, a simulation result using the thermal analysis model is output.

[0003] Further, for example, a simulation analysis device capable of performing simulation analysis of a crack generated in a joined body has been proposed (see Patent Literature 2). The device performs configuration analysis of a semiconductor package in which a first member that is joined to an upper surface of a joined body and a second member that is joined to a bottom surface of the joined body are stacked in a direction perpendicular to a joining surface and are enclosed in a sealing agent. Further, the device reads out physical property value information, size information, and shape information of the first member, the second member, and the joined body, and calculates a maximum principal stress acting on the joined body when heated to a given temperature. Further, the device calculates a displacement amount in the direction perpendicular to the joining surface generated in the joined body when heated to the given temperature, and evaluates that a crack is not generated in the joined body when the maximum principal stress is equal to or less than a first threshold value and the displacement amount is equal to or less than a second threshold value.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT LITERATURE

[0006] Patent Literature 1: Japanese Patent Application Publication No. 2022-033586

[0007] Patent Literature 2: Japanese Patent Application Publication No. 2014-174927 SUMMARY

[0008] PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] A protective member including an insulating film, a seal, or the like for protecting a periphery is included in a semiconductor package. Due to a mismatch in a thermal expansion rate of such a protective member and a material to be protected, or the like, the protective member is sometimes peeled from the material to be protected. Since the peeling of such a protective member can become a cause of failure of the semiconductor package, it is necessary to reduce stress of the protective member and suppress peeling of the protective member.

[0010] The present disclosure is made in view of the above, and aims to accurately simulate peeling between materials constituting a semiconductor package.

[0011] Means for solving the problem

[0012] The simulation device according to the first aspect includes a setting section that sets an adhesion state of an interface between each of materials of a semiconductor package including a plurality of materials, and a simulation section that simulates presence or absence of peeling between the materials when a force or heat is applied to the semiconductor package using a simulation model of the semiconductor package in which the adhesion state of the interface between each of the materials is set by the setting section.

[0013] The simulation method according to the second aspect is a simulation method performed by a simulation device including a setting section that sets an adhesion state of an interface between each of materials of a semiconductor package including a plurality of materials, and a simulation section that simulates presence or absence of peeling between the materials when a force or heat is applied to the semiconductor package using a simulation model of the semiconductor package in which the adhesion state of the interface between each of the materials is set by the setting section.

[0014] The simulation program according to the third aspect is a program that causes a computer to function as a setting section that sets an adhesion state of an interface between each of materials of a semiconductor package including a plurality of materials, and a simulation section that simulates presence or absence of peeling between the materials when a force or heat is applied to the semiconductor package using a simulation model of the semiconductor package in which the adhesion state of the interface between each of the materials is set by the setting section.

[0015] In the material selection method according to the fourth aspect, a material used in a semiconductor package is selected based on a simulation result of the simulation device described above.

[0016] In the semiconductor package manufacturing method according to the fifth aspect, a semiconductor package is manufactured using a material selected by the material selection method described above.

[0017] In the photosensitive insulating material according to the sixth aspect, the stress is 0 to 100 MPa, which is a simulation result of the simulation device described above.

[0018] Effects of the Invention

[0019] According to the simulation device, the method, and the program according to the present disclosure, peeling between materials constituting a semiconductor package can be simulated with high accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a block diagram showing a hardware structure of the simulation device according to the present embodiment.

[0021] Figure 2 is a functional block diagram of the simulation device according to the present embodiment.

[0022] Figure 3 is a side view and a partial enlarged view showing a schematic structure of a semiconductor package.

[0023] Figure 4 is a schematic view for visualizing a simulation model.

[0024] Figure 5 is a view for explaining setting of a bonding state in a simulation model.

[0025] Figure 6 is a view for explaining setting of a bonding state in a simulation model.

[0026] Figure 7 is a view for explaining setting of a bonding state in a simulation model.

[0027] Figure 8 is a view showing an example of a simulation result.

[0028] Figure 9 is a flowchart showing a flow of a simulation process.

[0029] Figure 10 is a functional block diagram of the simulation device according to the present embodiment. DETAILED DESCRIPTION

[0030] Hereinafter, an example of the present embodiment will be described with reference to the drawings.

[0031] <Simulation device>

[0032] Figure 1 is a block diagram showing a hardware structure of the simulation device 10 according to the present embodiment. As shown in the drawing, the simulation device 10 has a CPU (Central Processing Unit) 12, a memory 14, a storage device 16, an input device 18, an output device 20, a storage medium reading device 22, and a communication I / F (Interface) 24. Each structure is communicably connected to each other via a bus 26. Figure 1

[0033] ​An analog program for performing simulation processing described later is held in the storage device 16. The CPU 12 is a central arithmetic processing unit that executes various programs or controls the structures. That is, the CPU 12 reads a program from the storage device 16 and executes the program using the memory 14 as a work area. The CPU 12 performs the control of the above-described structures and various arithmetic processing according to the program stored in the storage device 16.

[0034] The memory 14 is constituted by a RAM (Random Access Memory) and temporarily stores programs and data as a work area. The storage device 16 is constituted by a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), or the like, and holds various programs including an operating system and various data.

[0035] The input device 18 is, for example, a keyboard, a mouse, or the like, which is a device for performing various inputs. The output device 20 is, for example, a display, a printer, or the like, which is a device for outputting various information. As the output device 20, a touch panel display is employed, which functions as the input device 18.

[0036] The storage medium reading device 22 performs reading of data stored in various storage media such as a CD (Compact Disc)-ROM, a DVD (Digital Versatile Disc)-ROM, a floppy disk, a USB (Universal Serial Bus) memory, or the like, and writing of data to the storage media. The communication I / F 24 is an interface for communication with other devices, and uses a standard such as Ethernet (registered trademark), FDDI, or Wi-Fi (registered trademark).

[0037] Next, the functional structure of the simulation device 10 according to the present embodiment will be described.

[0038] Figure 2 is a block diagram showing an example of the functional structure of the simulation device 10. As shown in Figure 2 The simulation device 10 includes a setting section 32 and a simulation section 34 as the functional structure. Further, a simulation model 40 is stored in a given storage area of the simulation device 10. Each functional structure is realized by the CPU 12 reading out the simulation program stored in the storage device 16 and expanding and executing it in the memory 14.

[0039] The simulation model 40 represents a semiconductor package including a plurality of materials, and is a model for simulating phenomena in which stresses and the like of each material are generated in the semiconductor package.

[0040] Here, we will describe the general structure of a semiconductor package. Figure 3 The left figure is a side view showing the schematic structure of the semiconductor package 50. Figure 3 The right figure is a partial enlarged view of the semiconductor package 50. The semiconductor package 50, which encapsulates a semiconductor chip 52 formed of silicon (Si) or the like, on which circuits are formed, includes a package substrate 54, solder beads 56, etc., and is mounted on a mounting substrate 90. Figure 3 The right figure shows a portion of the semiconductor package 50 in an enlarged view. Figure 3 The dashed section in the left figure includes an interlayer insulating layer 58, a printed circuit board 60 containing a circuit pattern based on copper foil (Cu), solder 62, and a semiconductor chip 52. Furthermore, this section includes: a protective member 64 covering the junction between the printed circuit board 60 and the solder 62; and a sealant (UF) 66 injected between the protective member 64 and the semiconductor chip 52.

[0041] Interlayer insulation layer 58 is, for example, a backing layer (BU) film. Protective component 64 is, for example, solder resist (SR), photosensitive insulating material, backing layer film, etc. Sealing component 66 is, for example, a liquid sealant, a non-conductive adhesive film, etc.

[0042] In this embodiment, the protective element 64 is described as a solder resist. Hereinafter, the protective element 64 will also be referred to as solder resist 64.

[0043] Solder resist 64 is in film or liquid form, and is applied or coated onto the surface of the substrate or other object being protected to safeguard it. For example... Figure 3 As shown in the right figure, when solder resist 64 is applied to protect the joint between the printed circuit board 60 and the solder 62, if only the layer of solder resist 64 is removed, the portion corresponding to the solder 62 becomes an opening. Near this opening ( Figure 3 As shown by the thick line in the right-hand diagram, there is a problem with solder resist 64 peeling. This is caused by factors such as the mismatch in the thermal expansion rates of the bonded materials, which increases the stress on the materials, resulting in peeling of the material within the semiconductor package 50. Therefore, it is necessary to analyze and simulate the stress on the materials using the structure of the semiconductor package to determine the range of stress that will prevent peeling.

[0044] Simulation model 40 is a model representing the opening of the solder resist 64 in the structure of the semiconductor package during the analysis of the aforementioned stresses. Figure 4 A schematic diagram of the simulation model 40 is shown. Figure 4 In the simulation model 40, the colors of each part are distinguished (with different shades) according to the materials that make up the semiconductor package 50.

[0045] like Figure 4As shown, the simulation model 40 is represented by a three-dimensional mesh structure. In Figure 4 , a horizontal plane is divided radially, and a vertical plane is divided in a grid shape, to constitute each mesh. Further, in the example of Figure 4 , the size of each mesh is made different depending on the portion of the semiconductor package 50. For example, the mesh of a portion, particularly a portion in which detailed analysis is desired, such as an interface between materials, is set to be fine, and the mesh of a portion other than this is set to be large.

[0046] In addition, the structure of the mesh of the simulation model 40 is not limited to the example of Figure 4 . For example, it can be set to a mesh of a cubic shape, or a mesh in which the shape is made different depending on the portion of the semiconductor package 50. Further, the size of each mesh can be made uniform.

[0047] Generally, in a simulation model of a semiconductor package 50, a model in which all interfaces of each material are bonded is made. The simulation model 40 of the present embodiment can set the bonding state of the interface between each material.

[0048] Specifically, as shown in Figure 5 , the corners of each mesh are set as nodes. In this case, by setting so that the nodes are shared by adjacent meshes to each other, "bonding" is expressed, and by setting so that the nodes are not shared, "non-bonding" is expressed. Figure 5 The example of Fig. 13 is a diagram showing a portion of a mesh of a portion in which a material A and a material B are adjacent. In Figure 5 , the mesh showing the material A is set as mesh 42A, and the mesh showing the material B is set as mesh 42B. Further, the black circles are nodes 44 of each mesh. In the case where the node of the portion at which the mesh 42A and the mesh 42B are adjacent (the node shown by the dotted line portion in Figure 5 ) is shared by the mesh 42A and the mesh 42B, it is shown that the material A and the material B are bonded. On the other hand, in the case where the node of the corresponding portion is not shared by the mesh 42A and the mesh 42B, but is maintained as each node, it is shown that the material A and the material B are not bonded (a state in which they are in contact but not bonded).

[0049] In addition, in Figure 5 , the mesh is shown in two dimensions in order to make the explanation simple. The same is true in the following Figure 7 .

[0050] In addition, the bonding state of the interface between materials in the simulation model 40 is not limited to the case where it is either bonded or not bonded, but the degree of bonding can be set. For example, non-bonding can be set to 0, bonding can be set to 1, and the degree of bonding can be set to a value of 0 to 1. As a method of setting the degree of bonding in the simulation model 40, for example, as shown in Figure 6As shown, in the adjacent areas of mesh 42A of material A and mesh 42B of material B, shared nodes 44 and non-shared nodes 44 are set at consecutive nodes 44. In the adjacent areas of mesh 42A and mesh 42B, by changing the ratio of shared nodes 44 to non-shared nodes 44, the degree of adhesion between material A and material B can be set.

[0051] The setting unit 32 receives setting values ​​including the shape, properties, and bonding indication of each material constituting the semiconductor package 50. The shape includes, for example, information such as the longitudinal and transverse dimensions and thickness of each material. The properties include, for example, thermal expansion coefficient, Young's modulus, and information required for stress simulation. For instance, if solder resist is used as a protective element 64, the properties included in the setting values ​​for the protective element 64 become information about the properties of the solder resist. The bonding indication indicates whether a particular part between which materials is bonded or unbonded. Furthermore, the bonding indication can be an indication of the degree of adhesion at the interface between the materials.

[0052] The setting unit 32 sets the received setting values ​​to the simulation model 40. Specifically, the setting unit 32 adjusts the spacing of the mesh structure in the simulation model 40 so that the shape of the part corresponding to each material becomes the shape of each material contained in the setting values. In addition, the setting unit 32 keeps the physical property information of each mesh corresponding to each material in the simulation model 40 as parameters.

[0053] Furthermore, the setting unit 32 sets the bonding state of the interfaces between each material in the simulation model 40. For example, the setting values ​​include bonding instructions indicating that the interface between the solder resist 64 and the solder 62 is set to unbonded, and the interfaces between other materials are set to bonded. In this case, such as Figure 7 As shown, the setting unit 32 is configured not to share the interface between the solder resist 64 and the solder 62 in the mesh constituting the simulation model 40. Figure 7 The setting section 32 is configured to set the nodes of adjacent meshes in the thicker section of the model. Furthermore, the setting section 32 is configured to share the nodes of adjacent meshes that correspond to the interface between other materials. Thus, a simulation model 40 representing the unbonded state of the interface between the solder resist 64 and the solder 62 is constructed.

[0054] Furthermore, the setting unit 32 can also set whether the materials are connected to each other or pushed against each other when a force of mutual pushing is applied at the interface between unbonded materials.

[0055] The simulation unit 34 uses a simulation model 40, whose shape, physical properties, and bonding state of the interfaces between materials are set by the setting unit 32, to simulate the presence or absence of material delamination when force or heat is applied to the semiconductor package 50. For example, the simulation unit 34 calculates the magnitude and direction of the stress on each material generated by the mutual pushing force between materials associated with thermal expansion, etc., for each mesh.

[0056] Furthermore, the simulation unit 34 simulates the presence or absence of delamination at the interface between materials based on the calculated magnitude and direction of stress in each material. For example, the simulation unit 34 calculates the magnitude and direction of stress at a given location (e.g., an opening) at the interface between materials based on the magnitude and direction of stress in each mesh, and simulates whether delamination occurs. Since existing technology can be used for the simulation of stress and delamination, detailed explanations are omitted.

[0057] The simulation unit 34 outputs simulation results representing stress and a failure model of the peeling area. Figure 8 The simulation results of stress and an example of a fault model are shown. Figure 8 The phrase "in the case of no bonding" refers to the method used in this embodiment (hereinafter referred to as "this method"). Figure 7 An example of setting the interface between solder resist 64 and solder 62 as not bonded, as shown. Figure 8 The "bonded case" is used as a comparative example with this method, where all interfaces between materials are set to bond, and other settings are set in the same way as in this method. Figure 8 In the simulation, the stress results for a portion of the opening containing solder resist 64 are represented by the difference in color (concentration) to indicate the magnitude of the stress calculated per mesh, and the direction of the stress generated at a given location in the opening of solder resist 64 is shown.

[0058] Through simulation using this method, it can be inferred that... Figure 8 The thick line portion of A represents a failure model where peeling occurs at the interface between the printed circuit board 60 and the solder resist 64, specifically on the upper surface of the printed circuit board 60. On the other hand, in a comparative method, it is presumed that... Figure 8 The thick line portion of B indicates a fault model where the printed circuit board 60 forms the interface between the printed circuit board 60 and the solder resist 64, and where peeling occurs on the side portion of the printed circuit board. The fault model determined experimentally for an actual semiconductor package 50 is consistent with the fault model of this method. Therefore, compared with the comparison method, this method can obtain simulation results that are closer to reality.

[0059] Next, the function of the simulation device 10 involved in this embodiment will be explained.

[0060] Figure 9is a flowchart showing a flow of simulation processing executed by the CPU 12 of the simulation device 10. The CPU 12 reads out a simulation program from the storage device 16, expands and executes it in the memory 14, whereby the CPU 12 functions as each functional structure of the simulation device 10, and executes the simulation processing shown in Figure 9

[0061] In step S10, the setting section 32 accepts setting values including the shape, the physical properties, and the adhesion instruction of each material constituting the semiconductor package 50. Next, in step S12, the setting section 32 adjusts the interval of the mesh structure or the like so that the shape of the portion corresponding to each material in the simulation model 40 becomes the shape of each material contained in the setting values. Further, the setting section 32 causes the simulation model 40 to hold information on the physical properties of each mesh corresponding to each material as a parameter. Next, in step S14, the setting section 32 sets the adhesion state (adhesion or non-adhesion) of the interface between each material in the simulation model 40 based on the adhesion instruction.

[0062] Next, in step S16, using the simulation model 40 in which the shape, the physical properties, and the adhesion state of the interface between each material are set, the magnitude and the direction of stress at the time when a force or heat is applied to the semiconductor package 50 are simulated for each mesh. Next, in step S18, the simulation section 34 simulates a failure model indicating the presence or absence of peeling of the interface between each material, that is, a peeling site, based on the magnitude and the direction of stress of each material simulated.

[0063] Next, in step S20, the simulation section 34 outputs the simulation results of the stress and the failure model, and ends the simulation processing.

[0064] As described above, the simulation device according to the present embodiment sets the adhesion state of the interface between each material in a simulation model indicating a semiconductor package containing a plurality of materials. Then, the simulation device simulates the presence or absence of peeling between materials at the time when a force or heat is applied to the semiconductor package using the simulation model in which the adhesion state of the interface between each material is set. Thereby, peeling between materials constituting the semiconductor package can be simulated with high accuracy.

[0065] ​Moreover, in the above-described embodiments, the simulation processing in which the CPU reads in and executes software (programs) can be executed by various processors other than the CPU. As the processor in this case, a PLD (Programmable Logic Device) such as an FPGA (Field-Programmable Gate Array) in which the circuit structure can be changed after manufacture, a processor having a circuit structure designed specifically for executing a specific processing such as an ASIC (Application Specific Integrated Circuit), and the like are exemplified. Moreover, the simulation processing can be executed by one of these various processors, or can be executed by a combination of two or more processors of the same kind or different kinds (for example, a plurality of FPGAs, and a combination of a CPU and an FPGA). Moreover, the hardware configuration of these various processors is more specifically an electrical circuit in which circuit elements such as semiconductor elements are combined.

[0066] Moreover, in the above-described embodiments, the manner in which the simulation program is stored (installed) in advance in the storage device is described, but the present application is not limited thereto. The program can be provided in a form in which it is stored in a storage medium such as a CD-ROM, a DVD-ROM, a USB memory, and the like. Moreover, the program can also be configured to be downloaded from an external device via a network.

[0067] <Modification of the Simulation Device>

[0068] In Figure 10 A functional block diagram of a simulation device 10A according to a modification is shown. As Figure 10 indicated, the simulation device 10A includes a presumption unit 36 in addition to the functional units of the simulation device 10 of the above-described embodiment.

[0069] The setting unit 32 receives setting values for a plurality of types in which the adhesion states differ, respectively, and sets the setting values for each type to the simulation model 40. That is, the simulation model 40 of a plurality of types in which the adhesion states differ, respectively, is constructed.

[0070] The presumption unit 36 receives information of a failure model determined in advance through experiments with respect to the actual semiconductor package 50. Then, the presumption unit 36 compares the failure model simulated using the simulation model 40 of each type with the actual failure model. The presumption unit 36 presumes the adhesion state represented by the type of the simulation result most consistent with the actual failure model as the adhesion state of the interface between each material of the actual semiconductor package, and outputs the presumption result.

[0071] According to the simulation device according to the present modification, the adhesion state of the interface between each material can be presumed with respect to an actual semiconductor package of which the adhesion state of the interface between each material is unknown.

[0072] <Material selection method>

[0073] The material selection method according to the present embodiment is a method of selecting a material used in a semiconductor package based on the simulation result of the simulation device 10 described above. Specifically, in the present material selection method, a material whose value of stress is included in a range in which deviation does not occur among materials is selected based on the simulation result of the simulation device 10.

[0074] For example, in the case of selecting a protective member 64 used in the semiconductor package 50, in a case where it is confirmed by simulation that peeling does not occur when the stress is 0 to 100 MPa, an insulating material in the range of stress 0 to 100 MPa is selected. As such an insulating material, for example, there are solder resist, photosensitive insulating material, build-up film, and the like.

[0075] <Manufacturing method of semiconductor package>

[0076] The manufacturing method of a semiconductor package according to the present embodiment is a manufacturing method of a semiconductor package 50 using a material selected by the material selection method described above. Specifically, a semiconductor package is manufactured by sequentially laminating materials selected based on the simulation result of the simulation device 10 in accordance with the set value set at the time of simulation. A more specific manufacturing method of a semiconductor package can be applied to the existing technology, and thus detailed description is omitted.

[0077] <Additional item>

[0078] The following additional item is disclosed.

[0079] (Additional item 1)

[0080] A simulation device includes:

[0081] a setting section that sets an adhesion state of an interface between each material of a simulation model representing a semiconductor package including a plurality of materials; and

[0082] a simulation section that simulates presence or absence of peeling between the materials when a force or heat is applied to the semiconductor package using the simulation model whose adhesion state of the interface between each material is set by the setting section.

[0083] (Additional item 2)

[0084] The simulation device according to additional item 1, the simulation model includes solder and an insulating material that protects the solder, as the materials.

[0085] (Additional item 3)

[0086] The simulation device according to additional item 2, the insulating material is a photosensitive insulating material.

[0087] (Paragraph 4)

[0088] The simulation device according to Paragraph 3, wherein the photosensitive insulating material is solder resist.

[0089] (Paragraph 5)

[0090] The simulation device according to any one of Paragraphs 1 to 4, wherein the setting section sets a degree of adhesion of the interface between the respective materials as the adhesion state.

[0091] (Paragraph 6)

[0092] The simulation device according to Paragraph 5, wherein the setting section sets adhesion or non-adhesion of the interface between the materials as the degree of adhesion.

[0093] (Paragraph 7)

[0094] The simulation device according to any one of Paragraphs 1 to 6, wherein the simulation section calculates a magnitude and a direction of stress of the materials, and simulates presence or absence of peeling of the interface between the materials based on the calculated magnitude and direction of stress.

[0095] (Paragraph 8)

[0096] The simulation device according to any one of Paragraphs 1 to 7, wherein the setting section sets a plurality of patterns as the adhesion state of the interface between the respective materials,

[0097] The simulation device comprises:

[0098] a presumption section that compares information indicating at which position between which materials of an actual semiconductor package peeling occurs and simulation results respectively regarding the plurality of patterns, and presumes, as the adhesion state of the interface between the respective materials of the actual semiconductor package, the adhesion state corresponding to the pattern in which the state of peeling most agrees with the actual semiconductor package.

[0099] (Paragraph 9)

[0100] A simulation method is a simulation method performed by a simulation device including a setting section and a simulation section,

[0101] the setting section sets an adhesion state of an interface between respective materials of a simulation model of a semiconductor package including a plurality of materials,

[0102] the simulation section simulates presence or absence of peeling between the materials when a force or heat acts on the semiconductor package using the simulation model in which the setting section sets the adhesion state of the interface between the respective materials.

[0103] (Paragraph 10)

[0104] A simulation program makes a computer function as a structure as follows:

[0105] a setting section that sets a state of adhesion of an interface between materials of a simulation model that represents a semiconductor package including a plurality of materials; and

[0106] a simulation section that simulates presence or absence of peeling between the materials when a force or heat is applied to the semiconductor package using the simulation model in which the state of adhesion of the interface between the materials is set by the setting section.

[0107] (Paragraph 11)

[0108] A material selection method that selects a material used in a semiconductor package based on a simulation result of the simulation device described in any one of Paragraphs 1 to 8.

[0109] (Paragraph 12)

[0110] A material selection method that selects a material in which a value of a stress is included in a range in which peeling does not occur between materials based on a simulation result of the simulation device described in Paragraph 7.

[0111] (Paragraph 13)

[0112] A manufacturing method that manufactures a semiconductor package using a material selected by the material selection method described in Paragraph 11 or Paragraph 12.

[0113] (Paragraph 14)

[0114] A photosensitive insulating material in which a magnitude of the stress is 0 to 100 MPa based on a simulation result of the simulation device described in Paragraph 7.

[0115] Explanation of Symbols

[0116] 10, 10A Simulation device

[0117] 12 CPU

[0118] 14 Memory

[0119] 16 Storage device

[0120] 18 Input device

[0121] 20 Output device

[0122] 22 Storage medium reading device

[0123] 24 Communication I / F

[0124] 26 Bus

[0125] 32 setting section

[0126] 34 simulation section

[0127] 36 presumption section

[0128] 40 simulation model

[0129] 42A, 42B mesh

[0130] 44 node

[0131] 50 semiconductor package

[0132] 52 semiconductor chip

[0133] 54 package substrate

[0134] 56 solder bead

[0135] 58 interlayer insulating layer

[0136] 60 printed board

[0137] 64 protection (solder resist)

[0138] 66 sealant

[0139] 90 mounting substrate

Claims

1. A simulation device, comprising: The setting unit sets the bonding state of the interfaces between the materials in a simulation model representing a semiconductor package containing multiple materials; and The simulation unit uses the simulation model, in which the bonding state of the interfaces between the materials is set by the setting unit, to simulate the presence or absence of delamination between the materials when force or heat is applied to the semiconductor package.

2. The simulation device according to claim 1, wherein, The simulation model includes solder and an insulating material that protects the solder, as the material.

3. The simulation device according to claim 2, wherein, The insulating material is a photosensitive insulating material.

4. The simulation device according to claim 3, wherein, The photosensitive insulating material is a solder resist.

5. The simulation apparatus according to any one of claims 1 to 4, wherein, The setting unit sets the degree of adhesion between the interfaces of the various materials, which is the adhesion state.

6. The simulation apparatus according to claim 5, wherein, The setting unit determines whether the interface between the materials is bonded or not, as the degree of bonding.

7. The simulation apparatus according to any one of claims 1 to 4, wherein, The simulation unit calculates the magnitude and direction of the stress in the material, and simulates the presence or absence of delamination at the interface between the materials based on the calculated magnitude and direction of the stress.

8. The simulation apparatus according to any one of claims 1 to 4, wherein, The setting unit sets multiple types to represent the bonding states of the interfaces between the various materials. The simulation device includes: The estimation unit compares information indicating at which location between which materials in the actual semiconductor package delamination occurs with simulation results for each of the multiple types, and estimates the bonding state corresponding to the type that best matches the actual semiconductor package as the bonding state of the interfaces between the materials of the actual semiconductor package.

9. A simulation method, executed by a simulation device comprising a setting unit and a simulation unit, The setting unit sets the bonding state of the interfaces between the materials in a simulation model representing a semiconductor package containing multiple materials. The simulation unit uses the simulation model, in which the bonding state of the interfaces between the materials is set by the setting unit, to simulate whether or not the materials peel off when force or heat is applied to the semiconductor package.

10. A simulation program that enables a computer to function as a structure: The setting unit sets the bonding state of the interfaces between the materials in a simulation model representing a semiconductor package containing multiple materials; and The simulation unit uses the simulation model, in which the bonding state of the interfaces between the materials is set by the setting unit, to simulate whether or not the materials peel off when force or heat is applied to the semiconductor package.

11. A method for selecting materials, The materials used in the semiconductor package are selected based on the simulation results from the simulation apparatus described in claim 1.

12. A method for selecting materials, Based on the simulation results from the simulation apparatus of claim 7, the stress value is selected to be within a range that does not deviate between materials.

13. A manufacturing method, The semiconductor package is manufactured using the material selected by the material selection method of claim 11 or claim 12.

14. A photosensitive insulating material, The simulation result of the simulation device according to claim 7 is that the magnitude of the stress is 0 to 100 MPa.

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