SPAD array control circuit and control method

Abstract

The embodiment of the invention provides an SPAD array control circuit and a control method. The SPAD array control circuit comprises a pixel unit array and a bias voltage adjusting circuit located outside the pixel unit array. The bias voltage adjusting circuit comprises a reference voltage source and a plurality of driving enhancement circuits, the reference voltage source provides a plurality of reference voltages, and the input end of each driving enhancement circuit receives one reference voltage and outputs the reference voltage to the pixel unit array; the pixel unit array comprises a plurality of pixel units, the first voltage end of each pixel unit selectively receives the reference voltage output by one driving enhancement circuit, and the second voltage end of each pixel unit is connected with the fixed voltage. According to the embodiment of the invention, the occupied area of the driving enhancement circuit can be reduced, and the integration level of the SPAD array is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a SPAD array control circuit and a control method. BACKGROUND

[0002] Single photon avalanche diodes (SPADs) may have different breakdown voltages due to temperature and process effects, so that even if the same operating voltage is provided to each SPAD in a SPAD array, the over-bias of each SPAD may not be the same.

[0003] Different over-biases of SPADs result in different detection characteristics (including time characteristics, pulse characteristics, detection probability / sensitivity characteristics, etc.) of the SPADs. Inappropriate over-biases also cause the SPADs to have working reliability problems or even not work, for example, too high over-biases cause the quenching circuit to bear too high a voltage, which exceeds the working voltage of the circuit and causes the circuit to burn out; too low over-biases cause the SPADs to be unable to sense photons to generate pulses. SUMMARY

[0004] Embodiments of the present application provide a SPAD array control circuit and a control method.

[0005] In a first aspect, embodiments of the present application provide a SPAD array control circuit, comprising a pixel unit array and a bias voltage adjustment circuit located outside the pixel unit array; The bias voltage adjustment circuit comprises a reference voltage source and a plurality of drive enhancement circuits, the reference voltage source provides a plurality of reference voltages, and the input end of each drive enhancement circuit receives one reference voltage and outputs to the pixel unit array; The pixel unit array comprises a plurality of pixel units, the first voltage end of the pixel unit selectively receives the reference voltage output by one of the drive enhancement circuits, and the second voltage end of the pixel unit is connected to a fixed voltage.

[0006] In a second aspect, embodiments of the present application provide a control method applied to a SPAD array control circuit, the SPAD array control circuit comprising a pixel unit array and a bias voltage adjustment circuit located outside the pixel unit array, the bias voltage adjustment circuit comprising a reference voltage source and a plurality of drive enhancement circuits, the input end of each drive enhancement circuit receiving one reference voltage and outputting to the pixel unit array; the pixel unit array comprising a plurality of pixel units, the first voltage end of the pixel unit selectively receiving the reference voltage output by one of the drive enhancement circuits, and the second voltage end of the pixel unit being connected to a fixed voltage; The control method comprises: A fixed voltage is provided to the second voltage terminal of each pixel unit in the pixel unit array, and the ideal reference voltage required for the first voltage terminal of each pixel unit is obtained; Based on the ideal reference voltage required by each pixel unit, determine the reference voltages that the reference voltage source needs to output; Based on the reference voltages that the reference voltage source needs to output, the number of pixel units that each reference voltage needs to drive, and the specifications of each driving enhancement circuit, the correspondence between each reference voltage, the driving enhancement circuit, and the pixel unit is determined, and the circuit connection is turned on.

[0007] This application provides a SPAD array control circuit and control method. The control circuit integrates the drive enhancement circuit within the bias voltage regulation circuit, eliminating the need for the drive enhancement circuit in each pixel unit. This significantly reduces the trace resource requirements of the drive enhancement circuit in the SPAD array. Furthermore, in this application, the drive enhancement circuit directly enhances the reference voltage output from the reference voltage source in the bias voltage regulation circuit before providing it to the SPAD array. This allows a single reference voltage, after its load-carrying capacity is increased by the drive enhancement circuit, to be used to drive multiple SPADs. The number of drive enhancement circuits can be consistent with the number of reference voltages and is much smaller than the number of pixel units in the SPAD array, thus greatly reducing the trace resource requirements of the bias voltage regulation circuit. In summary, this application not only significantly reduces the trace resource requirements in the SPAD array but also effectively overcomes the problem of a substantial increase in trace resource requirements caused by integrating the drive enhancement circuit into the bias voltage regulation circuit. Therefore, it can be widely applied in large-area SPAD arrays. Attached Figure Description

[0008] Figure 1 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 1 ; Figure 2 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 2 ; Figure 3 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 3 ; Figure 4 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 4 ; Figure 5 A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 5 ; Figure 6A schematic diagram of the structure of a SPAD array control circuit provided in this application embodiment. Figure 6 ; Figure 7 A flowchart illustrating a control method provided in an embodiment of this application; Figure 8 This is a schematic diagram of the composition structure of a pixel unit provided in an embodiment of this application. Detailed Implementation

[0009] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant application and not for limiting the application. Furthermore, it should be noted that, for ease of description, only the parts related to the relevant application are shown in the accompanying drawings.

[0010] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0011] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0012] It should be noted that the terms "first, second, and third" used in the embodiments of this application are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0013] SPAD is a semiconductor detector that operates based on Geiger mode, achieving high-sensitivity detection at the single-photon level through the avalanche multiplication effect. Its core materials include semiconductors such as indium gallium arsenide (InGaAs), which have short-wave infrared response, low power consumption, and small size characteristics, making them suitable for fields such as quantum communication, lidar, and 3D imaging.

[0014] A SPAD can essentially be considered a PN junction diode. SPADs utilize the avalanche breakdown effect to achieve single-photon detection. Similar to other diodes, a SPAD includes a cathode and an anode. When a reverse bias voltage is applied, the cathode is connected to a positive voltage (or a positive voltage relative to the anode), and the anode is connected to a negative voltage (or a negative voltage relative to the cathode). The reverse bias voltage refers to the voltage applied across the PN junction. For a SPAD, operating in a reverse bias state is a necessary condition for avalanche breakdown to occur.

[0015] The breakdown voltage is the critical voltage value at which avalanche breakdown occurs in a SPAD under a specific reverse bias voltage. When the reverse bias voltage is high enough, the electric field strength in the depletion region becomes very large. At this point, the charge carriers (electrons or holes) accelerated by the electric field in the depletion region gain sufficient kinetic energy. When they collide with lattice atoms, they can knock valence band electrons to the conduction band, generating new electron-hole pairs. The newly generated charge carriers are also accelerated by the strong electric field, continuing to collide and ionize to generate more charge carriers. This process grows exponentially, forming an "avalanche" effect, which leads to a sharp increase in reverse current. This phenomenon is avalanche breakdown.

[0016] Overbias voltage is the portion of a SPAD's operating voltage (reverse bias voltage) that exceeds its breakdown voltage; in other words, it is the difference between the reverse bias voltage and the breakdown voltage. Overbias voltage is the most critical and important parameter in SPAD design and application, directly determining key device performance parameters such as photon detection efficiency and avalanche settling time.

[0017] Due to factors such as temperature and manufacturing process, the breakdown voltage of SPADs of the same specification may vary. This means that even if the same operating voltage is supplied to each SPAD in the SPAD array, the overbias voltage of each SPAD may be different. The reverse bias voltage of a SPAD, also known as its operating voltage, is the difference between the voltage at the cathode and anode of the SPAD. Assuming the anode of the SPAD is grounded, its operating voltage in the standby state is equal to the cathode voltage, and the overbias voltage = operating voltage - breakdown voltage.

[0018] Different overbias voltages in SPADs will lead to variations in their detection characteristics (such as timing characteristics, pulse characteristics, detection probability / sensitivity characteristics, etc.). Inappropriate overbias voltages can also cause reliability issues or even malfunctions in SPADs. For example, excessive overbias voltage can cause the quenching circuit to withstand excessively high voltages, exceeding its operating voltage and causing the circuit to burn out; insufficient overbias voltage can prevent the SPAD from sensing photons and generating pulses. The impact of inconsistent breakdown voltages is even more severe in large arrays, potentially causing some detectors to fail to avalanche or even break down directly.

[0019] To address the issue of inconsistent and unsuitable over-bias voltages among SPADs in a SPAD array, this application utilizes an external bias voltage adjustment circuit to regulate the over-bias voltage of the SPADs. See [link to relevant documentation]. Figure 1 It shows a circuit diagram of an embodiment of this application for overbias regulation of a SPAD, such as... Figure 1 As shown, the SPAD array control circuit 10 in this application includes a pixel unit array 30 and a bias voltage adjustment circuit 20 located outside the pixel unit array 30. The pixel unit array 30 includes a plurality of pixel units 40, and each pixel unit 40 (or SPAD pixel unit) may consist of at least a SPAD (or SPAD pixel), a quenching circuit, and a second voltage selection circuit. Assume that the pixel unit array includes n pixel units, where n is a positive integer.

[0020] like Figure 1 As shown, the bias regulation circuit may include a reference voltage source 201 and multiple drive enhancement circuits 202. The reference voltage source 201 provides m different reference voltages V. ref1 ~V refm Each reference voltage is boosted by a drive enhancement circuit 202 before being sent to the pixel unit array 30. A second voltage selection circuit within each pixel unit 40 of the pixel unit array 30 selects a suitable reference voltage from the multiple reference voltages sent to the pixel unit array 30 and sends it to one terminal of the SPAD. The other terminal of all SPADs in the pixel unit array 30 receives a fixed voltage, thus ensuring that the overbias voltage (the difference between the voltage difference across the SPAD and its breakdown voltage) of all SPADs tends to be consistent and / or maintains a suitable level. This results in higher detection consistency and better performance for each SPAD in the pixel unit array 30.

[0021] It is understood that in this application, the bias adjustment circuit 20 is a circuit module disposed outside the pixel unit array 30. That is, the reference voltage source 201 and the multiple drive enhancement circuits 202 and the circuit connection traces between them are all disposed outside the pixel unit array 30. Compared with the traditional method of directly disposing of the drive enhancement circuit 202 in each pixel unit 40, the embodiments of this application do not occupy the trace resources inside the pixel unit array 30. Moreover, the number of drive enhancement circuits 202 does not need to match the number of pixel units 40 in the pixel unit array 30, which can greatly reduce the number of drive enhancement circuits 202, thereby further reducing the trace resource occupation required by the bias adjustment circuit 20 outside the pixel unit array 30. Therefore, this application can reduce circuit resource usage on two levels. On the one hand, it can reduce the wiring resource usage within the pixel unit array 30, which is beneficial to reducing the area of ​​the pixel unit 40, thus enabling the pixel unit array 30 to be widely used in large-area array detectors. On the other hand, this application can also effectively overcome the problem of excessive wiring resource usage outside the SPAD array caused by moving the driving enhancement circuit originally located inside the SPAD pixel unit in the SPAD detector in the traditional technology, thereby enabling the high integration of detector chips.

[0022] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0023] In one embodiment of this application, see [link to embodiment]. Figure 1 This illustrates a schematic diagram of the composition structure of a SPAD array control circuit 10 provided in an embodiment of this application. Figure 1 As shown, the SPAD array control circuit 10 includes: a pixel unit array 30 and a bias voltage adjustment circuit 20 located outside the pixel unit array 30; The bias regulation circuit 20 includes a reference voltage source 201 and multiple drive enhancement circuits 202. The reference voltage source 201 provides multiple reference voltages V. ref Each drive enhancement circuit 202 receives a reference voltage V at its input terminal. ref To increase the reference voltage V ref The carrying capacity is output to the pixel unit array 30; The pixel unit array 30 includes a plurality of pixel units 40, and the first voltage terminal of the pixel unit 40 selectively receives a reference voltage V output by one of the drive enhancement circuits 202. ref The second voltage terminal of pixel unit 40 is connected to a fixed voltage.

[0024] It should be noted that the accompanying drawings in the embodiments of this application are merely illustrative of the circuit composition and do not represent the actual arrangement of the circuit, etc.

[0025] like Figure 1As shown, the reference voltage source 201 includes m reference voltage output terminals, which output m reference voltages, denoted as V. ref1 ~V refm Wherein, the reference voltage V refj The corresponding drive enhancement circuit j, j=1, 2, ..., m, is provided. The bias adjustment circuit 20 includes m drive enhancement circuits 202, denoted as: drive enhancement circuit 1 to drive enhancement circuit m, with only one label 202 shown in the figure. In the embodiment of this application, the drive enhancement circuit 202 is used to adjust the reference voltage V. ref Drive enhancement is performed to improve its load-carrying capacity, but the reference voltage V is not changed. ref The voltage value is essentially a buffer or voltage follower. In addition, as a buffer, it can provide a certain degree of isolation between the input and output. Specifically, the buffer can isolate the bias regulation circuit 20 located at the input end and the pixel unit array 30 located at the output end, so that the instantaneous large current (avalanche current) generated by the pixel unit array 30 in the working state is less likely to affect the stability of the front-end bias regulation circuit 20, and avoid mutual interference between the two.

[0026] In this embodiment, the input terminal of the drive enhancement circuit j is connected to the reference voltage source 201, which provides the reference voltage V. refj The reference voltage output terminal is connected via a signal line, thereby driving the enhancement circuit j to receive the reference voltage V through the corresponding signal line. refj .

[0027] like Figure 1 As shown, the pixel unit array 30 includes a plurality of pixel units 40 (only one 40 is shown in the figure). Pixel units 40 can be SPAD pixel units, wherein at least a SPAD is included. For example, as... Figure 2 As shown, pixel unit 40 may include SPAD 401, second voltage selection circuit 402, and quenching circuit 403. Figure 2 Only labels 401, 402, and 403 are shown in the diagram. The second voltage selection circuit 402 is connected to the outputs of m drive enhancement circuits 202, selecting the reference voltage V output by one of the drive enhancement circuits 202. refThe output is supplied to one terminal of SPAD 401. It should be noted that the first voltage terminal of pixel unit 40 is equivalent to the input terminal selected by its internal second voltage selection circuit 402 to receive the reference voltage, and can also be regarded as one terminal of SPAD 401 within pixel unit 40 receiving the reference voltage through quenching circuit 403. For ease of description, the second voltage terminal of pixel unit 40 will be described as the second voltage terminal of SPAD 401 in the following text. Correspondingly, the first voltage terminal of pixel unit 40 can be regarded as the other terminal of SPAD 401 receiving a fixed voltage; therefore, the first voltage terminal of pixel unit 40 can be described as the first voltage terminal of SPAD 401.

[0028] In the embodiments of this application, such as Figure 2 As shown, SPAD 401 includes an anode and a cathode, with its anode receiving a reference voltage V through a quenching circuit 403. ref Its cathode receives a fixed voltage V power .

[0029] like Figure 2 As shown, since the anode of SPAD 401 is connected to the reference voltage V through the quenching circuit 403... ref Therefore, the positive terminal of SPAD 401 corresponds to the first voltage terminal of pixel unit 40, and the negative terminal of SPAD 401 corresponds to the second voltage terminal of pixel unit 40.

[0030] In other embodiments, the cathode of SPAD 401 may also receive a reference voltage V. ref Its anode receives a fixed voltage. The quenching circuit 403 can be located at either the anode or cathode of the SPAD 401, and the anode or cathode of the SPAD 401 receives a reference voltage V through the quenching circuit 403. ref Or a fixed voltage.

[0031] In this embodiment of the application, if the cathode terminal of SPAD 401 is set as the second voltage terminal of pixel unit 40, then as Figure 2 As shown, the cathode of SPAD 401 serves as the second voltage terminal of pixel unit 40 and is connected to the first fixed voltage V. power Wherein, the first fixed voltage V power This can be the power supply voltage. The anode of SPAD 401, serving as the first voltage terminal of pixel unit 40, is connected to the second voltage selection circuit 402 via quenching circuit 403, and is used to receive the reference voltage V selected and output by the second voltage selection circuit 402. ref .

[0032] In other embodiments, if the cathode terminal of SPAD 401 is set as the first voltage terminal of pixel unit 40, then as Figure 3As shown, the cathode terminal of SPAD 401 is connected to the second voltage selection circuit 402 as the first voltage terminal of pixel unit 40, and is used to receive the reference voltage V selected and output by the second voltage selection circuit 402. ref The anode of SPAD 401 serves as the second voltage terminal of pixel unit 40 and is connected to a second fixed voltage VSS via quenching circuit 403. The second fixed voltage VSS can be ground voltage.

[0033] Thus, in this embodiment, the bias adjustment circuit 20 is a circuit module located outside the pixel unit array 30. That is, the reference voltage source 201, the multiple drive enhancement circuits 202, and the circuit connection traces between them are all located outside the pixel unit array 30. Compared with the traditional method of directly placing the drive enhancement circuit 202 inside each pixel unit 40, this embodiment does not occupy the trace resources inside the pixel unit array 30. Moreover, the number of drive enhancement circuits 202 does not need to match the number of pixel units 40 in the pixel unit array 30, which can greatly reduce the number of drive enhancement circuits 202, thereby further reducing the trace resource occupation required by the bias adjustment circuit 20 outside the pixel unit array 30. Therefore, this application can reduce circuit resource usage on two levels. On the one hand, it can reduce the wiring resource usage within the pixel unit array 30, which is beneficial to reducing the area of ​​the pixel unit 40, thus enabling the pixel unit array 30 to be widely used in large-area array detectors. On the other hand, this application can also effectively overcome the problem of excessive wiring resource usage outside the SPAD array caused by moving the driving enhancement circuit originally located inside the SPAD pixel unit in the SPAD detector in the traditional technology, thereby enabling the high integration of detector chips.

[0034] In some embodiments, the number of drive enhancement circuits 202 is equal to the reference voltage V provided by the reference voltage source 201. ref The number is the same, but less than the number of pixel units 40 in pixel unit array 30.

[0035] It should be noted that, as Figures 1-3 As shown in either case, a reference voltage V ref It corresponds to one drive enhancement circuit 202 and can correspond to multiple pixel units 40, with a reference voltage V. ref Each drive enhancement circuit 202 corresponds to a specific drive enhancement circuit 202, and each drive enhancement circuit 202 is used to drive and enhance a corresponding reference voltage V. ref To enhance its load-carrying capacity, the number of second voltage selection circuits 402 is the same as the number of SPADs 401 and they are located inside the pixel unit 40, thereby selecting a suitable reference voltage V for the first voltage terminal of the SPAD 401. ref .

[0036] For example, the number of drive enhancement circuits 202 = reference voltage V ref The number of reference voltages V is m, and the number of pixel units 40 is n, where m < n. Thus, one drive enhancement circuit 202 can connect to and drive multiple pixel units 40. Compared to a scheme where the drive enhancement circuit is located inside the pixel unit, the number of drive enhancement circuits 202 is reduced, resulting in a smaller overall circuit area without affecting the driving of the pixel units 40. It can be understood that m reference voltages V... ref The voltage value can be partially or completely the same, or partially or completely different. In the embodiments of this application, the reference voltage V ref The quantity m is only related to the number of ports on the reference voltage source 201 that output the reference voltage.

[0037] Thus, the solution provided in this application embodiment can achieve this by providing a suitable reference voltage V. ref By providing a first voltage terminal to each SPAD401 to ensure that their overbias is consistent and appropriate, the drive enhancement circuit 202 does not need to be located inside the pixel unit 40, reducing the wiring inside the pixel unit 40. The pixel unit 40 can be made smaller, making it suitable for large-area arrays.

[0038] Furthermore, by moving the drive enhancement circuit 202 from inside the pixel unit 40 to the reference voltage output terminal of the bias adjustment circuit 20, a smaller number of drive enhancement circuits 202 can be centrally arranged, making the wiring arrangement of the multiple drive enhancement circuits 202 more concentrated, thereby further reducing the chip wiring resources occupied outside the SPAD array.

[0039] In some embodiments, multiple reference voltages V ref The numerical value is set according to preset rules, which may include, but are not limited to, at least one of arithmetic sequence, geometric sequence, and step sequence.

[0040] It should be noted that in actual circuit design, circuits with a certain regularity are generally easier to implement and control. Therefore, the embodiments of this application can set the reference voltages in an arithmetic progression, a geometric progression, or a step-like manner that conforms to a certain regularity. However, they can also be set in an increasing but not arithmetic progression manner, or in a manner without obvious regularity; no specific limitation is made in this regard.

[0041] For example Figure 4 As shown, in some embodiments, the reference voltage source 201 includes a voltage divider resistor string, which includes multiple resistors R1~R1 connected in series. m The multiple reference voltages output by the resistor string can vary in an increasing / decreasing sequence, or in a stepped manner, or the resistance values ​​can be set as needed to obtain the required reference voltage. The resistor string can be in the form of fixed resistors, variable resistors, field-effect transistors, etc.

[0042] The first resistor R1 in the voltage divider resistor string is grounded (GND), and the last resistor R... m Connected to the power supply voltage VDD, the connection point between two adjacent resistors is a voltage node. Some or all of these voltage nodes are used to correspond to different output reference voltages V. ref .

[0043] like Figure 4 As shown, resistors R1 to R m The resistors form a voltage divider string, where in this example, each voltage node is used to output a reference voltage V. ref The grounding node of resistor R1 also outputs a reference voltage V. ref1 Assume resistors R1 to R2 are... m If all resistors are of the same specification, then m reference voltages V can be output in an arithmetic sequence. ref Assume resistor R1 ~ resistor R m If the resistance increases proportionally, then m reference voltages V can be output in a geometric sequence. ref Resistors R1 to R m The resistance value can also be of other magnitudes to output a reference voltage V that meets the requirements. ref Alternatively, the number of resistors in the voltage divider resistor string can be greater than m, so that multiple equal / unequal resistors connected in series are equivalent to forming a larger resistor, thereby obtaining a larger voltage to output a larger reference voltage.

[0044] In some embodiments, such as Figure 4 As shown, in addition to the voltage divider resistor string, the reference voltage source 201 may also include amplifier P1 and transistor T1, wherein the non-inverting input terminal (+) of amplifier P1 receives the input reference voltage V. in The output terminal is connected to the gate of transistor T1. The first terminal of transistor T1 is connected to the power supply voltage VDD, and the second terminal of transistor T1 is connected to resistor R. m And the inverting input terminal (-) of amplifier P1. Among them, amplifier P1 can be an error amplifier (EA), and transistor T1 can be an N-type metal-oxide-semiconductor field-effect transistor (NMOS transistor).

[0045] In other embodiments, such as Figure 5 As shown, the reference voltage source 201 includes at least one sub-source 2011 (one denoted by a number 2011 is shown in the figure), each sub-source 2011 being used to provide a corresponding reference voltage V. ref .

[0046] likeFigure 5 As shown, corresponding to m reference voltages V ref The reference voltage source 201 may include m sub-power sources 2011, denoted as sub-power source 1 to sub-power source m, which respectively correspond to the output reference voltage V. ref1 ~Reference voltage V refm Here, each sub-power supply 2011 is an independent power supply, and its output reference voltage V can be set separately. ref .

[0047] In this embodiment, the reference voltage source 201 can be a global voltage source circuit composed of multiple independent voltage sources, for example... Figure 5 As shown, the independent voltage source, or sub-power supply 2011, can be a digital-to-analog converter (DAC) that outputs a reference voltage independently.

[0048] In some embodiments, such as Figure 4 or Figure 5 As shown, the drive enhancement circuit 202 can be a voltage follower (buffer). A voltage follower is a 1:1 amplifier formed by connecting its output terminal and inverting input terminal (-), used to enhance the input voltage without changing its resistance. For example... Figure 4 or Figure 5 As shown, the reference voltage output terminal of the reference voltage source 201 is connected to the non-inverting input terminal (+) of the corresponding voltage follower (buffer), and the corresponding reference voltage V refj The voltage is used as the input voltage of the voltage follower, and after being driven and enhanced by the voltage follower, it is output to the pixel unit 40.

[0049] In some embodiments, at least some of the drive enhancement circuits 202 have different drive boosting capabilities, and the number of pixel units 40 corresponding to the drive enhancement circuit 202 with stronger drive boosting capability is greater than the number of pixel units 40 corresponding to the drive enhancement circuit 202 with weaker drive boosting capability; wherein, the pixel unit 40 corresponding to the drive enhancement circuit 202 refers to the reference voltage V output by the drive enhancement circuit 202 selected for connection. ref 40 pixel units.

[0050] It should be noted that the driving enhancement circuits 202 of different specifications have varying driving boost capabilities. A larger driving enhancement circuit 202 with a stronger driving boost capability can drive more pixel units 40, while a smaller driving enhancement circuit 202 with a weaker driving boost capability can drive fewer pixel units 40. Therefore, in this embodiment, the driving enhancement circuit 202 can be configured to drive a number of pixel units 40 that are commensurate with its driving boost capability, ensuring that the efficient operation of the circuit is not affected.

[0051] In some embodiments, such as Figure 6 As shown, the bias regulation circuit 20 also includes multiple first voltage selection circuits 203, each corresponding to a multiple drive enhancement circuit 202. The first voltage selection circuit 203 is located between the reference voltage source 201 and the drive enhancement circuit 202, and is used to receive multiple reference voltages V provided by the reference voltage source 201. ref And select one output to the corresponding drive enhancement circuit 202.

[0052] Here, we take the reference voltage source 201 as an example of a voltage divider resistor string.

[0053] exist Figure 4 In the scheme shown, the voltage node between the drive enhancement circuit 202 and the voltage divider resistor is directly connected, and the reference voltage V obtained by the voltage divider resistor is... ref It is a fixed value (depending on the resistance of the voltage divider resistor). Figure 5 The scheme shown is similar, that is, the drive enhancement circuit 202 and its input reference voltage V ref To maintain a fixed matching relationship, when there are many pixel units 40 in the pixel unit array 30, they require the same or similar reference voltage V. ref At this time, these pixel units 40 need to be connected to the same drive enhancement circuit 202 to share the same reference voltage V. ref At this point, the drive enhancement circuit 202 is required to have a significant drive boost capability. However, the drive boost capability of the drive enhancement circuit 202 depends on its circuit specifications, which are determined by its circuit structure at the initial chip design stage and cannot be adjusted further. Figure 4 and Figure 5 In the scheme shown, due to the driving enhancement circuit 202 and its input reference voltage V ref The two voltages have a fixed matching relationship; therefore, a reference voltage V may exist. ref The problem of mismatch between the drive enhancement circuit 202 and the pixel unit 40.

[0054] Therefore, in this embodiment of the application, a first voltage selection circuit 203 is also provided before each drive enhancement circuit 202, such as... Figure 6 As shown, the input of each first voltage selection circuit 203 receives all reference voltages V from the output of the reference voltage source 201. ref The voltage is selected and output to the corresponding drive enhancement circuit 202 for drive boosting; then the input terminal of the second voltage selection circuit 402 in each pixel unit 40 receives the reference voltage V output by all drive enhancement circuits 202. ref And select one output to the first voltage terminal of the corresponding SPAD 401.

[0055] In this way, SPADs 401 with the same or similar required reference voltages can select the same drive enhancement circuit 202 with matching specifications (drive boost capability) through their respective second voltage selection circuits 402. Then, the drive enhancement circuit 202 selects a suitable reference voltage V through the corresponding first voltage selection circuit 203 based on the reference voltage required by these SPADs 401. ref Make the reference voltage V ref The matching degree between the drive enhancement circuit 202 and the pixel unit 40 is higher.

[0056] In this embodiment of the application, the same reference voltage V can be used. ref Several pixel units 40 are called similar pixel units. In the pixel unit array 30, the first voltage terminals of similar pixel units are selected to be connected to the same reference voltage V output by the driving enhancement circuit 202. ref More specifically, "same type pixel unit" refers to any two or more pixel units 40 whose difference in ideal reverse bias voltage is less than or equal to a first preset threshold.

[0057] It should be noted that while each pixel unit 40 in the pixel unit array 30 has the same specifications, as mentioned earlier, due to various factors, the breakdown voltage of the SPAD 401 in each pixel unit 40 may be different. This results in different overbias voltages even with the same reverse bias voltage, leading to poor detection consistency among the pixel units 40 in the pixel unit array 30 and affecting detector performance. Therefore, in this embodiment, the voltage at the second voltage terminal of each pixel unit 40 is set to a constant fixed voltage, and a slightly different reference voltage is provided to the first voltage terminal of each pixel unit 40. This ensures that the reverse bias voltage of each pixel unit 40 is its ideal reverse bias voltage (or closest to its ideal reverse bias voltage). In this case, the overbias voltage of the pixel unit 40 is its ideal overbias voltage (or closest to its ideal overbias voltage). The ideal overbias voltage is the overbias voltage that allows the pixel unit 40 to operate in its optimal state. It is understandable that the reverse bias voltage of pixel unit 40 is the same as the reverse bias voltage of its internal SPAD 401. Similarly, the overbias voltage and ideal overbias voltage of pixel unit 40 are the same as the overbias voltage and ideal overbias voltage of its internal SPAD 401, respectively. It should be noted that the ideal overbias voltage of the SPAD is one of the performance parameters of the SPAD, which can be designed during the fabrication process of the SPAD device or obtained through testing after fabrication, and is a known quantity.

[0058] like Figure 6 Since the reverse bias voltage of a SPAD is equal to the absolute value of the voltage difference across its terminals, and in this application, the second voltage terminal of the SPAD 401 receives a fixed voltage Vpower (taking Vpower as an example), while the first voltage terminal receives a reference voltage V...ref Therefore, the reverse bias voltage of SPAD 401 = V power -V ref (Ignore positive and negative signs). If the reverse bias voltage of SPAD 401 is equal to its ideal reverse bias voltage, it means that the reference voltage at the first voltage terminal of SPAD 401 is exactly its required ideal reference voltage, that is, the overbias voltage of SPAD 401 is exactly equal to its ideal overbias voltage.

[0059] It is understandable that, since the second voltage terminal of each pixel unit 40 receives the same fixed voltage V, power If the difference in ideal reverse bias voltage of different pixel units 40 is less than or equal to the first preset threshold, it means that the difference in ideal reference voltage required for their first voltage terminals is also less than or equal to the first preset threshold. In this embodiment, pixel units 40 that meet this characteristic are classified as similar pixel units. The first voltage terminals of these similar pixel units are connected to the same reference voltage output by the same driving enhancement circuit 202, so as to achieve the purpose of sharing the driving enhancement circuit 202 and achieving good detection performance.

[0060] Here, the first preset threshold is the maximum critical value of the allowable range of differences in ideal reverse bias voltage. If the difference in ideal reverse bias voltage between a certain pixel unit 40 and the other pixel units 40 is greater than the first preset threshold, then the pixel unit 40 itself is considered as a pixel unit of the same type. In this case, the reference voltage selected and received at the first voltage terminal of the pixel unit 40 is only used to drive the pixel unit 40.

[0061] In this way, during the circuit design phase, multiple drive enhancement circuits 202 with different driving capabilities can be designed (for example, according to their rules, they can be simply divided into large buffers and small buffers). Even multiple levels of drive enhancement circuits 202 can be designed according to the different degrees of drive capability enhancement. The larger the drive enhancement circuit 202 (the larger the circuit area), the more pixel units 40 can be voltage driven.

[0062] In this embodiment, multiple pixel units 40 with the same or similar required reference voltages can be grouped into one category as similar pixel units. Pixel units 40 within the same category can be voltage-driven and selected using the same driving enhancement circuit 202, and can also use the same reference voltage V. ref Pixel units that share a single drive enhancement circuit 202 for voltage drive boosting can also be considered to be within the same level / channel. This allows for the realization of the reference voltage V. ref The corresponding levels between the drive enhancement circuit 202 and the pixel unit 40.

[0063] In this way, each pixel unit 40 can select a suitable driving enhancement circuit 202 through the second voltage selection circuit 402, so that the driving enhancement circuit 202 with strong driving capability can drive and enhance more pixel units 40, while the driving enhancement circuit 202 with weak driving capability can drive and enhance fewer pixel units 40, thus improving applicability.

[0064] It should be noted that the first voltage selection circuit 203 and the second voltage selection circuit 402 in the embodiments of this application can both be decoders or decoders, such as multiplexers, and their selected signal outputs are controlled by corresponding control signals. The control signals can be provided by control units such as controllers.

[0065] This application provides a SPAD array control circuit 10, which moves the drive enhancement circuit 202 inside the pixel unit 40 to the bias adjustment circuit 20 outside the pixel unit 40. By providing different reference voltages to the first voltage terminals of different pixel units 40, the bias adjustment circuit 20 can adjust the overbias of each pixel unit 40 to be consistent and / or maintain a suitable level. This can make the detection performance of multiple pixel units 40 in the pixel unit array 30 similar and the reliability higher, and can also reduce the circuit area occupied inside the pixel unit 40, thereby realizing large-area array applications.

[0066] Based on the foregoing embodiments, this application also provides a control method applied to the aforementioned SPAD array control circuit 10. For example... Figure 7 As shown, the control method may include: S701: Provide a fixed voltage to the second voltage terminal of each pixel unit 40 in the pixel unit array 30, and obtain the ideal reference voltage required for the first voltage terminal of each pixel unit 40.

[0067] S702: Determine the reference voltages that the reference voltage source 201 needs to output based on the ideal reference voltage required by each pixel unit 40; S703: Based on the reference voltages that the reference voltage source 201 needs to output, the number of pixel units 40 that each reference voltage needs to drive, and the specifications of each drive enhancement circuit 202, determine the correspondence between each reference voltage, the drive enhancement circuit 202 and the pixel unit 40 and connect the circuits.

[0068] It should be noted that the second voltage terminal of each pixel unit 40 in the pixel unit array 30 receives the same fixed voltage, while the ideal reference voltage required for the first voltage terminal of each pixel unit 40 may be different and needs to be determined separately.

[0069] In step S701, obtaining the ideal reference voltage required for the first voltage terminal of each pixel unit 40 may include: Determine the ideal reverse bias voltage for each pixel unit 40; The ideal reference voltage required for the first voltage terminal of the pixel unit 40 is determined based on the ideal reverse bias voltage of each pixel unit 40 and the fixed voltage of the second voltage terminal.

[0070] It should be noted that the ideal reverse bias voltage is the reverse bias voltage that allows the SPAD 401 to operate at the ideal overbias voltage. Under the ideal overbias voltage, the SPAD 401 performs optimally. For the SPAD 401: reverse bias voltage = cathode voltage - anode voltage. Figure 6 For example, the cathode voltage (voltage at the second voltage terminal) of SPAD 401 is a fixed voltage V. power The anode voltage (voltage at the first voltage terminal) of SPAD401 is the reference voltage V connected through the quenching circuit 403. ref Then the reverse bias voltage of the SPAD = fixed voltage - reference voltage, where the fixed voltage is V. power Since the ideal reverse bias voltage is known, the ideal reference voltage required for the first voltage terminal can be calculated once the ideal reverse bias voltage is determined.

[0071] In other words, before providing the required ideal reference voltage to the first voltage terminal of each pixel unit 40 in the pixel unit array 30, the ideal reverse bias voltage of the pixel unit 40 must first be determined. In some embodiments, the pixel unit 40 may include a SPAD 401, a quenching circuit 403, and an inverter 404. The cathode or anode of the SPAD 401 serves as the first voltage terminal of the pixel unit 40 and is connected to the reference voltage V output by the drive enhancement circuit 202. ref The positive or negative terminal of SPAD 401 serves as the second voltage terminal of pixel unit 40 and is connected to a fixed voltage; the quenching circuit 403 is disposed on the negative or positive terminal of SPAD 401, and the input terminal of inverter 404 is connected to the intermediate node between SPAD 401 and quenching circuit 403.

[0072] For example, such as Figure 8 As shown, in the working state, the anode of SPAD 401 is connected to the reference voltage V through the quenching circuit 403 as the first voltage terminal. ref It is also connected to the input terminal of inverter 404 (the connection node is denoted as point Q). The input terminal (point Q) of inverter 404 is located between SPAD 401 and quenching circuit 403; the cathode of SPAD 401 is connected to a fixed voltage V as the second voltage terminal. power .

[0073] Exemplary, embodiments of this application may be based on, as Figure 8The circuit shown determines the ideal reverse bias voltage of pixel unit 40 before the SPAD array enters the working state. Specifically, it may include the following steps: S1: Obtain the ideal overbias voltage of SPAD 401 and the threshold voltage of inverter 404 within pixel unit 40; S2: Provide the same fixed reference voltage to the first voltage terminal of each pixel unit 40 in the pixel unit array 30; S3: Adjust the voltage of the second voltage terminal of each pixel unit 40 until the inverter 404 flips, and record the voltage of the second voltage terminal of the pixel unit 40 when each inverter 404 starts to flip (this voltage can be recorded as the flip voltage). S4: Determine the ideal reverse bias voltage of pixel unit 40 based on the flip voltage, the ideal over bias voltage of SPAD 401 in pixel unit 40, the fixed reference voltage, and the threshold voltage of inverter 404.

[0074] It should be noted that the ideal overbias voltage is the overbias voltage that allows SPAD 401 to operate in its optimal or near-optimal state, and is a known parameter; the threshold voltage of inverter 404 is the critical voltage value at the input terminal of inverter 404 when the output signal of inverter 404 flips, which is also a known parameter, with a fixed reference voltage V. ref-g Under this test environment, the voltage provided to the first voltage terminal of the pixel unit 40 remains constant, and it is also a known parameter.

[0075] like Figure 8 As shown, taking the anode of SPAD 401 connected to quenching circuit 403 as the first voltage terminal of pixel unit 40 and the cathode of SPAD 401 as the second voltage terminal of pixel unit 40 as an example, the fixed reference voltage V of the anode of SPAD 401 can be... ref-g When set to 0, the voltage at the cathode (second voltage terminal) of SPAD 401 is equal to the reverse bias voltage on SPAD 401 during voltage regulation. Let's assume the reverse bias voltage at the cathode of SPAD 401 during this process is denoted as V. op Then the cathode voltage V of SPAD 401 op =Breakdown voltage V br +overbias voltage V ov (Ignore the sign of the voltage and take the absolute value of the voltage).

[0076] It should be noted that, as Figure 8 As shown, the pixel unit 40 may also include a digital circuit 405. The output terminal of the inverter 404 is connected to the digital circuit 405. When the output signal of the inverter 404 is flipped, the digital circuit 405 outputs a valid signal.

[0077] In pixel unit 40, SPAD 401 receives incident photons and generates a pulse signal after triggering avalanche breakdown. Quenching circuit 403 performs a quenching operation after SPAD 401 enters the avalanche state to terminate the avalanche breakdown. Inverter 404 starts to flip and outputs rising or falling edge signals when the voltage at the anode of SPAD 401 reaches its threshold voltage. Digital circuit 405 acquires and counts the rising or falling edge signals output by inverter 404.

[0078] The specific transmission process of photoelectric signals in pixel unit 40 is as follows: Under a large reverse bias voltage (exceeding its breakdown voltage), SPAD 401 is in an excited state. When an incident photon enters the photosensitive area of ​​SPAD 401 and triggers an avalanche, SPAD 401 generates a pulse signal. Then, the quenching circuit 403 restores SPAD 401 to its state before the avalanche, preparing it to sense the next photon. The pulse signal output by SPAD 401 causes the potential V at the anode end (i.e., Q point) of SPAD 401 to... Q The potential changes until it reaches the threshold voltage V of inverter 404. th The inverter 404 flips and generates a rising or falling edge signal, which is transmitted to the digital circuit 405. The digital circuit 405 uses a counter or other counting unit to sample and count the rising or falling edge signal. The quenching circuit 403 can be an active quenching circuit or a passive quenching circuit, for example... Figure 8 The passive quenching circuit shown is a resistor Rc, where quenching circuit 403 is a resistor.

[0079] However, if the reverse bias voltage V across pixel unit 40 op Not greater than its breakdown voltage V br Therefore, even if photons reach SPAD 401, they cannot trigger an avalanche to generate a pulse signal.

[0080] Therefore, this embodiment of the application adjusts the voltage (i.e., reverse bias voltage) at the second voltage terminal of the pixel unit 40 to make the reverse bias voltage V across the pixel unit 40... op The voltage changes continuously until SPAD 401 can sense the photon output pulse signal and cause inverter 404 to flip. Record the voltage at the second voltage terminal at this moment (denoted as the flip voltage V). op-ref At this point, SPAD 401 and quenching circuit 403 form a series path, and both affect the switching voltage V. op-ref Voltage division is performed, and in this critical state, the voltage divided by SPAD 401 is exactly equal to its breakdown voltage V. br The voltage obtained by the quenching circuit 403 is also the potential V at point Q. Q Then it equals the switching voltage Vop-ref With breakdown voltage V br The difference between them, therefore, the following relationship exists: (1).

[0081] Furthermore, as can be seen from the aforementioned analysis, when the reverse bias voltage V on SPAD 401... op It is equal to its ideal reverse bias voltage V op-L At that time, the overbias voltage on SPAD 401 is exactly equal to its ideal overbias voltage V. ov-L Therefore, the following relationship exists: (2).

[0082] According to equations (1) and (2), we can obtain: (3).

[0083] In equation (3), the ideal overbias voltage V ov-L and threshold voltage V th All parameters are known, including the switching voltage V. op-ref The ideal reverse bias voltage V can be calculated by determining it using the methods described above. op-L .

[0084] It should also be noted that the voltage at the second voltage terminal of pixel unit 40 can be adjusted in steps. For example, it can be adjusted by gradually increasing the voltage from an initial voltage in certain steps, or by gradually decreasing the voltage from an initial voltage in certain steps. Alternatively, coarse adjustment followed by fine adjustment can be performed. For example, the voltage can be coarsely adjusted by gradually increasing the voltage value in larger steps until the inverter 404 flips, and then finely adjusted by gradually decreasing the voltage value in smaller steps until the inverter 404 flips, resulting in a more accurate flipping voltage. Furthermore, step adjustment can be performed from an initial voltage using both decreasing and increasing steps to avoid incorrect adjustment direction. After the inverter 404 flips in a certain step direction, fine adjustment can then be performed in the opposite step direction.

[0085] It should also be noted that in the aforementioned example, the fixed reference voltage was assumed to be 0. Therefore, the fixed reference voltage was omitted in the calculation. If the fixed reference voltage is not 0, it can be substituted into the calculation accordingly. The same principle applies to the case where the first voltage terminal is the cathode of SPAD 401 and the second voltage terminal is the anode of SPAD 401, except that the terminal with the fixed voltage changes, which will not be elaborated here.

[0086] In some embodiments, during step S701, the control method may further include the following during the process of adjusting the voltage at the second voltage terminal of each pixel unit 40: The same initial voltage is provided to the second voltage terminal of each pixel unit 40, and the voltage of the second voltage terminal of each pixel unit 40 is adjusted synchronously and uniformly. For a pixel unit 40 that has already output a pulse signal, while continuing to adjust the voltage of the second voltage terminal of the pixel unit 40, the fixed reference voltage of the first voltage terminal of the pixel unit 40 is adjusted synchronously so that the voltage difference between the second voltage terminal of the pixel unit 40 and the fixed reference voltage of the first voltage terminal is always less than or equal to the second preset threshold.

[0087] It should be noted that the pixel unit array 30 typically contains a large number of pixel units 40. Adjusting the voltage at the second voltage terminal of each pixel unit 40 individually would be time-consuming and difficult to implement. Therefore, in this embodiment, during the determination of the ideal reverse bias voltage for each pixel unit 40, the second voltage terminals of multiple pixel units 40 in the pixel unit array 30 are provided with the same voltage, and the adjustment is performed synchronously. That is, regardless of the degree of adjustment, the second voltage terminal of each pixel unit 40 maintains the same voltage.

[0088] Under this synchronous adjustment, some pixel units 40 may have low breakdown voltages. During the adjustment process, the reverse bias voltage across their terminals may exceed their breakdown voltage earlier, causing pixel units 40 to output pulse signals in the early stages of the adjustment process. If the voltage at the second voltage terminal of these pixel units 40 is further increased or decreased, it may lead to excessive reverse bias voltage on the pixel units 40. This could damage the quenching circuit 403 and / or the voltage division on the SPAD 401 when the SPAD 401 senses photon avalanche and generates avalanche current. Therefore, during the synchronous adjustment of the voltage at the second voltage terminal of all pixel units 401, for pixel units 40 that have already output pulse signals (i.e., the inverter 404 has already flipped), the fixed reference voltage connected to the first voltage terminal of these pixel units 40 needs to be adjusted synchronously to prevent the reverse bias voltage on these pixel units 40 from becoming too large, thus achieving a withstand voltage protection effect.

[0089] For example, the voltage difference (absolute value) between the second voltage terminal of these pixel units 40 and the fixed reference voltage of the first voltage terminal is always less than or equal to a second preset threshold. The second preset threshold may be different for each pixel unit 40. For example, the specific value of the second preset threshold can be determined based on the withstand voltage limit of these SPADs 401 and / or quenching circuits 403 to ensure that the voltage division on the SPADs 401 and / or quenching circuits 403 within each pixel unit 40 does not exceed its withstand voltage limit. Alternatively, the second preset threshold may be less than or equal to the flip voltage V corresponding to these pixel units 40. op-refSo that the flip voltage V corresponding to each pixel unit 40 is determined. op-ref Then, the reverse bias voltage on each pixel unit 40 is made lower than the critical value at which it can sense photons (i.e., the flip voltage V). op-ref This is equivalent to shutting down the pixel units 40 that have previously output pulse signals, thus avoiding unnecessary circuit losses.

[0090] For example, if the voltage at the second voltage terminal is increased or decreased by a certain value, the fixed reference voltage connected to the first voltage terminal of these pixel units 40 will also be increased or decreased by the same value, so that the reverse bias voltage of these pixel units 40 remains unchanged, avoiding damage to the device during the adjustment process and achieving withstand voltage protection.

[0091] In other words, in order to prevent some pixel units 40 with smaller breakdown voltages from burning out due to excessive reverse bias voltage caused by voltage adjustment at the second voltage terminal during the scanning process to determine the ideal reverse bias voltage of the pixel unit 40, which would exceed its withstand voltage limit, this embodiment of the application synchronously increases the fixed reference voltage at its first voltage terminal (for example, by selecting a larger voltage through the second voltage selection circuit 402) after the SPAD 401 starts outputting the pulse signal, thereby providing withstand voltage protection.

[0092] After step S701, step S702 is executed: based on the ideal reference voltage required by each pixel unit 40, the reference voltages that the reference voltage source 201 needs to output are determined.

[0093] It should be noted that, in this embodiment of the application, before selecting a reference voltage to be supplied to the first voltage terminal of the pixel unit 40, the ideal reverse bias voltage of the pixel unit 40 must first be determined through the aforementioned step S701. Based on the determined ideal reverse bias voltage and the known fixed voltage of the second voltage terminal, the ideal reference voltage required for the first voltage terminal of the pixel unit 40 is calculated.

[0094] That is, after determining the ideal reverse bias voltage for all pixel units 40, the voltage at the second voltage terminal of all pixel units 40 is uniformly adjusted to a fixed voltage V. power (with V) power (For example) Keeping it unchanged, based on the ideal reverse bias voltage V of each pixel unit 40 op-L and fixed voltage V power Determine the ideal reference voltage V required for its first voltage terminal. ref-L Ideal reference voltage V ref-L =V op-L -V power Or V ref-L =V power -V op-L .

[0095] In this way, the ideal reference voltage required for each pixel unit 40 is obtained, and then the reference voltage source 201 is set to output each reference voltage according to the ideal reference voltage required for these pixel units 40.

[0096] Specifically, since the number of ports that the reference voltage source 201 can output reference voltage may be less than the number of ideal reference voltages required by the pixel units 40 in the pixel unit array 30, several suitable reference voltages can be selected according to the ideal reference voltage values ​​required by the pixel units 40 in the pixel unit array 30 and output by the reference voltage source 201, so that the voltage range of the several reference voltages output by the reference voltage source 201 can cover all the ideal reference voltage values ​​required by the pixel units 40.

[0097] Furthermore, the magnitude of each reference voltage value output by the reference voltage source 201 can be set near the ideal reference voltage value required by some / all pixel units 40, so that some / all pixel units 40 can share the reference voltage and ensure better working performance.

[0098] Finally, step S703 is executed: based on the reference voltages that the reference voltage source 201 needs to output, the number of pixel units 40 that each reference voltage needs to drive, and the specifications of each drive enhancement circuit 202, the correspondence between each reference voltage, the drive enhancement circuit 202 and the pixel unit 40 is determined and the circuit connection is turned on.

[0099] It should be noted that multiple pixel units 40 with similar ideal reference voltages can be driven by the same reference voltage. That is, the number of reference voltages actually output by the reference voltage source 201 can be less than the number of pixel units 40.

[0100] In some embodiments, determining the correspondence between each reference voltage, the drive enhancement circuit 202, and the pixel unit 40 and connecting the circuit connections includes: Based on the ideal reference voltage required by each pixel unit 40, determine the pixel unit 40 that needs to be driven by each reference voltage; wherein, the difference between the ideal reference voltage required by the pixel unit 40 that needs to be driven by the reference voltage and the reference voltage is less than or equal to a third preset threshold. The number of pixel units 40 to be driven corresponding to each reference voltage and the specifications of each driving enhancement circuit 202 are obtained. Based on the number of pixel units 40 that each reference voltage needs to drive, select a matching drive enhancement circuit 202 and sequentially connect the reference voltage, the matching drive enhancement circuit 202, and the corresponding driven pixel units 40.

[0101] It should be noted that for several pixel units 40 driven by the same reference voltage, the difference between the ideal reference voltage and the reference voltage of these pixel units 40 (this difference can be the absolute value of the difference between the ideal reference voltage and the reference voltage) should be less than a third preset threshold. The third preset threshold is the allowable difference value for classifying multiple ideal reference voltages into one category.

[0102] In some embodiments, determining the pixel unit 40 driven by each reference voltage based on the ideal reference voltage required by each pixel unit 40 may include: Each pixel unit 40 in the pixel unit array 30 is classified to obtain multiple similar pixel units. The difference in the ideal reference voltage required by the similar pixel units is less than or equal to the first preset threshold. Based on the difference between the ideal reference voltage required by various similar pixel units 40 and the reference voltage, the similar pixel units that each reference voltage needs to drive are determined.

[0103] It should be noted that the first preset threshold is the maximum allowable difference in the ideal reference voltage required between pixel units of the same type. If the difference in the ideal reference voltage is less than or equal to the first preset threshold, it indicates that the ideal reference voltages of these pixel units 40 are close and can be classified into the same category. That is, within a group of pixel units of the same type, the difference in the required ideal reference voltage between any two pixel units 40 is less than or equal to the first preset threshold. Pixel units 40 that cannot be classified into the same category as other pixel units 40 form a single pixel unit of the same type. Here, the classification of pixel units 40 can be implemented by software or algorithms with statistical and classification functions. Furthermore, since pixel units of the same type are driven by the same reference voltage, the total number of categories of pixel units of the same type can be set to m, thus ensuring a one-to-one correspondence between different categories of pixel units of the same type and different reference voltages.

[0104] In other embodiments, determining the pixel unit 40 driven by each reference voltage based on the ideal reference voltage required by each pixel unit 40 may include: The ideal reference voltage required by each pixel unit 40 is compared with the reference voltage output by the reference voltage source 201, and the reference voltage V that is closest to the ideal reference voltage required by the pixel unit 40 is selected. ref The reference voltage V received by the pixel unit 40 is determined. ref .

[0105] It should be noted that, in this embodiment, the ideal reference voltage required by the pixel unit 40 and each reference voltage V that the reference voltage source 201 can output can also be directly used. ref The closest one is compared and selected as the reference voltage V for driving the pixel unit 40. refThus, the reference voltage V connected to the pixel unit 40 ref To achieve the best results, the voltage should be closest to the desired ideal reference voltage. Here, a reference voltage V can be used. ref Several pixel units 40 driven by the corresponding pixel unit are treated as the same type of pixel unit.

[0106] In some embodiments, the n pixel units 40 can be divided into m classes of similar pixel units. A first ideal reference voltage is determined from the ideal reference voltages of each pixel unit 40 in each class of similar pixel units. The first ideal reference voltage can be one of the maximum value, minimum value, average value, median value, weighted average value, etc., and the first ideal reference voltage is used as the reference voltage shared by the pixel units of the same class. Alternatively, statistical analysis can be performed on the m ideal reference voltages, and they can be adjusted according to the aforementioned arithmetic sequence, geometric sequence, or step number method to obtain the corresponding m reference voltages. A corresponding reference voltage source 201 is then designed to output the m reference voltages.

[0107] In some embodiments, a specification-matched drive enhancement circuit 202 is selected based on the number of pixel units 40 that need to be driven for each reference voltage, including: Determine the number of pixel units 40 in the same type of pixel unit that each reference voltage needs to drive; Arrange various similar pixel units according to the number of pixel units, and arrange each driving enhancement circuit 202 according to its size; Multiple similar pixel units and each driving enhancement circuit 202 are matched and connected sequentially according to the same arrangement rule.

[0108] It should be noted that there is a one-to-one correspondence between the m reference voltages and the m drive enhancement circuits 202. Larger drive enhancement circuits 202 (typically with larger areas) can typically support a greater number of pixel units 40. Therefore, pixel units of the same type can be sorted according to the number of pixel units 40 they contain, and the drive enhancement circuits 202 can be sorted according to the same sorting rules (from largest to smallest or smallest to largest) according to their size. Then, the drive enhancement circuits 202 and the pixel units 40 of the same type can be connected in the same order. That is, the largest drive enhancement circuit 202 connects to the largest number of pixel units 40, and the smallest drive enhancement circuit 202 connects to the smallest number of pixel units 40.

[0109] In this way, embodiments of this application can design multiple drive enhancement circuits 202 with different specifications (corresponding to different driving capabilities), grouping multiple pixel units 40 with the same or similar required reference voltage into one category. Pixel units 40 within the same category select the same reference voltage and are driven by the same drive enhancement circuit 202 for voltage boosting. This achieves a category-based correspondence between the reference voltage, the drive enhancement circuit 202, and the pixel units 40. This allows drive enhancement circuits 202 with stronger driving capabilities to drive and boost a larger number of pixel units 40, while drive enhancement circuits 202 with weaker driving capabilities drive and boost a smaller number of pixel units 40, resulting in better applicability.

[0110] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

[0111] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0112] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0113] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0114] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0115] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0116] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A SPAD array control circuit, characterized in that, It includes a pixel unit array and a bias adjustment circuit located outside the pixel unit array; The bias voltage adjustment circuit includes a reference voltage source and multiple drive enhancement circuits. The reference voltage source provides multiple reference voltages, and the input terminal of each drive enhancement circuit receives one of the reference voltages and outputs it to the pixel unit array. The pixel unit array includes multiple pixel units, the first voltage terminal of the pixel unit selectively receives a reference voltage output by one of the driving enhancement circuits, and the second voltage terminal of the pixel unit is connected to a fixed voltage.

2. The SPAD array control circuit according to claim 1, characterized in that, The number of drive enhancement circuits is the same as the number of the plurality of reference voltages provided by the reference voltage source, and is less than the number of pixel units in the pixel unit array.

3. The SPAD array control circuit according to claim 1, characterized in that, The values ​​of the multiple reference voltages are set according to a preset rule, which includes at least one of an arithmetic sequence, a geometric sequence, and a step sequence.

4. The SPAD array control circuit according to claim 3, characterized in that, The bias voltage regulation circuit further includes a plurality of first voltage selection circuits, each of which corresponds one-to-one with a plurality of drive enhancement circuits. The first voltage selection circuit is disposed between the reference voltage source and the drive enhancement circuit, and is used to receive the plurality of reference voltages provided by the reference voltage source and select one to output to the corresponding drive enhancement circuit.

5. The SPAD array control circuit according to any one of claims 1-4, characterized in that, At least some of the drive enhancement circuits have different drive boosting capabilities, and the number of pixel units corresponding to the drive enhancement circuit with stronger drive boosting capability is greater than the number of pixel units corresponding to the drive enhancement circuit with weaker drive boosting capability; wherein, the pixel unit corresponding to the drive enhancement circuit refers to the pixel unit that is selected to connect to the reference voltage output by the drive enhancement circuit.

6. The SPAD array control circuit according to claim 5, characterized in that, In the pixel unit array, the first voltage terminals of pixel units of the same type are selected to be connected to the same reference voltage output by the driving enhancement circuit; Among them, the same type of pixel unit refers to any two or more pixel units whose difference in ideal reverse bias voltage is less than or equal to the first preset threshold.

7. A control method for a SPAD array control circuit, characterized in that, The SPAD array control circuit is applied to a SPAD array control circuit, which includes a pixel unit array and a bias voltage adjustment circuit located outside the pixel unit array. The bias voltage adjustment circuit includes a reference voltage source and multiple drive enhancement circuits. The input terminal of each drive enhancement circuit receives a reference voltage and outputs it to the pixel unit array. The pixel unit array includes multiple pixel units, the first voltage terminal of the pixel unit selectively receives a reference voltage output by one of the driving enhancement circuits, and the second voltage terminal of the pixel unit is connected to a fixed voltage; The control method includes: A fixed voltage is provided to the second voltage terminal of each pixel unit in the pixel unit array, and the ideal reference voltage required for the first voltage terminal of each pixel unit is obtained; Based on the ideal reference voltage required by each pixel unit, determine the reference voltages that the reference voltage source needs to output; Based on the reference voltages that the reference voltage source needs to output, the number of pixel units that each reference voltage needs to drive, and the specifications of each driving enhancement circuit, the correspondence between each reference voltage, the driving enhancement circuit, and the pixel unit is determined, and the circuit connection is turned on.

8. The control method according to claim 7, characterized in that, The process of obtaining the ideal reference voltage required for the first voltage terminal of each pixel unit includes: Determine the ideal reverse bias voltage for each pixel unit; The ideal reference voltage required for the first voltage terminal of each pixel unit is determined based on the ideal reverse bias voltage of each pixel unit and the fixed voltage of the second voltage terminal.

9. The control method according to claim 8, characterized in that, The pixel unit includes at least a SPAD, a quenching circuit, and an inverter. The cathode or anode of the SPAD serves as the first voltage terminal of the pixel unit and is connected to the reference voltage output by the drive enhancement circuit. The anode or cathode of the SPAD serves as the second voltage terminal of the pixel unit and is connected to a fixed voltage. The quenching circuit is disposed on the cathode or anode of the SPAD, and the input terminal of the inverter is connected to the intermediate node between the SPAD and the quenching circuit. Determining the ideal reverse bias voltage for each pixel unit includes: Obtain the ideal over-bias voltage of the SPAD within the pixel unit and the threshold voltage of the inverter; The same fixed reference voltage is provided to the first voltage terminal of each pixel unit in the pixel unit array; Adjust the voltage at the second voltage terminal of each pixel unit until the inverter flips, and record the voltage at the second voltage terminal of the pixel unit when each inverter starts to flip; The ideal reverse bias voltage of the pixel unit is determined based on the voltage at the second voltage terminal of the pixel unit when the inverter starts to flip, the ideal over bias voltage of the SPAD in the pixel unit, the fixed reference voltage, and the threshold voltage of the inverter.

10. The control method according to claim 9, characterized in that, In the process of adjusting the voltage at the second voltage terminal of each pixel unit, the control method further includes: The same initial voltage is provided to the second voltage terminal of each pixel unit, and the voltage of the second voltage terminal of each pixel unit is adjusted synchronously and uniformly. For the pixel unit that has already output a pulse signal, while continuing to adjust the voltage of the second voltage terminal of the pixel unit, the fixed reference voltage of the first voltage terminal of the pixel unit is adjusted synchronously so that the voltage difference between the second voltage terminal of the pixel unit and the fixed reference voltage of the first voltage terminal is always less than or equal to the second preset threshold.

11. The control method according to any one of claims 7 to 10, characterized in that, The step of determining the correspondence between each of the reference voltages, the driving enhancement circuit, and the pixel unit, and then connecting the circuits, includes: Based on the ideal reference voltage required by each pixel unit, determine the pixel unit that needs to be driven by each reference voltage; wherein, the difference between the ideal reference voltage required by the pixel unit that needs to be driven and the reference voltage is less than or equal to a third preset threshold. The number of pixel units to be driven corresponding to each of the reference voltages and the specifications of each of the driving enhancement circuits are obtained; Based on the number of pixel units that each reference voltage needs to drive, select the specification-matching drive enhancement circuit, and sequentially connect the reference voltage, the specification-matching drive enhancement circuit, and the corresponding driven pixel units.

12. The control method according to claim 11, characterized in that, The step of determining the pixel unit driven by each reference voltage according to the ideal reference voltage required by each pixel unit includes: The pixel units in the pixel unit array are classified to obtain multiple types of similar pixel units. The difference in the ideal reference voltage required by the similar pixel units is less than or equal to a first preset threshold. Based on the difference between the ideal reference voltage required by various types of pixel units and each of the reference voltages, the pixel units of the same type that each reference voltage should drive are determined.

13. The control method according to claim 12, characterized in that, The step of selecting the specification-matching drive enhancement circuit based on the number of pixel units to be driven according to each of the reference voltages includes: Determine the number of pixel units in the same type of pixel unit that each reference voltage needs to drive; Arrange various similar pixel units according to the number of pixel units, and arrange each driving enhancement circuit according to its size; Multiple pixel units of the same type and each driving enhancement circuit are sequentially matched and connected according to the same arrangement rule.

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